From 2fc3ce22de0a4b61563e367899447dff14a1f5d1 Mon Sep 17 00:00:00 2001 From: Kjetil Kjeka Date: Sat, 23 Sep 2017 20:31:10 +0200 Subject: [PATCH] Run with updated version of rustfmt --- src/adc0/base_ofs/mod.rs | 4 +- src/adc0/cfg1/mod.rs | 73 ++-- src/adc0/cfg2/mod.rs | 4 +- src/adc0/clp0/mod.rs | 4 +- src/adc0/clp0_ofs/mod.rs | 4 +- src/adc0/clp1/mod.rs | 4 +- src/adc0/clp1_ofs/mod.rs | 4 +- src/adc0/clp2/mod.rs | 4 +- src/adc0/clp2_ofs/mod.rs | 4 +- src/adc0/clp3/mod.rs | 4 +- src/adc0/clp3_ofs/mod.rs | 4 +- src/adc0/clp9/mod.rs | 4 +- src/adc0/clp9_ofs/mod.rs | 4 +- src/adc0/clps/mod.rs | 4 +- src/adc0/clps_ofs/mod.rs | 4 +- src/adc0/clpx/mod.rs | 4 +- src/adc0/clpx_ofs/mod.rs | 4 +- src/adc0/cv/mod.rs | 4 +- src/adc0/g/mod.rs | 4 +- src/adc0/mod.rs | 177 ++++------ src/adc0/ofs/mod.rs | 4 +- src/adc0/r/mod.rs | 4 +- src/adc0/sc1/mod.rs | 175 ++++------ src/adc0/sc2/mod.rs | 67 ++-- src/adc0/sc3/mod.rs | 40 +-- src/adc0/ug/mod.rs | 4 +- src/adc0/usr_ofs/mod.rs | 4 +- src/adc0/xofs/mod.rs | 4 +- src/adc0/yofs/mod.rs | 4 +- src/adc1/base_ofs/mod.rs | 4 +- src/adc1/cfg1/mod.rs | 73 ++-- src/adc1/cfg2/mod.rs | 4 +- src/adc1/clp0/mod.rs | 4 +- src/adc1/clp0_ofs/mod.rs | 4 +- src/adc1/clp1/mod.rs | 4 +- src/adc1/clp1_ofs/mod.rs | 4 +- src/adc1/clp2/mod.rs | 4 +- src/adc1/clp2_ofs/mod.rs | 4 +- src/adc1/clp3/mod.rs | 4 +- src/adc1/clp3_ofs/mod.rs | 4 +- src/adc1/clp9/mod.rs | 4 +- src/adc1/clp9_ofs/mod.rs | 4 +- src/adc1/clps/mod.rs | 4 +- src/adc1/clps_ofs/mod.rs | 4 +- src/adc1/clpx/mod.rs | 4 +- src/adc1/clpx_ofs/mod.rs | 4 +- src/adc1/cv/mod.rs | 4 +- src/adc1/g/mod.rs | 4 +- src/adc1/mod.rs | 177 ++++------ src/adc1/ofs/mod.rs | 4 +- src/adc1/r/mod.rs | 4 +- src/adc1/sc1/mod.rs | 175 ++++------ src/adc1/sc2/mod.rs | 67 ++-- src/adc1/sc3/mod.rs | 40 +-- src/adc1/ug/mod.rs | 4 +- src/adc1/usr_ofs/mod.rs | 4 +- src/adc1/xofs/mod.rs | 4 +- src/adc1/yofs/mod.rs | 4 +- src/aips/mod.rs | 51 +-- src/aips/mpra/mod.rs | 112 +++---- src/aips/opacra/mod.rs | 220 +++++------- src/aips/opacrb/mod.rs | 148 +++------ src/aips/opacrc/mod.rs | 148 +++------ src/aips/opacrd/mod.rs | 184 ++++------ src/aips/opacre/mod.rs | 76 ++--- src/aips/opacrf/mod.rs | 220 +++++------- src/aips/opacrg/mod.rs | 40 +-- src/aips/opacrh/mod.rs | 40 +-- src/aips/opacri/mod.rs | 184 ++++------ src/aips/opacrj/mod.rs | 112 +++---- src/aips/opacrk/mod.rs | 40 +-- src/aips/opacrl/mod.rs | 112 +++---- src/aips/pacra/mod.rs | 76 ++--- src/aips/pacrb/mod.rs | 112 +++---- src/aips/pacrc/mod.rs | 4 +- src/aips/pacrd/mod.rs | 76 ++--- src/can0/cbt/mod.rs | 16 +- src/can0/crcr/mod.rs | 4 +- src/can0/ctrl1/mod.rs | 124 +++---- src/can0/ctrl1_pn/mod.rs | 91 ++--- src/can0/ctrl2/mod.rs | 88 ++--- src/can0/ctrl2_pn/mod.rs | 4 +- src/can0/ecr/mod.rs | 4 +- src/can0/embedded_ram/mod.rs | 4 +- src/can0/esr1/mod.rs | 184 ++++------ src/can0/esr2/mod.rs | 13 +- src/can0/fdcbt/mod.rs | 4 +- src/can0/fdcrc/mod.rs | 4 +- src/can0/fdctrl/mod.rs | 64 ++-- src/can0/flt_dlc/mod.rs | 4 +- src/can0/flt_id1/mod.rs | 28 +- src/can0/flt_id2_idmask/mod.rs | 28 +- src/can0/iflag1/mod.rs | 4 +- src/can0/imask1/mod.rs | 4 +- src/can0/mcr/mod.rs | 166 ++++----- src/can0/mod.rs | 177 ++++------ src/can0/pl1_hi/mod.rs | 4 +- src/can0/pl1_lo/mod.rs | 4 +- src/can0/pl2_plmask_hi/mod.rs | 4 +- src/can0/pl2_plmask_lo/mod.rs | 4 +- src/can0/rx14mask/mod.rs | 4 +- src/can0/rx15mask/mod.rs | 4 +- src/can0/rxfgmask/mod.rs | 4 +- src/can0/rxfir/mod.rs | 4 +- src/can0/rximr0/mod.rs | 4 +- src/can0/rximr1/mod.rs | 4 +- src/can0/rximr10/mod.rs | 4 +- src/can0/rximr11/mod.rs | 4 +- src/can0/rximr12/mod.rs | 4 +- src/can0/rximr13/mod.rs | 4 +- src/can0/rximr14/mod.rs | 4 +- src/can0/rximr15/mod.rs | 4 +- src/can0/rximr2/mod.rs | 4 +- src/can0/rximr3/mod.rs | 4 +- src/can0/rximr4/mod.rs | 4 +- src/can0/rximr5/mod.rs | 4 +- src/can0/rximr6/mod.rs | 4 +- src/can0/rximr7/mod.rs | 4 +- src/can0/rximr8/mod.rs | 4 +- src/can0/rximr9/mod.rs | 4 +- src/can0/rxmgmask/mod.rs | 4 +- src/can0/timer/mod.rs | 4 +- src/can0/wmb0_cs/mod.rs | 16 +- src/can0/wmb0_d03/mod.rs | 4 +- src/can0/wmb0_d47/mod.rs | 4 +- src/can0/wmb0_id/mod.rs | 4 +- src/can0/wmb1_cs/mod.rs | 16 +- src/can0/wmb1_d03/mod.rs | 4 +- src/can0/wmb1_d47/mod.rs | 4 +- src/can0/wmb1_id/mod.rs | 4 +- src/can0/wmb2_cs/mod.rs | 16 +- src/can0/wmb2_d03/mod.rs | 4 +- src/can0/wmb2_d47/mod.rs | 4 +- src/can0/wmb2_id/mod.rs | 4 +- src/can0/wmb3_cs/mod.rs | 16 +- src/can0/wmb3_d03/mod.rs | 4 +- src/can0/wmb3_d47/mod.rs | 4 +- src/can0/wmb3_id/mod.rs | 4 +- src/can0/wu_mtc/mod.rs | 28 +- src/can1/cbt/mod.rs | 16 +- src/can1/crcr/mod.rs | 4 +- src/can1/ctrl1/mod.rs | 124 +++---- src/can1/ctrl1_pn/mod.rs | 91 ++--- src/can1/ctrl2/mod.rs | 88 ++--- src/can1/ctrl2_pn/mod.rs | 4 +- src/can1/ecr/mod.rs | 4 +- src/can1/embedded_ram/mod.rs | 4 +- src/can1/esr1/mod.rs | 184 ++++------ src/can1/esr2/mod.rs | 13 +- src/can1/fdcbt/mod.rs | 4 +- src/can1/fdcrc/mod.rs | 4 +- src/can1/fdctrl/mod.rs | 64 ++-- src/can1/flt_dlc/mod.rs | 4 +- src/can1/flt_id1/mod.rs | 28 +- src/can1/flt_id2_idmask/mod.rs | 28 +- src/can1/iflag1/mod.rs | 4 +- src/can1/imask1/mod.rs | 4 +- src/can1/mcr/mod.rs | 166 ++++----- src/can1/mod.rs | 177 ++++------ src/can1/pl1_hi/mod.rs | 4 +- src/can1/pl1_lo/mod.rs | 4 +- src/can1/pl2_plmask_hi/mod.rs | 4 +- src/can1/pl2_plmask_lo/mod.rs | 4 +- src/can1/rx14mask/mod.rs | 4 +- src/can1/rx15mask/mod.rs | 4 +- src/can1/rxfgmask/mod.rs | 4 +- src/can1/rxfir/mod.rs | 4 +- src/can1/rximr0/mod.rs | 4 +- src/can1/rximr1/mod.rs | 4 +- src/can1/rximr10/mod.rs | 4 +- src/can1/rximr11/mod.rs | 4 +- src/can1/rximr12/mod.rs | 4 +- src/can1/rximr13/mod.rs | 4 +- src/can1/rximr14/mod.rs | 4 +- src/can1/rximr15/mod.rs | 4 +- src/can1/rximr2/mod.rs | 4 +- src/can1/rximr3/mod.rs | 4 +- src/can1/rximr4/mod.rs | 4 +- src/can1/rximr5/mod.rs | 4 +- src/can1/rximr6/mod.rs | 4 +- src/can1/rximr7/mod.rs | 4 +- src/can1/rximr8/mod.rs | 4 +- src/can1/rximr9/mod.rs | 4 +- src/can1/rxmgmask/mod.rs | 4 +- src/can1/timer/mod.rs | 4 +- src/can1/wmb0_cs/mod.rs | 16 +- src/can1/wmb0_d03/mod.rs | 4 +- src/can1/wmb0_d47/mod.rs | 4 +- src/can1/wmb0_id/mod.rs | 4 +- src/can1/wmb1_cs/mod.rs | 16 +- src/can1/wmb1_d03/mod.rs | 4 +- src/can1/wmb1_d47/mod.rs | 4 +- src/can1/wmb1_id/mod.rs | 4 +- src/can1/wmb2_cs/mod.rs | 16 +- src/can1/wmb2_d03/mod.rs | 4 +- src/can1/wmb2_d47/mod.rs | 4 +- src/can1/wmb2_id/mod.rs | 4 +- src/can1/wmb3_cs/mod.rs | 16 +- src/can1/wmb3_d03/mod.rs | 4 +- src/can1/wmb3_d47/mod.rs | 4 +- src/can1/wmb3_id/mod.rs | 4 +- src/can1/wu_mtc/mod.rs | 28 +- src/can2/cbt/mod.rs | 16 +- src/can2/crcr/mod.rs | 4 +- src/can2/ctrl1/mod.rs | 124 +++---- src/can2/ctrl1_pn/mod.rs | 91 ++--- src/can2/ctrl2/mod.rs | 88 ++--- src/can2/ctrl2_pn/mod.rs | 4 +- src/can2/ecr/mod.rs | 4 +- src/can2/embedded_ram/mod.rs | 4 +- src/can2/esr1/mod.rs | 184 ++++------ src/can2/esr2/mod.rs | 13 +- src/can2/fdcbt/mod.rs | 4 +- src/can2/fdcrc/mod.rs | 4 +- src/can2/fdctrl/mod.rs | 64 ++-- src/can2/flt_dlc/mod.rs | 4 +- src/can2/flt_id1/mod.rs | 28 +- src/can2/flt_id2_idmask/mod.rs | 28 +- src/can2/iflag1/mod.rs | 4 +- src/can2/imask1/mod.rs | 4 +- src/can2/mcr/mod.rs | 166 ++++----- src/can2/mod.rs | 177 ++++------ src/can2/pl1_hi/mod.rs | 4 +- src/can2/pl1_lo/mod.rs | 4 +- src/can2/pl2_plmask_hi/mod.rs | 4 +- src/can2/pl2_plmask_lo/mod.rs | 4 +- src/can2/rx14mask/mod.rs | 4 +- src/can2/rx15mask/mod.rs | 4 +- src/can2/rxfgmask/mod.rs | 4 +- src/can2/rxfir/mod.rs | 4 +- src/can2/rximr0/mod.rs | 4 +- src/can2/rximr1/mod.rs | 4 +- src/can2/rximr10/mod.rs | 4 +- src/can2/rximr11/mod.rs | 4 +- src/can2/rximr12/mod.rs | 4 +- src/can2/rximr13/mod.rs | 4 +- src/can2/rximr14/mod.rs | 4 +- src/can2/rximr15/mod.rs | 4 +- src/can2/rximr2/mod.rs | 4 +- src/can2/rximr3/mod.rs | 4 +- src/can2/rximr4/mod.rs | 4 +- src/can2/rximr5/mod.rs | 4 +- src/can2/rximr6/mod.rs | 4 +- src/can2/rximr7/mod.rs | 4 +- src/can2/rximr8/mod.rs | 4 +- src/can2/rximr9/mod.rs | 4 +- src/can2/rxmgmask/mod.rs | 4 +- src/can2/timer/mod.rs | 4 +- src/can2/wmb0_cs/mod.rs | 16 +- src/can2/wmb0_d03/mod.rs | 4 +- src/can2/wmb0_d47/mod.rs | 4 +- src/can2/wmb0_id/mod.rs | 4 +- src/can2/wmb1_cs/mod.rs | 16 +- src/can2/wmb1_d03/mod.rs | 4 +- src/can2/wmb1_d47/mod.rs | 4 +- src/can2/wmb1_id/mod.rs | 4 +- src/can2/wmb2_cs/mod.rs | 16 +- src/can2/wmb2_d03/mod.rs | 4 +- src/can2/wmb2_d47/mod.rs | 4 +- src/can2/wmb2_id/mod.rs | 4 +- src/can2/wmb3_cs/mod.rs | 16 +- src/can2/wmb3_d03/mod.rs | 4 +- src/can2/wmb3_d47/mod.rs | 4 +- src/can2/wmb3_id/mod.rs | 4 +- src/can2/wu_mtc/mod.rs | 28 +- src/cmp0/c0/mod.rs | 208 ++++-------- src/cmp0/c1/mod.rs | 154 +++------ src/cmp0/c2/mod.rs | 91 ++--- src/cmp0/mod.rs | 9 +- src/crc/ctrl/mod.rs | 88 ++--- src/crc/data/mod.rs | 4 +- src/crc/datah/mod.rs | 4 +- src/crc/datahl/mod.rs | 4 +- src/crc/datahu/mod.rs | 4 +- src/crc/datal/mod.rs | 4 +- src/crc/datall/mod.rs | 4 +- src/crc/datalu/mod.rs | 4 +- src/crc/gpoly/mod.rs | 4 +- src/crc/mod.rs | 9 +- src/cse_pram/embedded_ram0/mod.rs | 4 +- src/cse_pram/embedded_ram0hl/mod.rs | 4 +- src/cse_pram/embedded_ram0hu/mod.rs | 4 +- src/cse_pram/embedded_ram0ll/mod.rs | 4 +- src/cse_pram/embedded_ram0lu/mod.rs | 4 +- src/cse_pram/embedded_ram1/mod.rs | 4 +- src/cse_pram/embedded_ram10/mod.rs | 4 +- src/cse_pram/embedded_ram10hl/mod.rs | 4 +- src/cse_pram/embedded_ram10hu/mod.rs | 4 +- src/cse_pram/embedded_ram10ll/mod.rs | 4 +- src/cse_pram/embedded_ram10lu/mod.rs | 4 +- src/cse_pram/embedded_ram11/mod.rs | 4 +- src/cse_pram/embedded_ram11hl/mod.rs | 4 +- src/cse_pram/embedded_ram11hu/mod.rs | 4 +- src/cse_pram/embedded_ram11ll/mod.rs | 4 +- src/cse_pram/embedded_ram11lu/mod.rs | 4 +- src/cse_pram/embedded_ram12/mod.rs | 4 +- src/cse_pram/embedded_ram12hl/mod.rs | 4 +- src/cse_pram/embedded_ram12hu/mod.rs | 4 +- src/cse_pram/embedded_ram12ll/mod.rs | 4 +- src/cse_pram/embedded_ram12lu/mod.rs | 4 +- src/cse_pram/embedded_ram13/mod.rs | 4 +- src/cse_pram/embedded_ram13hl/mod.rs | 4 +- src/cse_pram/embedded_ram13hu/mod.rs | 4 +- src/cse_pram/embedded_ram13ll/mod.rs | 4 +- src/cse_pram/embedded_ram13lu/mod.rs | 4 +- src/cse_pram/embedded_ram14/mod.rs | 4 +- src/cse_pram/embedded_ram14hl/mod.rs | 4 +- src/cse_pram/embedded_ram14hu/mod.rs | 4 +- src/cse_pram/embedded_ram14ll/mod.rs | 4 +- src/cse_pram/embedded_ram14lu/mod.rs | 4 +- src/cse_pram/embedded_ram15/mod.rs | 4 +- src/cse_pram/embedded_ram15hl/mod.rs | 4 +- src/cse_pram/embedded_ram15hu/mod.rs | 4 +- src/cse_pram/embedded_ram15ll/mod.rs | 4 +- src/cse_pram/embedded_ram15lu/mod.rs | 4 +- src/cse_pram/embedded_ram16/mod.rs | 4 +- src/cse_pram/embedded_ram16hl/mod.rs | 4 +- src/cse_pram/embedded_ram16hu/mod.rs | 4 +- src/cse_pram/embedded_ram16ll/mod.rs | 4 +- src/cse_pram/embedded_ram16lu/mod.rs | 4 +- src/cse_pram/embedded_ram17/mod.rs | 4 +- src/cse_pram/embedded_ram17hl/mod.rs | 4 +- src/cse_pram/embedded_ram17hu/mod.rs | 4 +- src/cse_pram/embedded_ram17ll/mod.rs | 4 +- src/cse_pram/embedded_ram17lu/mod.rs | 4 +- src/cse_pram/embedded_ram18/mod.rs | 4 +- src/cse_pram/embedded_ram18hl/mod.rs | 4 +- src/cse_pram/embedded_ram18hu/mod.rs | 4 +- src/cse_pram/embedded_ram18ll/mod.rs | 4 +- src/cse_pram/embedded_ram18lu/mod.rs | 4 +- src/cse_pram/embedded_ram19/mod.rs | 4 +- src/cse_pram/embedded_ram19hl/mod.rs | 4 +- src/cse_pram/embedded_ram19hu/mod.rs | 4 +- src/cse_pram/embedded_ram19ll/mod.rs | 4 +- src/cse_pram/embedded_ram19lu/mod.rs | 4 +- src/cse_pram/embedded_ram1hl/mod.rs | 4 +- src/cse_pram/embedded_ram1hu/mod.rs | 4 +- src/cse_pram/embedded_ram1ll/mod.rs | 4 +- src/cse_pram/embedded_ram1lu/mod.rs | 4 +- src/cse_pram/embedded_ram2/mod.rs | 4 +- src/cse_pram/embedded_ram20/mod.rs | 4 +- src/cse_pram/embedded_ram20hl/mod.rs | 4 +- src/cse_pram/embedded_ram20hu/mod.rs | 4 +- src/cse_pram/embedded_ram20ll/mod.rs | 4 +- src/cse_pram/embedded_ram20lu/mod.rs | 4 +- src/cse_pram/embedded_ram21/mod.rs | 4 +- src/cse_pram/embedded_ram21hl/mod.rs | 4 +- src/cse_pram/embedded_ram21hu/mod.rs | 4 +- src/cse_pram/embedded_ram21ll/mod.rs | 4 +- src/cse_pram/embedded_ram21lu/mod.rs | 4 +- src/cse_pram/embedded_ram22/mod.rs | 4 +- src/cse_pram/embedded_ram22hl/mod.rs | 4 +- src/cse_pram/embedded_ram22hu/mod.rs | 4 +- src/cse_pram/embedded_ram22ll/mod.rs | 4 +- src/cse_pram/embedded_ram22lu/mod.rs | 4 +- src/cse_pram/embedded_ram23/mod.rs | 4 +- src/cse_pram/embedded_ram23hl/mod.rs | 4 +- src/cse_pram/embedded_ram23hu/mod.rs | 4 +- src/cse_pram/embedded_ram23ll/mod.rs | 4 +- src/cse_pram/embedded_ram23lu/mod.rs | 4 +- src/cse_pram/embedded_ram24/mod.rs | 4 +- src/cse_pram/embedded_ram24hl/mod.rs | 4 +- src/cse_pram/embedded_ram24hu/mod.rs | 4 +- src/cse_pram/embedded_ram24ll/mod.rs | 4 +- src/cse_pram/embedded_ram24lu/mod.rs | 4 +- src/cse_pram/embedded_ram25/mod.rs | 4 +- src/cse_pram/embedded_ram25hl/mod.rs | 4 +- src/cse_pram/embedded_ram25hu/mod.rs | 4 +- src/cse_pram/embedded_ram25ll/mod.rs | 4 +- src/cse_pram/embedded_ram25lu/mod.rs | 4 +- src/cse_pram/embedded_ram26/mod.rs | 4 +- src/cse_pram/embedded_ram26hl/mod.rs | 4 +- src/cse_pram/embedded_ram26hu/mod.rs | 4 +- src/cse_pram/embedded_ram26ll/mod.rs | 4 +- src/cse_pram/embedded_ram26lu/mod.rs | 4 +- src/cse_pram/embedded_ram27/mod.rs | 4 +- src/cse_pram/embedded_ram27hl/mod.rs | 4 +- src/cse_pram/embedded_ram27hu/mod.rs | 4 +- src/cse_pram/embedded_ram27ll/mod.rs | 4 +- src/cse_pram/embedded_ram27lu/mod.rs | 4 +- src/cse_pram/embedded_ram28/mod.rs | 4 +- src/cse_pram/embedded_ram28hl/mod.rs | 4 +- src/cse_pram/embedded_ram28hu/mod.rs | 4 +- src/cse_pram/embedded_ram28ll/mod.rs | 4 +- src/cse_pram/embedded_ram28lu/mod.rs | 4 +- src/cse_pram/embedded_ram29/mod.rs | 4 +- src/cse_pram/embedded_ram29hl/mod.rs | 4 +- src/cse_pram/embedded_ram29hu/mod.rs | 4 +- src/cse_pram/embedded_ram29ll/mod.rs | 4 +- src/cse_pram/embedded_ram29lu/mod.rs | 4 +- src/cse_pram/embedded_ram2hl/mod.rs | 4 +- src/cse_pram/embedded_ram2hu/mod.rs | 4 +- src/cse_pram/embedded_ram2ll/mod.rs | 4 +- src/cse_pram/embedded_ram2lu/mod.rs | 4 +- src/cse_pram/embedded_ram3/mod.rs | 4 +- src/cse_pram/embedded_ram30/mod.rs | 4 +- src/cse_pram/embedded_ram30hl/mod.rs | 4 +- src/cse_pram/embedded_ram30hu/mod.rs | 4 +- src/cse_pram/embedded_ram30ll/mod.rs | 4 +- src/cse_pram/embedded_ram30lu/mod.rs | 4 +- src/cse_pram/embedded_ram31/mod.rs | 4 +- src/cse_pram/embedded_ram31hl/mod.rs | 4 +- src/cse_pram/embedded_ram31hu/mod.rs | 4 +- src/cse_pram/embedded_ram31ll/mod.rs | 4 +- src/cse_pram/embedded_ram31lu/mod.rs | 4 +- src/cse_pram/embedded_ram3hl/mod.rs | 4 +- src/cse_pram/embedded_ram3hu/mod.rs | 4 +- src/cse_pram/embedded_ram3ll/mod.rs | 4 +- src/cse_pram/embedded_ram3lu/mod.rs | 4 +- src/cse_pram/embedded_ram4/mod.rs | 4 +- src/cse_pram/embedded_ram4hl/mod.rs | 4 +- src/cse_pram/embedded_ram4hu/mod.rs | 4 +- src/cse_pram/embedded_ram4ll/mod.rs | 4 +- src/cse_pram/embedded_ram4lu/mod.rs | 4 +- src/cse_pram/embedded_ram5/mod.rs | 4 +- src/cse_pram/embedded_ram5hl/mod.rs | 4 +- src/cse_pram/embedded_ram5hu/mod.rs | 4 +- src/cse_pram/embedded_ram5ll/mod.rs | 4 +- src/cse_pram/embedded_ram5lu/mod.rs | 4 +- src/cse_pram/embedded_ram6/mod.rs | 4 +- src/cse_pram/embedded_ram6hl/mod.rs | 4 +- src/cse_pram/embedded_ram6hu/mod.rs | 4 +- src/cse_pram/embedded_ram6ll/mod.rs | 4 +- src/cse_pram/embedded_ram6lu/mod.rs | 4 +- src/cse_pram/embedded_ram7/mod.rs | 4 +- src/cse_pram/embedded_ram7hl/mod.rs | 4 +- src/cse_pram/embedded_ram7hu/mod.rs | 4 +- src/cse_pram/embedded_ram7ll/mod.rs | 4 +- src/cse_pram/embedded_ram7lu/mod.rs | 4 +- src/cse_pram/embedded_ram8/mod.rs | 4 +- src/cse_pram/embedded_ram8hl/mod.rs | 4 +- src/cse_pram/embedded_ram8hu/mod.rs | 4 +- src/cse_pram/embedded_ram8ll/mod.rs | 4 +- src/cse_pram/embedded_ram8lu/mod.rs | 4 +- src/cse_pram/embedded_ram9/mod.rs | 4 +- src/cse_pram/embedded_ram9hl/mod.rs | 4 +- src/cse_pram/embedded_ram9hu/mod.rs | 4 +- src/cse_pram/embedded_ram9ll/mod.rs | 4 +- src/cse_pram/embedded_ram9lu/mod.rs | 4 +- src/cse_pram/mod.rs | 96 ++---- src/dma/cdne/mod.rs | 12 +- src/dma/ceei/mod.rs | 6 +- src/dma/cerq/mod.rs | 6 +- src/dma/cerr/mod.rs | 6 +- src/dma/cint/mod.rs | 6 +- src/dma/cr/mod.rs | 34 +- src/dma/dchpri0/mod.rs | 22 +- src/dma/dchpri1/mod.rs | 22 +- src/dma/dchpri10/mod.rs | 22 +- src/dma/dchpri11/mod.rs | 22 +- src/dma/dchpri12/mod.rs | 22 +- src/dma/dchpri13/mod.rs | 22 +- src/dma/dchpri14/mod.rs | 22 +- src/dma/dchpri15/mod.rs | 22 +- src/dma/dchpri2/mod.rs | 22 +- src/dma/dchpri3/mod.rs | 22 +- src/dma/dchpri4/mod.rs | 22 +- src/dma/dchpri5/mod.rs | 22 +- src/dma/dchpri6/mod.rs | 22 +- src/dma/dchpri7/mod.rs | 22 +- src/dma/dchpri8/mod.rs | 22 +- src/dma/dchpri9/mod.rs | 22 +- src/dma/ears/mod.rs | 196 ++++------- src/dma/eei/mod.rs | 100 ++---- src/dma/erq/mod.rs | 196 ++++------- src/dma/err/mod.rs | 196 ++++------- src/dma/es/mod.rs | 52 ++- src/dma/hrs/mod.rs | 100 ++---- src/dma/int/mod.rs | 196 ++++------- src/dma/mod.rs | 480 ++++++++++----------------- src/dma/seei/mod.rs | 6 +- src/dma/serq/mod.rs | 6 +- src/dma/ssrt/mod.rs | 12 +- src/dma/tcd0_attr/mod.rs | 34 +- src/dma/tcd0_biter_elinkno/mod.rs | 16 +- src/dma/tcd0_biter_elinkyes/mod.rs | 16 +- src/dma/tcd0_citer_elinkno/mod.rs | 16 +- src/dma/tcd0_citer_elinkyes/mod.rs | 16 +- src/dma/tcd0_csr/mod.rs | 79 ++--- src/dma/tcd0_daddr/mod.rs | 4 +- src/dma/tcd0_dlastsga/mod.rs | 4 +- src/dma/tcd0_doff/mod.rs | 4 +- src/dma/tcd0_nbytes_mlno/mod.rs | 4 +- src/dma/tcd0_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd0_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd0_saddr/mod.rs | 4 +- src/dma/tcd0_slast/mod.rs | 4 +- src/dma/tcd0_soff/mod.rs | 4 +- src/dma/tcd10_attr/mod.rs | 34 +- src/dma/tcd10_biter_elinkno/mod.rs | 16 +- src/dma/tcd10_biter_elinkyes/mod.rs | 16 +- src/dma/tcd10_citer_elinkno/mod.rs | 16 +- src/dma/tcd10_citer_elinkyes/mod.rs | 16 +- src/dma/tcd10_csr/mod.rs | 79 ++--- src/dma/tcd10_daddr/mod.rs | 4 +- src/dma/tcd10_dlastsga/mod.rs | 4 +- src/dma/tcd10_doff/mod.rs | 4 +- src/dma/tcd10_nbytes_mlno/mod.rs | 4 +- src/dma/tcd10_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd10_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd10_saddr/mod.rs | 4 +- src/dma/tcd10_slast/mod.rs | 4 +- src/dma/tcd10_soff/mod.rs | 4 +- src/dma/tcd11_attr/mod.rs | 34 +- src/dma/tcd11_biter_elinkno/mod.rs | 16 +- src/dma/tcd11_biter_elinkyes/mod.rs | 16 +- src/dma/tcd11_citer_elinkno/mod.rs | 16 +- src/dma/tcd11_citer_elinkyes/mod.rs | 16 +- src/dma/tcd11_csr/mod.rs | 79 ++--- src/dma/tcd11_daddr/mod.rs | 4 +- src/dma/tcd11_dlastsga/mod.rs | 4 +- src/dma/tcd11_doff/mod.rs | 4 +- src/dma/tcd11_nbytes_mlno/mod.rs | 4 +- src/dma/tcd11_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd11_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd11_saddr/mod.rs | 4 +- src/dma/tcd11_slast/mod.rs | 4 +- src/dma/tcd11_soff/mod.rs | 4 +- src/dma/tcd12_attr/mod.rs | 34 +- src/dma/tcd12_biter_elinkno/mod.rs | 16 +- src/dma/tcd12_biter_elinkyes/mod.rs | 16 +- src/dma/tcd12_citer_elinkno/mod.rs | 16 +- src/dma/tcd12_citer_elinkyes/mod.rs | 16 +- src/dma/tcd12_csr/mod.rs | 79 ++--- src/dma/tcd12_daddr/mod.rs | 4 +- src/dma/tcd12_dlastsga/mod.rs | 4 +- src/dma/tcd12_doff/mod.rs | 4 +- src/dma/tcd12_nbytes_mlno/mod.rs | 4 +- src/dma/tcd12_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd12_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd12_saddr/mod.rs | 4 +- src/dma/tcd12_slast/mod.rs | 4 +- src/dma/tcd12_soff/mod.rs | 4 +- src/dma/tcd13_attr/mod.rs | 34 +- src/dma/tcd13_biter_elinkno/mod.rs | 16 +- src/dma/tcd13_biter_elinkyes/mod.rs | 16 +- src/dma/tcd13_citer_elinkno/mod.rs | 16 +- src/dma/tcd13_citer_elinkyes/mod.rs | 16 +- src/dma/tcd13_csr/mod.rs | 79 ++--- src/dma/tcd13_daddr/mod.rs | 4 +- src/dma/tcd13_dlastsga/mod.rs | 4 +- src/dma/tcd13_doff/mod.rs | 4 +- src/dma/tcd13_nbytes_mlno/mod.rs | 4 +- src/dma/tcd13_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd13_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd13_saddr/mod.rs | 4 +- src/dma/tcd13_slast/mod.rs | 4 +- src/dma/tcd13_soff/mod.rs | 4 +- src/dma/tcd14_attr/mod.rs | 34 +- src/dma/tcd14_biter_elinkno/mod.rs | 16 +- src/dma/tcd14_biter_elinkyes/mod.rs | 16 +- src/dma/tcd14_citer_elinkno/mod.rs | 16 +- src/dma/tcd14_citer_elinkyes/mod.rs | 16 +- src/dma/tcd14_csr/mod.rs | 79 ++--- src/dma/tcd14_daddr/mod.rs | 4 +- src/dma/tcd14_dlastsga/mod.rs | 4 +- src/dma/tcd14_doff/mod.rs | 4 +- src/dma/tcd14_nbytes_mlno/mod.rs | 4 +- src/dma/tcd14_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd14_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd14_saddr/mod.rs | 4 +- src/dma/tcd14_slast/mod.rs | 4 +- src/dma/tcd14_soff/mod.rs | 4 +- src/dma/tcd15_attr/mod.rs | 34 +- src/dma/tcd15_biter_elinkno/mod.rs | 16 +- src/dma/tcd15_biter_elinkyes/mod.rs | 16 +- src/dma/tcd15_citer_elinkno/mod.rs | 16 +- src/dma/tcd15_citer_elinkyes/mod.rs | 16 +- src/dma/tcd15_csr/mod.rs | 79 ++--- src/dma/tcd15_daddr/mod.rs | 4 +- src/dma/tcd15_dlastsga/mod.rs | 4 +- src/dma/tcd15_doff/mod.rs | 4 +- src/dma/tcd15_nbytes_mlno/mod.rs | 4 +- src/dma/tcd15_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd15_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd15_saddr/mod.rs | 4 +- src/dma/tcd15_slast/mod.rs | 4 +- src/dma/tcd15_soff/mod.rs | 4 +- src/dma/tcd1_attr/mod.rs | 34 +- src/dma/tcd1_biter_elinkno/mod.rs | 16 +- src/dma/tcd1_biter_elinkyes/mod.rs | 16 +- src/dma/tcd1_citer_elinkno/mod.rs | 16 +- src/dma/tcd1_citer_elinkyes/mod.rs | 16 +- src/dma/tcd1_csr/mod.rs | 79 ++--- src/dma/tcd1_daddr/mod.rs | 4 +- src/dma/tcd1_dlastsga/mod.rs | 4 +- src/dma/tcd1_doff/mod.rs | 4 +- src/dma/tcd1_nbytes_mlno/mod.rs | 4 +- src/dma/tcd1_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd1_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd1_saddr/mod.rs | 4 +- src/dma/tcd1_slast/mod.rs | 4 +- src/dma/tcd1_soff/mod.rs | 4 +- src/dma/tcd2_attr/mod.rs | 34 +- src/dma/tcd2_biter_elinkno/mod.rs | 16 +- src/dma/tcd2_biter_elinkyes/mod.rs | 16 +- src/dma/tcd2_citer_elinkno/mod.rs | 16 +- src/dma/tcd2_citer_elinkyes/mod.rs | 16 +- src/dma/tcd2_csr/mod.rs | 79 ++--- src/dma/tcd2_daddr/mod.rs | 4 +- src/dma/tcd2_dlastsga/mod.rs | 4 +- src/dma/tcd2_doff/mod.rs | 4 +- src/dma/tcd2_nbytes_mlno/mod.rs | 4 +- src/dma/tcd2_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd2_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd2_saddr/mod.rs | 4 +- src/dma/tcd2_slast/mod.rs | 4 +- src/dma/tcd2_soff/mod.rs | 4 +- src/dma/tcd3_attr/mod.rs | 34 +- src/dma/tcd3_biter_elinkno/mod.rs | 16 +- src/dma/tcd3_biter_elinkyes/mod.rs | 16 +- src/dma/tcd3_citer_elinkno/mod.rs | 16 +- src/dma/tcd3_citer_elinkyes/mod.rs | 16 +- src/dma/tcd3_csr/mod.rs | 79 ++--- src/dma/tcd3_daddr/mod.rs | 4 +- src/dma/tcd3_dlastsga/mod.rs | 4 +- src/dma/tcd3_doff/mod.rs | 4 +- src/dma/tcd3_nbytes_mlno/mod.rs | 4 +- src/dma/tcd3_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd3_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd3_saddr/mod.rs | 4 +- src/dma/tcd3_slast/mod.rs | 4 +- src/dma/tcd3_soff/mod.rs | 4 +- src/dma/tcd4_attr/mod.rs | 34 +- src/dma/tcd4_biter_elinkno/mod.rs | 16 +- src/dma/tcd4_biter_elinkyes/mod.rs | 16 +- src/dma/tcd4_citer_elinkno/mod.rs | 16 +- src/dma/tcd4_citer_elinkyes/mod.rs | 16 +- src/dma/tcd4_csr/mod.rs | 79 ++--- src/dma/tcd4_daddr/mod.rs | 4 +- src/dma/tcd4_dlastsga/mod.rs | 4 +- src/dma/tcd4_doff/mod.rs | 4 +- src/dma/tcd4_nbytes_mlno/mod.rs | 4 +- src/dma/tcd4_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd4_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd4_saddr/mod.rs | 4 +- src/dma/tcd4_slast/mod.rs | 4 +- src/dma/tcd4_soff/mod.rs | 4 +- src/dma/tcd5_attr/mod.rs | 34 +- src/dma/tcd5_biter_elinkno/mod.rs | 16 +- src/dma/tcd5_biter_elinkyes/mod.rs | 16 +- src/dma/tcd5_citer_elinkno/mod.rs | 16 +- src/dma/tcd5_citer_elinkyes/mod.rs | 16 +- src/dma/tcd5_csr/mod.rs | 79 ++--- src/dma/tcd5_daddr/mod.rs | 4 +- src/dma/tcd5_dlastsga/mod.rs | 4 +- src/dma/tcd5_doff/mod.rs | 4 +- src/dma/tcd5_nbytes_mlno/mod.rs | 4 +- src/dma/tcd5_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd5_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd5_saddr/mod.rs | 4 +- src/dma/tcd5_slast/mod.rs | 4 +- src/dma/tcd5_soff/mod.rs | 4 +- src/dma/tcd6_attr/mod.rs | 34 +- src/dma/tcd6_biter_elinkno/mod.rs | 16 +- src/dma/tcd6_biter_elinkyes/mod.rs | 16 +- src/dma/tcd6_citer_elinkno/mod.rs | 16 +- src/dma/tcd6_citer_elinkyes/mod.rs | 16 +- src/dma/tcd6_csr/mod.rs | 79 ++--- src/dma/tcd6_daddr/mod.rs | 4 +- src/dma/tcd6_dlastsga/mod.rs | 4 +- src/dma/tcd6_doff/mod.rs | 4 +- src/dma/tcd6_nbytes_mlno/mod.rs | 4 +- src/dma/tcd6_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd6_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd6_saddr/mod.rs | 4 +- src/dma/tcd6_slast/mod.rs | 4 +- src/dma/tcd6_soff/mod.rs | 4 +- src/dma/tcd7_attr/mod.rs | 34 +- src/dma/tcd7_biter_elinkno/mod.rs | 16 +- src/dma/tcd7_biter_elinkyes/mod.rs | 16 +- src/dma/tcd7_citer_elinkno/mod.rs | 16 +- src/dma/tcd7_citer_elinkyes/mod.rs | 16 +- src/dma/tcd7_csr/mod.rs | 79 ++--- src/dma/tcd7_daddr/mod.rs | 4 +- src/dma/tcd7_dlastsga/mod.rs | 4 +- src/dma/tcd7_doff/mod.rs | 4 +- src/dma/tcd7_nbytes_mlno/mod.rs | 4 +- src/dma/tcd7_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd7_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd7_saddr/mod.rs | 4 +- src/dma/tcd7_slast/mod.rs | 4 +- src/dma/tcd7_soff/mod.rs | 4 +- src/dma/tcd8_attr/mod.rs | 34 +- src/dma/tcd8_biter_elinkno/mod.rs | 16 +- src/dma/tcd8_biter_elinkyes/mod.rs | 16 +- src/dma/tcd8_citer_elinkno/mod.rs | 16 +- src/dma/tcd8_citer_elinkyes/mod.rs | 16 +- src/dma/tcd8_csr/mod.rs | 79 ++--- src/dma/tcd8_daddr/mod.rs | 4 +- src/dma/tcd8_dlastsga/mod.rs | 4 +- src/dma/tcd8_doff/mod.rs | 4 +- src/dma/tcd8_nbytes_mlno/mod.rs | 4 +- src/dma/tcd8_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd8_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd8_saddr/mod.rs | 4 +- src/dma/tcd8_slast/mod.rs | 4 +- src/dma/tcd8_soff/mod.rs | 4 +- src/dma/tcd9_attr/mod.rs | 34 +- src/dma/tcd9_biter_elinkno/mod.rs | 16 +- src/dma/tcd9_biter_elinkyes/mod.rs | 16 +- src/dma/tcd9_citer_elinkno/mod.rs | 16 +- src/dma/tcd9_citer_elinkyes/mod.rs | 16 +- src/dma/tcd9_csr/mod.rs | 79 ++--- src/dma/tcd9_daddr/mod.rs | 4 +- src/dma/tcd9_dlastsga/mod.rs | 4 +- src/dma/tcd9_doff/mod.rs | 4 +- src/dma/tcd9_nbytes_mlno/mod.rs | 4 +- src/dma/tcd9_nbytes_mloffno/mod.rs | 28 +- src/dma/tcd9_nbytes_mloffyes/mod.rs | 28 +- src/dma/tcd9_saddr/mod.rs | 4 +- src/dma/tcd9_slast/mod.rs | 4 +- src/dma/tcd9_soff/mod.rs | 4 +- src/dmamux/chcfg0/mod.rs | 10 +- src/dmamux/chcfg1/mod.rs | 10 +- src/dmamux/chcfg10/mod.rs | 10 +- src/dmamux/chcfg11/mod.rs | 10 +- src/dmamux/chcfg12/mod.rs | 10 +- src/dmamux/chcfg13/mod.rs | 10 +- src/dmamux/chcfg14/mod.rs | 10 +- src/dmamux/chcfg15/mod.rs | 10 +- src/dmamux/chcfg2/mod.rs | 10 +- src/dmamux/chcfg3/mod.rs | 10 +- src/dmamux/chcfg4/mod.rs | 10 +- src/dmamux/chcfg5/mod.rs | 10 +- src/dmamux/chcfg6/mod.rs | 10 +- src/dmamux/chcfg7/mod.rs | 10 +- src/dmamux/chcfg8/mod.rs | 10 +- src/dmamux/chcfg9/mod.rs | 10 +- src/dmamux/mod.rs | 48 +-- src/eim/eichd0_word0/mod.rs | 4 +- src/eim/eichd0_word1/mod.rs | 4 +- src/eim/eichd1_word0/mod.rs | 4 +- src/eim/eichd1_word1/mod.rs | 4 +- src/eim/eichen/mod.rs | 28 +- src/eim/eimcr/mod.rs | 16 +- src/eim/mod.rs | 18 +- src/erm/cr0/mod.rs | 52 ++- src/erm/ear0/mod.rs | 4 +- src/erm/ear1/mod.rs | 4 +- src/erm/mod.rs | 12 +- src/erm/sr0/mod.rs | 52 ++- src/ewm/ctrl/mod.rs | 4 +- src/ewm/mod.rs | 15 +- src/flexio/ctrl/mod.rs | 58 ++-- src/flexio/mod.rs | 141 +++----- src/flexio/param/mod.rs | 4 +- src/flexio/pin/mod.rs | 4 +- src/flexio/shiftbuf0/mod.rs | 4 +- src/flexio/shiftbuf1/mod.rs | 4 +- src/flexio/shiftbuf2/mod.rs | 4 +- src/flexio/shiftbuf3/mod.rs | 4 +- src/flexio/shiftbufbbs0/mod.rs | 4 +- src/flexio/shiftbufbbs1/mod.rs | 4 +- src/flexio/shiftbufbbs2/mod.rs | 4 +- src/flexio/shiftbufbbs3/mod.rs | 4 +- src/flexio/shiftbufbis0/mod.rs | 4 +- src/flexio/shiftbufbis1/mod.rs | 4 +- src/flexio/shiftbufbis2/mod.rs | 4 +- src/flexio/shiftbufbis3/mod.rs | 4 +- src/flexio/shiftbufbys0/mod.rs | 4 +- src/flexio/shiftbufbys1/mod.rs | 4 +- src/flexio/shiftbufbys2/mod.rs | 4 +- src/flexio/shiftbufbys3/mod.rs | 4 +- src/flexio/shiftcfg0/mod.rs | 28 +- src/flexio/shiftcfg1/mod.rs | 28 +- src/flexio/shiftcfg2/mod.rs | 28 +- src/flexio/shiftcfg3/mod.rs | 28 +- src/flexio/shiftctl0/mod.rs | 61 ++-- src/flexio/shiftctl1/mod.rs | 61 ++-- src/flexio/shiftctl2/mod.rs | 61 ++-- src/flexio/shiftctl3/mod.rs | 61 ++-- src/flexio/shifteien/mod.rs | 4 +- src/flexio/shifterr/mod.rs | 4 +- src/flexio/shiftsden/mod.rs | 4 +- src/flexio/shiftsien/mod.rs | 4 +- src/flexio/shiftstat/mod.rs | 4 +- src/flexio/timcfg0/mod.rs | 214 ++++-------- src/flexio/timcfg1/mod.rs | 214 ++++-------- src/flexio/timcfg2/mod.rs | 214 ++++-------- src/flexio/timcfg3/mod.rs | 214 ++++-------- src/flexio/timcmp0/mod.rs | 4 +- src/flexio/timcmp1/mod.rs | 4 +- src/flexio/timcmp2/mod.rs | 4 +- src/flexio/timcmp3/mod.rs | 4 +- src/flexio/timctl0/mod.rs | 88 ++--- src/flexio/timctl1/mod.rs | 88 ++--- src/flexio/timctl2/mod.rs | 88 ++--- src/flexio/timctl3/mod.rs | 88 ++--- src/flexio/timien/mod.rs | 4 +- src/flexio/timstat/mod.rs | 4 +- src/flexio/verid/mod.rs | 13 +- src/ftfc/fccob0/mod.rs | 4 +- src/ftfc/fccob1/mod.rs | 4 +- src/ftfc/fccob2/mod.rs | 4 +- src/ftfc/fccob3/mod.rs | 4 +- src/ftfc/fccob4/mod.rs | 4 +- src/ftfc/fccob5/mod.rs | 4 +- src/ftfc/fccob6/mod.rs | 4 +- src/ftfc/fccob7/mod.rs | 4 +- src/ftfc/fccob8/mod.rs | 4 +- src/ftfc/fccob9/mod.rs | 4 +- src/ftfc/fccoba/mod.rs | 4 +- src/ftfc/fccobb/mod.rs | 4 +- src/ftfc/fcnfg/mod.rs | 34 +- src/ftfc/fcsestat/mod.rs | 4 +- src/ftfc/fdprot/mod.rs | 19 +- src/ftfc/feprot/mod.rs | 4 +- src/ftfc/fercnfg/mod.rs | 10 +- src/ftfc/ferstat/mod.rs | 4 +- src/ftfc/fopt/mod.rs | 4 +- src/ftfc/fprot0/mod.rs | 4 +- src/ftfc/fprot1/mod.rs | 4 +- src/ftfc/fprot2/mod.rs | 4 +- src/ftfc/fprot3/mod.rs | 4 +- src/ftfc/fsec/mod.rs | 37 +-- src/ftfc/fstat/mod.rs | 40 +-- src/ftfc/mod.rs | 75 ++--- src/ftm0/c0sc/mod.rs | 64 ++-- src/ftm0/c0v/mod.rs | 4 +- src/ftm0/c1sc/mod.rs | 64 ++-- src/ftm0/c1v/mod.rs | 4 +- src/ftm0/c2sc/mod.rs | 64 ++-- src/ftm0/c2v/mod.rs | 4 +- src/ftm0/c3sc/mod.rs | 64 ++-- src/ftm0/c3v/mod.rs | 4 +- src/ftm0/c4sc/mod.rs | 64 ++-- src/ftm0/c4v/mod.rs | 4 +- src/ftm0/c5sc/mod.rs | 64 ++-- src/ftm0/c5v/mod.rs | 4 +- src/ftm0/c6sc/mod.rs | 64 ++-- src/ftm0/c6v/mod.rs | 4 +- src/ftm0/c7sc/mod.rs | 64 ++-- src/ftm0/c7v/mod.rs | 4 +- src/ftm0/cnt/mod.rs | 4 +- src/ftm0/cntin/mod.rs | 4 +- src/ftm0/combine/mod.rs | 244 +++++--------- src/ftm0/conf/mod.rs | 16 +- src/ftm0/deadtime/mod.rs | 25 +- src/ftm0/exttrig/mod.rs | 118 +++---- src/ftm0/filter/mod.rs | 4 +- src/ftm0/fltctrl/mod.rs | 106 +++--- src/ftm0/fltpol/mod.rs | 52 ++- src/ftm0/fms/mod.rs | 52 ++- src/ftm0/hcr/mod.rs | 4 +- src/ftm0/invctrl/mod.rs | 52 ++- src/ftm0/mod.rs | 132 +++----- src/ftm0/mod_/mod.rs | 4 +- src/ftm0/mode/mod.rs | 58 ++-- src/ftm0/outinit/mod.rs | 100 ++---- src/ftm0/outmask/mod.rs | 100 ++---- src/ftm0/pair0deadtime/mod.rs | 25 +- src/ftm0/pair1deadtime/mod.rs | 25 +- src/ftm0/pair2deadtime/mod.rs | 25 +- src/ftm0/pair3deadtime/mod.rs | 25 +- src/ftm0/pol/mod.rs | 100 ++---- src/ftm0/pwmload/mod.rs | 136 +++----- src/ftm0/qdctrl/mod.rs | 58 ++-- src/ftm0/sc/mod.rs | 316 ++++++------------ src/ftm0/status/mod.rs | 52 ++- src/ftm0/swoctrl/mod.rs | 196 ++++------- src/ftm0/sync/mod.rs | 82 ++--- src/ftm0/synconf/mod.rs | 142 +++----- src/ftm1/c0sc/mod.rs | 64 ++-- src/ftm1/c0v/mod.rs | 4 +- src/ftm1/c1sc/mod.rs | 64 ++-- src/ftm1/c1v/mod.rs | 4 +- src/ftm1/c2sc/mod.rs | 64 ++-- src/ftm1/c2v/mod.rs | 4 +- src/ftm1/c3sc/mod.rs | 64 ++-- src/ftm1/c3v/mod.rs | 4 +- src/ftm1/c4sc/mod.rs | 64 ++-- src/ftm1/c4v/mod.rs | 4 +- src/ftm1/c5sc/mod.rs | 64 ++-- src/ftm1/c5v/mod.rs | 4 +- src/ftm1/c6sc/mod.rs | 64 ++-- src/ftm1/c6v/mod.rs | 4 +- src/ftm1/c7sc/mod.rs | 64 ++-- src/ftm1/c7v/mod.rs | 4 +- src/ftm1/cnt/mod.rs | 4 +- src/ftm1/cntin/mod.rs | 4 +- src/ftm1/combine/mod.rs | 244 +++++--------- src/ftm1/conf/mod.rs | 16 +- src/ftm1/deadtime/mod.rs | 25 +- src/ftm1/exttrig/mod.rs | 118 +++---- src/ftm1/filter/mod.rs | 4 +- src/ftm1/fltctrl/mod.rs | 106 +++--- src/ftm1/fltpol/mod.rs | 52 ++- src/ftm1/fms/mod.rs | 52 ++- src/ftm1/hcr/mod.rs | 4 +- src/ftm1/invctrl/mod.rs | 52 ++- src/ftm1/mod.rs | 132 +++----- src/ftm1/mod_/mod.rs | 4 +- src/ftm1/mode/mod.rs | 58 ++-- src/ftm1/outinit/mod.rs | 100 ++---- src/ftm1/outmask/mod.rs | 100 ++---- src/ftm1/pair0deadtime/mod.rs | 25 +- src/ftm1/pair1deadtime/mod.rs | 25 +- src/ftm1/pair2deadtime/mod.rs | 25 +- src/ftm1/pair3deadtime/mod.rs | 25 +- src/ftm1/pol/mod.rs | 100 ++---- src/ftm1/pwmload/mod.rs | 136 +++----- src/ftm1/qdctrl/mod.rs | 58 ++-- src/ftm1/sc/mod.rs | 316 ++++++------------ src/ftm1/status/mod.rs | 52 ++- src/ftm1/swoctrl/mod.rs | 196 ++++------- src/ftm1/sync/mod.rs | 82 ++--- src/ftm1/synconf/mod.rs | 142 +++----- src/ftm2/c0sc/mod.rs | 64 ++-- src/ftm2/c0v/mod.rs | 4 +- src/ftm2/c1sc/mod.rs | 64 ++-- src/ftm2/c1v/mod.rs | 4 +- src/ftm2/c2sc/mod.rs | 64 ++-- src/ftm2/c2v/mod.rs | 4 +- src/ftm2/c3sc/mod.rs | 64 ++-- src/ftm2/c3v/mod.rs | 4 +- src/ftm2/c4sc/mod.rs | 64 ++-- src/ftm2/c4v/mod.rs | 4 +- src/ftm2/c5sc/mod.rs | 64 ++-- src/ftm2/c5v/mod.rs | 4 +- src/ftm2/c6sc/mod.rs | 64 ++-- src/ftm2/c6v/mod.rs | 4 +- src/ftm2/c7sc/mod.rs | 64 ++-- src/ftm2/c7v/mod.rs | 4 +- src/ftm2/cnt/mod.rs | 4 +- src/ftm2/cntin/mod.rs | 4 +- src/ftm2/combine/mod.rs | 244 +++++--------- src/ftm2/conf/mod.rs | 16 +- src/ftm2/deadtime/mod.rs | 25 +- src/ftm2/exttrig/mod.rs | 118 +++---- src/ftm2/filter/mod.rs | 4 +- src/ftm2/fltctrl/mod.rs | 106 +++--- src/ftm2/fltpol/mod.rs | 52 ++- src/ftm2/fms/mod.rs | 52 ++- src/ftm2/hcr/mod.rs | 4 +- src/ftm2/invctrl/mod.rs | 52 ++- src/ftm2/mod.rs | 132 +++----- src/ftm2/mod_/mod.rs | 4 +- src/ftm2/mode/mod.rs | 58 ++-- src/ftm2/outinit/mod.rs | 100 ++---- src/ftm2/outmask/mod.rs | 100 ++---- src/ftm2/pair0deadtime/mod.rs | 25 +- src/ftm2/pair1deadtime/mod.rs | 25 +- src/ftm2/pair2deadtime/mod.rs | 25 +- src/ftm2/pair3deadtime/mod.rs | 25 +- src/ftm2/pol/mod.rs | 100 ++---- src/ftm2/pwmload/mod.rs | 136 +++----- src/ftm2/qdctrl/mod.rs | 58 ++-- src/ftm2/sc/mod.rs | 316 ++++++------------ src/ftm2/status/mod.rs | 52 ++- src/ftm2/swoctrl/mod.rs | 196 ++++------- src/ftm2/sync/mod.rs | 82 ++--- src/ftm2/synconf/mod.rs | 142 +++----- src/ftm3/c0sc/mod.rs | 64 ++-- src/ftm3/c0v/mod.rs | 4 +- src/ftm3/c1sc/mod.rs | 64 ++-- src/ftm3/c1v/mod.rs | 4 +- src/ftm3/c2sc/mod.rs | 64 ++-- src/ftm3/c2v/mod.rs | 4 +- src/ftm3/c3sc/mod.rs | 64 ++-- src/ftm3/c3v/mod.rs | 4 +- src/ftm3/c4sc/mod.rs | 64 ++-- src/ftm3/c4v/mod.rs | 4 +- src/ftm3/c5sc/mod.rs | 64 ++-- src/ftm3/c5v/mod.rs | 4 +- src/ftm3/c6sc/mod.rs | 64 ++-- src/ftm3/c6v/mod.rs | 4 +- src/ftm3/c7sc/mod.rs | 64 ++-- src/ftm3/c7v/mod.rs | 4 +- src/ftm3/cnt/mod.rs | 4 +- src/ftm3/cntin/mod.rs | 4 +- src/ftm3/combine/mod.rs | 244 +++++--------- src/ftm3/conf/mod.rs | 16 +- src/ftm3/deadtime/mod.rs | 25 +- src/ftm3/exttrig/mod.rs | 118 +++---- src/ftm3/filter/mod.rs | 4 +- src/ftm3/fltctrl/mod.rs | 106 +++--- src/ftm3/fltpol/mod.rs | 52 ++- src/ftm3/fms/mod.rs | 52 ++- src/ftm3/hcr/mod.rs | 4 +- src/ftm3/invctrl/mod.rs | 52 ++- src/ftm3/mod.rs | 132 +++----- src/ftm3/mod_/mod.rs | 4 +- src/ftm3/mode/mod.rs | 58 ++-- src/ftm3/outinit/mod.rs | 100 ++---- src/ftm3/outmask/mod.rs | 100 ++---- src/ftm3/pair0deadtime/mod.rs | 25 +- src/ftm3/pair1deadtime/mod.rs | 25 +- src/ftm3/pair2deadtime/mod.rs | 25 +- src/ftm3/pair3deadtime/mod.rs | 25 +- src/ftm3/pol/mod.rs | 100 ++---- src/ftm3/pwmload/mod.rs | 136 +++----- src/ftm3/qdctrl/mod.rs | 58 ++-- src/ftm3/sc/mod.rs | 316 ++++++------------ src/ftm3/status/mod.rs | 52 ++- src/ftm3/swoctrl/mod.rs | 196 ++++------- src/ftm3/sync/mod.rs | 82 ++--- src/ftm3/synconf/mod.rs | 142 +++----- src/interrupt/mod.rs | 264 +++++---------- src/lib.rs | 209 +++++------- src/lmem/lmem_pcccr/mod.rs | 76 ++--- src/lmem/lmem_pcccvr/mod.rs | 4 +- src/lmem/lmem_pcclcr/mod.rs | 88 ++--- src/lmem/lmem_pccsar/mod.rs | 10 +- src/lmem/mod.rs | 15 +- src/lmem/pccrmr/mod.rs | 388 ++++++++-------------- src/lpi2c0/mccr0/mod.rs | 4 +- src/lpi2c0/mccr1/mod.rs | 4 +- src/lpi2c0/mcfgr0/mod.rs | 64 ++-- src/lpi2c0/mcfgr1/mod.rs | 157 +++------ src/lpi2c0/mcfgr2/mod.rs | 4 +- src/lpi2c0/mcfgr3/mod.rs | 4 +- src/lpi2c0/mcr/mod.rs | 64 ++-- src/lpi2c0/mder/mod.rs | 28 +- src/lpi2c0/mdmr/mod.rs | 4 +- src/lpi2c0/mfcr/mod.rs | 4 +- src/lpi2c0/mfsr/mod.rs | 4 +- src/lpi2c0/mier/mod.rs | 112 +++---- src/lpi2c0/mod.rs | 84 ++--- src/lpi2c0/mrdr/mod.rs | 10 +- src/lpi2c0/msr/mod.rs | 112 +++---- src/lpi2c0/mtdr/mod.rs | 19 +- src/lpi2c0/param/mod.rs | 4 +- src/lpi2c0/samr/mod.rs | 4 +- src/lpi2c0/sasr/mod.rs | 10 +- src/lpi2c0/scfgr1/mod.rs | 154 +++------ src/lpi2c0/scfgr2/mod.rs | 4 +- src/lpi2c0/scr/mod.rs | 52 ++- src/lpi2c0/sder/mod.rs | 40 +-- src/lpi2c0/sier/mod.rs | 148 +++------ src/lpi2c0/srdr/mod.rs | 13 +- src/lpi2c0/ssr/mod.rs | 112 +++---- src/lpi2c0/star/mod.rs | 16 +- src/lpi2c0/stdr/mod.rs | 4 +- src/lpi2c0/verid/mod.rs | 13 +- src/lpit0/clrten/mod.rs | 28 +- src/lpit0/cval0/mod.rs | 4 +- src/lpit0/cval1/mod.rs | 4 +- src/lpit0/cval2/mod.rs | 4 +- src/lpit0/cval3/mod.rs | 4 +- src/lpit0/mcr/mod.rs | 52 ++- src/lpit0/mier/mod.rs | 52 ++- src/lpit0/mod.rs | 57 ++-- src/lpit0/msr/mod.rs | 52 ++- src/lpit0/param/mod.rs | 4 +- src/lpit0/setten/mod.rs | 52 ++- src/lpit0/tctrl0/mod.rs | 88 ++--- src/lpit0/tctrl1/mod.rs | 88 ++--- src/lpit0/tctrl2/mod.rs | 88 ++--- src/lpit0/tctrl3/mod.rs | 88 ++--- src/lpit0/tval0/mod.rs | 19 +- src/lpit0/tval1/mod.rs | 19 +- src/lpit0/tval2/mod.rs | 19 +- src/lpit0/tval3/mod.rs | 19 +- src/lpit0/verid/mod.rs | 4 +- src/lpspi0/ccr/mod.rs | 4 +- src/lpspi0/cfgr0/mod.rs | 64 ++-- src/lpspi0/cfgr1/mod.rs | 118 +++---- src/lpspi0/cr/mod.rs | 64 ++-- src/lpspi0/der/mod.rs | 28 +- src/lpspi0/dmr0/mod.rs | 4 +- src/lpspi0/dmr1/mod.rs | 4 +- src/lpspi0/fcr/mod.rs | 4 +- src/lpspi0/fsr/mod.rs | 4 +- src/lpspi0/ier/mod.rs | 100 ++---- src/lpspi0/mod.rs | 51 +-- src/lpspi0/param/mod.rs | 4 +- src/lpspi0/rdr/mod.rs | 4 +- src/lpspi0/rsr/mod.rs | 16 +- src/lpspi0/sr/mod.rs | 94 ++---- src/lpspi0/tcr/mod.rs | 193 ++++------- src/lpspi0/verid/mod.rs | 10 +- src/lpspi1/ccr/mod.rs | 4 +- src/lpspi1/cfgr0/mod.rs | 64 ++-- src/lpspi1/cfgr1/mod.rs | 118 +++---- src/lpspi1/cr/mod.rs | 64 ++-- src/lpspi1/der/mod.rs | 28 +- src/lpspi1/dmr0/mod.rs | 4 +- src/lpspi1/dmr1/mod.rs | 4 +- src/lpspi1/fcr/mod.rs | 4 +- src/lpspi1/fsr/mod.rs | 4 +- src/lpspi1/ier/mod.rs | 100 ++---- src/lpspi1/mod.rs | 51 +-- src/lpspi1/param/mod.rs | 4 +- src/lpspi1/rdr/mod.rs | 4 +- src/lpspi1/rsr/mod.rs | 16 +- src/lpspi1/sr/mod.rs | 94 ++---- src/lpspi1/tcr/mod.rs | 193 ++++------- src/lpspi1/verid/mod.rs | 10 +- src/lpspi2/ccr/mod.rs | 4 +- src/lpspi2/cfgr0/mod.rs | 64 ++-- src/lpspi2/cfgr1/mod.rs | 118 +++---- src/lpspi2/cr/mod.rs | 64 ++-- src/lpspi2/der/mod.rs | 28 +- src/lpspi2/dmr0/mod.rs | 4 +- src/lpspi2/dmr1/mod.rs | 4 +- src/lpspi2/fcr/mod.rs | 4 +- src/lpspi2/fsr/mod.rs | 4 +- src/lpspi2/ier/mod.rs | 100 ++---- src/lpspi2/mod.rs | 51 +-- src/lpspi2/param/mod.rs | 4 +- src/lpspi2/rdr/mod.rs | 4 +- src/lpspi2/rsr/mod.rs | 16 +- src/lpspi2/sr/mod.rs | 94 ++---- src/lpspi2/tcr/mod.rs | 193 ++++------- src/lpspi2/verid/mod.rs | 10 +- src/lptmr0/cmr/mod.rs | 4 +- src/lptmr0/cnr/mod.rs | 4 +- src/lptmr0/csr/mod.rs | 100 ++---- src/lptmr0/mod.rs | 12 +- src/lptmr0/psr/mod.rs | 40 +-- src/lpuart0/baud/mod.rs | 334 +++++++------------ src/lpuart0/ctrl/mod.rs | 334 +++++++------------ src/lpuart0/data/mod.rs | 28 +- src/lpuart0/fifo/mod.rs | 142 +++----- src/lpuart0/global/mod.rs | 16 +- src/lpuart0/match_/mod.rs | 4 +- src/lpuart0/mod.rs | 36 +- src/lpuart0/modir/mod.rs | 97 ++---- src/lpuart0/param/mod.rs | 4 +- src/lpuart0/pincfg/mod.rs | 22 +- src/lpuart0/stat/mod.rs | 166 ++++----- src/lpuart0/verid/mod.rs | 13 +- src/lpuart0/water/mod.rs | 4 +- src/lpuart1/baud/mod.rs | 334 +++++++------------ src/lpuart1/ctrl/mod.rs | 334 +++++++------------ src/lpuart1/data/mod.rs | 28 +- src/lpuart1/fifo/mod.rs | 142 +++----- src/lpuart1/global/mod.rs | 16 +- src/lpuart1/match_/mod.rs | 4 +- src/lpuart1/mod.rs | 36 +- src/lpuart1/modir/mod.rs | 97 ++---- src/lpuart1/param/mod.rs | 4 +- src/lpuart1/pincfg/mod.rs | 22 +- src/lpuart1/stat/mod.rs | 166 ++++----- src/lpuart1/verid/mod.rs | 13 +- src/lpuart1/water/mod.rs | 4 +- src/lpuart2/baud/mod.rs | 334 +++++++------------ src/lpuart2/ctrl/mod.rs | 334 +++++++------------ src/lpuart2/data/mod.rs | 28 +- src/lpuart2/fifo/mod.rs | 142 +++----- src/lpuart2/global/mod.rs | 16 +- src/lpuart2/match_/mod.rs | 4 +- src/lpuart2/mod.rs | 36 +- src/lpuart2/modir/mod.rs | 97 ++---- src/lpuart2/param/mod.rs | 4 +- src/lpuart2/pincfg/mod.rs | 22 +- src/lpuart2/stat/mod.rs | 166 ++++----- src/lpuart2/verid/mod.rs | 13 +- src/lpuart2/water/mod.rs | 4 +- src/mcm/cpcr/mod.rs | 100 ++---- src/mcm/cpo/mod.rs | 34 +- src/mcm/iscr/mod.rs | 112 +++---- src/mcm/lmdr0/mod.rs | 106 +++--- src/mcm/lmdr1/mod.rs | 106 +++--- src/mcm/lmdr2/mod.rs | 61 ++-- src/mcm/lmfar/mod.rs | 4 +- src/mcm/lmfatr/mod.rs | 19 +- src/mcm/lmfdhr/mod.rs | 4 +- src/mcm/lmfdlr/mod.rs | 4 +- src/mcm/lmpecr/mod.rs | 40 +-- src/mcm/lmpeir/mod.rs | 13 +- src/mcm/mod.rs | 45 +-- src/mcm/pid/mod.rs | 4 +- src/mcm/plamc/mod.rs | 13 +- src/mcm/plasc/mod.rs | 13 +- src/mscm/cp0cfg0/mod.rs | 4 +- src/mscm/cp0cfg1/mod.rs | 4 +- src/mscm/cp0cfg2/mod.rs | 4 +- src/mscm/cp0cfg3/mod.rs | 46 +-- src/mscm/cp0count/mod.rs | 4 +- src/mscm/cp0master/mod.rs | 4 +- src/mscm/cp0num/mod.rs | 4 +- src/mscm/cp0type/mod.rs | 4 +- src/mscm/cpx_cfg0/mod.rs | 4 +- src/mscm/cpx_cfg1/mod.rs | 4 +- src/mscm/cpx_cfg2/mod.rs | 4 +- src/mscm/cpx_cfg3/mod.rs | 46 +-- src/mscm/cpx_count/mod.rs | 4 +- src/mscm/cpx_master/mod.rs | 4 +- src/mscm/cpx_num/mod.rs | 4 +- src/mscm/cpx_type/mod.rs | 4 +- src/mscm/mod.rs | 60 ++-- src/mscm/ocmdr0/mod.rs | 112 +++---- src/mscm/ocmdr1/mod.rs | 112 +++---- src/mscm/ocmdr2/mod.rs | 112 +++---- src/mscm/ocmdr3/mod.rs | 112 +++---- src/pcc/mod.rs | 348 +++++++------------ src/pcc/pcc_adc0/mod.rs | 70 ++-- src/pcc/pcc_adc1/mod.rs | 70 ++-- src/pcc/pcc_cmp0/mod.rs | 22 +- src/pcc/pcc_crc/mod.rs | 22 +- src/pcc/pcc_dmamux/mod.rs | 22 +- src/pcc/pcc_ewm/mod.rs | 22 +- src/pcc/pcc_flex_can0/mod.rs | 22 +- src/pcc/pcc_flex_can1/mod.rs | 22 +- src/pcc/pcc_flex_can2/mod.rs | 22 +- src/pcc/pcc_flexio/mod.rs | 70 ++-- src/pcc/pcc_ftfc/mod.rs | 22 +- src/pcc/pcc_ftm0/mod.rs | 70 ++-- src/pcc/pcc_ftm1/mod.rs | 70 ++-- src/pcc/pcc_ftm2/mod.rs | 70 ++-- src/pcc/pcc_ftm3/mod.rs | 70 ++-- src/pcc/pcc_lpi2c0/mod.rs | 70 ++-- src/pcc/pcc_lpit/mod.rs | 70 ++-- src/pcc/pcc_lpspi0/mod.rs | 70 ++-- src/pcc/pcc_lpspi1/mod.rs | 70 ++-- src/pcc/pcc_lpspi2/mod.rs | 70 ++-- src/pcc/pcc_lptmr0/mod.rs | 130 +++----- src/pcc/pcc_lpuart0/mod.rs | 70 ++-- src/pcc/pcc_lpuart1/mod.rs | 70 ++-- src/pcc/pcc_lpuart2/mod.rs | 70 ++-- src/pcc/pcc_pdb0/mod.rs | 22 +- src/pcc/pcc_pdb1/mod.rs | 22 +- src/pcc/pcc_porta/mod.rs | 22 +- src/pcc/pcc_portb/mod.rs | 22 +- src/pcc/pcc_portc/mod.rs | 22 +- src/pcc/pcc_portd/mod.rs | 22 +- src/pcc/pcc_porte/mod.rs | 22 +- src/pcc/pcc_rtc/mod.rs | 22 +- src/pcc/pccdummy0/mod.rs | 4 +- src/pcc/pccdummy1/mod.rs | 4 +- src/pcc/pccdummy10/mod.rs | 4 +- src/pcc/pccdummy100/mod.rs | 4 +- src/pcc/pccdummy101/mod.rs | 4 +- src/pcc/pccdummy103/mod.rs | 4 +- src/pcc/pccdummy104/mod.rs | 4 +- src/pcc/pccdummy105/mod.rs | 4 +- src/pcc/pccdummy109/mod.rs | 4 +- src/pcc/pccdummy11/mod.rs | 4 +- src/pcc/pccdummy110/mod.rs | 4 +- src/pcc/pccdummy111/mod.rs | 4 +- src/pcc/pccdummy112/mod.rs | 4 +- src/pcc/pccdummy113/mod.rs | 4 +- src/pcc/pccdummy114/mod.rs | 4 +- src/pcc/pccdummy12/mod.rs | 4 +- src/pcc/pccdummy13/mod.rs | 4 +- src/pcc/pccdummy14/mod.rs | 4 +- src/pcc/pccdummy15/mod.rs | 4 +- src/pcc/pccdummy16/mod.rs | 4 +- src/pcc/pccdummy17/mod.rs | 4 +- src/pcc/pccdummy18/mod.rs | 4 +- src/pcc/pccdummy19/mod.rs | 4 +- src/pcc/pccdummy2/mod.rs | 4 +- src/pcc/pccdummy20/mod.rs | 4 +- src/pcc/pccdummy21/mod.rs | 4 +- src/pcc/pccdummy22/mod.rs | 4 +- src/pcc/pccdummy23/mod.rs | 4 +- src/pcc/pccdummy24/mod.rs | 4 +- src/pcc/pccdummy25/mod.rs | 4 +- src/pcc/pccdummy26/mod.rs | 4 +- src/pcc/pccdummy27/mod.rs | 4 +- src/pcc/pccdummy28/mod.rs | 4 +- src/pcc/pccdummy29/mod.rs | 4 +- src/pcc/pccdummy3/mod.rs | 4 +- src/pcc/pccdummy30/mod.rs | 4 +- src/pcc/pccdummy31/mod.rs | 4 +- src/pcc/pccdummy34/mod.rs | 4 +- src/pcc/pccdummy35/mod.rs | 4 +- src/pcc/pccdummy4/mod.rs | 4 +- src/pcc/pccdummy40/mod.rs | 4 +- src/pcc/pccdummy41/mod.rs | 4 +- src/pcc/pccdummy42/mod.rs | 4 +- src/pcc/pccdummy47/mod.rs | 4 +- src/pcc/pccdummy48/mod.rs | 4 +- src/pcc/pccdummy5/mod.rs | 4 +- src/pcc/pccdummy51/mod.rs | 4 +- src/pcc/pccdummy52/mod.rs | 4 +- src/pcc/pccdummy53/mod.rs | 4 +- src/pcc/pccdummy6/mod.rs | 4 +- src/pcc/pccdummy60/mod.rs | 4 +- src/pcc/pccdummy62/mod.rs | 4 +- src/pcc/pccdummy63/mod.rs | 4 +- src/pcc/pccdummy65/mod.rs | 4 +- src/pcc/pccdummy66/mod.rs | 4 +- src/pcc/pccdummy67/mod.rs | 4 +- src/pcc/pccdummy68/mod.rs | 4 +- src/pcc/pccdummy69/mod.rs | 4 +- src/pcc/pccdummy7/mod.rs | 4 +- src/pcc/pccdummy70/mod.rs | 4 +- src/pcc/pccdummy71/mod.rs | 4 +- src/pcc/pccdummy72/mod.rs | 4 +- src/pcc/pccdummy78/mod.rs | 4 +- src/pcc/pccdummy79/mod.rs | 4 +- src/pcc/pccdummy8/mod.rs | 4 +- src/pcc/pccdummy80/mod.rs | 4 +- src/pcc/pccdummy81/mod.rs | 4 +- src/pcc/pccdummy82/mod.rs | 4 +- src/pcc/pccdummy83/mod.rs | 4 +- src/pcc/pccdummy84/mod.rs | 4 +- src/pcc/pccdummy85/mod.rs | 4 +- src/pcc/pccdummy86/mod.rs | 4 +- src/pcc/pccdummy87/mod.rs | 4 +- src/pcc/pccdummy88/mod.rs | 4 +- src/pcc/pccdummy89/mod.rs | 4 +- src/pcc/pccdummy9/mod.rs | 4 +- src/pcc/pccdummy91/mod.rs | 4 +- src/pcc/pccdummy92/mod.rs | 4 +- src/pcc/pccdummy93/mod.rs | 4 +- src/pcc/pccdummy94/mod.rs | 4 +- src/pcc/pccdummy95/mod.rs | 4 +- src/pcc/pccdummy96/mod.rs | 4 +- src/pcc/pccdummy98/mod.rs | 4 +- src/pcc/pccdummy99/mod.rs | 4 +- src/pdb0/chc1/mod.rs | 37 +-- src/pdb0/chdly0/mod.rs | 4 +- src/pdb0/chdly1/mod.rs | 4 +- src/pdb0/chdly2/mod.rs | 4 +- src/pdb0/chdly3/mod.rs | 4 +- src/pdb0/chdly4/mod.rs | 4 +- src/pdb0/chdly5/mod.rs | 4 +- src/pdb0/chdly6/mod.rs | 4 +- src/pdb0/chdly7/mod.rs | 4 +- src/pdb0/chs/mod.rs | 13 +- src/pdb0/cnt/mod.rs | 4 +- src/pdb0/dly1/mod.rs | 4 +- src/pdb0/dly2/mod.rs | 4 +- src/pdb0/idly/mod.rs | 4 +- src/pdb0/mod.rs | 78 ++--- src/pdb0/mod_/mod.rs | 4 +- src/pdb0/podly/mod.rs | 4 +- src/pdb0/poen/mod.rs | 19 +- src/pdb0/sc/mod.rs | 190 ++++------- src/pdb1/chc1/mod.rs | 37 +-- src/pdb1/chdly0/mod.rs | 4 +- src/pdb1/chdly1/mod.rs | 4 +- src/pdb1/chdly2/mod.rs | 4 +- src/pdb1/chdly3/mod.rs | 4 +- src/pdb1/chdly4/mod.rs | 4 +- src/pdb1/chdly5/mod.rs | 4 +- src/pdb1/chdly6/mod.rs | 4 +- src/pdb1/chdly7/mod.rs | 4 +- src/pdb1/chs/mod.rs | 13 +- src/pdb1/cnt/mod.rs | 4 +- src/pdb1/dly1/mod.rs | 4 +- src/pdb1/dly2/mod.rs | 4 +- src/pdb1/idly/mod.rs | 4 +- src/pdb1/mod.rs | 78 ++--- src/pdb1/mod_/mod.rs | 4 +- src/pdb1/podly/mod.rs | 4 +- src/pdb1/poen/mod.rs | 19 +- src/pdb1/sc/mod.rs | 190 ++++------- src/pmc/lpotrim/mod.rs | 4 +- src/pmc/lvdsc1/mod.rs | 31 +- src/pmc/lvdsc2/mod.rs | 22 +- src/pmc/mod.rs | 12 +- src/pmc/regsc/mod.rs | 40 +-- src/porta/dfcr/mod.rs | 16 +- src/porta/dfer/mod.rs | 7 +- src/porta/dfwr/mod.rs | 4 +- src/porta/gpchr/mod.rs | 6 +- src/porta/gpclr/mod.rs | 6 +- src/porta/isfr/mod.rs | 13 +- src/porta/mod.rs | 114 +++---- src/porta/pcr0/mod.rs | 127 +++---- src/porta/pcr1/mod.rs | 127 +++---- src/porta/pcr10/mod.rs | 127 +++---- src/porta/pcr11/mod.rs | 127 +++---- src/porta/pcr12/mod.rs | 127 +++---- src/porta/pcr13/mod.rs | 127 +++---- src/porta/pcr14/mod.rs | 127 +++---- src/porta/pcr15/mod.rs | 127 +++---- src/porta/pcr16/mod.rs | 127 +++---- src/porta/pcr17/mod.rs | 127 +++---- src/porta/pcr18/mod.rs | 127 +++---- src/porta/pcr19/mod.rs | 127 +++---- src/porta/pcr2/mod.rs | 127 +++---- src/porta/pcr20/mod.rs | 127 +++---- src/porta/pcr21/mod.rs | 127 +++---- src/porta/pcr22/mod.rs | 127 +++---- src/porta/pcr23/mod.rs | 127 +++---- src/porta/pcr24/mod.rs | 127 +++---- src/porta/pcr25/mod.rs | 127 +++---- src/porta/pcr26/mod.rs | 127 +++---- src/porta/pcr27/mod.rs | 127 +++---- src/porta/pcr28/mod.rs | 127 +++---- src/porta/pcr29/mod.rs | 127 +++---- src/porta/pcr3/mod.rs | 127 +++---- src/porta/pcr30/mod.rs | 127 +++---- src/porta/pcr31/mod.rs | 127 +++---- src/porta/pcr4/mod.rs | 127 +++---- src/porta/pcr5/mod.rs | 133 +++----- src/porta/pcr6/mod.rs | 127 +++---- src/porta/pcr7/mod.rs | 127 +++---- src/porta/pcr8/mod.rs | 127 +++---- src/porta/pcr9/mod.rs | 127 +++---- src/portb/dfcr/mod.rs | 16 +- src/portb/dfer/mod.rs | 7 +- src/portb/dfwr/mod.rs | 4 +- src/portb/gpchr/mod.rs | 6 +- src/portb/gpclr/mod.rs | 6 +- src/portb/isfr/mod.rs | 13 +- src/portb/mod.rs | 114 +++---- src/portb/pcr0/mod.rs | 127 +++---- src/portb/pcr1/mod.rs | 127 +++---- src/portb/pcr10/mod.rs | 127 +++---- src/portb/pcr11/mod.rs | 127 +++---- src/portb/pcr12/mod.rs | 127 +++---- src/portb/pcr13/mod.rs | 127 +++---- src/portb/pcr14/mod.rs | 127 +++---- src/portb/pcr15/mod.rs | 127 +++---- src/portb/pcr16/mod.rs | 127 +++---- src/portb/pcr17/mod.rs | 127 +++---- src/portb/pcr18/mod.rs | 127 +++---- src/portb/pcr19/mod.rs | 127 +++---- src/portb/pcr2/mod.rs | 127 +++---- src/portb/pcr20/mod.rs | 127 +++---- src/portb/pcr21/mod.rs | 127 +++---- src/portb/pcr22/mod.rs | 127 +++---- src/portb/pcr23/mod.rs | 127 +++---- src/portb/pcr24/mod.rs | 127 +++---- src/portb/pcr25/mod.rs | 127 +++---- src/portb/pcr26/mod.rs | 127 +++---- src/portb/pcr27/mod.rs | 127 +++---- src/portb/pcr28/mod.rs | 127 +++---- src/portb/pcr29/mod.rs | 127 +++---- src/portb/pcr3/mod.rs | 127 +++---- src/portb/pcr30/mod.rs | 127 +++---- src/portb/pcr31/mod.rs | 127 +++---- src/portb/pcr4/mod.rs | 127 +++---- src/portb/pcr5/mod.rs | 127 +++---- src/portb/pcr6/mod.rs | 127 +++---- src/portb/pcr7/mod.rs | 127 +++---- src/portb/pcr8/mod.rs | 127 +++---- src/portb/pcr9/mod.rs | 127 +++---- src/portc/dfcr/mod.rs | 16 +- src/portc/dfer/mod.rs | 7 +- src/portc/dfwr/mod.rs | 4 +- src/portc/gpchr/mod.rs | 6 +- src/portc/gpclr/mod.rs | 6 +- src/portc/isfr/mod.rs | 13 +- src/portc/mod.rs | 114 +++---- src/portc/pcr0/mod.rs | 127 +++---- src/portc/pcr1/mod.rs | 127 +++---- src/portc/pcr10/mod.rs | 127 +++---- src/portc/pcr11/mod.rs | 127 +++---- src/portc/pcr12/mod.rs | 127 +++---- src/portc/pcr13/mod.rs | 127 +++---- src/portc/pcr14/mod.rs | 127 +++---- src/portc/pcr15/mod.rs | 127 +++---- src/portc/pcr16/mod.rs | 127 +++---- src/portc/pcr17/mod.rs | 127 +++---- src/portc/pcr18/mod.rs | 127 +++---- src/portc/pcr19/mod.rs | 127 +++---- src/portc/pcr2/mod.rs | 127 +++---- src/portc/pcr20/mod.rs | 127 +++---- src/portc/pcr21/mod.rs | 127 +++---- src/portc/pcr22/mod.rs | 127 +++---- src/portc/pcr23/mod.rs | 127 +++---- src/portc/pcr24/mod.rs | 127 +++---- src/portc/pcr25/mod.rs | 127 +++---- src/portc/pcr26/mod.rs | 127 +++---- src/portc/pcr27/mod.rs | 127 +++---- src/portc/pcr28/mod.rs | 127 +++---- src/portc/pcr29/mod.rs | 127 +++---- src/portc/pcr3/mod.rs | 127 +++---- src/portc/pcr30/mod.rs | 127 +++---- src/portc/pcr31/mod.rs | 127 +++---- src/portc/pcr4/mod.rs | 127 +++---- src/portc/pcr5/mod.rs | 127 +++---- src/portc/pcr6/mod.rs | 127 +++---- src/portc/pcr7/mod.rs | 127 +++---- src/portc/pcr8/mod.rs | 127 +++---- src/portc/pcr9/mod.rs | 127 +++---- src/portd/dfcr/mod.rs | 16 +- src/portd/dfer/mod.rs | 7 +- src/portd/dfwr/mod.rs | 4 +- src/portd/gpchr/mod.rs | 6 +- src/portd/gpclr/mod.rs | 6 +- src/portd/isfr/mod.rs | 13 +- src/portd/mod.rs | 114 +++---- src/portd/pcr0/mod.rs | 127 +++---- src/portd/pcr1/mod.rs | 127 +++---- src/portd/pcr10/mod.rs | 127 +++---- src/portd/pcr11/mod.rs | 127 +++---- src/portd/pcr12/mod.rs | 127 +++---- src/portd/pcr13/mod.rs | 127 +++---- src/portd/pcr14/mod.rs | 127 +++---- src/portd/pcr15/mod.rs | 127 +++---- src/portd/pcr16/mod.rs | 127 +++---- src/portd/pcr17/mod.rs | 127 +++---- src/portd/pcr18/mod.rs | 127 +++---- src/portd/pcr19/mod.rs | 127 +++---- src/portd/pcr2/mod.rs | 127 +++---- src/portd/pcr20/mod.rs | 127 +++---- src/portd/pcr21/mod.rs | 127 +++---- src/portd/pcr22/mod.rs | 127 +++---- src/portd/pcr23/mod.rs | 127 +++---- src/portd/pcr24/mod.rs | 127 +++---- src/portd/pcr25/mod.rs | 127 +++---- src/portd/pcr26/mod.rs | 127 +++---- src/portd/pcr27/mod.rs | 127 +++---- src/portd/pcr28/mod.rs | 127 +++---- src/portd/pcr29/mod.rs | 127 +++---- src/portd/pcr3/mod.rs | 133 +++----- src/portd/pcr30/mod.rs | 127 +++---- src/portd/pcr31/mod.rs | 127 +++---- src/portd/pcr4/mod.rs | 127 +++---- src/portd/pcr5/mod.rs | 127 +++---- src/portd/pcr6/mod.rs | 127 +++---- src/portd/pcr7/mod.rs | 127 +++---- src/portd/pcr8/mod.rs | 127 +++---- src/portd/pcr9/mod.rs | 127 +++---- src/porte/dfcr/mod.rs | 16 +- src/porte/dfer/mod.rs | 7 +- src/porte/dfwr/mod.rs | 4 +- src/porte/gpchr/mod.rs | 6 +- src/porte/gpclr/mod.rs | 6 +- src/porte/isfr/mod.rs | 13 +- src/porte/mod.rs | 114 +++---- src/porte/pcr0/mod.rs | 127 +++---- src/porte/pcr1/mod.rs | 127 +++---- src/porte/pcr10/mod.rs | 127 +++---- src/porte/pcr11/mod.rs | 127 +++---- src/porte/pcr12/mod.rs | 127 +++---- src/porte/pcr13/mod.rs | 127 +++---- src/porte/pcr14/mod.rs | 127 +++---- src/porte/pcr15/mod.rs | 127 +++---- src/porte/pcr16/mod.rs | 127 +++---- src/porte/pcr17/mod.rs | 127 +++---- src/porte/pcr18/mod.rs | 127 +++---- src/porte/pcr19/mod.rs | 127 +++---- src/porte/pcr2/mod.rs | 127 +++---- src/porte/pcr20/mod.rs | 127 +++---- src/porte/pcr21/mod.rs | 127 +++---- src/porte/pcr22/mod.rs | 127 +++---- src/porte/pcr23/mod.rs | 127 +++---- src/porte/pcr24/mod.rs | 127 +++---- src/porte/pcr25/mod.rs | 127 +++---- src/porte/pcr26/mod.rs | 127 +++---- src/porte/pcr27/mod.rs | 127 +++---- src/porte/pcr28/mod.rs | 127 +++---- src/porte/pcr29/mod.rs | 127 +++---- src/porte/pcr3/mod.rs | 127 +++---- src/porte/pcr30/mod.rs | 127 +++---- src/porte/pcr31/mod.rs | 127 +++---- src/porte/pcr4/mod.rs | 127 +++---- src/porte/pcr5/mod.rs | 127 +++---- src/porte/pcr6/mod.rs | 127 +++---- src/porte/pcr7/mod.rs | 127 +++---- src/porte/pcr8/mod.rs | 127 +++---- src/porte/pcr9/mod.rs | 127 +++---- src/pta/mod.rs | 21 +- src/pta/pddr/mod.rs | 4 +- src/pta/pdir/mod.rs | 4 +- src/pta/pdor/mod.rs | 4 +- src/pta/pidr/mod.rs | 4 +- src/ptb/mod.rs | 21 +- src/ptb/pddr/mod.rs | 4 +- src/ptb/pdir/mod.rs | 4 +- src/ptb/pdor/mod.rs | 4 +- src/ptb/pidr/mod.rs | 4 +- src/ptc/mod.rs | 21 +- src/ptc/pddr/mod.rs | 4 +- src/ptc/pdir/mod.rs | 4 +- src/ptc/pdor/mod.rs | 4 +- src/ptc/pidr/mod.rs | 4 +- src/ptd/mod.rs | 21 +- src/ptd/pddr/mod.rs | 4 +- src/ptd/pdir/mod.rs | 4 +- src/ptd/pdor/mod.rs | 4 +- src/ptd/pidr/mod.rs | 4 +- src/pte/mod.rs | 21 +- src/pte/pddr/mod.rs | 4 +- src/pte/pdir/mod.rs | 4 +- src/pte/pdor/mod.rs | 4 +- src/pte/pidr/mod.rs | 4 +- src/rcm/mod.rs | 18 +- src/rcm/param/mod.rs | 88 ++--- src/rcm/rpc/mod.rs | 37 +-- src/rcm/srie/mod.rs | 142 +++----- src/rcm/srs/mod.rs | 67 ++-- src/rcm/ssrs/mod.rs | 130 +++----- src/rcm/verid/mod.rs | 10 +- src/rtc/cr/mod.rs | 67 ++-- src/rtc/ier/mod.rs | 100 ++---- src/rtc/lr/mod.rs | 52 ++- src/rtc/mod.rs | 24 +- src/rtc/sr/mod.rs | 34 +- src/rtc/tar/mod.rs | 4 +- src/rtc/tcr/mod.rs | 49 +-- src/rtc/tpr/mod.rs | 4 +- src/rtc/tsr/mod.rs | 4 +- src/scg/clkoutcnfg/mod.rs | 37 +-- src/scg/csr/mod.rs | 142 +++----- src/scg/firccfg/mod.rs | 28 +- src/scg/firccsr/mod.rs | 61 ++-- src/scg/fircdiv/mod.rs | 100 ++---- src/scg/hccr/mod.rs | 274 ++++++--------- src/scg/mod.rs | 57 ++-- src/scg/param/mod.rs | 4 +- src/scg/rccr/mod.rs | 274 ++++++--------- src/scg/sirccfg/mod.rs | 16 +- src/scg/sirccsr/mod.rs | 64 ++-- src/scg/sircdiv/mod.rs | 100 ++---- src/scg/sosccfg/mod.rs | 49 +-- src/scg/sosccsr/mod.rs | 76 ++--- src/scg/soscdiv/mod.rs | 100 ++---- src/scg/spllcfg/mod.rs | 4 +- src/scg/spllcsr/mod.rs | 70 ++-- src/scg/splldiv/mod.rs | 100 ++---- src/scg/vccr/mod.rs | 256 +++++--------- src/scg/verid/mod.rs | 4 +- src/sim/adcopt/mod.rs | 166 ++++----- src/sim/chipctl/mod.rs | 265 +++++---------- src/sim/clkdiv4/mod.rs | 16 +- src/sim/fcfg1/mod.rs | 34 +- src/sim/ftmopt0/mod.rs | 160 +++------ src/sim/ftmopt1/mod.rs | 88 ++--- src/sim/lpoclks/mod.rs | 76 ++--- src/sim/misctrl0/mod.rs | 4 +- src/sim/misctrl1/mod.rs | 4 +- src/sim/mod.rs | 45 +-- src/sim/platcgc/mod.rs | 64 ++-- src/sim/sdid/mod.rs | 43 +-- src/sim/uidh/mod.rs | 4 +- src/sim/uidl/mod.rs | 4 +- src/sim/uidmh/mod.rs | 4 +- src/sim/uidml/mod.rs | 4 +- src/smc/mod.rs | 18 +- src/smc/param/mod.rs | 28 +- src/smc/pmctrl/mod.rs | 52 ++- src/smc/pmprot/mod.rs | 28 +- src/smc/pmstat/mod.rs | 4 +- src/smc/stopctrl/mod.rs | 19 +- src/smc/verid/mod.rs | 10 +- src/trgmux/mod.rs | 78 ++--- src/trgmux/trgmux_adc0/mod.rs | 16 +- src/trgmux/trgmux_adc1/mod.rs | 16 +- src/trgmux/trgmux_cmp0/mod.rs | 16 +- src/trgmux/trgmux_dmamux0/mod.rs | 16 +- src/trgmux/trgmux_extout0/mod.rs | 16 +- src/trgmux/trgmux_extout1/mod.rs | 16 +- src/trgmux/trgmux_flexio/mod.rs | 16 +- src/trgmux/trgmux_ftm0/mod.rs | 16 +- src/trgmux/trgmux_ftm1/mod.rs | 16 +- src/trgmux/trgmux_ftm2/mod.rs | 16 +- src/trgmux/trgmux_ftm3/mod.rs | 16 +- src/trgmux/trgmux_lpi2c0/mod.rs | 16 +- src/trgmux/trgmux_lpit0/mod.rs | 16 +- src/trgmux/trgmux_lpspi0/mod.rs | 16 +- src/trgmux/trgmux_lpspi1/mod.rs | 16 +- src/trgmux/trgmux_lptmr0/mod.rs | 16 +- src/trgmux/trgmux_lpuart0/mod.rs | 16 +- src/trgmux/trgmux_lpuart1/mod.rs | 16 +- src/trgmux/trgmux_pdb0/mod.rs | 16 +- src/trgmux/trgmux_pdb1/mod.rs | 16 +- src/trgmux/trgmuxdummy16/mod.rs | 4 +- src/trgmux/trgmuxdummy22/mod.rs | 4 +- src/trgmux/trgmuxdummy5/mod.rs | 4 +- src/trgmux/trgmuxdummy6/mod.rs | 4 +- src/trgmux/trgmuxdummy8/mod.rs | 4 +- src/trgmux/trgmuxdummy9/mod.rs | 4 +- src/wdog/cnt/mod.rs | 4 +- src/wdog/cs/mod.rs | 136 +++----- src/wdog/mod.rs | 12 +- src/wdog/toval/mod.rs | 4 +- src/wdog/win/mod.rs | 4 +- 1658 files changed, 25191 insertions(+), 42351 deletions(-) diff --git a/src/adc0/base_ofs/mod.rs b/src/adc0/base_ofs/mod.rs index f4f9616..9ab16c0 100644 --- a/src/adc0/base_ofs/mod.rs +++ b/src/adc0/base_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::BASE_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/cfg1/mod.rs b/src/adc0/cfg1/mod.rs index 10dd2e3..3b72ade 100644 --- a/src/adc0/cfg1/mod.rs +++ b/src/adc0/cfg1/mod.rs @@ -22,7 +22,9 @@ impl super::CFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CFG1 { #[doc = "Possible values of the field `ADICLK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADICLKR { - #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] - _00, - #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] - _01, - #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] - _10, - #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] - _11, + #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00, + #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01, + #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10, + #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11, } impl ADICLKR { #[doc = r" Value of the field as raw bits"] @@ -99,14 +97,10 @@ impl ADICLKR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "8-bit conversion."] - _00, - #[doc = "12-bit conversion."] - _01, - #[doc = "10-bit conversion."] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit conversion."] _00, + #[doc = "12-bit conversion."] _01, + #[doc = "10-bit conversion."] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -149,14 +143,10 @@ impl MODER { #[doc = "Possible values of the field `ADIV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADIVR { - #[doc = "The divide ratio is 1 and the clock rate is input clock."] - _00, - #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] - _01, - #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] - _10, - #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] - _11, + #[doc = "The divide ratio is 1 and the clock rate is input clock."] _00, + #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01, + #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10, + #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11, } impl ADIVR { #[doc = r" Value of the field as raw bits"] @@ -204,14 +194,10 @@ impl ADIVR { } #[doc = "Values that can be written to the field `ADICLK`"] pub enum ADICLKW { - #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] - _00, - #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] - _01, - #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] - _10, - #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] - _11, + #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00, + #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01, + #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10, + #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11, } impl ADICLKW { #[allow(missing_docs)] @@ -270,12 +256,9 @@ impl<'a> _ADICLKW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "8-bit conversion."] - _00, - #[doc = "12-bit conversion."] - _01, - #[doc = "10-bit conversion."] - _10, + #[doc = "8-bit conversion."] _00, + #[doc = "12-bit conversion."] _01, + #[doc = "10-bit conversion."] _10, } impl MODEW { #[allow(missing_docs)] @@ -326,14 +309,10 @@ impl<'a> _MODEW<'a> { } #[doc = "Values that can be written to the field `ADIV`"] pub enum ADIVW { - #[doc = "The divide ratio is 1 and the clock rate is input clock."] - _00, - #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] - _01, - #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] - _10, - #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] - _11, + #[doc = "The divide ratio is 1 and the clock rate is input clock."] _00, + #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01, + #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10, + #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11, } impl ADIVW { #[allow(missing_docs)] diff --git a/src/adc0/cfg2/mod.rs b/src/adc0/cfg2/mod.rs index 389c319..15edfa1 100644 --- a/src/adc0/cfg2/mod.rs +++ b/src/adc0/cfg2/mod.rs @@ -22,7 +22,9 @@ impl super::CFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp0/mod.rs b/src/adc0/clp0/mod.rs index d08eee2..e30d4c4 100644 --- a/src/adc0/clp0/mod.rs +++ b/src/adc0/clp0/mod.rs @@ -22,7 +22,9 @@ impl super::CLP0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp0_ofs/mod.rs b/src/adc0/clp0_ofs/mod.rs index dca8074..b40c708 100644 --- a/src/adc0/clp0_ofs/mod.rs +++ b/src/adc0/clp0_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP0_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp1/mod.rs b/src/adc0/clp1/mod.rs index 508ae61..275e48b 100644 --- a/src/adc0/clp1/mod.rs +++ b/src/adc0/clp1/mod.rs @@ -22,7 +22,9 @@ impl super::CLP1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp1_ofs/mod.rs b/src/adc0/clp1_ofs/mod.rs index 9cc7f69..d4ab5a9 100644 --- a/src/adc0/clp1_ofs/mod.rs +++ b/src/adc0/clp1_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP1_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp2/mod.rs b/src/adc0/clp2/mod.rs index cf3aac8..b2d9022 100644 --- a/src/adc0/clp2/mod.rs +++ b/src/adc0/clp2/mod.rs @@ -22,7 +22,9 @@ impl super::CLP2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp2_ofs/mod.rs b/src/adc0/clp2_ofs/mod.rs index 64e9cc5..5cbe400 100644 --- a/src/adc0/clp2_ofs/mod.rs +++ b/src/adc0/clp2_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP2_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp3/mod.rs b/src/adc0/clp3/mod.rs index 94bcdd5..abb9e3b 100644 --- a/src/adc0/clp3/mod.rs +++ b/src/adc0/clp3/mod.rs @@ -22,7 +22,9 @@ impl super::CLP3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp3_ofs/mod.rs b/src/adc0/clp3_ofs/mod.rs index ce00a7f..0e191ac 100644 --- a/src/adc0/clp3_ofs/mod.rs +++ b/src/adc0/clp3_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP3_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp9/mod.rs b/src/adc0/clp9/mod.rs index 2e5dc84..d0609fa 100644 --- a/src/adc0/clp9/mod.rs +++ b/src/adc0/clp9/mod.rs @@ -22,7 +22,9 @@ impl super::CLP9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clp9_ofs/mod.rs b/src/adc0/clp9_ofs/mod.rs index 58ee8a7..2a2b7c0 100644 --- a/src/adc0/clp9_ofs/mod.rs +++ b/src/adc0/clp9_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP9_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clps/mod.rs b/src/adc0/clps/mod.rs index 9215e8e..b8c4c98 100644 --- a/src/adc0/clps/mod.rs +++ b/src/adc0/clps/mod.rs @@ -22,7 +22,9 @@ impl super::CLPS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clps_ofs/mod.rs b/src/adc0/clps_ofs/mod.rs index edc53e2..092789d 100644 --- a/src/adc0/clps_ofs/mod.rs +++ b/src/adc0/clps_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLPS_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clpx/mod.rs b/src/adc0/clpx/mod.rs index f4d2db3..dba2765 100644 --- a/src/adc0/clpx/mod.rs +++ b/src/adc0/clpx/mod.rs @@ -22,7 +22,9 @@ impl super::CLPX { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/clpx_ofs/mod.rs b/src/adc0/clpx_ofs/mod.rs index 79c0a5a..e284c5b 100644 --- a/src/adc0/clpx_ofs/mod.rs +++ b/src/adc0/clpx_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLPX_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/cv/mod.rs b/src/adc0/cv/mod.rs index aaa4874..a789581 100644 --- a/src/adc0/cv/mod.rs +++ b/src/adc0/cv/mod.rs @@ -22,7 +22,9 @@ impl super::CV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/g/mod.rs b/src/adc0/g/mod.rs index 3a952e9..bfd0ba1 100644 --- a/src/adc0/g/mod.rs +++ b/src/adc0/g/mod.rs @@ -22,7 +22,9 @@ impl super::G { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/mod.rs b/src/adc0/mod.rs index 6d25066..5a8a710 100644 --- a/src/adc0/mod.rs +++ b/src/adc0/mod.rs @@ -2,124 +2,77 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - ADC Status and Control Register 1"] - pub sc1a: SC1, - #[doc = "0x04 - ADC Status and Control Register 1"] - pub sc1b: SC1, - #[doc = "0x08 - ADC Status and Control Register 1"] - pub sc1c: SC1, - #[doc = "0x0c - ADC Status and Control Register 1"] - pub sc1d: SC1, - #[doc = "0x10 - ADC Status and Control Register 1"] - pub sc1e: SC1, - #[doc = "0x14 - ADC Status and Control Register 1"] - pub sc1f: SC1, - #[doc = "0x18 - ADC Status and Control Register 1"] - pub sc1g: SC1, - #[doc = "0x1c - ADC Status and Control Register 1"] - pub sc1h: SC1, - #[doc = "0x20 - ADC Status and Control Register 1"] - pub sc1i: SC1, - #[doc = "0x24 - ADC Status and Control Register 1"] - pub sc1j: SC1, - #[doc = "0x28 - ADC Status and Control Register 1"] - pub sc1k: SC1, - #[doc = "0x2c - ADC Status and Control Register 1"] - pub sc1l: SC1, - #[doc = "0x30 - ADC Status and Control Register 1"] - pub sc1m: SC1, - #[doc = "0x34 - ADC Status and Control Register 1"] - pub sc1n: SC1, - #[doc = "0x38 - ADC Status and Control Register 1"] - pub sc1o: SC1, - #[doc = "0x3c - ADC Status and Control Register 1"] - pub sc1p: SC1, - #[doc = "0x40 - ADC Configuration Register 1"] - pub cfg1: CFG1, - #[doc = "0x44 - ADC Configuration Register 2"] - pub cfg2: CFG2, - #[doc = "0x48 - ADC Data Result Registers"] - pub ra: R, - #[doc = "0x4c - ADC Data Result Registers"] - pub rb: R, - #[doc = "0x50 - ADC Data Result Registers"] - pub rc: R, - #[doc = "0x54 - ADC Data Result Registers"] - pub rd: R, - #[doc = "0x58 - ADC Data Result Registers"] - pub re: R, - #[doc = "0x5c - ADC Data Result Registers"] - pub rf: R, - #[doc = "0x60 - ADC Data Result Registers"] - pub rg: R, - #[doc = "0x64 - ADC Data Result Registers"] - pub rh: R, - #[doc = "0x68 - ADC Data Result Registers"] - pub ri: R, - #[doc = "0x6c - ADC Data Result Registers"] - pub rj: R, - #[doc = "0x70 - ADC Data Result Registers"] - pub rk: R, - #[doc = "0x74 - ADC Data Result Registers"] - pub rl: R, - #[doc = "0x78 - ADC Data Result Registers"] - pub rm: R, - #[doc = "0x7c - ADC Data Result Registers"] - pub rn: R, - #[doc = "0x80 - ADC Data Result Registers"] - pub ro: R, - #[doc = "0x84 - ADC Data Result Registers"] - pub rp: R, - #[doc = "0x88 - Compare Value Registers"] - pub cv1: CV, - #[doc = "0x8c - Compare Value Registers"] - pub cv2: CV, - #[doc = "0x90 - Status and Control Register 2"] - pub sc2: SC2, - #[doc = "0x94 - Status and Control Register 3"] - pub sc3: SC3, - #[doc = "0x98 - BASE Offset Register"] - pub base_ofs: BASE_OFS, - #[doc = "0x9c - ADC Offset Correction Register"] - pub ofs: OFS, - #[doc = "0xa0 - USER Offset Correction Register"] - pub usr_ofs: USR_OFS, - #[doc = "0xa4 - ADC X Offset Correction Register"] - pub xofs: XOFS, - #[doc = "0xa8 - ADC Y Offset Correction Register"] - pub yofs: YOFS, - #[doc = "0xac - ADC Gain Register"] - pub g: G, - #[doc = "0xb0 - ADC User Gain Register"] - pub ug: UG, - #[doc = "0xb4 - ADC General Calibration Value Register S"] - pub clps: CLPS, - #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] - pub clp3: CLP3, - #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] - pub clp2: CLP2, - #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] - pub clp1: CLP1, - #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] - pub clp0: CLP0, - #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] - pub clpx: CLPX, - #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] - pub clp9: CLP9, - #[doc = "0xd0 - ADC General Calibration Offset Value Register S"] - pub clps_ofs: CLPS_OFS, + #[doc = "0x00 - ADC Status and Control Register 1"] pub sc1a: SC1, + #[doc = "0x04 - ADC Status and Control Register 1"] pub sc1b: SC1, + #[doc = "0x08 - ADC Status and Control Register 1"] pub sc1c: SC1, + #[doc = "0x0c - ADC Status and Control Register 1"] pub sc1d: SC1, + #[doc = "0x10 - ADC Status and Control Register 1"] pub sc1e: SC1, + #[doc = "0x14 - ADC Status and Control Register 1"] pub sc1f: SC1, + #[doc = "0x18 - ADC Status and Control Register 1"] pub sc1g: SC1, + #[doc = "0x1c - ADC Status and Control Register 1"] pub sc1h: SC1, + #[doc = "0x20 - ADC Status and Control Register 1"] pub sc1i: SC1, + #[doc = "0x24 - ADC Status and Control Register 1"] pub sc1j: SC1, + #[doc = "0x28 - ADC Status and Control Register 1"] pub sc1k: SC1, + #[doc = "0x2c - ADC Status and Control Register 1"] pub sc1l: SC1, + #[doc = "0x30 - ADC Status and Control Register 1"] pub sc1m: SC1, + #[doc = "0x34 - ADC Status and Control Register 1"] pub sc1n: SC1, + #[doc = "0x38 - ADC Status and Control Register 1"] pub sc1o: SC1, + #[doc = "0x3c - ADC Status and Control Register 1"] pub sc1p: SC1, + #[doc = "0x40 - ADC Configuration Register 1"] pub cfg1: CFG1, + #[doc = "0x44 - ADC Configuration Register 2"] pub cfg2: CFG2, + #[doc = "0x48 - ADC Data Result Registers"] pub ra: R, + #[doc = "0x4c - ADC Data Result Registers"] pub rb: R, + #[doc = "0x50 - ADC Data Result Registers"] pub rc: R, + #[doc = "0x54 - ADC Data Result Registers"] pub rd: R, + #[doc = "0x58 - ADC Data Result Registers"] pub re: R, + #[doc = "0x5c - ADC Data Result Registers"] pub rf: R, + #[doc = "0x60 - ADC Data Result Registers"] pub rg: R, + #[doc = "0x64 - ADC Data Result Registers"] pub rh: R, + #[doc = "0x68 - ADC Data Result Registers"] pub ri: R, + #[doc = "0x6c - ADC Data Result Registers"] pub rj: R, + #[doc = "0x70 - ADC Data Result Registers"] pub rk: R, + #[doc = "0x74 - ADC Data Result Registers"] pub rl: R, + #[doc = "0x78 - ADC Data Result Registers"] pub rm: R, + #[doc = "0x7c - ADC Data Result Registers"] pub rn: R, + #[doc = "0x80 - ADC Data Result Registers"] pub ro: R, + #[doc = "0x84 - ADC Data Result Registers"] pub rp: R, + #[doc = "0x88 - Compare Value Registers"] pub cv1: CV, + #[doc = "0x8c - Compare Value Registers"] pub cv2: CV, + #[doc = "0x90 - Status and Control Register 2"] pub sc2: SC2, + #[doc = "0x94 - Status and Control Register 3"] pub sc3: SC3, + #[doc = "0x98 - BASE Offset Register"] pub base_ofs: BASE_OFS, + #[doc = "0x9c - ADC Offset Correction Register"] pub ofs: OFS, + #[doc = "0xa0 - USER Offset Correction Register"] pub usr_ofs: USR_OFS, + #[doc = "0xa4 - ADC X Offset Correction Register"] pub xofs: XOFS, + #[doc = "0xa8 - ADC Y Offset Correction Register"] pub yofs: YOFS, + #[doc = "0xac - ADC Gain Register"] pub g: G, + #[doc = "0xb0 - ADC User Gain Register"] pub ug: UG, + #[doc = "0xb4 - ADC General Calibration Value Register S"] pub clps: CLPS, + #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] pub clp3: CLP3, + #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] pub clp2: CLP2, + #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] pub clp1: CLP1, + #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] pub clp0: CLP0, + #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] pub clpx: CLPX, + #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] pub clp9: CLP9, + #[doc = "0xd0 - ADC General Calibration Offset Value Register S"] pub clps_ofs: CLPS_OFS, #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"] - pub clp3_ofs: CLP3_OFS, + pub clp3_ofs: + CLP3_OFS, #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"] - pub clp2_ofs: CLP2_OFS, + pub clp2_ofs: + CLP2_OFS, #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"] - pub clp1_ofs: CLP1_OFS, + pub clp1_ofs: + CLP1_OFS, #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"] - pub clp0_ofs: CLP0_OFS, + pub clp0_ofs: + CLP0_OFS, #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"] - pub clpx_ofs: CLPX_OFS, + pub clpx_ofs: + CLPX_OFS, #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"] - pub clp9_ofs: CLP9_OFS, + pub clp9_ofs: + CLP9_OFS, } #[doc = "ADC Status and Control Register 1"] pub struct SC1 { diff --git a/src/adc0/ofs/mod.rs b/src/adc0/ofs/mod.rs index 744994d..e2f1050 100644 --- a/src/adc0/ofs/mod.rs +++ b/src/adc0/ofs/mod.rs @@ -22,7 +22,9 @@ impl super::OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/r/mod.rs b/src/adc0/r/mod.rs index ce24e1b..1d20cd6 100644 --- a/src/adc0/r/mod.rs +++ b/src/adc0/r/mod.rs @@ -6,7 +6,9 @@ impl super::R { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/adc0/sc1/mod.rs b/src/adc0/sc1/mod.rs index 6490b4b..4043f66 100644 --- a/src/adc0/sc1/mod.rs +++ b/src/adc0/sc1/mod.rs @@ -22,7 +22,9 @@ impl super::SC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,62 +45,36 @@ impl super::SC1 { #[doc = "Possible values of the field `ADCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADCHR { - #[doc = "Exernal channel 0 is selected as input."] - _00000, - #[doc = "Exernal channel 1 is selected as input."] - _00001, - #[doc = "Exernal channel 2 is selected as input."] - _00010, - #[doc = "Exernal channel 3 is selected as input."] - _00011, - #[doc = "Exernal channel 4 is selected as input."] - _00100, - #[doc = "Exernal channel 5 is selected as input."] - _00101, - #[doc = "Exernal channel 6 is selected as input."] - _00110, - #[doc = "Exernal channel 7 is selected as input."] - _00111, - #[doc = "Exernal channel 8 is selected as input."] - _01000, - #[doc = "Exernal channel 9 is selected as input."] - _01001, - #[doc = "Exernal channel 10 is selected as input."] - _01010, - #[doc = "Exernal channel 11 is selected as input."] - _01011, - #[doc = "Exernal channel 12 is selected as input."] - _01100, - #[doc = "Exernal channel 13 is selected as input."] - _01101, - #[doc = "Exernal channel 14 is selected as input."] - _01110, - #[doc = "Exernal channel 15 is selected as input."] - _01111, - #[doc = "Exernal channel 18 is selected as input."] - _10010, - #[doc = "Exernal channel 19 is selected as input."] - _10011, - #[doc = "Internal channel 0 is selected as input."] - _10101, - #[doc = "Internal channel 1 is selected as input."] - _10110, - #[doc = "Internal channel 2 is selected as input."] - _10111, - #[doc = "Temp Sensor"] - _11010, - #[doc = "Band Gap"] - _11011, - #[doc = "Internal channel 3 is selected as input."] - _11100, + #[doc = "Exernal channel 0 is selected as input."] _00000, + #[doc = "Exernal channel 1 is selected as input."] _00001, + #[doc = "Exernal channel 2 is selected as input."] _00010, + #[doc = "Exernal channel 3 is selected as input."] _00011, + #[doc = "Exernal channel 4 is selected as input."] _00100, + #[doc = "Exernal channel 5 is selected as input."] _00101, + #[doc = "Exernal channel 6 is selected as input."] _00110, + #[doc = "Exernal channel 7 is selected as input."] _00111, + #[doc = "Exernal channel 8 is selected as input."] _01000, + #[doc = "Exernal channel 9 is selected as input."] _01001, + #[doc = "Exernal channel 10 is selected as input."] _01010, + #[doc = "Exernal channel 11 is selected as input."] _01011, + #[doc = "Exernal channel 12 is selected as input."] _01100, + #[doc = "Exernal channel 13 is selected as input."] _01101, + #[doc = "Exernal channel 14 is selected as input."] _01110, + #[doc = "Exernal channel 15 is selected as input."] _01111, + #[doc = "Exernal channel 18 is selected as input."] _10010, + #[doc = "Exernal channel 19 is selected as input."] _10011, + #[doc = "Internal channel 0 is selected as input."] _10101, + #[doc = "Internal channel 1 is selected as input."] _10110, + #[doc = "Internal channel 2 is selected as input."] _10111, + #[doc = "Temp Sensor"] _11010, + #[doc = "Band Gap"] _11011, + #[doc = "Internal channel 3 is selected as input."] _11100, #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11101, #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11110, - #[doc = "Module is disabled"] - _11111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Module is disabled"] _11111, + #[doc = r" Reserved"] _Reserved(u8), } impl ADCHR { #[doc = r" Value of the field as raw bits"] @@ -309,10 +285,8 @@ impl ADCHR { #[doc = "Possible values of the field `AIEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AIENR { - #[doc = "Conversion complete interrupt is disabled."] - _0, - #[doc = "Conversion complete interrupt is enabled."] - _1, + #[doc = "Conversion complete interrupt is disabled."] _0, + #[doc = "Conversion complete interrupt is enabled."] _1, } impl AIENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -356,10 +330,8 @@ impl AIENR { #[doc = "Possible values of the field `COCO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COCOR { - #[doc = "Conversion is not completed."] - _0, - #[doc = "Conversion is completed."] - _1, + #[doc = "Conversion is not completed."] _0, + #[doc = "Conversion is completed."] _1, } impl COCOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -402,60 +374,35 @@ impl COCOR { } #[doc = "Values that can be written to the field `ADCH`"] pub enum ADCHW { - #[doc = "Exernal channel 0 is selected as input."] - _00000, - #[doc = "Exernal channel 1 is selected as input."] - _00001, - #[doc = "Exernal channel 2 is selected as input."] - _00010, - #[doc = "Exernal channel 3 is selected as input."] - _00011, - #[doc = "Exernal channel 4 is selected as input."] - _00100, - #[doc = "Exernal channel 5 is selected as input."] - _00101, - #[doc = "Exernal channel 6 is selected as input."] - _00110, - #[doc = "Exernal channel 7 is selected as input."] - _00111, - #[doc = "Exernal channel 8 is selected as input."] - _01000, - #[doc = "Exernal channel 9 is selected as input."] - _01001, - #[doc = "Exernal channel 10 is selected as input."] - _01010, - #[doc = "Exernal channel 11 is selected as input."] - _01011, - #[doc = "Exernal channel 12 is selected as input."] - _01100, - #[doc = "Exernal channel 13 is selected as input."] - _01101, - #[doc = "Exernal channel 14 is selected as input."] - _01110, - #[doc = "Exernal channel 15 is selected as input."] - _01111, - #[doc = "Exernal channel 18 is selected as input."] - _10010, - #[doc = "Exernal channel 19 is selected as input."] - _10011, - #[doc = "Internal channel 0 is selected as input."] - _10101, - #[doc = "Internal channel 1 is selected as input."] - _10110, - #[doc = "Internal channel 2 is selected as input."] - _10111, - #[doc = "Temp Sensor"] - _11010, - #[doc = "Band Gap"] - _11011, - #[doc = "Internal channel 3 is selected as input."] - _11100, + #[doc = "Exernal channel 0 is selected as input."] _00000, + #[doc = "Exernal channel 1 is selected as input."] _00001, + #[doc = "Exernal channel 2 is selected as input."] _00010, + #[doc = "Exernal channel 3 is selected as input."] _00011, + #[doc = "Exernal channel 4 is selected as input."] _00100, + #[doc = "Exernal channel 5 is selected as input."] _00101, + #[doc = "Exernal channel 6 is selected as input."] _00110, + #[doc = "Exernal channel 7 is selected as input."] _00111, + #[doc = "Exernal channel 8 is selected as input."] _01000, + #[doc = "Exernal channel 9 is selected as input."] _01001, + #[doc = "Exernal channel 10 is selected as input."] _01010, + #[doc = "Exernal channel 11 is selected as input."] _01011, + #[doc = "Exernal channel 12 is selected as input."] _01100, + #[doc = "Exernal channel 13 is selected as input."] _01101, + #[doc = "Exernal channel 14 is selected as input."] _01110, + #[doc = "Exernal channel 15 is selected as input."] _01111, + #[doc = "Exernal channel 18 is selected as input."] _10010, + #[doc = "Exernal channel 19 is selected as input."] _10011, + #[doc = "Internal channel 0 is selected as input."] _10101, + #[doc = "Internal channel 1 is selected as input."] _10110, + #[doc = "Internal channel 2 is selected as input."] _10111, + #[doc = "Temp Sensor"] _11010, + #[doc = "Band Gap"] _11011, + #[doc = "Internal channel 3 is selected as input."] _11100, #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11101, #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11110, - #[doc = "Module is disabled"] - _11111, + #[doc = "Module is disabled"] _11111, } impl ADCHW { #[allow(missing_docs)] @@ -650,10 +597,8 @@ impl<'a> _ADCHW<'a> { } #[doc = "Values that can be written to the field `AIEN`"] pub enum AIENW { - #[doc = "Conversion complete interrupt is disabled."] - _0, - #[doc = "Conversion complete interrupt is enabled."] - _1, + #[doc = "Conversion complete interrupt is disabled."] _0, + #[doc = "Conversion complete interrupt is enabled."] _1, } impl AIENW { #[allow(missing_docs)] diff --git a/src/adc0/sc2/mod.rs b/src/adc0/sc2/mod.rs index d5648f5..93c5601 100644 --- a/src/adc0/sc2/mod.rs +++ b/src/adc0/sc2/mod.rs @@ -22,7 +22,9 @@ impl super::SC2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::SC2 { #[doc = "Possible values of the field `REFSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REFSELR { - #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] - _00, + #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00, #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."] _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl REFSELR { #[doc = r" Value of the field as raw bits"] @@ -84,8 +84,7 @@ impl REFSELR { #[doc = "Possible values of the field `DMAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAENR { - #[doc = "DMA is disabled."] - _0, + #[doc = "DMA is disabled."] _0, #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."] _1, } @@ -173,10 +172,8 @@ impl ACFGTR { #[doc = "Possible values of the field `ACFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACFER { - #[doc = "Compare function disabled."] - _0, - #[doc = "Compare function enabled."] - _1, + #[doc = "Compare function disabled."] _0, + #[doc = "Compare function enabled."] _1, } impl ACFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -220,10 +217,8 @@ impl ACFER { #[doc = "Possible values of the field `ADTRG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADTRGR { - #[doc = "Software trigger selected."] - _0, - #[doc = "Hardware trigger selected."] - _1, + #[doc = "Software trigger selected."] _0, + #[doc = "Hardware trigger selected."] _1, } impl ADTRGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +262,8 @@ impl ADTRGR { #[doc = "Possible values of the field `ADACT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADACTR { - #[doc = "Conversion not in progress."] - _0, - #[doc = "Conversion in progress."] - _1, + #[doc = "Conversion not in progress."] _0, + #[doc = "Conversion in progress."] _1, } impl ADACTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,12 +318,9 @@ impl TRGPRNUMR { #[doc = "Possible values of the field `TRGSTLAT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSTLATR { - #[doc = "No trigger request has been latched"] - _0, - #[doc = "A trigger request has been latched"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No trigger request has been latched"] _0, + #[doc = "A trigger request has been latched"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl TRGSTLATR { #[doc = r" Value of the field as raw bits"] @@ -366,12 +356,9 @@ impl TRGSTLATR { #[doc = "Possible values of the field `TRGSTERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSTERRR { - #[doc = "No error has occurred"] - _0, - #[doc = "An error has occurred"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No error has occurred"] _0, + #[doc = "An error has occurred"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl TRGSTERRR { #[doc = r" Value of the field as raw bits"] @@ -406,8 +393,7 @@ impl TRGSTERRR { } #[doc = "Values that can be written to the field `REFSEL`"] pub enum REFSELW { - #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] - _00, + #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00, #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."] _01, } @@ -454,8 +440,7 @@ impl<'a> _REFSELW<'a> { } #[doc = "Values that can be written to the field `DMAEN`"] pub enum DMAENW { - #[doc = "DMA is disabled."] - _0, + #[doc = "DMA is disabled."] _0, #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."] _1, } @@ -558,10 +543,8 @@ impl<'a> _ACFGTW<'a> { } #[doc = "Values that can be written to the field `ACFE`"] pub enum ACFEW { - #[doc = "Compare function disabled."] - _0, - #[doc = "Compare function enabled."] - _1, + #[doc = "Compare function disabled."] _0, + #[doc = "Compare function enabled."] _1, } impl ACFEW { #[allow(missing_docs)] @@ -616,10 +599,8 @@ impl<'a> _ACFEW<'a> { } #[doc = "Values that can be written to the field `ADTRG`"] pub enum ADTRGW { - #[doc = "Software trigger selected."] - _0, - #[doc = "Hardware trigger selected."] - _1, + #[doc = "Software trigger selected."] _0, + #[doc = "Hardware trigger selected."] _1, } impl ADTRGW { #[allow(missing_docs)] diff --git a/src/adc0/sc3/mod.rs b/src/adc0/sc3/mod.rs index deca775..7e4cf08 100644 --- a/src/adc0/sc3/mod.rs +++ b/src/adc0/sc3/mod.rs @@ -22,7 +22,9 @@ impl super::SC3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::SC3 { #[doc = "Possible values of the field `AVGS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVGSR { - #[doc = "4 samples averaged."] - _00, - #[doc = "8 samples averaged."] - _01, - #[doc = "16 samples averaged."] - _10, - #[doc = "32 samples averaged."] - _11, + #[doc = "4 samples averaged."] _00, + #[doc = "8 samples averaged."] _01, + #[doc = "16 samples averaged."] _10, + #[doc = "32 samples averaged."] _11, } impl AVGSR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl AVGSR { #[doc = "Possible values of the field `AVGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVGER { - #[doc = "Hardware average function disabled."] - _0, - #[doc = "Hardware average function enabled."] - _1, + #[doc = "Hardware average function disabled."] _0, + #[doc = "Hardware average function enabled."] _1, } impl AVGER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -213,14 +209,10 @@ impl CALR { } #[doc = "Values that can be written to the field `AVGS`"] pub enum AVGSW { - #[doc = "4 samples averaged."] - _00, - #[doc = "8 samples averaged."] - _01, - #[doc = "16 samples averaged."] - _10, - #[doc = "32 samples averaged."] - _11, + #[doc = "4 samples averaged."] _00, + #[doc = "8 samples averaged."] _01, + #[doc = "16 samples averaged."] _10, + #[doc = "32 samples averaged."] _11, } impl AVGSW { #[allow(missing_docs)] @@ -279,10 +271,8 @@ impl<'a> _AVGSW<'a> { } #[doc = "Values that can be written to the field `AVGE`"] pub enum AVGEW { - #[doc = "Hardware average function disabled."] - _0, - #[doc = "Hardware average function enabled."] - _1, + #[doc = "Hardware average function disabled."] _0, + #[doc = "Hardware average function enabled."] _1, } impl AVGEW { #[allow(missing_docs)] diff --git a/src/adc0/ug/mod.rs b/src/adc0/ug/mod.rs index 9a1f8b0..bec77dd 100644 --- a/src/adc0/ug/mod.rs +++ b/src/adc0/ug/mod.rs @@ -22,7 +22,9 @@ impl super::UG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/usr_ofs/mod.rs b/src/adc0/usr_ofs/mod.rs index d4207a3..873ee71 100644 --- a/src/adc0/usr_ofs/mod.rs +++ b/src/adc0/usr_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::USR_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/xofs/mod.rs b/src/adc0/xofs/mod.rs index ff8bd92..ec51697 100644 --- a/src/adc0/xofs/mod.rs +++ b/src/adc0/xofs/mod.rs @@ -22,7 +22,9 @@ impl super::XOFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc0/yofs/mod.rs b/src/adc0/yofs/mod.rs index a677692..81cbe07 100644 --- a/src/adc0/yofs/mod.rs +++ b/src/adc0/yofs/mod.rs @@ -22,7 +22,9 @@ impl super::YOFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/base_ofs/mod.rs b/src/adc1/base_ofs/mod.rs index f4f9616..9ab16c0 100644 --- a/src/adc1/base_ofs/mod.rs +++ b/src/adc1/base_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::BASE_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/cfg1/mod.rs b/src/adc1/cfg1/mod.rs index 10dd2e3..3b72ade 100644 --- a/src/adc1/cfg1/mod.rs +++ b/src/adc1/cfg1/mod.rs @@ -22,7 +22,9 @@ impl super::CFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CFG1 { #[doc = "Possible values of the field `ADICLK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADICLKR { - #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] - _00, - #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] - _01, - #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] - _10, - #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] - _11, + #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00, + #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01, + #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10, + #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11, } impl ADICLKR { #[doc = r" Value of the field as raw bits"] @@ -99,14 +97,10 @@ impl ADICLKR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "8-bit conversion."] - _00, - #[doc = "12-bit conversion."] - _01, - #[doc = "10-bit conversion."] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit conversion."] _00, + #[doc = "12-bit conversion."] _01, + #[doc = "10-bit conversion."] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -149,14 +143,10 @@ impl MODER { #[doc = "Possible values of the field `ADIV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADIVR { - #[doc = "The divide ratio is 1 and the clock rate is input clock."] - _00, - #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] - _01, - #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] - _10, - #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] - _11, + #[doc = "The divide ratio is 1 and the clock rate is input clock."] _00, + #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01, + #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10, + #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11, } impl ADIVR { #[doc = r" Value of the field as raw bits"] @@ -204,14 +194,10 @@ impl ADIVR { } #[doc = "Values that can be written to the field `ADICLK`"] pub enum ADICLKW { - #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] - _00, - #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] - _01, - #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] - _10, - #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] - _11, + #[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00, + #[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01, + #[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10, + #[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11, } impl ADICLKW { #[allow(missing_docs)] @@ -270,12 +256,9 @@ impl<'a> _ADICLKW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "8-bit conversion."] - _00, - #[doc = "12-bit conversion."] - _01, - #[doc = "10-bit conversion."] - _10, + #[doc = "8-bit conversion."] _00, + #[doc = "12-bit conversion."] _01, + #[doc = "10-bit conversion."] _10, } impl MODEW { #[allow(missing_docs)] @@ -326,14 +309,10 @@ impl<'a> _MODEW<'a> { } #[doc = "Values that can be written to the field `ADIV`"] pub enum ADIVW { - #[doc = "The divide ratio is 1 and the clock rate is input clock."] - _00, - #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] - _01, - #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] - _10, - #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] - _11, + #[doc = "The divide ratio is 1 and the clock rate is input clock."] _00, + #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01, + #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10, + #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11, } impl ADIVW { #[allow(missing_docs)] diff --git a/src/adc1/cfg2/mod.rs b/src/adc1/cfg2/mod.rs index 389c319..15edfa1 100644 --- a/src/adc1/cfg2/mod.rs +++ b/src/adc1/cfg2/mod.rs @@ -22,7 +22,9 @@ impl super::CFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp0/mod.rs b/src/adc1/clp0/mod.rs index d08eee2..e30d4c4 100644 --- a/src/adc1/clp0/mod.rs +++ b/src/adc1/clp0/mod.rs @@ -22,7 +22,9 @@ impl super::CLP0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp0_ofs/mod.rs b/src/adc1/clp0_ofs/mod.rs index dca8074..b40c708 100644 --- a/src/adc1/clp0_ofs/mod.rs +++ b/src/adc1/clp0_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP0_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp1/mod.rs b/src/adc1/clp1/mod.rs index 508ae61..275e48b 100644 --- a/src/adc1/clp1/mod.rs +++ b/src/adc1/clp1/mod.rs @@ -22,7 +22,9 @@ impl super::CLP1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp1_ofs/mod.rs b/src/adc1/clp1_ofs/mod.rs index 9cc7f69..d4ab5a9 100644 --- a/src/adc1/clp1_ofs/mod.rs +++ b/src/adc1/clp1_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP1_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp2/mod.rs b/src/adc1/clp2/mod.rs index cf3aac8..b2d9022 100644 --- a/src/adc1/clp2/mod.rs +++ b/src/adc1/clp2/mod.rs @@ -22,7 +22,9 @@ impl super::CLP2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp2_ofs/mod.rs b/src/adc1/clp2_ofs/mod.rs index 64e9cc5..5cbe400 100644 --- a/src/adc1/clp2_ofs/mod.rs +++ b/src/adc1/clp2_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP2_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp3/mod.rs b/src/adc1/clp3/mod.rs index 94bcdd5..abb9e3b 100644 --- a/src/adc1/clp3/mod.rs +++ b/src/adc1/clp3/mod.rs @@ -22,7 +22,9 @@ impl super::CLP3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp3_ofs/mod.rs b/src/adc1/clp3_ofs/mod.rs index ce00a7f..0e191ac 100644 --- a/src/adc1/clp3_ofs/mod.rs +++ b/src/adc1/clp3_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP3_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp9/mod.rs b/src/adc1/clp9/mod.rs index 2e5dc84..d0609fa 100644 --- a/src/adc1/clp9/mod.rs +++ b/src/adc1/clp9/mod.rs @@ -22,7 +22,9 @@ impl super::CLP9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clp9_ofs/mod.rs b/src/adc1/clp9_ofs/mod.rs index 58ee8a7..2a2b7c0 100644 --- a/src/adc1/clp9_ofs/mod.rs +++ b/src/adc1/clp9_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLP9_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clps/mod.rs b/src/adc1/clps/mod.rs index 9215e8e..b8c4c98 100644 --- a/src/adc1/clps/mod.rs +++ b/src/adc1/clps/mod.rs @@ -22,7 +22,9 @@ impl super::CLPS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clps_ofs/mod.rs b/src/adc1/clps_ofs/mod.rs index edc53e2..092789d 100644 --- a/src/adc1/clps_ofs/mod.rs +++ b/src/adc1/clps_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLPS_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clpx/mod.rs b/src/adc1/clpx/mod.rs index f4d2db3..dba2765 100644 --- a/src/adc1/clpx/mod.rs +++ b/src/adc1/clpx/mod.rs @@ -22,7 +22,9 @@ impl super::CLPX { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/clpx_ofs/mod.rs b/src/adc1/clpx_ofs/mod.rs index 79c0a5a..e284c5b 100644 --- a/src/adc1/clpx_ofs/mod.rs +++ b/src/adc1/clpx_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::CLPX_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/cv/mod.rs b/src/adc1/cv/mod.rs index aaa4874..a789581 100644 --- a/src/adc1/cv/mod.rs +++ b/src/adc1/cv/mod.rs @@ -22,7 +22,9 @@ impl super::CV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/g/mod.rs b/src/adc1/g/mod.rs index 3a952e9..bfd0ba1 100644 --- a/src/adc1/g/mod.rs +++ b/src/adc1/g/mod.rs @@ -22,7 +22,9 @@ impl super::G { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/mod.rs b/src/adc1/mod.rs index 6d25066..5a8a710 100644 --- a/src/adc1/mod.rs +++ b/src/adc1/mod.rs @@ -2,124 +2,77 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - ADC Status and Control Register 1"] - pub sc1a: SC1, - #[doc = "0x04 - ADC Status and Control Register 1"] - pub sc1b: SC1, - #[doc = "0x08 - ADC Status and Control Register 1"] - pub sc1c: SC1, - #[doc = "0x0c - ADC Status and Control Register 1"] - pub sc1d: SC1, - #[doc = "0x10 - ADC Status and Control Register 1"] - pub sc1e: SC1, - #[doc = "0x14 - ADC Status and Control Register 1"] - pub sc1f: SC1, - #[doc = "0x18 - ADC Status and Control Register 1"] - pub sc1g: SC1, - #[doc = "0x1c - ADC Status and Control Register 1"] - pub sc1h: SC1, - #[doc = "0x20 - ADC Status and Control Register 1"] - pub sc1i: SC1, - #[doc = "0x24 - ADC Status and Control Register 1"] - pub sc1j: SC1, - #[doc = "0x28 - ADC Status and Control Register 1"] - pub sc1k: SC1, - #[doc = "0x2c - ADC Status and Control Register 1"] - pub sc1l: SC1, - #[doc = "0x30 - ADC Status and Control Register 1"] - pub sc1m: SC1, - #[doc = "0x34 - ADC Status and Control Register 1"] - pub sc1n: SC1, - #[doc = "0x38 - ADC Status and Control Register 1"] - pub sc1o: SC1, - #[doc = "0x3c - ADC Status and Control Register 1"] - pub sc1p: SC1, - #[doc = "0x40 - ADC Configuration Register 1"] - pub cfg1: CFG1, - #[doc = "0x44 - ADC Configuration Register 2"] - pub cfg2: CFG2, - #[doc = "0x48 - ADC Data Result Registers"] - pub ra: R, - #[doc = "0x4c - ADC Data Result Registers"] - pub rb: R, - #[doc = "0x50 - ADC Data Result Registers"] - pub rc: R, - #[doc = "0x54 - ADC Data Result Registers"] - pub rd: R, - #[doc = "0x58 - ADC Data Result Registers"] - pub re: R, - #[doc = "0x5c - ADC Data Result Registers"] - pub rf: R, - #[doc = "0x60 - ADC Data Result Registers"] - pub rg: R, - #[doc = "0x64 - ADC Data Result Registers"] - pub rh: R, - #[doc = "0x68 - ADC Data Result Registers"] - pub ri: R, - #[doc = "0x6c - ADC Data Result Registers"] - pub rj: R, - #[doc = "0x70 - ADC Data Result Registers"] - pub rk: R, - #[doc = "0x74 - ADC Data Result Registers"] - pub rl: R, - #[doc = "0x78 - ADC Data Result Registers"] - pub rm: R, - #[doc = "0x7c - ADC Data Result Registers"] - pub rn: R, - #[doc = "0x80 - ADC Data Result Registers"] - pub ro: R, - #[doc = "0x84 - ADC Data Result Registers"] - pub rp: R, - #[doc = "0x88 - Compare Value Registers"] - pub cv1: CV, - #[doc = "0x8c - Compare Value Registers"] - pub cv2: CV, - #[doc = "0x90 - Status and Control Register 2"] - pub sc2: SC2, - #[doc = "0x94 - Status and Control Register 3"] - pub sc3: SC3, - #[doc = "0x98 - BASE Offset Register"] - pub base_ofs: BASE_OFS, - #[doc = "0x9c - ADC Offset Correction Register"] - pub ofs: OFS, - #[doc = "0xa0 - USER Offset Correction Register"] - pub usr_ofs: USR_OFS, - #[doc = "0xa4 - ADC X Offset Correction Register"] - pub xofs: XOFS, - #[doc = "0xa8 - ADC Y Offset Correction Register"] - pub yofs: YOFS, - #[doc = "0xac - ADC Gain Register"] - pub g: G, - #[doc = "0xb0 - ADC User Gain Register"] - pub ug: UG, - #[doc = "0xb4 - ADC General Calibration Value Register S"] - pub clps: CLPS, - #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] - pub clp3: CLP3, - #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] - pub clp2: CLP2, - #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] - pub clp1: CLP1, - #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] - pub clp0: CLP0, - #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] - pub clpx: CLPX, - #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] - pub clp9: CLP9, - #[doc = "0xd0 - ADC General Calibration Offset Value Register S"] - pub clps_ofs: CLPS_OFS, + #[doc = "0x00 - ADC Status and Control Register 1"] pub sc1a: SC1, + #[doc = "0x04 - ADC Status and Control Register 1"] pub sc1b: SC1, + #[doc = "0x08 - ADC Status and Control Register 1"] pub sc1c: SC1, + #[doc = "0x0c - ADC Status and Control Register 1"] pub sc1d: SC1, + #[doc = "0x10 - ADC Status and Control Register 1"] pub sc1e: SC1, + #[doc = "0x14 - ADC Status and Control Register 1"] pub sc1f: SC1, + #[doc = "0x18 - ADC Status and Control Register 1"] pub sc1g: SC1, + #[doc = "0x1c - ADC Status and Control Register 1"] pub sc1h: SC1, + #[doc = "0x20 - ADC Status and Control Register 1"] pub sc1i: SC1, + #[doc = "0x24 - ADC Status and Control Register 1"] pub sc1j: SC1, + #[doc = "0x28 - ADC Status and Control Register 1"] pub sc1k: SC1, + #[doc = "0x2c - ADC Status and Control Register 1"] pub sc1l: SC1, + #[doc = "0x30 - ADC Status and Control Register 1"] pub sc1m: SC1, + #[doc = "0x34 - ADC Status and Control Register 1"] pub sc1n: SC1, + #[doc = "0x38 - ADC Status and Control Register 1"] pub sc1o: SC1, + #[doc = "0x3c - ADC Status and Control Register 1"] pub sc1p: SC1, + #[doc = "0x40 - ADC Configuration Register 1"] pub cfg1: CFG1, + #[doc = "0x44 - ADC Configuration Register 2"] pub cfg2: CFG2, + #[doc = "0x48 - ADC Data Result Registers"] pub ra: R, + #[doc = "0x4c - ADC Data Result Registers"] pub rb: R, + #[doc = "0x50 - ADC Data Result Registers"] pub rc: R, + #[doc = "0x54 - ADC Data Result Registers"] pub rd: R, + #[doc = "0x58 - ADC Data Result Registers"] pub re: R, + #[doc = "0x5c - ADC Data Result Registers"] pub rf: R, + #[doc = "0x60 - ADC Data Result Registers"] pub rg: R, + #[doc = "0x64 - ADC Data Result Registers"] pub rh: R, + #[doc = "0x68 - ADC Data Result Registers"] pub ri: R, + #[doc = "0x6c - ADC Data Result Registers"] pub rj: R, + #[doc = "0x70 - ADC Data Result Registers"] pub rk: R, + #[doc = "0x74 - ADC Data Result Registers"] pub rl: R, + #[doc = "0x78 - ADC Data Result Registers"] pub rm: R, + #[doc = "0x7c - ADC Data Result Registers"] pub rn: R, + #[doc = "0x80 - ADC Data Result Registers"] pub ro: R, + #[doc = "0x84 - ADC Data Result Registers"] pub rp: R, + #[doc = "0x88 - Compare Value Registers"] pub cv1: CV, + #[doc = "0x8c - Compare Value Registers"] pub cv2: CV, + #[doc = "0x90 - Status and Control Register 2"] pub sc2: SC2, + #[doc = "0x94 - Status and Control Register 3"] pub sc3: SC3, + #[doc = "0x98 - BASE Offset Register"] pub base_ofs: BASE_OFS, + #[doc = "0x9c - ADC Offset Correction Register"] pub ofs: OFS, + #[doc = "0xa0 - USER Offset Correction Register"] pub usr_ofs: USR_OFS, + #[doc = "0xa4 - ADC X Offset Correction Register"] pub xofs: XOFS, + #[doc = "0xa8 - ADC Y Offset Correction Register"] pub yofs: YOFS, + #[doc = "0xac - ADC Gain Register"] pub g: G, + #[doc = "0xb0 - ADC User Gain Register"] pub ug: UG, + #[doc = "0xb4 - ADC General Calibration Value Register S"] pub clps: CLPS, + #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] pub clp3: CLP3, + #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] pub clp2: CLP2, + #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] pub clp1: CLP1, + #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] pub clp0: CLP0, + #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] pub clpx: CLPX, + #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] pub clp9: CLP9, + #[doc = "0xd0 - ADC General Calibration Offset Value Register S"] pub clps_ofs: CLPS_OFS, #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"] - pub clp3_ofs: CLP3_OFS, + pub clp3_ofs: + CLP3_OFS, #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"] - pub clp2_ofs: CLP2_OFS, + pub clp2_ofs: + CLP2_OFS, #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"] - pub clp1_ofs: CLP1_OFS, + pub clp1_ofs: + CLP1_OFS, #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"] - pub clp0_ofs: CLP0_OFS, + pub clp0_ofs: + CLP0_OFS, #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"] - pub clpx_ofs: CLPX_OFS, + pub clpx_ofs: + CLPX_OFS, #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"] - pub clp9_ofs: CLP9_OFS, + pub clp9_ofs: + CLP9_OFS, } #[doc = "ADC Status and Control Register 1"] pub struct SC1 { diff --git a/src/adc1/ofs/mod.rs b/src/adc1/ofs/mod.rs index 744994d..e2f1050 100644 --- a/src/adc1/ofs/mod.rs +++ b/src/adc1/ofs/mod.rs @@ -22,7 +22,9 @@ impl super::OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/r/mod.rs b/src/adc1/r/mod.rs index ce24e1b..1d20cd6 100644 --- a/src/adc1/r/mod.rs +++ b/src/adc1/r/mod.rs @@ -6,7 +6,9 @@ impl super::R { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/adc1/sc1/mod.rs b/src/adc1/sc1/mod.rs index 6490b4b..4043f66 100644 --- a/src/adc1/sc1/mod.rs +++ b/src/adc1/sc1/mod.rs @@ -22,7 +22,9 @@ impl super::SC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,62 +45,36 @@ impl super::SC1 { #[doc = "Possible values of the field `ADCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADCHR { - #[doc = "Exernal channel 0 is selected as input."] - _00000, - #[doc = "Exernal channel 1 is selected as input."] - _00001, - #[doc = "Exernal channel 2 is selected as input."] - _00010, - #[doc = "Exernal channel 3 is selected as input."] - _00011, - #[doc = "Exernal channel 4 is selected as input."] - _00100, - #[doc = "Exernal channel 5 is selected as input."] - _00101, - #[doc = "Exernal channel 6 is selected as input."] - _00110, - #[doc = "Exernal channel 7 is selected as input."] - _00111, - #[doc = "Exernal channel 8 is selected as input."] - _01000, - #[doc = "Exernal channel 9 is selected as input."] - _01001, - #[doc = "Exernal channel 10 is selected as input."] - _01010, - #[doc = "Exernal channel 11 is selected as input."] - _01011, - #[doc = "Exernal channel 12 is selected as input."] - _01100, - #[doc = "Exernal channel 13 is selected as input."] - _01101, - #[doc = "Exernal channel 14 is selected as input."] - _01110, - #[doc = "Exernal channel 15 is selected as input."] - _01111, - #[doc = "Exernal channel 18 is selected as input."] - _10010, - #[doc = "Exernal channel 19 is selected as input."] - _10011, - #[doc = "Internal channel 0 is selected as input."] - _10101, - #[doc = "Internal channel 1 is selected as input."] - _10110, - #[doc = "Internal channel 2 is selected as input."] - _10111, - #[doc = "Temp Sensor"] - _11010, - #[doc = "Band Gap"] - _11011, - #[doc = "Internal channel 3 is selected as input."] - _11100, + #[doc = "Exernal channel 0 is selected as input."] _00000, + #[doc = "Exernal channel 1 is selected as input."] _00001, + #[doc = "Exernal channel 2 is selected as input."] _00010, + #[doc = "Exernal channel 3 is selected as input."] _00011, + #[doc = "Exernal channel 4 is selected as input."] _00100, + #[doc = "Exernal channel 5 is selected as input."] _00101, + #[doc = "Exernal channel 6 is selected as input."] _00110, + #[doc = "Exernal channel 7 is selected as input."] _00111, + #[doc = "Exernal channel 8 is selected as input."] _01000, + #[doc = "Exernal channel 9 is selected as input."] _01001, + #[doc = "Exernal channel 10 is selected as input."] _01010, + #[doc = "Exernal channel 11 is selected as input."] _01011, + #[doc = "Exernal channel 12 is selected as input."] _01100, + #[doc = "Exernal channel 13 is selected as input."] _01101, + #[doc = "Exernal channel 14 is selected as input."] _01110, + #[doc = "Exernal channel 15 is selected as input."] _01111, + #[doc = "Exernal channel 18 is selected as input."] _10010, + #[doc = "Exernal channel 19 is selected as input."] _10011, + #[doc = "Internal channel 0 is selected as input."] _10101, + #[doc = "Internal channel 1 is selected as input."] _10110, + #[doc = "Internal channel 2 is selected as input."] _10111, + #[doc = "Temp Sensor"] _11010, + #[doc = "Band Gap"] _11011, + #[doc = "Internal channel 3 is selected as input."] _11100, #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11101, #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11110, - #[doc = "Module is disabled"] - _11111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Module is disabled"] _11111, + #[doc = r" Reserved"] _Reserved(u8), } impl ADCHR { #[doc = r" Value of the field as raw bits"] @@ -309,10 +285,8 @@ impl ADCHR { #[doc = "Possible values of the field `AIEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AIENR { - #[doc = "Conversion complete interrupt is disabled."] - _0, - #[doc = "Conversion complete interrupt is enabled."] - _1, + #[doc = "Conversion complete interrupt is disabled."] _0, + #[doc = "Conversion complete interrupt is enabled."] _1, } impl AIENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -356,10 +330,8 @@ impl AIENR { #[doc = "Possible values of the field `COCO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COCOR { - #[doc = "Conversion is not completed."] - _0, - #[doc = "Conversion is completed."] - _1, + #[doc = "Conversion is not completed."] _0, + #[doc = "Conversion is completed."] _1, } impl COCOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -402,60 +374,35 @@ impl COCOR { } #[doc = "Values that can be written to the field `ADCH`"] pub enum ADCHW { - #[doc = "Exernal channel 0 is selected as input."] - _00000, - #[doc = "Exernal channel 1 is selected as input."] - _00001, - #[doc = "Exernal channel 2 is selected as input."] - _00010, - #[doc = "Exernal channel 3 is selected as input."] - _00011, - #[doc = "Exernal channel 4 is selected as input."] - _00100, - #[doc = "Exernal channel 5 is selected as input."] - _00101, - #[doc = "Exernal channel 6 is selected as input."] - _00110, - #[doc = "Exernal channel 7 is selected as input."] - _00111, - #[doc = "Exernal channel 8 is selected as input."] - _01000, - #[doc = "Exernal channel 9 is selected as input."] - _01001, - #[doc = "Exernal channel 10 is selected as input."] - _01010, - #[doc = "Exernal channel 11 is selected as input."] - _01011, - #[doc = "Exernal channel 12 is selected as input."] - _01100, - #[doc = "Exernal channel 13 is selected as input."] - _01101, - #[doc = "Exernal channel 14 is selected as input."] - _01110, - #[doc = "Exernal channel 15 is selected as input."] - _01111, - #[doc = "Exernal channel 18 is selected as input."] - _10010, - #[doc = "Exernal channel 19 is selected as input."] - _10011, - #[doc = "Internal channel 0 is selected as input."] - _10101, - #[doc = "Internal channel 1 is selected as input."] - _10110, - #[doc = "Internal channel 2 is selected as input."] - _10111, - #[doc = "Temp Sensor"] - _11010, - #[doc = "Band Gap"] - _11011, - #[doc = "Internal channel 3 is selected as input."] - _11100, + #[doc = "Exernal channel 0 is selected as input."] _00000, + #[doc = "Exernal channel 1 is selected as input."] _00001, + #[doc = "Exernal channel 2 is selected as input."] _00010, + #[doc = "Exernal channel 3 is selected as input."] _00011, + #[doc = "Exernal channel 4 is selected as input."] _00100, + #[doc = "Exernal channel 5 is selected as input."] _00101, + #[doc = "Exernal channel 6 is selected as input."] _00110, + #[doc = "Exernal channel 7 is selected as input."] _00111, + #[doc = "Exernal channel 8 is selected as input."] _01000, + #[doc = "Exernal channel 9 is selected as input."] _01001, + #[doc = "Exernal channel 10 is selected as input."] _01010, + #[doc = "Exernal channel 11 is selected as input."] _01011, + #[doc = "Exernal channel 12 is selected as input."] _01100, + #[doc = "Exernal channel 13 is selected as input."] _01101, + #[doc = "Exernal channel 14 is selected as input."] _01110, + #[doc = "Exernal channel 15 is selected as input."] _01111, + #[doc = "Exernal channel 18 is selected as input."] _10010, + #[doc = "Exernal channel 19 is selected as input."] _10011, + #[doc = "Internal channel 0 is selected as input."] _10101, + #[doc = "Internal channel 1 is selected as input."] _10110, + #[doc = "Internal channel 2 is selected as input."] _10111, + #[doc = "Temp Sensor"] _11010, + #[doc = "Band Gap"] _11011, + #[doc = "Internal channel 3 is selected as input."] _11100, #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11101, #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."] _11110, - #[doc = "Module is disabled"] - _11111, + #[doc = "Module is disabled"] _11111, } impl ADCHW { #[allow(missing_docs)] @@ -650,10 +597,8 @@ impl<'a> _ADCHW<'a> { } #[doc = "Values that can be written to the field `AIEN`"] pub enum AIENW { - #[doc = "Conversion complete interrupt is disabled."] - _0, - #[doc = "Conversion complete interrupt is enabled."] - _1, + #[doc = "Conversion complete interrupt is disabled."] _0, + #[doc = "Conversion complete interrupt is enabled."] _1, } impl AIENW { #[allow(missing_docs)] diff --git a/src/adc1/sc2/mod.rs b/src/adc1/sc2/mod.rs index d5648f5..93c5601 100644 --- a/src/adc1/sc2/mod.rs +++ b/src/adc1/sc2/mod.rs @@ -22,7 +22,9 @@ impl super::SC2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::SC2 { #[doc = "Possible values of the field `REFSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REFSELR { - #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] - _00, + #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00, #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."] _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl REFSELR { #[doc = r" Value of the field as raw bits"] @@ -84,8 +84,7 @@ impl REFSELR { #[doc = "Possible values of the field `DMAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAENR { - #[doc = "DMA is disabled."] - _0, + #[doc = "DMA is disabled."] _0, #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."] _1, } @@ -173,10 +172,8 @@ impl ACFGTR { #[doc = "Possible values of the field `ACFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACFER { - #[doc = "Compare function disabled."] - _0, - #[doc = "Compare function enabled."] - _1, + #[doc = "Compare function disabled."] _0, + #[doc = "Compare function enabled."] _1, } impl ACFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -220,10 +217,8 @@ impl ACFER { #[doc = "Possible values of the field `ADTRG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADTRGR { - #[doc = "Software trigger selected."] - _0, - #[doc = "Hardware trigger selected."] - _1, + #[doc = "Software trigger selected."] _0, + #[doc = "Hardware trigger selected."] _1, } impl ADTRGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +262,8 @@ impl ADTRGR { #[doc = "Possible values of the field `ADACT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADACTR { - #[doc = "Conversion not in progress."] - _0, - #[doc = "Conversion in progress."] - _1, + #[doc = "Conversion not in progress."] _0, + #[doc = "Conversion in progress."] _1, } impl ADACTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,12 +318,9 @@ impl TRGPRNUMR { #[doc = "Possible values of the field `TRGSTLAT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSTLATR { - #[doc = "No trigger request has been latched"] - _0, - #[doc = "A trigger request has been latched"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No trigger request has been latched"] _0, + #[doc = "A trigger request has been latched"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl TRGSTLATR { #[doc = r" Value of the field as raw bits"] @@ -366,12 +356,9 @@ impl TRGSTLATR { #[doc = "Possible values of the field `TRGSTERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSTERRR { - #[doc = "No error has occurred"] - _0, - #[doc = "An error has occurred"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No error has occurred"] _0, + #[doc = "An error has occurred"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl TRGSTERRR { #[doc = r" Value of the field as raw bits"] @@ -406,8 +393,7 @@ impl TRGSTERRR { } #[doc = "Values that can be written to the field `REFSEL`"] pub enum REFSELW { - #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] - _00, + #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00, #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."] _01, } @@ -454,8 +440,7 @@ impl<'a> _REFSELW<'a> { } #[doc = "Values that can be written to the field `DMAEN`"] pub enum DMAENW { - #[doc = "DMA is disabled."] - _0, + #[doc = "DMA is disabled."] _0, #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."] _1, } @@ -558,10 +543,8 @@ impl<'a> _ACFGTW<'a> { } #[doc = "Values that can be written to the field `ACFE`"] pub enum ACFEW { - #[doc = "Compare function disabled."] - _0, - #[doc = "Compare function enabled."] - _1, + #[doc = "Compare function disabled."] _0, + #[doc = "Compare function enabled."] _1, } impl ACFEW { #[allow(missing_docs)] @@ -616,10 +599,8 @@ impl<'a> _ACFEW<'a> { } #[doc = "Values that can be written to the field `ADTRG`"] pub enum ADTRGW { - #[doc = "Software trigger selected."] - _0, - #[doc = "Hardware trigger selected."] - _1, + #[doc = "Software trigger selected."] _0, + #[doc = "Hardware trigger selected."] _1, } impl ADTRGW { #[allow(missing_docs)] diff --git a/src/adc1/sc3/mod.rs b/src/adc1/sc3/mod.rs index deca775..7e4cf08 100644 --- a/src/adc1/sc3/mod.rs +++ b/src/adc1/sc3/mod.rs @@ -22,7 +22,9 @@ impl super::SC3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::SC3 { #[doc = "Possible values of the field `AVGS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVGSR { - #[doc = "4 samples averaged."] - _00, - #[doc = "8 samples averaged."] - _01, - #[doc = "16 samples averaged."] - _10, - #[doc = "32 samples averaged."] - _11, + #[doc = "4 samples averaged."] _00, + #[doc = "8 samples averaged."] _01, + #[doc = "16 samples averaged."] _10, + #[doc = "32 samples averaged."] _11, } impl AVGSR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl AVGSR { #[doc = "Possible values of the field `AVGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVGER { - #[doc = "Hardware average function disabled."] - _0, - #[doc = "Hardware average function enabled."] - _1, + #[doc = "Hardware average function disabled."] _0, + #[doc = "Hardware average function enabled."] _1, } impl AVGER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -213,14 +209,10 @@ impl CALR { } #[doc = "Values that can be written to the field `AVGS`"] pub enum AVGSW { - #[doc = "4 samples averaged."] - _00, - #[doc = "8 samples averaged."] - _01, - #[doc = "16 samples averaged."] - _10, - #[doc = "32 samples averaged."] - _11, + #[doc = "4 samples averaged."] _00, + #[doc = "8 samples averaged."] _01, + #[doc = "16 samples averaged."] _10, + #[doc = "32 samples averaged."] _11, } impl AVGSW { #[allow(missing_docs)] @@ -279,10 +271,8 @@ impl<'a> _AVGSW<'a> { } #[doc = "Values that can be written to the field `AVGE`"] pub enum AVGEW { - #[doc = "Hardware average function disabled."] - _0, - #[doc = "Hardware average function enabled."] - _1, + #[doc = "Hardware average function disabled."] _0, + #[doc = "Hardware average function enabled."] _1, } impl AVGEW { #[allow(missing_docs)] diff --git a/src/adc1/ug/mod.rs b/src/adc1/ug/mod.rs index 9a1f8b0..bec77dd 100644 --- a/src/adc1/ug/mod.rs +++ b/src/adc1/ug/mod.rs @@ -22,7 +22,9 @@ impl super::UG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/usr_ofs/mod.rs b/src/adc1/usr_ofs/mod.rs index d4207a3..873ee71 100644 --- a/src/adc1/usr_ofs/mod.rs +++ b/src/adc1/usr_ofs/mod.rs @@ -22,7 +22,9 @@ impl super::USR_OFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/xofs/mod.rs b/src/adc1/xofs/mod.rs index ff8bd92..ec51697 100644 --- a/src/adc1/xofs/mod.rs +++ b/src/adc1/xofs/mod.rs @@ -22,7 +22,9 @@ impl super::XOFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/adc1/yofs/mod.rs b/src/adc1/yofs/mod.rs index a677692..81cbe07 100644 --- a/src/adc1/yofs/mod.rs +++ b/src/adc1/yofs/mod.rs @@ -22,7 +22,9 @@ impl super::YOFS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/aips/mod.rs b/src/aips/mod.rs index da1d72f..f409d3f 100644 --- a/src/aips/mod.rs +++ b/src/aips/mod.rs @@ -2,42 +2,25 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Master Privilege Register A"] - pub mpra: MPRA, + #[doc = "0x00 - Master Privilege Register A"] pub mpra: MPRA, _reserved0: [u8; 28usize], - #[doc = "0x20 - Peripheral Access Control Register"] - pub pacra: PACRA, - #[doc = "0x24 - Peripheral Access Control Register"] - pub pacrb: PACRB, - #[doc = "0x28 - Peripheral Access Control Register"] - pub pacrc: PACRC, - #[doc = "0x2c - Peripheral Access Control Register"] - pub pacrd: PACRD, + #[doc = "0x20 - Peripheral Access Control Register"] pub pacra: PACRA, + #[doc = "0x24 - Peripheral Access Control Register"] pub pacrb: PACRB, + #[doc = "0x28 - Peripheral Access Control Register"] pub pacrc: PACRC, + #[doc = "0x2c - Peripheral Access Control Register"] pub pacrd: PACRD, _reserved1: [u8; 16usize], - #[doc = "0x40 - Off-Platform Peripheral Access Control Register"] - pub opacra: OPACRA, - #[doc = "0x44 - Off-Platform Peripheral Access Control Register"] - pub opacrb: OPACRB, - #[doc = "0x48 - Off-Platform Peripheral Access Control Register"] - pub opacrc: OPACRC, - #[doc = "0x4c - Off-Platform Peripheral Access Control Register"] - pub opacrd: OPACRD, - #[doc = "0x50 - Off-Platform Peripheral Access Control Register"] - pub opacre: OPACRE, - #[doc = "0x54 - Off-Platform Peripheral Access Control Register"] - pub opacrf: OPACRF, - #[doc = "0x58 - Off-Platform Peripheral Access Control Register"] - pub opacrg: OPACRG, - #[doc = "0x5c - Off-Platform Peripheral Access Control Register"] - pub opacrh: OPACRH, - #[doc = "0x60 - Off-Platform Peripheral Access Control Register"] - pub opacri: OPACRI, - #[doc = "0x64 - Off-Platform Peripheral Access Control Register"] - pub opacrj: OPACRJ, - #[doc = "0x68 - Off-Platform Peripheral Access Control Register"] - pub opacrk: OPACRK, - #[doc = "0x6c - Off-Platform Peripheral Access Control Register"] - pub opacrl: OPACRL, + #[doc = "0x40 - Off-Platform Peripheral Access Control Register"] pub opacra: OPACRA, + #[doc = "0x44 - Off-Platform Peripheral Access Control Register"] pub opacrb: OPACRB, + #[doc = "0x48 - Off-Platform Peripheral Access Control Register"] pub opacrc: OPACRC, + #[doc = "0x4c - Off-Platform Peripheral Access Control Register"] pub opacrd: OPACRD, + #[doc = "0x50 - Off-Platform Peripheral Access Control Register"] pub opacre: OPACRE, + #[doc = "0x54 - Off-Platform Peripheral Access Control Register"] pub opacrf: OPACRF, + #[doc = "0x58 - Off-Platform Peripheral Access Control Register"] pub opacrg: OPACRG, + #[doc = "0x5c - Off-Platform Peripheral Access Control Register"] pub opacrh: OPACRH, + #[doc = "0x60 - Off-Platform Peripheral Access Control Register"] pub opacri: OPACRI, + #[doc = "0x64 - Off-Platform Peripheral Access Control Register"] pub opacrj: OPACRJ, + #[doc = "0x68 - Off-Platform Peripheral Access Control Register"] pub opacrk: OPACRK, + #[doc = "0x6c - Off-Platform Peripheral Access Control Register"] pub opacrl: OPACRL, } #[doc = "Master Privilege Register A"] pub struct MPRA { diff --git a/src/aips/mpra/mod.rs b/src/aips/mpra/mod.rs index 479910c..6e409ce 100644 --- a/src/aips/mpra/mod.rs +++ b/src/aips/mpra/mod.rs @@ -22,7 +22,9 @@ impl super::MPRA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MPRA { #[doc = "Possible values of the field `MPL2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MPL2R { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MPL2R { #[doc = "Possible values of the field `MTW2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTW2R { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl MTW2R { #[doc = "Possible values of the field `MTR2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR2R { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl MTR2R { #[doc = "Possible values of the field `MPL1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MPL1R { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl MPL1R { #[doc = "Possible values of the field `MTW1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTW1R { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl MTW1R { #[doc = "Possible values of the field `MTR1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR1R { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl MTR1R { #[doc = "Possible values of the field `MPL0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MPL0R { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl MPL0R { #[doc = "Possible values of the field `MTW0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTW0R { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl MTW0R { #[doc = "Possible values of the field `MTR0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR0R { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl MTR0R { } #[doc = "Values that can be written to the field `MPL2`"] pub enum MPL2W { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL2W { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _MPL2W<'a> { } #[doc = "Values that can be written to the field `MTW2`"] pub enum MTW2W { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW2W { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _MTW2W<'a> { } #[doc = "Values that can be written to the field `MTR2`"] pub enum MTR2W { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR2W { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _MTR2W<'a> { } #[doc = "Values that can be written to the field `MPL1`"] pub enum MPL1W { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL1W { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _MPL1W<'a> { } #[doc = "Values that can be written to the field `MTW1`"] pub enum MTW1W { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW1W { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _MTW1W<'a> { } #[doc = "Values that can be written to the field `MTR1`"] pub enum MTR1W { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR1W { #[allow(missing_docs)] @@ -813,10 +785,8 @@ impl<'a> _MTR1W<'a> { } #[doc = "Values that can be written to the field `MPL0`"] pub enum MPL0W { - #[doc = "Accesses from this master are forced to user-mode."] - _0, - #[doc = "Accesses from this master are not forced to user-mode."] - _1, + #[doc = "Accesses from this master are forced to user-mode."] _0, + #[doc = "Accesses from this master are not forced to user-mode."] _1, } impl MPL0W { #[allow(missing_docs)] @@ -871,10 +841,8 @@ impl<'a> _MPL0W<'a> { } #[doc = "Values that can be written to the field `MTW0`"] pub enum MTW0W { - #[doc = "This master is not trusted for write accesses."] - _0, - #[doc = "This master is trusted for write accesses."] - _1, + #[doc = "This master is not trusted for write accesses."] _0, + #[doc = "This master is trusted for write accesses."] _1, } impl MTW0W { #[allow(missing_docs)] @@ -929,10 +897,8 @@ impl<'a> _MTW0W<'a> { } #[doc = "Values that can be written to the field `MTR0`"] pub enum MTR0W { - #[doc = "This master is not trusted for read accesses."] - _0, - #[doc = "This master is trusted for read accesses."] - _1, + #[doc = "This master is not trusted for read accesses."] _0, + #[doc = "This master is trusted for read accesses."] _1, } impl MTR0W { #[allow(missing_docs)] diff --git a/src/aips/opacra/mod.rs b/src/aips/opacra/mod.rs index 18a4f0e..b84b5fa 100644 --- a/src/aips/opacra/mod.rs +++ b/src/aips/opacra/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRA { #[doc = "Possible values of the field `TP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP7R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP7R { #[doc = "Possible values of the field `WP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP7R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP7R { #[doc = "Possible values of the field `SP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP7R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP7R { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP6R { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP5R { #[doc = "Possible values of the field `TP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP4R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP4R { #[doc = "Possible values of the field `WP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP4R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP4R { #[doc = "Possible values of the field `SP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP4R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl SP4R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -795,10 +765,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -842,10 +810,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -888,10 +854,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP7`"] pub enum TP7W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7W { #[allow(missing_docs)] @@ -946,10 +910,8 @@ impl<'a> _TP7W<'a> { } #[doc = "Values that can be written to the field `WP7`"] pub enum WP7W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7W { #[allow(missing_docs)] @@ -1004,10 +966,8 @@ impl<'a> _WP7W<'a> { } #[doc = "Values that can be written to the field `SP7`"] pub enum SP7W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7W { #[allow(missing_docs)] @@ -1062,10 +1022,8 @@ impl<'a> _SP7W<'a> { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -1120,10 +1078,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -1178,10 +1134,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -1236,10 +1190,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -1294,10 +1246,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -1352,10 +1302,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -1410,10 +1358,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP4`"] pub enum TP4W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4W { #[allow(missing_docs)] @@ -1468,10 +1414,8 @@ impl<'a> _TP4W<'a> { } #[doc = "Values that can be written to the field `WP4`"] pub enum WP4W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4W { #[allow(missing_docs)] @@ -1526,10 +1470,8 @@ impl<'a> _WP4W<'a> { } #[doc = "Values that can be written to the field `SP4`"] pub enum SP4W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4W { #[allow(missing_docs)] @@ -1584,10 +1526,8 @@ impl<'a> _SP4W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -1642,10 +1582,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -1700,10 +1638,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -1758,10 +1694,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -1816,10 +1750,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -1874,10 +1806,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/opacrb/mod.rs b/src/aips/opacrb/mod.rs index a2cbcb4..519f451 100644 --- a/src/aips/opacrb/mod.rs +++ b/src/aips/opacrb/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRB { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRB { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP6R { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP5R { #[doc = "Possible values of the field `TP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP4R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP4R { #[doc = "Possible values of the field `WP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP4R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP4R { #[doc = "Possible values of the field `SP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP4R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP4R { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -606,10 +584,8 @@ impl SP3R { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -664,10 +640,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -722,10 +696,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -780,10 +752,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -838,10 +808,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -896,10 +864,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -954,10 +920,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP4`"] pub enum TP4W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4W { #[allow(missing_docs)] @@ -1012,10 +976,8 @@ impl<'a> _TP4W<'a> { } #[doc = "Values that can be written to the field `WP4`"] pub enum WP4W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4W { #[allow(missing_docs)] @@ -1070,10 +1032,8 @@ impl<'a> _WP4W<'a> { } #[doc = "Values that can be written to the field `SP4`"] pub enum SP4W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4W { #[allow(missing_docs)] @@ -1128,10 +1088,8 @@ impl<'a> _SP4W<'a> { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -1186,10 +1144,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -1244,10 +1200,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] diff --git a/src/aips/opacrc/mod.rs b/src/aips/opacrc/mod.rs index bbeb803..7e54d8e 100644 --- a/src/aips/opacrc/mod.rs +++ b/src/aips/opacrc/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRC { #[doc = "Possible values of the field `TP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP7R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP7R { #[doc = "Possible values of the field `WP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP7R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP7R { #[doc = "Possible values of the field `SP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP7R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP7R { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP6R { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP2R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -606,10 +584,8 @@ impl SP1R { } #[doc = "Values that can be written to the field `TP7`"] pub enum TP7W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7W { #[allow(missing_docs)] @@ -664,10 +640,8 @@ impl<'a> _TP7W<'a> { } #[doc = "Values that can be written to the field `WP7`"] pub enum WP7W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7W { #[allow(missing_docs)] @@ -722,10 +696,8 @@ impl<'a> _WP7W<'a> { } #[doc = "Values that can be written to the field `SP7`"] pub enum SP7W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7W { #[allow(missing_docs)] @@ -780,10 +752,8 @@ impl<'a> _SP7W<'a> { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -838,10 +808,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -896,10 +864,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -954,10 +920,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -1012,10 +976,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -1070,10 +1032,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] @@ -1128,10 +1088,8 @@ impl<'a> _SP2W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -1186,10 +1144,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -1244,10 +1200,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] diff --git a/src/aips/opacrd/mod.rs b/src/aips/opacrd/mod.rs index a819c2d..e2bfeba 100644 --- a/src/aips/opacrd/mod.rs +++ b/src/aips/opacrd/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRD { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP5R { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP3R { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP2R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -747,10 +719,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -805,10 +775,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -863,10 +831,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -921,10 +887,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -979,10 +943,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -1037,10 +999,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] @@ -1095,10 +1055,8 @@ impl<'a> _SP3W<'a> { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -1153,10 +1111,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -1211,10 +1167,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] @@ -1269,10 +1223,8 @@ impl<'a> _SP2W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -1327,10 +1279,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -1385,10 +1335,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -1443,10 +1391,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -1501,10 +1447,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -1559,10 +1503,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/opacre/mod.rs b/src/aips/opacre/mod.rs index 06bd701..38e27f0 100644 --- a/src/aips/opacre/mod.rs +++ b/src/aips/opacre/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRE { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP6R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -324,10 +314,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -382,10 +370,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -440,10 +426,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -498,10 +482,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -556,10 +538,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -614,10 +594,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/opacrf/mod.rs b/src/aips/opacrf/mod.rs index 95e65b5..8c1e667 100644 --- a/src/aips/opacrf/mod.rs +++ b/src/aips/opacrf/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRF { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP5R { #[doc = "Possible values of the field `TP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP4R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP4R { #[doc = "Possible values of the field `WP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP4R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP4R { #[doc = "Possible values of the field `SP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP4R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP4R { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP3R { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl SP2R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -795,10 +765,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -842,10 +810,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -888,10 +854,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -946,10 +910,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -1004,10 +966,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -1062,10 +1022,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP4`"] pub enum TP4W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4W { #[allow(missing_docs)] @@ -1120,10 +1078,8 @@ impl<'a> _TP4W<'a> { } #[doc = "Values that can be written to the field `WP4`"] pub enum WP4W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4W { #[allow(missing_docs)] @@ -1178,10 +1134,8 @@ impl<'a> _WP4W<'a> { } #[doc = "Values that can be written to the field `SP4`"] pub enum SP4W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4W { #[allow(missing_docs)] @@ -1236,10 +1190,8 @@ impl<'a> _SP4W<'a> { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -1294,10 +1246,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -1352,10 +1302,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] @@ -1410,10 +1358,8 @@ impl<'a> _SP3W<'a> { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -1468,10 +1414,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -1526,10 +1470,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] @@ -1584,10 +1526,8 @@ impl<'a> _SP2W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -1642,10 +1582,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -1700,10 +1638,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -1758,10 +1694,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -1816,10 +1750,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -1874,10 +1806,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/opacrg/mod.rs b/src/aips/opacrg/mod.rs index 3ffe282..76e4c78 100644 --- a/src/aips/opacrg/mod.rs +++ b/src/aips/opacrg/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRG { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl SP2R { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -299,10 +291,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] diff --git a/src/aips/opacrh/mod.rs b/src/aips/opacrh/mod.rs index f579192..aa01657 100644 --- a/src/aips/opacrh/mod.rs +++ b/src/aips/opacrh/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRH { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl SP2R { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -299,10 +291,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] diff --git a/src/aips/opacri/mod.rs b/src/aips/opacri/mod.rs index f5f4872..b013da6 100644 --- a/src/aips/opacri/mod.rs +++ b/src/aips/opacri/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRI { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP6R { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP5R { #[doc = "Possible values of the field `TP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP4R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP4R { #[doc = "Possible values of the field `WP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP4R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP4R { #[doc = "Possible values of the field `SP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP4R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl SP4R { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl SP3R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -747,10 +719,8 @@ impl SP1R { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -805,10 +775,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -863,10 +831,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -921,10 +887,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -979,10 +943,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -1037,10 +999,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -1095,10 +1055,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP4`"] pub enum TP4W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4W { #[allow(missing_docs)] @@ -1153,10 +1111,8 @@ impl<'a> _TP4W<'a> { } #[doc = "Values that can be written to the field `WP4`"] pub enum WP4W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4W { #[allow(missing_docs)] @@ -1211,10 +1167,8 @@ impl<'a> _WP4W<'a> { } #[doc = "Values that can be written to the field `SP4`"] pub enum SP4W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4W { #[allow(missing_docs)] @@ -1269,10 +1223,8 @@ impl<'a> _SP4W<'a> { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -1327,10 +1279,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -1385,10 +1335,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] @@ -1443,10 +1391,8 @@ impl<'a> _SP3W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -1501,10 +1447,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -1559,10 +1503,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] diff --git a/src/aips/opacrj/mod.rs b/src/aips/opacrj/mod.rs index 543692f..c384e11 100644 --- a/src/aips/opacrj/mod.rs +++ b/src/aips/opacrj/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRJ { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRJ { #[doc = "Possible values of the field `TP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP4R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP4R { #[doc = "Possible values of the field `WP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP4R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP4R { #[doc = "Possible values of the field `SP4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP4R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP4R { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP3R { #[doc = "Possible values of the field `TP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP2R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP2R { #[doc = "Possible values of the field `WP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP2R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP2R { #[doc = "Possible values of the field `SP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP2R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl SP2R { } #[doc = "Values that can be written to the field `TP4`"] pub enum TP4W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP4W { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _TP4W<'a> { } #[doc = "Values that can be written to the field `WP4`"] pub enum WP4W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP4W { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _WP4W<'a> { } #[doc = "Values that can be written to the field `SP4`"] pub enum SP4W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP4W { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _SP4W<'a> { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] @@ -813,10 +785,8 @@ impl<'a> _SP3W<'a> { } #[doc = "Values that can be written to the field `TP2`"] pub enum TP2W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP2W { #[allow(missing_docs)] @@ -871,10 +841,8 @@ impl<'a> _TP2W<'a> { } #[doc = "Values that can be written to the field `WP2`"] pub enum WP2W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP2W { #[allow(missing_docs)] @@ -929,10 +897,8 @@ impl<'a> _WP2W<'a> { } #[doc = "Values that can be written to the field `SP2`"] pub enum SP2W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP2W { #[allow(missing_docs)] diff --git a/src/aips/opacrk/mod.rs b/src/aips/opacrk/mod.rs index 53f6114..ac53774 100644 --- a/src/aips/opacrk/mod.rs +++ b/src/aips/opacrk/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRK { #[doc = "Possible values of the field `TP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP3R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP3R { #[doc = "Possible values of the field `WP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP3R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP3R { #[doc = "Possible values of the field `SP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP3R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl SP3R { } #[doc = "Values that can be written to the field `TP3`"] pub enum TP3W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP3W { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _TP3W<'a> { } #[doc = "Values that can be written to the field `WP3`"] pub enum WP3W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP3W { #[allow(missing_docs)] @@ -299,10 +291,8 @@ impl<'a> _WP3W<'a> { } #[doc = "Values that can be written to the field `SP3`"] pub enum SP3W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP3W { #[allow(missing_docs)] diff --git a/src/aips/opacrl/mod.rs b/src/aips/opacrl/mod.rs index 6ab9fa9..7dcda8f 100644 --- a/src/aips/opacrl/mod.rs +++ b/src/aips/opacrl/mod.rs @@ -22,7 +22,9 @@ impl super::OPACRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OPACRL { #[doc = "Possible values of the field `TP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP7R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP7R { #[doc = "Possible values of the field `WP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP7R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP7R { #[doc = "Possible values of the field `SP7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP7R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP7R { #[doc = "Possible values of the field `TP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP6R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP6R { #[doc = "Possible values of the field `WP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP6R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP6R { #[doc = "Possible values of the field `SP6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP6R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP6R { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl SP5R { } #[doc = "Values that can be written to the field `TP7`"] pub enum TP7W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP7W { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _TP7W<'a> { } #[doc = "Values that can be written to the field `WP7`"] pub enum WP7W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP7W { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _WP7W<'a> { } #[doc = "Values that can be written to the field `SP7`"] pub enum SP7W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP7W { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _SP7W<'a> { } #[doc = "Values that can be written to the field `TP6`"] pub enum TP6W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP6W { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TP6W<'a> { } #[doc = "Values that can be written to the field `WP6`"] pub enum WP6W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP6W { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _WP6W<'a> { } #[doc = "Values that can be written to the field `SP6`"] pub enum SP6W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP6W { #[allow(missing_docs)] @@ -813,10 +785,8 @@ impl<'a> _SP6W<'a> { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -871,10 +841,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -929,10 +897,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] diff --git a/src/aips/pacra/mod.rs b/src/aips/pacra/mod.rs index 460dc2b..858e929 100644 --- a/src/aips/pacra/mod.rs +++ b/src/aips/pacra/mod.rs @@ -22,7 +22,9 @@ impl super::PACRA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PACRA { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -324,10 +314,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -382,10 +370,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -440,10 +426,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -498,10 +482,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -556,10 +538,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -614,10 +594,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/pacrb/mod.rs b/src/aips/pacrb/mod.rs index 7190249..20d03d3 100644 --- a/src/aips/pacrb/mod.rs +++ b/src/aips/pacrb/mod.rs @@ -22,7 +22,9 @@ impl super::PACRB { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PACRB { #[doc = "Possible values of the field `TP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP5R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP5R { #[doc = "Possible values of the field `WP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP5R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP5R { #[doc = "Possible values of the field `SP5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP5R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP5R { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP5`"] pub enum TP5W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP5W { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _TP5W<'a> { } #[doc = "Values that can be written to the field `WP5`"] pub enum WP5W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP5W { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _WP5W<'a> { } #[doc = "Values that can be written to the field `SP5`"] pub enum SP5W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP5W { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _SP5W<'a> { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -813,10 +785,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -871,10 +841,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -929,10 +897,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/aips/pacrc/mod.rs b/src/aips/pacrc/mod.rs index 1b98531..be94e1b 100644 --- a/src/aips/pacrc/mod.rs +++ b/src/aips/pacrc/mod.rs @@ -6,7 +6,9 @@ impl super::PACRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } impl R { diff --git a/src/aips/pacrd/mod.rs b/src/aips/pacrd/mod.rs index 885b38a..e661dbb 100644 --- a/src/aips/pacrd/mod.rs +++ b/src/aips/pacrd/mod.rs @@ -22,7 +22,9 @@ impl super::PACRD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PACRD { #[doc = "Possible values of the field `TP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP1R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TP1R { #[doc = "Possible values of the field `WP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP1R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WP1R { #[doc = "Possible values of the field `SP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP1R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SP1R { #[doc = "Possible values of the field `TP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TP0R { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TP0R { #[doc = "Possible values of the field `WP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WP0R { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl WP0R { #[doc = "Possible values of the field `SP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SP0R { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -324,10 +314,8 @@ impl SP0R { } #[doc = "Values that can be written to the field `TP1`"] pub enum TP1W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP1W { #[allow(missing_docs)] @@ -382,10 +370,8 @@ impl<'a> _TP1W<'a> { } #[doc = "Values that can be written to the field `WP1`"] pub enum WP1W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP1W { #[allow(missing_docs)] @@ -440,10 +426,8 @@ impl<'a> _WP1W<'a> { } #[doc = "Values that can be written to the field `SP1`"] pub enum SP1W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP1W { #[allow(missing_docs)] @@ -498,10 +482,8 @@ impl<'a> _SP1W<'a> { } #[doc = "Values that can be written to the field `TP0`"] pub enum TP0W { - #[doc = "Accesses from an untrusted master are allowed."] - _0, - #[doc = "Accesses from an untrusted master are not allowed."] - _1, + #[doc = "Accesses from an untrusted master are allowed."] _0, + #[doc = "Accesses from an untrusted master are not allowed."] _1, } impl TP0W { #[allow(missing_docs)] @@ -556,10 +538,8 @@ impl<'a> _TP0W<'a> { } #[doc = "Values that can be written to the field `WP0`"] pub enum WP0W { - #[doc = "This peripheral allows write accesses."] - _0, - #[doc = "This peripheral is write protected."] - _1, + #[doc = "This peripheral allows write accesses."] _0, + #[doc = "This peripheral is write protected."] _1, } impl WP0W { #[allow(missing_docs)] @@ -614,10 +594,8 @@ impl<'a> _WP0W<'a> { } #[doc = "Values that can be written to the field `SP0`"] pub enum SP0W { - #[doc = "This peripheral does not require supervisor privilege level for accesses."] - _0, - #[doc = "This peripheral requires supervisor privilege level for accesses."] - _1, + #[doc = "This peripheral does not require supervisor privilege level for accesses."] _0, + #[doc = "This peripheral requires supervisor privilege level for accesses."] _1, } impl SP0W { #[allow(missing_docs)] diff --git a/src/can0/cbt/mod.rs b/src/can0/cbt/mod.rs index f421eda..cb70aeb 100644 --- a/src/can0/cbt/mod.rs +++ b/src/can0/cbt/mod.rs @@ -22,7 +22,9 @@ impl super::CBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -98,10 +100,8 @@ impl EPRESDIVR { #[doc = "Possible values of the field `BTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BTFR { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -219,10 +219,8 @@ impl<'a> _EPRESDIVW<'a> { } #[doc = "Values that can be written to the field `BTF`"] pub enum BTFW { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFW { #[allow(missing_docs)] diff --git a/src/can0/crcr/mod.rs b/src/can0/crcr/mod.rs index 4235705..07b066c 100644 --- a/src/can0/crcr/mod.rs +++ b/src/can0/crcr/mod.rs @@ -6,7 +6,9 @@ impl super::CRCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/ctrl1/mod.rs b/src/can0/ctrl1/mod.rs index 95f49d5..ad0efed 100644 --- a/src/can0/ctrl1/mod.rs +++ b/src/can0/ctrl1/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl PROPSEGR { #[doc = "Possible values of the field `LOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOMR { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl LOMR { #[doc = "Possible values of the field `LBUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBUFR { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl LBUFR { #[doc = "Possible values of the field `TSYN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSYNR { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl TSYNR { #[doc = "Possible values of the field `BOFFREC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFRECR { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl BOFFRECR { #[doc = "Possible values of the field `SMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMPR { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -289,10 +282,8 @@ impl SMPR { #[doc = "Possible values of the field `RWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNMSKR { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -336,10 +327,8 @@ impl RWRNMSKR { #[doc = "Possible values of the field `TWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNMSKR { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -383,10 +372,8 @@ impl TWRNMSKR { #[doc = "Possible values of the field `LPB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPBR { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +419,7 @@ impl LPBR { pub enum CLKSRCR { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +463,8 @@ impl CLKSRCR { #[doc = "Possible values of the field `ERRMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSKR { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +508,8 @@ impl ERRMSKR { #[doc = "Possible values of the field `BOFFMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFMSKR { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -629,10 +611,8 @@ impl<'a> _PROPSEGW<'a> { } #[doc = "Values that can be written to the field `LOM`"] pub enum LOMW { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMW { #[allow(missing_docs)] @@ -687,10 +667,8 @@ impl<'a> _LOMW<'a> { } #[doc = "Values that can be written to the field `LBUF`"] pub enum LBUFW { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFW { #[allow(missing_docs)] @@ -745,10 +723,8 @@ impl<'a> _LBUFW<'a> { } #[doc = "Values that can be written to the field `TSYN`"] pub enum TSYNW { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNW { #[allow(missing_docs)] @@ -803,10 +779,8 @@ impl<'a> _TSYNW<'a> { } #[doc = "Values that can be written to the field `BOFFREC`"] pub enum BOFFRECW { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECW { #[allow(missing_docs)] @@ -861,8 +835,7 @@ impl<'a> _BOFFRECW<'a> { } #[doc = "Values that can be written to the field `SMP`"] pub enum SMPW { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -919,10 +892,8 @@ impl<'a> _SMPW<'a> { } #[doc = "Values that can be written to the field `RWRNMSK`"] pub enum RWRNMSKW { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKW { #[allow(missing_docs)] @@ -977,10 +948,8 @@ impl<'a> _RWRNMSKW<'a> { } #[doc = "Values that can be written to the field `TWRNMSK`"] pub enum TWRNMSKW { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKW { #[allow(missing_docs)] @@ -1035,10 +1004,8 @@ impl<'a> _TWRNMSKW<'a> { } #[doc = "Values that can be written to the field `LPB`"] pub enum LPBW { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBW { #[allow(missing_docs)] @@ -1095,8 +1062,7 @@ impl<'a> _LPBW<'a> { pub enum CLKSRCW { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCW { #[allow(missing_docs)] @@ -1151,10 +1117,8 @@ impl<'a> _CLKSRCW<'a> { } #[doc = "Values that can be written to the field `ERRMSK`"] pub enum ERRMSKW { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKW { #[allow(missing_docs)] @@ -1209,10 +1173,8 @@ impl<'a> _ERRMSKW<'a> { } #[doc = "Values that can be written to the field `BOFFMSK`"] pub enum BOFFMSKW { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKW { #[allow(missing_docs)] diff --git a/src/can0/ctrl1_pn/mod.rs b/src/can0/ctrl1_pn/mod.rs index 0fe8a14..dc76bb4 100644 --- a/src/can0/ctrl1_pn/mod.rs +++ b/src/can0/ctrl1_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CTRL1_PN { #[doc = "Possible values of the field `FCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCSR { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSR { #[doc = r" Value of the field as raw bits"] @@ -99,12 +97,9 @@ impl FCSR { #[doc = "Possible values of the field `IDFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDFSR { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -155,12 +150,9 @@ impl IDFSR { #[doc = "Possible values of the field `PLFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLFSR { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -217,8 +209,7 @@ pub enum NMATCHR { _00000010, #[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."] _11111111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl NMATCHR { #[doc = r" Value of the field as raw bits"] @@ -261,10 +252,8 @@ impl NMATCHR { #[doc = "Possible values of the field `WUMF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMF_MSKR { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -308,10 +297,8 @@ impl WUMF_MSKR { #[doc = "Possible values of the field `WTOF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOF_MSKR { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -354,14 +341,10 @@ impl WTOF_MSKR { } #[doc = "Values that can be written to the field `FCS`"] pub enum FCSW { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSW { #[allow(missing_docs)] @@ -420,12 +403,9 @@ impl<'a> _FCSW<'a> { } #[doc = "Values that can be written to the field `IDFS`"] pub enum IDFSW { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -486,12 +466,9 @@ impl<'a> _IDFSW<'a> { } #[doc = "Values that can be written to the field `PLFS`"] pub enum PLFSW { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -608,10 +585,8 @@ impl<'a> _NMATCHW<'a> { } #[doc = "Values that can be written to the field `WUMF_MSK`"] pub enum WUMF_MSKW { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKW { #[allow(missing_docs)] @@ -666,10 +641,8 @@ impl<'a> _WUMF_MSKW<'a> { } #[doc = "Values that can be written to the field `WTOF_MSK`"] pub enum WTOF_MSKW { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKW { #[allow(missing_docs)] diff --git a/src/can0/ctrl2/mod.rs b/src/can0/ctrl2/mod.rs index fcb2804..dfec61f 100644 --- a/src/can0/ctrl2/mod.rs +++ b/src/can0/ctrl2/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL2 { #[doc = "Possible values of the field `EDFLTDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDFLTDISR { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EDFLTDISR { #[doc = "Possible values of the field `ISOCANFDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISOCANFDENR { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ISOCANFDENR { #[doc = "Possible values of the field `PREXCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PREXCENR { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +274,8 @@ impl EACENR { #[doc = "Possible values of the field `RRS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RRSR { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +319,8 @@ impl RRSR { #[doc = "Possible values of the field `MRP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MRPR { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +386,8 @@ impl RFFNR { #[doc = "Possible values of the field `BOFFDONEMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEMSKR { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +431,8 @@ impl BOFFDONEMSKR { #[doc = "Possible values of the field `ERRMSK_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSK_FASTR { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -487,10 +475,8 @@ impl ERRMSK_FASTR { } #[doc = "Values that can be written to the field `EDFLTDIS`"] pub enum EDFLTDISW { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISW { #[allow(missing_docs)] @@ -545,10 +531,8 @@ impl<'a> _EDFLTDISW<'a> { } #[doc = "Values that can be written to the field `ISOCANFDEN`"] pub enum ISOCANFDENW { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENW { #[allow(missing_docs)] @@ -603,10 +587,8 @@ impl<'a> _ISOCANFDENW<'a> { } #[doc = "Values that can be written to the field `PREXCEN`"] pub enum PREXCENW { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENW { #[allow(missing_docs)] @@ -777,10 +759,8 @@ impl<'a> _EACENW<'a> { } #[doc = "Values that can be written to the field `RRS`"] pub enum RRSW { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSW { #[allow(missing_docs)] @@ -835,10 +815,8 @@ impl<'a> _RRSW<'a> { } #[doc = "Values that can be written to the field `MRP`"] pub enum MRPW { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPW { #[allow(missing_docs)] @@ -923,10 +901,8 @@ impl<'a> _RFFNW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEMSK`"] pub enum BOFFDONEMSKW { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKW { #[allow(missing_docs)] @@ -981,10 +957,8 @@ impl<'a> _BOFFDONEMSKW<'a> { } #[doc = "Values that can be written to the field `ERRMSK_FAST`"] pub enum ERRMSK_FASTW { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTW { #[allow(missing_docs)] diff --git a/src/can0/ctrl2_pn/mod.rs b/src/can0/ctrl2_pn/mod.rs index 01029c8..7831ff2 100644 --- a/src/can0/ctrl2_pn/mod.rs +++ b/src/can0/ctrl2_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/ecr/mod.rs b/src/can0/ecr/mod.rs index ab42b4e..22c7322 100644 --- a/src/can0/ecr/mod.rs +++ b/src/can0/ecr/mod.rs @@ -22,7 +22,9 @@ impl super::ECR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/embedded_ram/mod.rs b/src/can0/embedded_ram/mod.rs index 91a2c94..5fe0f4f 100644 --- a/src/can0/embedded_ram/mod.rs +++ b/src/can0/embedded_ram/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/esr1/mod.rs b/src/can0/esr1/mod.rs index f1f6be4..4798194 100644 --- a/src/can0/esr1/mod.rs +++ b/src/can0/esr1/mod.rs @@ -22,7 +22,9 @@ impl super::ESR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ESR1 { #[doc = "Possible values of the field `ERRINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERRINTR { #[doc = "Possible values of the field `BOFFINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl BOFFINTR { #[doc = "Possible values of the field `RX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXR { - #[doc = "FlexCAN is not receiving a message."] - _0, - #[doc = "FlexCAN is receiving a message."] - _1, + #[doc = "FlexCAN is not receiving a message."] _0, + #[doc = "FlexCAN is receiving a message."] _1, } impl RXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,14 +180,10 @@ impl RXR { #[doc = "Possible values of the field `FLTCONF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTCONFR { - #[doc = "Error Active"] - _00, - #[doc = "Error Passive"] - _01, - #[doc = "Bus Off"] - _1X, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Error Active"] _00, + #[doc = "Error Passive"] _01, + #[doc = "Bus Off"] _1X, + #[doc = r" Reserved"] _Reserved(u8), } impl FLTCONFR { #[doc = r" Value of the field as raw bits"] @@ -234,10 +226,8 @@ impl FLTCONFR { #[doc = "Possible values of the field `TX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXR { - #[doc = "FlexCAN is not transmitting a message."] - _0, - #[doc = "FlexCAN is transmitting a message."] - _1, + #[doc = "FlexCAN is not transmitting a message."] _0, + #[doc = "FlexCAN is transmitting a message."] _1, } impl TXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -281,10 +271,8 @@ impl TXR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No such occurrence."] - _0, - #[doc = "CAN bus is now IDLE."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "CAN bus is now IDLE."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -328,10 +316,8 @@ impl IDLER { #[doc = "Possible values of the field `RXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "RXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "RXERRCNT is greater than or equal to 96."] _1, } impl RXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -375,10 +361,8 @@ impl RXWRNR { #[doc = "Possible values of the field `TXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "TXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "TXERRCNT is greater than or equal to 96."] _1, } impl TXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -422,10 +406,8 @@ impl TXWRNR { #[doc = "Possible values of the field `STFERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -469,10 +451,8 @@ impl STFERRR { #[doc = "Possible values of the field `FRMERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -516,10 +496,8 @@ impl FRMERRR { #[doc = "Possible values of the field `CRCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -563,10 +541,8 @@ impl CRCERRR { #[doc = "Possible values of the field `ACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACKERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "An ACK error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "An ACK error occurred since last read of this register."] _1, } impl ACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -610,10 +586,8 @@ impl ACKERRR { #[doc = "Possible values of the field `BIT0ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -657,10 +631,8 @@ impl BIT0ERRR { #[doc = "Possible values of the field `BIT1ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -704,8 +676,7 @@ impl BIT1ERRR { #[doc = "Possible values of the field `RWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -751,8 +722,7 @@ impl RWRNINTR { #[doc = "Possible values of the field `TWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -798,10 +768,8 @@ impl TWRNINTR { #[doc = "Possible values of the field `SYNCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCHR { - #[doc = "FlexCAN is not synchronized to the CAN bus."] - _0, - #[doc = "FlexCAN is synchronized to the CAN bus."] - _1, + #[doc = "FlexCAN is not synchronized to the CAN bus."] _0, + #[doc = "FlexCAN is synchronized to the CAN bus."] _1, } impl SYNCHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -845,10 +813,8 @@ impl SYNCHR { #[doc = "Possible values of the field `BOFFDONEINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,8 +858,7 @@ impl BOFFDONEINTR { #[doc = "Possible values of the field `ERRINT_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINT_FASTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -939,10 +904,8 @@ impl ERRINT_FASTR { #[doc = "Possible values of the field `ERROVR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERROVRR { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -986,10 +949,8 @@ impl ERROVRR { #[doc = "Possible values of the field `STFERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1033,10 +994,8 @@ impl STFERR_FASTR { #[doc = "Possible values of the field `FRMERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1080,10 +1039,8 @@ impl FRMERR_FASTR { #[doc = "Possible values of the field `CRCERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1127,10 +1084,8 @@ impl CRCERR_FASTR { #[doc = "Possible values of the field `BIT0ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1174,10 +1129,8 @@ impl BIT0ERR_FASTR { #[doc = "Possible values of the field `BIT1ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1220,10 +1173,8 @@ impl BIT1ERR_FASTR { } #[doc = "Values that can be written to the field `ERRINT`"] pub enum ERRINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTW { #[allow(missing_docs)] @@ -1278,10 +1229,8 @@ impl<'a> _ERRINTW<'a> { } #[doc = "Values that can be written to the field `BOFFINT`"] pub enum BOFFINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTW { #[allow(missing_docs)] @@ -1336,8 +1285,7 @@ impl<'a> _BOFFINTW<'a> { } #[doc = "Values that can be written to the field `RWRNINT`"] pub enum RWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1394,8 +1342,7 @@ impl<'a> _RWRNINTW<'a> { } #[doc = "Values that can be written to the field `TWRNINT`"] pub enum TWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1452,10 +1399,8 @@ impl<'a> _TWRNINTW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEINT`"] pub enum BOFFDONEINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTW { #[allow(missing_docs)] @@ -1510,8 +1455,7 @@ impl<'a> _BOFFDONEINTW<'a> { } #[doc = "Values that can be written to the field `ERRINT_FAST`"] pub enum ERRINT_FASTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -1568,10 +1512,8 @@ impl<'a> _ERRINT_FASTW<'a> { } #[doc = "Values that can be written to the field `ERROVR`"] pub enum ERROVRW { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRW { #[allow(missing_docs)] diff --git a/src/can0/esr2/mod.rs b/src/can0/esr2/mod.rs index d4f29f2..8f2635b 100644 --- a/src/can0/esr2/mod.rs +++ b/src/can0/esr2/mod.rs @@ -6,14 +6,15 @@ impl super::ESR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `IMB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IMBR { - #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] - _0, + #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] _0, #[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."] _1, } @@ -59,10 +60,8 @@ impl IMBR { #[doc = "Possible values of the field `VPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VPSR { - #[doc = "Contents of IMB and LPTM are invalid."] - _0, - #[doc = "Contents of IMB and LPTM are valid."] - _1, + #[doc = "Contents of IMB and LPTM are invalid."] _0, + #[doc = "Contents of IMB and LPTM are valid."] _1, } impl VPSR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can0/fdcbt/mod.rs b/src/can0/fdcbt/mod.rs index d5b4147..0ddab6e 100644 --- a/src/can0/fdcbt/mod.rs +++ b/src/can0/fdcbt/mod.rs @@ -22,7 +22,9 @@ impl super::FDCBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/fdcrc/mod.rs b/src/can0/fdcrc/mod.rs index b213def..d0da073 100644 --- a/src/can0/fdcrc/mod.rs +++ b/src/can0/fdcrc/mod.rs @@ -6,7 +6,9 @@ impl super::FDCRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/fdctrl/mod.rs b/src/can0/fdctrl/mod.rs index e337ada..cf39ab2 100644 --- a/src/can0/fdctrl/mod.rs +++ b/src/can0/fdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl TDCOFFR { #[doc = "Possible values of the field `TDCFAIL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCFAILR { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl TDCFAILR { #[doc = "Possible values of the field `TDCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCENR { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -159,14 +157,10 @@ impl TDCENR { #[doc = "Possible values of the field `MBDSR0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBDSR0R { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0R { #[doc = r" Value of the field as raw bits"] @@ -215,10 +209,8 @@ impl MBDSR0R { #[doc = "Possible values of the field `FDRATE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FDRATER { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -276,10 +268,8 @@ impl<'a> _TDCOFFW<'a> { } #[doc = "Values that can be written to the field `TDCFAIL`"] pub enum TDCFAILW { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILW { #[allow(missing_docs)] @@ -334,10 +324,8 @@ impl<'a> _TDCFAILW<'a> { } #[doc = "Values that can be written to the field `TDCEN`"] pub enum TDCENW { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENW { #[allow(missing_docs)] @@ -392,14 +380,10 @@ impl<'a> _TDCENW<'a> { } #[doc = "Values that can be written to the field `MBDSR0`"] pub enum MBDSR0W { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0W { #[allow(missing_docs)] @@ -458,10 +442,8 @@ impl<'a> _MBDSR0W<'a> { } #[doc = "Values that can be written to the field `FDRATE`"] pub enum FDRATEW { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATEW { #[allow(missing_docs)] diff --git a/src/can0/flt_dlc/mod.rs b/src/can0/flt_dlc/mod.rs index 74c52b5..db8cb41 100644 --- a/src/can0/flt_dlc/mod.rs +++ b/src/can0/flt_dlc/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_DLC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/flt_id1/mod.rs b/src/can0/flt_id1/mod.rs index 7af09e6..528a567 100644 --- a/src/can0/flt_id1/mod.rs +++ b/src/can0/flt_id1/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID1R { #[doc = "Possible values of the field `FLT_RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_RTRR { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl FLT_RTRR { #[doc = "Possible values of the field `FLT_IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_IDER { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID1W<'a> { } #[doc = "Values that can be written to the field `FLT_RTR`"] pub enum FLT_RTRW { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _FLT_RTRW<'a> { } #[doc = "Values that can be written to the field `FLT_IDE`"] pub enum FLT_IDEW { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDEW { #[allow(missing_docs)] diff --git a/src/can0/flt_id2_idmask/mod.rs b/src/can0/flt_id2_idmask/mod.rs index e836809..66cd275 100644 --- a/src/can0/flt_id2_idmask/mod.rs +++ b/src/can0/flt_id2_idmask/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID2_IDMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID2_IDMASKR { #[doc = "Possible values of the field `RTR_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTR_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl RTR_MSKR { #[doc = "Possible values of the field `IDE_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDE_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID2_IDMASKW<'a> { } #[doc = "Values that can be written to the field `RTR_MSK`"] pub enum RTR_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _RTR_MSKW<'a> { } #[doc = "Values that can be written to the field `IDE_MSK`"] pub enum IDE_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKW { #[allow(missing_docs)] diff --git a/src/can0/iflag1/mod.rs b/src/can0/iflag1/mod.rs index 62b4c8f..20a7322 100644 --- a/src/can0/iflag1/mod.rs +++ b/src/can0/iflag1/mod.rs @@ -22,7 +22,9 @@ impl super::IFLAG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/imask1/mod.rs b/src/can0/imask1/mod.rs index b6debac..1f67ed9 100644 --- a/src/can0/imask1/mod.rs +++ b/src/can0/imask1/mod.rs @@ -22,7 +22,9 @@ impl super::IMASK1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/mcr/mod.rs b/src/can0/mcr/mod.rs index 0f6af62..3c5653b 100644 --- a/src/can0/mcr/mod.rs +++ b/src/can0/mcr/mod.rs @@ -22,7 +22,9 @@ impl super::MCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,11 @@ impl MAXMBR { #[doc = "Possible values of the field `IDAM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDAMR { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMR { #[doc = r" Value of the field as raw bits"] @@ -157,10 +156,8 @@ impl FDENR { #[doc = "Possible values of the field `AEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AENR { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -204,10 +201,8 @@ impl AENR { #[doc = "Possible values of the field `LPRIOEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPRIOENR { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -251,10 +246,8 @@ impl LPRIOENR { #[doc = "Possible values of the field `PNET_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PNET_ENR { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -298,10 +291,8 @@ impl PNET_ENR { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -347,8 +338,7 @@ impl DMAR { pub enum IRMQR { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -392,10 +382,8 @@ impl IRMQR { #[doc = "Possible values of the field `SRXDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRXDISR { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -439,10 +427,8 @@ impl SRXDISR { #[doc = "Possible values of the field `LPMACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPMACKR { - #[doc = "FlexCAN is not in a low-power mode."] - _0, - #[doc = "FlexCAN is in a low-power mode."] - _1, + #[doc = "FlexCAN is not in a low-power mode."] _0, + #[doc = "FlexCAN is in a low-power mode."] _1, } impl LPMACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -554,10 +540,8 @@ impl SUPVR { #[doc = "Possible values of the field `FRZACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZACKR { - #[doc = "FlexCAN not in Freeze mode, prescaler running."] - _0, - #[doc = "FlexCAN in Freeze mode, prescaler stopped."] - _1, + #[doc = "FlexCAN not in Freeze mode, prescaler running."] _0, + #[doc = "FlexCAN in Freeze mode, prescaler stopped."] _1, } impl FRZACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -601,10 +585,8 @@ impl FRZACKR { #[doc = "Possible values of the field `SOFTRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFTRSTR { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +630,8 @@ impl SOFTRSTR { #[doc = "Possible values of the field `NOTRDY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOTRDYR { - #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl NOTRDYR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -690,10 +670,8 @@ impl NOTRDYR { #[doc = "Possible values of the field `HALT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HALTR { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -737,10 +715,8 @@ impl HALTR { #[doc = "Possible values of the field `RFEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFENR { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -784,10 +760,8 @@ impl RFENR { #[doc = "Possible values of the field `FRZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZR { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -831,10 +805,8 @@ impl FRZR { #[doc = "Possible values of the field `MDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MDISR { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,14 +864,11 @@ impl<'a> _MAXMBW<'a> { } #[doc = "Values that can be written to the field `IDAM`"] pub enum IDAMW { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMW { #[allow(missing_docs)] @@ -1016,10 +985,8 @@ impl<'a> _FDENW<'a> { } #[doc = "Values that can be written to the field `AEN`"] pub enum AENW { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENW { #[allow(missing_docs)] @@ -1074,10 +1041,8 @@ impl<'a> _AENW<'a> { } #[doc = "Values that can be written to the field `LPRIOEN`"] pub enum LPRIOENW { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENW { #[allow(missing_docs)] @@ -1132,10 +1097,8 @@ impl<'a> _LPRIOENW<'a> { } #[doc = "Values that can be written to the field `PNET_EN`"] pub enum PNET_ENW { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENW { #[allow(missing_docs)] @@ -1190,10 +1153,8 @@ impl<'a> _PNET_ENW<'a> { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAW { #[allow(missing_docs)] @@ -1250,8 +1211,7 @@ impl<'a> _DMAW<'a> { pub enum IRMQW { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQW { #[allow(missing_docs)] @@ -1306,10 +1266,8 @@ impl<'a> _IRMQW<'a> { } #[doc = "Values that can be written to the field `SRXDIS`"] pub enum SRXDISW { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISW { #[allow(missing_docs)] @@ -1445,10 +1403,8 @@ impl<'a> _SUPVW<'a> { } #[doc = "Values that can be written to the field `SOFTRST`"] pub enum SOFTRSTW { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTW { #[allow(missing_docs)] @@ -1503,10 +1459,8 @@ impl<'a> _SOFTRSTW<'a> { } #[doc = "Values that can be written to the field `HALT`"] pub enum HALTW { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTW { #[allow(missing_docs)] @@ -1561,10 +1515,8 @@ impl<'a> _HALTW<'a> { } #[doc = "Values that can be written to the field `RFEN`"] pub enum RFENW { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENW { #[allow(missing_docs)] @@ -1619,10 +1571,8 @@ impl<'a> _RFENW<'a> { } #[doc = "Values that can be written to the field `FRZ`"] pub enum FRZW { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZW { #[allow(missing_docs)] @@ -1677,10 +1627,8 @@ impl<'a> _FRZW<'a> { } #[doc = "Values that can be written to the field `MDIS`"] pub enum MDISW { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISW { #[allow(missing_docs)] diff --git a/src/can0/mod.rs b/src/can0/mod.rs index bd086bc..054059d 100644 --- a/src/can0/mod.rs +++ b/src/can0/mod.rs @@ -2,93 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Module Configuration Register"] - pub mcr: MCR, - #[doc = "0x04 - Control 1 register"] - pub ctrl1: CTRL1, - #[doc = "0x08 - Free Running Timer"] - pub timer: TIMER, + #[doc = "0x00 - Module Configuration Register"] pub mcr: MCR, + #[doc = "0x04 - Control 1 register"] pub ctrl1: CTRL1, + #[doc = "0x08 - Free Running Timer"] pub timer: TIMER, _reserved0: [u8; 4usize], - #[doc = "0x10 - Rx Mailboxes Global Mask Register"] - pub rxmgmask: RXMGMASK, - #[doc = "0x14 - Rx 14 Mask register"] - pub rx14mask: RX14MASK, - #[doc = "0x18 - Rx 15 Mask register"] - pub rx15mask: RX15MASK, - #[doc = "0x1c - Error Counter"] - pub ecr: ECR, - #[doc = "0x20 - Error and Status 1 register"] - pub esr1: ESR1, + #[doc = "0x10 - Rx Mailboxes Global Mask Register"] pub rxmgmask: RXMGMASK, + #[doc = "0x14 - Rx 14 Mask register"] pub rx14mask: RX14MASK, + #[doc = "0x18 - Rx 15 Mask register"] pub rx15mask: RX15MASK, + #[doc = "0x1c - Error Counter"] pub ecr: ECR, + #[doc = "0x20 - Error and Status 1 register"] pub esr1: ESR1, _reserved1: [u8; 4usize], - #[doc = "0x28 - Interrupt Masks 1 register"] - pub imask1: IMASK1, + #[doc = "0x28 - Interrupt Masks 1 register"] pub imask1: IMASK1, _reserved2: [u8; 4usize], - #[doc = "0x30 - Interrupt Flags 1 register"] - pub iflag1: IFLAG1, - #[doc = "0x34 - Control 2 register"] - pub ctrl2: CTRL2, - #[doc = "0x38 - Error and Status 2 register"] - pub esr2: ESR2, + #[doc = "0x30 - Interrupt Flags 1 register"] pub iflag1: IFLAG1, + #[doc = "0x34 - Control 2 register"] pub ctrl2: CTRL2, + #[doc = "0x38 - Error and Status 2 register"] pub esr2: ESR2, _reserved3: [u8; 8usize], - #[doc = "0x44 - CRC Register"] - pub crcr: CRCR, - #[doc = "0x48 - Rx FIFO Global Mask register"] - pub rxfgmask: RXFGMASK, - #[doc = "0x4c - Rx FIFO Information Register"] - pub rxfir: RXFIR, - #[doc = "0x50 - CAN Bit Timing Register"] - pub cbt: CBT, + #[doc = "0x44 - CRC Register"] pub crcr: CRCR, + #[doc = "0x48 - Rx FIFO Global Mask register"] pub rxfgmask: RXFGMASK, + #[doc = "0x4c - Rx FIFO Information Register"] pub rxfir: RXFIR, + #[doc = "0x50 - CAN Bit Timing Register"] pub cbt: CBT, _reserved4: [u8; 44usize], - #[doc = "0x80 - Embedded RAM"] - pub embedded_ram: [EMBEDDEDRAM; 128], + #[doc = "0x80 - Embedded RAM"] pub embedded_ram: [EMBEDDEDRAM; 128], _reserved5: [u8; 1536usize], - #[doc = "0x880 - Rx Individual Mask Registers"] - pub rximr0: RXIMR0, - #[doc = "0x884 - Rx Individual Mask Registers"] - pub rximr1: RXIMR1, - #[doc = "0x888 - Rx Individual Mask Registers"] - pub rximr2: RXIMR2, - #[doc = "0x88c - Rx Individual Mask Registers"] - pub rximr3: RXIMR3, - #[doc = "0x890 - Rx Individual Mask Registers"] - pub rximr4: RXIMR4, - #[doc = "0x894 - Rx Individual Mask Registers"] - pub rximr5: RXIMR5, - #[doc = "0x898 - Rx Individual Mask Registers"] - pub rximr6: RXIMR6, - #[doc = "0x89c - Rx Individual Mask Registers"] - pub rximr7: RXIMR7, - #[doc = "0x8a0 - Rx Individual Mask Registers"] - pub rximr8: RXIMR8, - #[doc = "0x8a4 - Rx Individual Mask Registers"] - pub rximr9: RXIMR9, - #[doc = "0x8a8 - Rx Individual Mask Registers"] - pub rximr10: RXIMR10, - #[doc = "0x8ac - Rx Individual Mask Registers"] - pub rximr11: RXIMR11, - #[doc = "0x8b0 - Rx Individual Mask Registers"] - pub rximr12: RXIMR12, - #[doc = "0x8b4 - Rx Individual Mask Registers"] - pub rximr13: RXIMR13, - #[doc = "0x8b8 - Rx Individual Mask Registers"] - pub rximr14: RXIMR14, - #[doc = "0x8bc - Rx Individual Mask Registers"] - pub rximr15: RXIMR15, + #[doc = "0x880 - Rx Individual Mask Registers"] pub rximr0: RXIMR0, + #[doc = "0x884 - Rx Individual Mask Registers"] pub rximr1: RXIMR1, + #[doc = "0x888 - Rx Individual Mask Registers"] pub rximr2: RXIMR2, + #[doc = "0x88c - Rx Individual Mask Registers"] pub rximr3: RXIMR3, + #[doc = "0x890 - Rx Individual Mask Registers"] pub rximr4: RXIMR4, + #[doc = "0x894 - Rx Individual Mask Registers"] pub rximr5: RXIMR5, + #[doc = "0x898 - Rx Individual Mask Registers"] pub rximr6: RXIMR6, + #[doc = "0x89c - Rx Individual Mask Registers"] pub rximr7: RXIMR7, + #[doc = "0x8a0 - Rx Individual Mask Registers"] pub rximr8: RXIMR8, + #[doc = "0x8a4 - Rx Individual Mask Registers"] pub rximr9: RXIMR9, + #[doc = "0x8a8 - Rx Individual Mask Registers"] pub rximr10: RXIMR10, + #[doc = "0x8ac - Rx Individual Mask Registers"] pub rximr11: RXIMR11, + #[doc = "0x8b0 - Rx Individual Mask Registers"] pub rximr12: RXIMR12, + #[doc = "0x8b4 - Rx Individual Mask Registers"] pub rximr13: RXIMR13, + #[doc = "0x8b8 - Rx Individual Mask Registers"] pub rximr14: RXIMR14, + #[doc = "0x8bc - Rx Individual Mask Registers"] pub rximr15: RXIMR15, _reserved6: [u8; 576usize], - #[doc = "0xb00 - Pretended Networking Control 1 Register"] - pub ctrl1_pn: CTRL1_PN, - #[doc = "0xb04 - Pretended Networking Control 2 Register"] - pub ctrl2_pn: CTRL2_PN, - #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] - pub wu_mtc: WU_MTC, - #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] - pub flt_id1: FLT_ID1, - #[doc = "0xb10 - Pretended Networking DLC Filter Register"] - pub flt_dlc: FLT_DLC, - #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] - pub pl1_lo: PL1_LO, - #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] - pub pl1_hi: PL1_HI, + #[doc = "0xb00 - Pretended Networking Control 1 Register"] pub ctrl1_pn: CTRL1_PN, + #[doc = "0xb04 - Pretended Networking Control 2 Register"] pub ctrl2_pn: CTRL2_PN, + #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] pub wu_mtc: WU_MTC, + #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] pub flt_id1: FLT_ID1, + #[doc = "0xb10 - Pretended Networking DLC Filter Register"] pub flt_dlc: FLT_DLC, + #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] pub pl1_lo: PL1_LO, + #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] pub pl1_hi: PL1_HI, #[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"] pub flt_id2_idmask: FLT_ID2_IDMASK, #[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"] @@ -96,45 +56,26 @@ pub struct RegisterBlock { #[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"] pub pl2_plmask_hi: PL2_PLMASK_HI, _reserved7: [u8; 24usize], - #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] - pub wmb0_cs: WMB0_CS, - #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] - pub wmb0_id: WMB0_ID, - #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb0_d03: WMB0_D03, - #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] - pub wmb0_d47: WMB0_D47, - #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] - pub wmb1_cs: WMB1_CS, - #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] - pub wmb1_id: WMB1_ID, - #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb1_d03: WMB1_D03, - #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] - pub wmb1_d47: WMB1_D47, - #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] - pub wmb2_cs: WMB2_CS, - #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] - pub wmb2_id: WMB2_ID, - #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb2_d03: WMB2_D03, - #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] - pub wmb2_d47: WMB2_D47, - #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] - pub wmb3_cs: WMB3_CS, - #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] - pub wmb3_id: WMB3_ID, - #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb3_d03: WMB3_D03, - #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] - pub wmb3_d47: WMB3_D47, + #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] pub wmb0_cs: WMB0_CS, + #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] pub wmb0_id: WMB0_ID, + #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] pub wmb0_d03: WMB0_D03, + #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] pub wmb0_d47: WMB0_D47, + #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] pub wmb1_cs: WMB1_CS, + #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] pub wmb1_id: WMB1_ID, + #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] pub wmb1_d03: WMB1_D03, + #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] pub wmb1_d47: WMB1_D47, + #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] pub wmb2_cs: WMB2_CS, + #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] pub wmb2_id: WMB2_ID, + #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] pub wmb2_d03: WMB2_D03, + #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] pub wmb2_d47: WMB2_D47, + #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] pub wmb3_cs: WMB3_CS, + #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] pub wmb3_id: WMB3_ID, + #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] pub wmb3_d03: WMB3_D03, + #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] pub wmb3_d47: WMB3_D47, _reserved8: [u8; 128usize], - #[doc = "0xc00 - CAN FD Control Register"] - pub fdctrl: FDCTRL, - #[doc = "0xc04 - CAN FD Bit Timing Register"] - pub fdcbt: FDCBT, - #[doc = "0xc08 - CAN FD CRC Register"] - pub fdcrc: FDCRC, + #[doc = "0xc00 - CAN FD Control Register"] pub fdctrl: FDCTRL, + #[doc = "0xc04 - CAN FD Bit Timing Register"] pub fdcbt: FDCBT, + #[doc = "0xc08 - CAN FD CRC Register"] pub fdcrc: FDCRC, } #[doc = "Module Configuration Register"] pub struct MCR { diff --git a/src/can0/pl1_hi/mod.rs b/src/can0/pl1_hi/mod.rs index 7b090b3..ab431b7 100644 --- a/src/can0/pl1_hi/mod.rs +++ b/src/can0/pl1_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/pl1_lo/mod.rs b/src/can0/pl1_lo/mod.rs index 363ae74..6e07f19 100644 --- a/src/can0/pl1_lo/mod.rs +++ b/src/can0/pl1_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/pl2_plmask_hi/mod.rs b/src/can0/pl2_plmask_hi/mod.rs index f4943ba..32cc6bd 100644 --- a/src/can0/pl2_plmask_hi/mod.rs +++ b/src/can0/pl2_plmask_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/pl2_plmask_lo/mod.rs b/src/can0/pl2_plmask_lo/mod.rs index eb939de..358d16f 100644 --- a/src/can0/pl2_plmask_lo/mod.rs +++ b/src/can0/pl2_plmask_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rx14mask/mod.rs b/src/can0/rx14mask/mod.rs index 068409e..5670ed6 100644 --- a/src/can0/rx14mask/mod.rs +++ b/src/can0/rx14mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX14MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rx15mask/mod.rs b/src/can0/rx15mask/mod.rs index 5f05ad1..e97bce8 100644 --- a/src/can0/rx15mask/mod.rs +++ b/src/can0/rx15mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX15MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rxfgmask/mod.rs b/src/can0/rxfgmask/mod.rs index 2cafbce..db4555e 100644 --- a/src/can0/rxfgmask/mod.rs +++ b/src/can0/rxfgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXFGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rxfir/mod.rs b/src/can0/rxfir/mod.rs index 50db283..2221db3 100644 --- a/src/can0/rxfir/mod.rs +++ b/src/can0/rxfir/mod.rs @@ -6,7 +6,9 @@ impl super::RXFIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/rximr0/mod.rs b/src/can0/rximr0/mod.rs index 9632744..301c690 100644 --- a/src/can0/rximr0/mod.rs +++ b/src/can0/rximr0/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr1/mod.rs b/src/can0/rximr1/mod.rs index f9c8ab4..fb71a89 100644 --- a/src/can0/rximr1/mod.rs +++ b/src/can0/rximr1/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr10/mod.rs b/src/can0/rximr10/mod.rs index 7f61429..b43cc60 100644 --- a/src/can0/rximr10/mod.rs +++ b/src/can0/rximr10/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr11/mod.rs b/src/can0/rximr11/mod.rs index 20d5cdb..644a727 100644 --- a/src/can0/rximr11/mod.rs +++ b/src/can0/rximr11/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr12/mod.rs b/src/can0/rximr12/mod.rs index a3a94dd..779cda3 100644 --- a/src/can0/rximr12/mod.rs +++ b/src/can0/rximr12/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr13/mod.rs b/src/can0/rximr13/mod.rs index 974628a..b457c29 100644 --- a/src/can0/rximr13/mod.rs +++ b/src/can0/rximr13/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr14/mod.rs b/src/can0/rximr14/mod.rs index 193e9ae..d637965 100644 --- a/src/can0/rximr14/mod.rs +++ b/src/can0/rximr14/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr15/mod.rs b/src/can0/rximr15/mod.rs index 899ec96..8b60538 100644 --- a/src/can0/rximr15/mod.rs +++ b/src/can0/rximr15/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr2/mod.rs b/src/can0/rximr2/mod.rs index bffb2eb..b79c370 100644 --- a/src/can0/rximr2/mod.rs +++ b/src/can0/rximr2/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr3/mod.rs b/src/can0/rximr3/mod.rs index df84bb2..dc21ee1 100644 --- a/src/can0/rximr3/mod.rs +++ b/src/can0/rximr3/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr4/mod.rs b/src/can0/rximr4/mod.rs index d1ffc2a..2a5d5a7 100644 --- a/src/can0/rximr4/mod.rs +++ b/src/can0/rximr4/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr5/mod.rs b/src/can0/rximr5/mod.rs index 2d67f95..7500c7a 100644 --- a/src/can0/rximr5/mod.rs +++ b/src/can0/rximr5/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr6/mod.rs b/src/can0/rximr6/mod.rs index b5879da..c7582e2 100644 --- a/src/can0/rximr6/mod.rs +++ b/src/can0/rximr6/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr7/mod.rs b/src/can0/rximr7/mod.rs index 674dc6b..a5de575 100644 --- a/src/can0/rximr7/mod.rs +++ b/src/can0/rximr7/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr8/mod.rs b/src/can0/rximr8/mod.rs index 6fac312..626ec56 100644 --- a/src/can0/rximr8/mod.rs +++ b/src/can0/rximr8/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rximr9/mod.rs b/src/can0/rximr9/mod.rs index b21a830..4acd2f7 100644 --- a/src/can0/rximr9/mod.rs +++ b/src/can0/rximr9/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/rxmgmask/mod.rs b/src/can0/rxmgmask/mod.rs index da42c27..dc87f29 100644 --- a/src/can0/rxmgmask/mod.rs +++ b/src/can0/rxmgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXMGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/timer/mod.rs b/src/can0/timer/mod.rs index c5d0eb6..7a46bca 100644 --- a/src/can0/timer/mod.rs +++ b/src/can0/timer/mod.rs @@ -22,7 +22,9 @@ impl super::TIMER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can0/wmb0_cs/mod.rs b/src/can0/wmb0_cs/mod.rs index 4562128..fa731f4 100644 --- a/src/can0/wmb0_cs/mod.rs +++ b/src/can0/wmb0_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can0/wmb0_d03/mod.rs b/src/can0/wmb0_d03/mod.rs index 4d5dc99..90e28be 100644 --- a/src/can0/wmb0_d03/mod.rs +++ b/src/can0/wmb0_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb0_d47/mod.rs b/src/can0/wmb0_d47/mod.rs index b074c72..f567362 100644 --- a/src/can0/wmb0_d47/mod.rs +++ b/src/can0/wmb0_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb0_id/mod.rs b/src/can0/wmb0_id/mod.rs index 9621d2c..e76a1a5 100644 --- a/src/can0/wmb0_id/mod.rs +++ b/src/can0/wmb0_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb1_cs/mod.rs b/src/can0/wmb1_cs/mod.rs index 4c426aa..f54e732 100644 --- a/src/can0/wmb1_cs/mod.rs +++ b/src/can0/wmb1_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can0/wmb1_d03/mod.rs b/src/can0/wmb1_d03/mod.rs index 78d7079..7eb5aeb 100644 --- a/src/can0/wmb1_d03/mod.rs +++ b/src/can0/wmb1_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb1_d47/mod.rs b/src/can0/wmb1_d47/mod.rs index 3499051..b4df930 100644 --- a/src/can0/wmb1_d47/mod.rs +++ b/src/can0/wmb1_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb1_id/mod.rs b/src/can0/wmb1_id/mod.rs index c1e4593..5466ab1 100644 --- a/src/can0/wmb1_id/mod.rs +++ b/src/can0/wmb1_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb2_cs/mod.rs b/src/can0/wmb2_cs/mod.rs index df6e9c2..f37b0a2 100644 --- a/src/can0/wmb2_cs/mod.rs +++ b/src/can0/wmb2_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can0/wmb2_d03/mod.rs b/src/can0/wmb2_d03/mod.rs index 83ad28a..15406c4 100644 --- a/src/can0/wmb2_d03/mod.rs +++ b/src/can0/wmb2_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb2_d47/mod.rs b/src/can0/wmb2_d47/mod.rs index 0d57550..30b3c6b 100644 --- a/src/can0/wmb2_d47/mod.rs +++ b/src/can0/wmb2_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb2_id/mod.rs b/src/can0/wmb2_id/mod.rs index a4c67b3..c421aa6 100644 --- a/src/can0/wmb2_id/mod.rs +++ b/src/can0/wmb2_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb3_cs/mod.rs b/src/can0/wmb3_cs/mod.rs index 92c6dd9..05b7b1f 100644 --- a/src/can0/wmb3_cs/mod.rs +++ b/src/can0/wmb3_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can0/wmb3_d03/mod.rs b/src/can0/wmb3_d03/mod.rs index 064dfa5..64f4c8f 100644 --- a/src/can0/wmb3_d03/mod.rs +++ b/src/can0/wmb3_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb3_d47/mod.rs b/src/can0/wmb3_d47/mod.rs index 494d46c..a60b2ae 100644 --- a/src/can0/wmb3_d47/mod.rs +++ b/src/can0/wmb3_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wmb3_id/mod.rs b/src/can0/wmb3_id/mod.rs index 25d4e25..6b7ac79 100644 --- a/src/can0/wmb3_id/mod.rs +++ b/src/can0/wmb3_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can0/wu_mtc/mod.rs b/src/can0/wu_mtc/mod.rs index 30239c5..04c03ba 100644 --- a/src/can0/wu_mtc/mod.rs +++ b/src/can0/wu_mtc/mod.rs @@ -22,7 +22,9 @@ impl super::WU_MTC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl MCOUNTERR { #[doc = "Possible values of the field `WUMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMFR { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl WUMFR { #[doc = "Possible values of the field `WTOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOFR { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -147,10 +145,8 @@ impl WTOFR { } #[doc = "Values that can be written to the field `WUMF`"] pub enum WUMFW { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFW { #[allow(missing_docs)] @@ -205,10 +201,8 @@ impl<'a> _WUMFW<'a> { } #[doc = "Values that can be written to the field `WTOF`"] pub enum WTOFW { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFW { #[allow(missing_docs)] diff --git a/src/can1/cbt/mod.rs b/src/can1/cbt/mod.rs index f421eda..cb70aeb 100644 --- a/src/can1/cbt/mod.rs +++ b/src/can1/cbt/mod.rs @@ -22,7 +22,9 @@ impl super::CBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -98,10 +100,8 @@ impl EPRESDIVR { #[doc = "Possible values of the field `BTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BTFR { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -219,10 +219,8 @@ impl<'a> _EPRESDIVW<'a> { } #[doc = "Values that can be written to the field `BTF`"] pub enum BTFW { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFW { #[allow(missing_docs)] diff --git a/src/can1/crcr/mod.rs b/src/can1/crcr/mod.rs index 4235705..07b066c 100644 --- a/src/can1/crcr/mod.rs +++ b/src/can1/crcr/mod.rs @@ -6,7 +6,9 @@ impl super::CRCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/ctrl1/mod.rs b/src/can1/ctrl1/mod.rs index 95f49d5..ad0efed 100644 --- a/src/can1/ctrl1/mod.rs +++ b/src/can1/ctrl1/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl PROPSEGR { #[doc = "Possible values of the field `LOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOMR { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl LOMR { #[doc = "Possible values of the field `LBUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBUFR { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl LBUFR { #[doc = "Possible values of the field `TSYN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSYNR { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl TSYNR { #[doc = "Possible values of the field `BOFFREC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFRECR { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl BOFFRECR { #[doc = "Possible values of the field `SMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMPR { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -289,10 +282,8 @@ impl SMPR { #[doc = "Possible values of the field `RWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNMSKR { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -336,10 +327,8 @@ impl RWRNMSKR { #[doc = "Possible values of the field `TWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNMSKR { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -383,10 +372,8 @@ impl TWRNMSKR { #[doc = "Possible values of the field `LPB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPBR { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +419,7 @@ impl LPBR { pub enum CLKSRCR { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +463,8 @@ impl CLKSRCR { #[doc = "Possible values of the field `ERRMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSKR { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +508,8 @@ impl ERRMSKR { #[doc = "Possible values of the field `BOFFMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFMSKR { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -629,10 +611,8 @@ impl<'a> _PROPSEGW<'a> { } #[doc = "Values that can be written to the field `LOM`"] pub enum LOMW { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMW { #[allow(missing_docs)] @@ -687,10 +667,8 @@ impl<'a> _LOMW<'a> { } #[doc = "Values that can be written to the field `LBUF`"] pub enum LBUFW { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFW { #[allow(missing_docs)] @@ -745,10 +723,8 @@ impl<'a> _LBUFW<'a> { } #[doc = "Values that can be written to the field `TSYN`"] pub enum TSYNW { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNW { #[allow(missing_docs)] @@ -803,10 +779,8 @@ impl<'a> _TSYNW<'a> { } #[doc = "Values that can be written to the field `BOFFREC`"] pub enum BOFFRECW { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECW { #[allow(missing_docs)] @@ -861,8 +835,7 @@ impl<'a> _BOFFRECW<'a> { } #[doc = "Values that can be written to the field `SMP`"] pub enum SMPW { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -919,10 +892,8 @@ impl<'a> _SMPW<'a> { } #[doc = "Values that can be written to the field `RWRNMSK`"] pub enum RWRNMSKW { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKW { #[allow(missing_docs)] @@ -977,10 +948,8 @@ impl<'a> _RWRNMSKW<'a> { } #[doc = "Values that can be written to the field `TWRNMSK`"] pub enum TWRNMSKW { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKW { #[allow(missing_docs)] @@ -1035,10 +1004,8 @@ impl<'a> _TWRNMSKW<'a> { } #[doc = "Values that can be written to the field `LPB`"] pub enum LPBW { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBW { #[allow(missing_docs)] @@ -1095,8 +1062,7 @@ impl<'a> _LPBW<'a> { pub enum CLKSRCW { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCW { #[allow(missing_docs)] @@ -1151,10 +1117,8 @@ impl<'a> _CLKSRCW<'a> { } #[doc = "Values that can be written to the field `ERRMSK`"] pub enum ERRMSKW { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKW { #[allow(missing_docs)] @@ -1209,10 +1173,8 @@ impl<'a> _ERRMSKW<'a> { } #[doc = "Values that can be written to the field `BOFFMSK`"] pub enum BOFFMSKW { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKW { #[allow(missing_docs)] diff --git a/src/can1/ctrl1_pn/mod.rs b/src/can1/ctrl1_pn/mod.rs index 0fe8a14..dc76bb4 100644 --- a/src/can1/ctrl1_pn/mod.rs +++ b/src/can1/ctrl1_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CTRL1_PN { #[doc = "Possible values of the field `FCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCSR { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSR { #[doc = r" Value of the field as raw bits"] @@ -99,12 +97,9 @@ impl FCSR { #[doc = "Possible values of the field `IDFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDFSR { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -155,12 +150,9 @@ impl IDFSR { #[doc = "Possible values of the field `PLFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLFSR { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -217,8 +209,7 @@ pub enum NMATCHR { _00000010, #[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."] _11111111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl NMATCHR { #[doc = r" Value of the field as raw bits"] @@ -261,10 +252,8 @@ impl NMATCHR { #[doc = "Possible values of the field `WUMF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMF_MSKR { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -308,10 +297,8 @@ impl WUMF_MSKR { #[doc = "Possible values of the field `WTOF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOF_MSKR { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -354,14 +341,10 @@ impl WTOF_MSKR { } #[doc = "Values that can be written to the field `FCS`"] pub enum FCSW { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSW { #[allow(missing_docs)] @@ -420,12 +403,9 @@ impl<'a> _FCSW<'a> { } #[doc = "Values that can be written to the field `IDFS`"] pub enum IDFSW { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -486,12 +466,9 @@ impl<'a> _IDFSW<'a> { } #[doc = "Values that can be written to the field `PLFS`"] pub enum PLFSW { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -608,10 +585,8 @@ impl<'a> _NMATCHW<'a> { } #[doc = "Values that can be written to the field `WUMF_MSK`"] pub enum WUMF_MSKW { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKW { #[allow(missing_docs)] @@ -666,10 +641,8 @@ impl<'a> _WUMF_MSKW<'a> { } #[doc = "Values that can be written to the field `WTOF_MSK`"] pub enum WTOF_MSKW { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKW { #[allow(missing_docs)] diff --git a/src/can1/ctrl2/mod.rs b/src/can1/ctrl2/mod.rs index fcb2804..dfec61f 100644 --- a/src/can1/ctrl2/mod.rs +++ b/src/can1/ctrl2/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL2 { #[doc = "Possible values of the field `EDFLTDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDFLTDISR { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EDFLTDISR { #[doc = "Possible values of the field `ISOCANFDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISOCANFDENR { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ISOCANFDENR { #[doc = "Possible values of the field `PREXCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PREXCENR { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +274,8 @@ impl EACENR { #[doc = "Possible values of the field `RRS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RRSR { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +319,8 @@ impl RRSR { #[doc = "Possible values of the field `MRP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MRPR { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +386,8 @@ impl RFFNR { #[doc = "Possible values of the field `BOFFDONEMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEMSKR { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +431,8 @@ impl BOFFDONEMSKR { #[doc = "Possible values of the field `ERRMSK_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSK_FASTR { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -487,10 +475,8 @@ impl ERRMSK_FASTR { } #[doc = "Values that can be written to the field `EDFLTDIS`"] pub enum EDFLTDISW { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISW { #[allow(missing_docs)] @@ -545,10 +531,8 @@ impl<'a> _EDFLTDISW<'a> { } #[doc = "Values that can be written to the field `ISOCANFDEN`"] pub enum ISOCANFDENW { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENW { #[allow(missing_docs)] @@ -603,10 +587,8 @@ impl<'a> _ISOCANFDENW<'a> { } #[doc = "Values that can be written to the field `PREXCEN`"] pub enum PREXCENW { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENW { #[allow(missing_docs)] @@ -777,10 +759,8 @@ impl<'a> _EACENW<'a> { } #[doc = "Values that can be written to the field `RRS`"] pub enum RRSW { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSW { #[allow(missing_docs)] @@ -835,10 +815,8 @@ impl<'a> _RRSW<'a> { } #[doc = "Values that can be written to the field `MRP`"] pub enum MRPW { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPW { #[allow(missing_docs)] @@ -923,10 +901,8 @@ impl<'a> _RFFNW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEMSK`"] pub enum BOFFDONEMSKW { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKW { #[allow(missing_docs)] @@ -981,10 +957,8 @@ impl<'a> _BOFFDONEMSKW<'a> { } #[doc = "Values that can be written to the field `ERRMSK_FAST`"] pub enum ERRMSK_FASTW { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTW { #[allow(missing_docs)] diff --git a/src/can1/ctrl2_pn/mod.rs b/src/can1/ctrl2_pn/mod.rs index 01029c8..7831ff2 100644 --- a/src/can1/ctrl2_pn/mod.rs +++ b/src/can1/ctrl2_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/ecr/mod.rs b/src/can1/ecr/mod.rs index ab42b4e..22c7322 100644 --- a/src/can1/ecr/mod.rs +++ b/src/can1/ecr/mod.rs @@ -22,7 +22,9 @@ impl super::ECR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/embedded_ram/mod.rs b/src/can1/embedded_ram/mod.rs index 91a2c94..5fe0f4f 100644 --- a/src/can1/embedded_ram/mod.rs +++ b/src/can1/embedded_ram/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/esr1/mod.rs b/src/can1/esr1/mod.rs index f1f6be4..4798194 100644 --- a/src/can1/esr1/mod.rs +++ b/src/can1/esr1/mod.rs @@ -22,7 +22,9 @@ impl super::ESR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ESR1 { #[doc = "Possible values of the field `ERRINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERRINTR { #[doc = "Possible values of the field `BOFFINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl BOFFINTR { #[doc = "Possible values of the field `RX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXR { - #[doc = "FlexCAN is not receiving a message."] - _0, - #[doc = "FlexCAN is receiving a message."] - _1, + #[doc = "FlexCAN is not receiving a message."] _0, + #[doc = "FlexCAN is receiving a message."] _1, } impl RXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,14 +180,10 @@ impl RXR { #[doc = "Possible values of the field `FLTCONF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTCONFR { - #[doc = "Error Active"] - _00, - #[doc = "Error Passive"] - _01, - #[doc = "Bus Off"] - _1X, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Error Active"] _00, + #[doc = "Error Passive"] _01, + #[doc = "Bus Off"] _1X, + #[doc = r" Reserved"] _Reserved(u8), } impl FLTCONFR { #[doc = r" Value of the field as raw bits"] @@ -234,10 +226,8 @@ impl FLTCONFR { #[doc = "Possible values of the field `TX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXR { - #[doc = "FlexCAN is not transmitting a message."] - _0, - #[doc = "FlexCAN is transmitting a message."] - _1, + #[doc = "FlexCAN is not transmitting a message."] _0, + #[doc = "FlexCAN is transmitting a message."] _1, } impl TXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -281,10 +271,8 @@ impl TXR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No such occurrence."] - _0, - #[doc = "CAN bus is now IDLE."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "CAN bus is now IDLE."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -328,10 +316,8 @@ impl IDLER { #[doc = "Possible values of the field `RXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "RXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "RXERRCNT is greater than or equal to 96."] _1, } impl RXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -375,10 +361,8 @@ impl RXWRNR { #[doc = "Possible values of the field `TXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "TXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "TXERRCNT is greater than or equal to 96."] _1, } impl TXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -422,10 +406,8 @@ impl TXWRNR { #[doc = "Possible values of the field `STFERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -469,10 +451,8 @@ impl STFERRR { #[doc = "Possible values of the field `FRMERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -516,10 +496,8 @@ impl FRMERRR { #[doc = "Possible values of the field `CRCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -563,10 +541,8 @@ impl CRCERRR { #[doc = "Possible values of the field `ACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACKERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "An ACK error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "An ACK error occurred since last read of this register."] _1, } impl ACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -610,10 +586,8 @@ impl ACKERRR { #[doc = "Possible values of the field `BIT0ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -657,10 +631,8 @@ impl BIT0ERRR { #[doc = "Possible values of the field `BIT1ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -704,8 +676,7 @@ impl BIT1ERRR { #[doc = "Possible values of the field `RWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -751,8 +722,7 @@ impl RWRNINTR { #[doc = "Possible values of the field `TWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -798,10 +768,8 @@ impl TWRNINTR { #[doc = "Possible values of the field `SYNCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCHR { - #[doc = "FlexCAN is not synchronized to the CAN bus."] - _0, - #[doc = "FlexCAN is synchronized to the CAN bus."] - _1, + #[doc = "FlexCAN is not synchronized to the CAN bus."] _0, + #[doc = "FlexCAN is synchronized to the CAN bus."] _1, } impl SYNCHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -845,10 +813,8 @@ impl SYNCHR { #[doc = "Possible values of the field `BOFFDONEINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,8 +858,7 @@ impl BOFFDONEINTR { #[doc = "Possible values of the field `ERRINT_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINT_FASTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -939,10 +904,8 @@ impl ERRINT_FASTR { #[doc = "Possible values of the field `ERROVR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERROVRR { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -986,10 +949,8 @@ impl ERROVRR { #[doc = "Possible values of the field `STFERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1033,10 +994,8 @@ impl STFERR_FASTR { #[doc = "Possible values of the field `FRMERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1080,10 +1039,8 @@ impl FRMERR_FASTR { #[doc = "Possible values of the field `CRCERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1127,10 +1084,8 @@ impl CRCERR_FASTR { #[doc = "Possible values of the field `BIT0ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1174,10 +1129,8 @@ impl BIT0ERR_FASTR { #[doc = "Possible values of the field `BIT1ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1220,10 +1173,8 @@ impl BIT1ERR_FASTR { } #[doc = "Values that can be written to the field `ERRINT`"] pub enum ERRINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTW { #[allow(missing_docs)] @@ -1278,10 +1229,8 @@ impl<'a> _ERRINTW<'a> { } #[doc = "Values that can be written to the field `BOFFINT`"] pub enum BOFFINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTW { #[allow(missing_docs)] @@ -1336,8 +1285,7 @@ impl<'a> _BOFFINTW<'a> { } #[doc = "Values that can be written to the field `RWRNINT`"] pub enum RWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1394,8 +1342,7 @@ impl<'a> _RWRNINTW<'a> { } #[doc = "Values that can be written to the field `TWRNINT`"] pub enum TWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1452,10 +1399,8 @@ impl<'a> _TWRNINTW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEINT`"] pub enum BOFFDONEINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTW { #[allow(missing_docs)] @@ -1510,8 +1455,7 @@ impl<'a> _BOFFDONEINTW<'a> { } #[doc = "Values that can be written to the field `ERRINT_FAST`"] pub enum ERRINT_FASTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -1568,10 +1512,8 @@ impl<'a> _ERRINT_FASTW<'a> { } #[doc = "Values that can be written to the field `ERROVR`"] pub enum ERROVRW { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRW { #[allow(missing_docs)] diff --git a/src/can1/esr2/mod.rs b/src/can1/esr2/mod.rs index d4f29f2..8f2635b 100644 --- a/src/can1/esr2/mod.rs +++ b/src/can1/esr2/mod.rs @@ -6,14 +6,15 @@ impl super::ESR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `IMB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IMBR { - #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] - _0, + #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] _0, #[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."] _1, } @@ -59,10 +60,8 @@ impl IMBR { #[doc = "Possible values of the field `VPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VPSR { - #[doc = "Contents of IMB and LPTM are invalid."] - _0, - #[doc = "Contents of IMB and LPTM are valid."] - _1, + #[doc = "Contents of IMB and LPTM are invalid."] _0, + #[doc = "Contents of IMB and LPTM are valid."] _1, } impl VPSR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can1/fdcbt/mod.rs b/src/can1/fdcbt/mod.rs index d5b4147..0ddab6e 100644 --- a/src/can1/fdcbt/mod.rs +++ b/src/can1/fdcbt/mod.rs @@ -22,7 +22,9 @@ impl super::FDCBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/fdcrc/mod.rs b/src/can1/fdcrc/mod.rs index b213def..d0da073 100644 --- a/src/can1/fdcrc/mod.rs +++ b/src/can1/fdcrc/mod.rs @@ -6,7 +6,9 @@ impl super::FDCRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/fdctrl/mod.rs b/src/can1/fdctrl/mod.rs index e337ada..cf39ab2 100644 --- a/src/can1/fdctrl/mod.rs +++ b/src/can1/fdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl TDCOFFR { #[doc = "Possible values of the field `TDCFAIL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCFAILR { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl TDCFAILR { #[doc = "Possible values of the field `TDCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCENR { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -159,14 +157,10 @@ impl TDCENR { #[doc = "Possible values of the field `MBDSR0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBDSR0R { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0R { #[doc = r" Value of the field as raw bits"] @@ -215,10 +209,8 @@ impl MBDSR0R { #[doc = "Possible values of the field `FDRATE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FDRATER { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -276,10 +268,8 @@ impl<'a> _TDCOFFW<'a> { } #[doc = "Values that can be written to the field `TDCFAIL`"] pub enum TDCFAILW { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILW { #[allow(missing_docs)] @@ -334,10 +324,8 @@ impl<'a> _TDCFAILW<'a> { } #[doc = "Values that can be written to the field `TDCEN`"] pub enum TDCENW { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENW { #[allow(missing_docs)] @@ -392,14 +380,10 @@ impl<'a> _TDCENW<'a> { } #[doc = "Values that can be written to the field `MBDSR0`"] pub enum MBDSR0W { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0W { #[allow(missing_docs)] @@ -458,10 +442,8 @@ impl<'a> _MBDSR0W<'a> { } #[doc = "Values that can be written to the field `FDRATE`"] pub enum FDRATEW { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATEW { #[allow(missing_docs)] diff --git a/src/can1/flt_dlc/mod.rs b/src/can1/flt_dlc/mod.rs index 74c52b5..db8cb41 100644 --- a/src/can1/flt_dlc/mod.rs +++ b/src/can1/flt_dlc/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_DLC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/flt_id1/mod.rs b/src/can1/flt_id1/mod.rs index 7af09e6..528a567 100644 --- a/src/can1/flt_id1/mod.rs +++ b/src/can1/flt_id1/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID1R { #[doc = "Possible values of the field `FLT_RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_RTRR { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl FLT_RTRR { #[doc = "Possible values of the field `FLT_IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_IDER { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID1W<'a> { } #[doc = "Values that can be written to the field `FLT_RTR`"] pub enum FLT_RTRW { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _FLT_RTRW<'a> { } #[doc = "Values that can be written to the field `FLT_IDE`"] pub enum FLT_IDEW { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDEW { #[allow(missing_docs)] diff --git a/src/can1/flt_id2_idmask/mod.rs b/src/can1/flt_id2_idmask/mod.rs index e836809..66cd275 100644 --- a/src/can1/flt_id2_idmask/mod.rs +++ b/src/can1/flt_id2_idmask/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID2_IDMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID2_IDMASKR { #[doc = "Possible values of the field `RTR_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTR_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl RTR_MSKR { #[doc = "Possible values of the field `IDE_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDE_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID2_IDMASKW<'a> { } #[doc = "Values that can be written to the field `RTR_MSK`"] pub enum RTR_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _RTR_MSKW<'a> { } #[doc = "Values that can be written to the field `IDE_MSK`"] pub enum IDE_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKW { #[allow(missing_docs)] diff --git a/src/can1/iflag1/mod.rs b/src/can1/iflag1/mod.rs index 62b4c8f..20a7322 100644 --- a/src/can1/iflag1/mod.rs +++ b/src/can1/iflag1/mod.rs @@ -22,7 +22,9 @@ impl super::IFLAG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/imask1/mod.rs b/src/can1/imask1/mod.rs index b6debac..1f67ed9 100644 --- a/src/can1/imask1/mod.rs +++ b/src/can1/imask1/mod.rs @@ -22,7 +22,9 @@ impl super::IMASK1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/mcr/mod.rs b/src/can1/mcr/mod.rs index 0f6af62..3c5653b 100644 --- a/src/can1/mcr/mod.rs +++ b/src/can1/mcr/mod.rs @@ -22,7 +22,9 @@ impl super::MCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,11 @@ impl MAXMBR { #[doc = "Possible values of the field `IDAM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDAMR { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMR { #[doc = r" Value of the field as raw bits"] @@ -157,10 +156,8 @@ impl FDENR { #[doc = "Possible values of the field `AEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AENR { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -204,10 +201,8 @@ impl AENR { #[doc = "Possible values of the field `LPRIOEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPRIOENR { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -251,10 +246,8 @@ impl LPRIOENR { #[doc = "Possible values of the field `PNET_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PNET_ENR { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -298,10 +291,8 @@ impl PNET_ENR { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -347,8 +338,7 @@ impl DMAR { pub enum IRMQR { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -392,10 +382,8 @@ impl IRMQR { #[doc = "Possible values of the field `SRXDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRXDISR { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -439,10 +427,8 @@ impl SRXDISR { #[doc = "Possible values of the field `LPMACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPMACKR { - #[doc = "FlexCAN is not in a low-power mode."] - _0, - #[doc = "FlexCAN is in a low-power mode."] - _1, + #[doc = "FlexCAN is not in a low-power mode."] _0, + #[doc = "FlexCAN is in a low-power mode."] _1, } impl LPMACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -554,10 +540,8 @@ impl SUPVR { #[doc = "Possible values of the field `FRZACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZACKR { - #[doc = "FlexCAN not in Freeze mode, prescaler running."] - _0, - #[doc = "FlexCAN in Freeze mode, prescaler stopped."] - _1, + #[doc = "FlexCAN not in Freeze mode, prescaler running."] _0, + #[doc = "FlexCAN in Freeze mode, prescaler stopped."] _1, } impl FRZACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -601,10 +585,8 @@ impl FRZACKR { #[doc = "Possible values of the field `SOFTRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFTRSTR { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +630,8 @@ impl SOFTRSTR { #[doc = "Possible values of the field `NOTRDY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOTRDYR { - #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl NOTRDYR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -690,10 +670,8 @@ impl NOTRDYR { #[doc = "Possible values of the field `HALT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HALTR { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -737,10 +715,8 @@ impl HALTR { #[doc = "Possible values of the field `RFEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFENR { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -784,10 +760,8 @@ impl RFENR { #[doc = "Possible values of the field `FRZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZR { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -831,10 +805,8 @@ impl FRZR { #[doc = "Possible values of the field `MDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MDISR { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,14 +864,11 @@ impl<'a> _MAXMBW<'a> { } #[doc = "Values that can be written to the field `IDAM`"] pub enum IDAMW { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMW { #[allow(missing_docs)] @@ -1016,10 +985,8 @@ impl<'a> _FDENW<'a> { } #[doc = "Values that can be written to the field `AEN`"] pub enum AENW { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENW { #[allow(missing_docs)] @@ -1074,10 +1041,8 @@ impl<'a> _AENW<'a> { } #[doc = "Values that can be written to the field `LPRIOEN`"] pub enum LPRIOENW { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENW { #[allow(missing_docs)] @@ -1132,10 +1097,8 @@ impl<'a> _LPRIOENW<'a> { } #[doc = "Values that can be written to the field `PNET_EN`"] pub enum PNET_ENW { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENW { #[allow(missing_docs)] @@ -1190,10 +1153,8 @@ impl<'a> _PNET_ENW<'a> { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAW { #[allow(missing_docs)] @@ -1250,8 +1211,7 @@ impl<'a> _DMAW<'a> { pub enum IRMQW { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQW { #[allow(missing_docs)] @@ -1306,10 +1266,8 @@ impl<'a> _IRMQW<'a> { } #[doc = "Values that can be written to the field `SRXDIS`"] pub enum SRXDISW { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISW { #[allow(missing_docs)] @@ -1445,10 +1403,8 @@ impl<'a> _SUPVW<'a> { } #[doc = "Values that can be written to the field `SOFTRST`"] pub enum SOFTRSTW { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTW { #[allow(missing_docs)] @@ -1503,10 +1459,8 @@ impl<'a> _SOFTRSTW<'a> { } #[doc = "Values that can be written to the field `HALT`"] pub enum HALTW { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTW { #[allow(missing_docs)] @@ -1561,10 +1515,8 @@ impl<'a> _HALTW<'a> { } #[doc = "Values that can be written to the field `RFEN`"] pub enum RFENW { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENW { #[allow(missing_docs)] @@ -1619,10 +1571,8 @@ impl<'a> _RFENW<'a> { } #[doc = "Values that can be written to the field `FRZ`"] pub enum FRZW { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZW { #[allow(missing_docs)] @@ -1677,10 +1627,8 @@ impl<'a> _FRZW<'a> { } #[doc = "Values that can be written to the field `MDIS`"] pub enum MDISW { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISW { #[allow(missing_docs)] diff --git a/src/can1/mod.rs b/src/can1/mod.rs index bd086bc..054059d 100644 --- a/src/can1/mod.rs +++ b/src/can1/mod.rs @@ -2,93 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Module Configuration Register"] - pub mcr: MCR, - #[doc = "0x04 - Control 1 register"] - pub ctrl1: CTRL1, - #[doc = "0x08 - Free Running Timer"] - pub timer: TIMER, + #[doc = "0x00 - Module Configuration Register"] pub mcr: MCR, + #[doc = "0x04 - Control 1 register"] pub ctrl1: CTRL1, + #[doc = "0x08 - Free Running Timer"] pub timer: TIMER, _reserved0: [u8; 4usize], - #[doc = "0x10 - Rx Mailboxes Global Mask Register"] - pub rxmgmask: RXMGMASK, - #[doc = "0x14 - Rx 14 Mask register"] - pub rx14mask: RX14MASK, - #[doc = "0x18 - Rx 15 Mask register"] - pub rx15mask: RX15MASK, - #[doc = "0x1c - Error Counter"] - pub ecr: ECR, - #[doc = "0x20 - Error and Status 1 register"] - pub esr1: ESR1, + #[doc = "0x10 - Rx Mailboxes Global Mask Register"] pub rxmgmask: RXMGMASK, + #[doc = "0x14 - Rx 14 Mask register"] pub rx14mask: RX14MASK, + #[doc = "0x18 - Rx 15 Mask register"] pub rx15mask: RX15MASK, + #[doc = "0x1c - Error Counter"] pub ecr: ECR, + #[doc = "0x20 - Error and Status 1 register"] pub esr1: ESR1, _reserved1: [u8; 4usize], - #[doc = "0x28 - Interrupt Masks 1 register"] - pub imask1: IMASK1, + #[doc = "0x28 - Interrupt Masks 1 register"] pub imask1: IMASK1, _reserved2: [u8; 4usize], - #[doc = "0x30 - Interrupt Flags 1 register"] - pub iflag1: IFLAG1, - #[doc = "0x34 - Control 2 register"] - pub ctrl2: CTRL2, - #[doc = "0x38 - Error and Status 2 register"] - pub esr2: ESR2, + #[doc = "0x30 - Interrupt Flags 1 register"] pub iflag1: IFLAG1, + #[doc = "0x34 - Control 2 register"] pub ctrl2: CTRL2, + #[doc = "0x38 - Error and Status 2 register"] pub esr2: ESR2, _reserved3: [u8; 8usize], - #[doc = "0x44 - CRC Register"] - pub crcr: CRCR, - #[doc = "0x48 - Rx FIFO Global Mask register"] - pub rxfgmask: RXFGMASK, - #[doc = "0x4c - Rx FIFO Information Register"] - pub rxfir: RXFIR, - #[doc = "0x50 - CAN Bit Timing Register"] - pub cbt: CBT, + #[doc = "0x44 - CRC Register"] pub crcr: CRCR, + #[doc = "0x48 - Rx FIFO Global Mask register"] pub rxfgmask: RXFGMASK, + #[doc = "0x4c - Rx FIFO Information Register"] pub rxfir: RXFIR, + #[doc = "0x50 - CAN Bit Timing Register"] pub cbt: CBT, _reserved4: [u8; 44usize], - #[doc = "0x80 - Embedded RAM"] - pub embedded_ram: [EMBEDDEDRAM; 128], + #[doc = "0x80 - Embedded RAM"] pub embedded_ram: [EMBEDDEDRAM; 128], _reserved5: [u8; 1536usize], - #[doc = "0x880 - Rx Individual Mask Registers"] - pub rximr0: RXIMR0, - #[doc = "0x884 - Rx Individual Mask Registers"] - pub rximr1: RXIMR1, - #[doc = "0x888 - Rx Individual Mask Registers"] - pub rximr2: RXIMR2, - #[doc = "0x88c - Rx Individual Mask Registers"] - pub rximr3: RXIMR3, - #[doc = "0x890 - Rx Individual Mask Registers"] - pub rximr4: RXIMR4, - #[doc = "0x894 - Rx Individual Mask Registers"] - pub rximr5: RXIMR5, - #[doc = "0x898 - Rx Individual Mask Registers"] - pub rximr6: RXIMR6, - #[doc = "0x89c - Rx Individual Mask Registers"] - pub rximr7: RXIMR7, - #[doc = "0x8a0 - Rx Individual Mask Registers"] - pub rximr8: RXIMR8, - #[doc = "0x8a4 - Rx Individual Mask Registers"] - pub rximr9: RXIMR9, - #[doc = "0x8a8 - Rx Individual Mask Registers"] - pub rximr10: RXIMR10, - #[doc = "0x8ac - Rx Individual Mask Registers"] - pub rximr11: RXIMR11, - #[doc = "0x8b0 - Rx Individual Mask Registers"] - pub rximr12: RXIMR12, - #[doc = "0x8b4 - Rx Individual Mask Registers"] - pub rximr13: RXIMR13, - #[doc = "0x8b8 - Rx Individual Mask Registers"] - pub rximr14: RXIMR14, - #[doc = "0x8bc - Rx Individual Mask Registers"] - pub rximr15: RXIMR15, + #[doc = "0x880 - Rx Individual Mask Registers"] pub rximr0: RXIMR0, + #[doc = "0x884 - Rx Individual Mask Registers"] pub rximr1: RXIMR1, + #[doc = "0x888 - Rx Individual Mask Registers"] pub rximr2: RXIMR2, + #[doc = "0x88c - Rx Individual Mask Registers"] pub rximr3: RXIMR3, + #[doc = "0x890 - Rx Individual Mask Registers"] pub rximr4: RXIMR4, + #[doc = "0x894 - Rx Individual Mask Registers"] pub rximr5: RXIMR5, + #[doc = "0x898 - Rx Individual Mask Registers"] pub rximr6: RXIMR6, + #[doc = "0x89c - Rx Individual Mask Registers"] pub rximr7: RXIMR7, + #[doc = "0x8a0 - Rx Individual Mask Registers"] pub rximr8: RXIMR8, + #[doc = "0x8a4 - Rx Individual Mask Registers"] pub rximr9: RXIMR9, + #[doc = "0x8a8 - Rx Individual Mask Registers"] pub rximr10: RXIMR10, + #[doc = "0x8ac - Rx Individual Mask Registers"] pub rximr11: RXIMR11, + #[doc = "0x8b0 - Rx Individual Mask Registers"] pub rximr12: RXIMR12, + #[doc = "0x8b4 - Rx Individual Mask Registers"] pub rximr13: RXIMR13, + #[doc = "0x8b8 - Rx Individual Mask Registers"] pub rximr14: RXIMR14, + #[doc = "0x8bc - Rx Individual Mask Registers"] pub rximr15: RXIMR15, _reserved6: [u8; 576usize], - #[doc = "0xb00 - Pretended Networking Control 1 Register"] - pub ctrl1_pn: CTRL1_PN, - #[doc = "0xb04 - Pretended Networking Control 2 Register"] - pub ctrl2_pn: CTRL2_PN, - #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] - pub wu_mtc: WU_MTC, - #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] - pub flt_id1: FLT_ID1, - #[doc = "0xb10 - Pretended Networking DLC Filter Register"] - pub flt_dlc: FLT_DLC, - #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] - pub pl1_lo: PL1_LO, - #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] - pub pl1_hi: PL1_HI, + #[doc = "0xb00 - Pretended Networking Control 1 Register"] pub ctrl1_pn: CTRL1_PN, + #[doc = "0xb04 - Pretended Networking Control 2 Register"] pub ctrl2_pn: CTRL2_PN, + #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] pub wu_mtc: WU_MTC, + #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] pub flt_id1: FLT_ID1, + #[doc = "0xb10 - Pretended Networking DLC Filter Register"] pub flt_dlc: FLT_DLC, + #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] pub pl1_lo: PL1_LO, + #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] pub pl1_hi: PL1_HI, #[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"] pub flt_id2_idmask: FLT_ID2_IDMASK, #[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"] @@ -96,45 +56,26 @@ pub struct RegisterBlock { #[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"] pub pl2_plmask_hi: PL2_PLMASK_HI, _reserved7: [u8; 24usize], - #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] - pub wmb0_cs: WMB0_CS, - #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] - pub wmb0_id: WMB0_ID, - #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb0_d03: WMB0_D03, - #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] - pub wmb0_d47: WMB0_D47, - #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] - pub wmb1_cs: WMB1_CS, - #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] - pub wmb1_id: WMB1_ID, - #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb1_d03: WMB1_D03, - #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] - pub wmb1_d47: WMB1_D47, - #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] - pub wmb2_cs: WMB2_CS, - #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] - pub wmb2_id: WMB2_ID, - #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb2_d03: WMB2_D03, - #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] - pub wmb2_d47: WMB2_D47, - #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] - pub wmb3_cs: WMB3_CS, - #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] - pub wmb3_id: WMB3_ID, - #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb3_d03: WMB3_D03, - #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] - pub wmb3_d47: WMB3_D47, + #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] pub wmb0_cs: WMB0_CS, + #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] pub wmb0_id: WMB0_ID, + #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] pub wmb0_d03: WMB0_D03, + #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] pub wmb0_d47: WMB0_D47, + #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] pub wmb1_cs: WMB1_CS, + #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] pub wmb1_id: WMB1_ID, + #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] pub wmb1_d03: WMB1_D03, + #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] pub wmb1_d47: WMB1_D47, + #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] pub wmb2_cs: WMB2_CS, + #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] pub wmb2_id: WMB2_ID, + #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] pub wmb2_d03: WMB2_D03, + #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] pub wmb2_d47: WMB2_D47, + #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] pub wmb3_cs: WMB3_CS, + #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] pub wmb3_id: WMB3_ID, + #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] pub wmb3_d03: WMB3_D03, + #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] pub wmb3_d47: WMB3_D47, _reserved8: [u8; 128usize], - #[doc = "0xc00 - CAN FD Control Register"] - pub fdctrl: FDCTRL, - #[doc = "0xc04 - CAN FD Bit Timing Register"] - pub fdcbt: FDCBT, - #[doc = "0xc08 - CAN FD CRC Register"] - pub fdcrc: FDCRC, + #[doc = "0xc00 - CAN FD Control Register"] pub fdctrl: FDCTRL, + #[doc = "0xc04 - CAN FD Bit Timing Register"] pub fdcbt: FDCBT, + #[doc = "0xc08 - CAN FD CRC Register"] pub fdcrc: FDCRC, } #[doc = "Module Configuration Register"] pub struct MCR { diff --git a/src/can1/pl1_hi/mod.rs b/src/can1/pl1_hi/mod.rs index 7b090b3..ab431b7 100644 --- a/src/can1/pl1_hi/mod.rs +++ b/src/can1/pl1_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/pl1_lo/mod.rs b/src/can1/pl1_lo/mod.rs index 363ae74..6e07f19 100644 --- a/src/can1/pl1_lo/mod.rs +++ b/src/can1/pl1_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/pl2_plmask_hi/mod.rs b/src/can1/pl2_plmask_hi/mod.rs index f4943ba..32cc6bd 100644 --- a/src/can1/pl2_plmask_hi/mod.rs +++ b/src/can1/pl2_plmask_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/pl2_plmask_lo/mod.rs b/src/can1/pl2_plmask_lo/mod.rs index eb939de..358d16f 100644 --- a/src/can1/pl2_plmask_lo/mod.rs +++ b/src/can1/pl2_plmask_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rx14mask/mod.rs b/src/can1/rx14mask/mod.rs index 068409e..5670ed6 100644 --- a/src/can1/rx14mask/mod.rs +++ b/src/can1/rx14mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX14MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rx15mask/mod.rs b/src/can1/rx15mask/mod.rs index 5f05ad1..e97bce8 100644 --- a/src/can1/rx15mask/mod.rs +++ b/src/can1/rx15mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX15MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rxfgmask/mod.rs b/src/can1/rxfgmask/mod.rs index 2cafbce..db4555e 100644 --- a/src/can1/rxfgmask/mod.rs +++ b/src/can1/rxfgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXFGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rxfir/mod.rs b/src/can1/rxfir/mod.rs index 50db283..2221db3 100644 --- a/src/can1/rxfir/mod.rs +++ b/src/can1/rxfir/mod.rs @@ -6,7 +6,9 @@ impl super::RXFIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/rximr0/mod.rs b/src/can1/rximr0/mod.rs index 9632744..301c690 100644 --- a/src/can1/rximr0/mod.rs +++ b/src/can1/rximr0/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr1/mod.rs b/src/can1/rximr1/mod.rs index f9c8ab4..fb71a89 100644 --- a/src/can1/rximr1/mod.rs +++ b/src/can1/rximr1/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr10/mod.rs b/src/can1/rximr10/mod.rs index 7f61429..b43cc60 100644 --- a/src/can1/rximr10/mod.rs +++ b/src/can1/rximr10/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr11/mod.rs b/src/can1/rximr11/mod.rs index 20d5cdb..644a727 100644 --- a/src/can1/rximr11/mod.rs +++ b/src/can1/rximr11/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr12/mod.rs b/src/can1/rximr12/mod.rs index a3a94dd..779cda3 100644 --- a/src/can1/rximr12/mod.rs +++ b/src/can1/rximr12/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr13/mod.rs b/src/can1/rximr13/mod.rs index 974628a..b457c29 100644 --- a/src/can1/rximr13/mod.rs +++ b/src/can1/rximr13/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr14/mod.rs b/src/can1/rximr14/mod.rs index 193e9ae..d637965 100644 --- a/src/can1/rximr14/mod.rs +++ b/src/can1/rximr14/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr15/mod.rs b/src/can1/rximr15/mod.rs index 899ec96..8b60538 100644 --- a/src/can1/rximr15/mod.rs +++ b/src/can1/rximr15/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr2/mod.rs b/src/can1/rximr2/mod.rs index bffb2eb..b79c370 100644 --- a/src/can1/rximr2/mod.rs +++ b/src/can1/rximr2/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr3/mod.rs b/src/can1/rximr3/mod.rs index df84bb2..dc21ee1 100644 --- a/src/can1/rximr3/mod.rs +++ b/src/can1/rximr3/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr4/mod.rs b/src/can1/rximr4/mod.rs index d1ffc2a..2a5d5a7 100644 --- a/src/can1/rximr4/mod.rs +++ b/src/can1/rximr4/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr5/mod.rs b/src/can1/rximr5/mod.rs index 2d67f95..7500c7a 100644 --- a/src/can1/rximr5/mod.rs +++ b/src/can1/rximr5/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr6/mod.rs b/src/can1/rximr6/mod.rs index b5879da..c7582e2 100644 --- a/src/can1/rximr6/mod.rs +++ b/src/can1/rximr6/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr7/mod.rs b/src/can1/rximr7/mod.rs index 674dc6b..a5de575 100644 --- a/src/can1/rximr7/mod.rs +++ b/src/can1/rximr7/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr8/mod.rs b/src/can1/rximr8/mod.rs index 6fac312..626ec56 100644 --- a/src/can1/rximr8/mod.rs +++ b/src/can1/rximr8/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rximr9/mod.rs b/src/can1/rximr9/mod.rs index b21a830..4acd2f7 100644 --- a/src/can1/rximr9/mod.rs +++ b/src/can1/rximr9/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/rxmgmask/mod.rs b/src/can1/rxmgmask/mod.rs index da42c27..dc87f29 100644 --- a/src/can1/rxmgmask/mod.rs +++ b/src/can1/rxmgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXMGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/timer/mod.rs b/src/can1/timer/mod.rs index c5d0eb6..7a46bca 100644 --- a/src/can1/timer/mod.rs +++ b/src/can1/timer/mod.rs @@ -22,7 +22,9 @@ impl super::TIMER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can1/wmb0_cs/mod.rs b/src/can1/wmb0_cs/mod.rs index 4562128..fa731f4 100644 --- a/src/can1/wmb0_cs/mod.rs +++ b/src/can1/wmb0_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can1/wmb0_d03/mod.rs b/src/can1/wmb0_d03/mod.rs index 4d5dc99..90e28be 100644 --- a/src/can1/wmb0_d03/mod.rs +++ b/src/can1/wmb0_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb0_d47/mod.rs b/src/can1/wmb0_d47/mod.rs index b074c72..f567362 100644 --- a/src/can1/wmb0_d47/mod.rs +++ b/src/can1/wmb0_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb0_id/mod.rs b/src/can1/wmb0_id/mod.rs index 9621d2c..e76a1a5 100644 --- a/src/can1/wmb0_id/mod.rs +++ b/src/can1/wmb0_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb1_cs/mod.rs b/src/can1/wmb1_cs/mod.rs index 4c426aa..f54e732 100644 --- a/src/can1/wmb1_cs/mod.rs +++ b/src/can1/wmb1_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can1/wmb1_d03/mod.rs b/src/can1/wmb1_d03/mod.rs index 78d7079..7eb5aeb 100644 --- a/src/can1/wmb1_d03/mod.rs +++ b/src/can1/wmb1_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb1_d47/mod.rs b/src/can1/wmb1_d47/mod.rs index 3499051..b4df930 100644 --- a/src/can1/wmb1_d47/mod.rs +++ b/src/can1/wmb1_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb1_id/mod.rs b/src/can1/wmb1_id/mod.rs index c1e4593..5466ab1 100644 --- a/src/can1/wmb1_id/mod.rs +++ b/src/can1/wmb1_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb2_cs/mod.rs b/src/can1/wmb2_cs/mod.rs index df6e9c2..f37b0a2 100644 --- a/src/can1/wmb2_cs/mod.rs +++ b/src/can1/wmb2_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can1/wmb2_d03/mod.rs b/src/can1/wmb2_d03/mod.rs index 83ad28a..15406c4 100644 --- a/src/can1/wmb2_d03/mod.rs +++ b/src/can1/wmb2_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb2_d47/mod.rs b/src/can1/wmb2_d47/mod.rs index 0d57550..30b3c6b 100644 --- a/src/can1/wmb2_d47/mod.rs +++ b/src/can1/wmb2_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb2_id/mod.rs b/src/can1/wmb2_id/mod.rs index a4c67b3..c421aa6 100644 --- a/src/can1/wmb2_id/mod.rs +++ b/src/can1/wmb2_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb3_cs/mod.rs b/src/can1/wmb3_cs/mod.rs index 92c6dd9..05b7b1f 100644 --- a/src/can1/wmb3_cs/mod.rs +++ b/src/can1/wmb3_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can1/wmb3_d03/mod.rs b/src/can1/wmb3_d03/mod.rs index 064dfa5..64f4c8f 100644 --- a/src/can1/wmb3_d03/mod.rs +++ b/src/can1/wmb3_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb3_d47/mod.rs b/src/can1/wmb3_d47/mod.rs index 494d46c..a60b2ae 100644 --- a/src/can1/wmb3_d47/mod.rs +++ b/src/can1/wmb3_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wmb3_id/mod.rs b/src/can1/wmb3_id/mod.rs index 25d4e25..6b7ac79 100644 --- a/src/can1/wmb3_id/mod.rs +++ b/src/can1/wmb3_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can1/wu_mtc/mod.rs b/src/can1/wu_mtc/mod.rs index 30239c5..04c03ba 100644 --- a/src/can1/wu_mtc/mod.rs +++ b/src/can1/wu_mtc/mod.rs @@ -22,7 +22,9 @@ impl super::WU_MTC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl MCOUNTERR { #[doc = "Possible values of the field `WUMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMFR { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl WUMFR { #[doc = "Possible values of the field `WTOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOFR { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -147,10 +145,8 @@ impl WTOFR { } #[doc = "Values that can be written to the field `WUMF`"] pub enum WUMFW { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFW { #[allow(missing_docs)] @@ -205,10 +201,8 @@ impl<'a> _WUMFW<'a> { } #[doc = "Values that can be written to the field `WTOF`"] pub enum WTOFW { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFW { #[allow(missing_docs)] diff --git a/src/can2/cbt/mod.rs b/src/can2/cbt/mod.rs index f421eda..cb70aeb 100644 --- a/src/can2/cbt/mod.rs +++ b/src/can2/cbt/mod.rs @@ -22,7 +22,9 @@ impl super::CBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -98,10 +100,8 @@ impl EPRESDIVR { #[doc = "Possible values of the field `BTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BTFR { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -219,10 +219,8 @@ impl<'a> _EPRESDIVW<'a> { } #[doc = "Values that can be written to the field `BTF`"] pub enum BTFW { - #[doc = "Extended bit time definitions disabled."] - _0, - #[doc = "Extended bit time definitions enabled."] - _1, + #[doc = "Extended bit time definitions disabled."] _0, + #[doc = "Extended bit time definitions enabled."] _1, } impl BTFW { #[allow(missing_docs)] diff --git a/src/can2/crcr/mod.rs b/src/can2/crcr/mod.rs index 4235705..07b066c 100644 --- a/src/can2/crcr/mod.rs +++ b/src/can2/crcr/mod.rs @@ -6,7 +6,9 @@ impl super::CRCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/ctrl1/mod.rs b/src/can2/ctrl1/mod.rs index 95f49d5..ad0efed 100644 --- a/src/can2/ctrl1/mod.rs +++ b/src/can2/ctrl1/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl PROPSEGR { #[doc = "Possible values of the field `LOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOMR { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl LOMR { #[doc = "Possible values of the field `LBUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBUFR { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl LBUFR { #[doc = "Possible values of the field `TSYN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSYNR { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl TSYNR { #[doc = "Possible values of the field `BOFFREC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFRECR { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl BOFFRECR { #[doc = "Possible values of the field `SMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMPR { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -289,10 +282,8 @@ impl SMPR { #[doc = "Possible values of the field `RWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNMSKR { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -336,10 +327,8 @@ impl RWRNMSKR { #[doc = "Possible values of the field `TWRNMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNMSKR { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -383,10 +372,8 @@ impl TWRNMSKR { #[doc = "Possible values of the field `LPB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPBR { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +419,7 @@ impl LPBR { pub enum CLKSRCR { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +463,8 @@ impl CLKSRCR { #[doc = "Possible values of the field `ERRMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSKR { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +508,8 @@ impl ERRMSKR { #[doc = "Possible values of the field `BOFFMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFMSKR { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -629,10 +611,8 @@ impl<'a> _PROPSEGW<'a> { } #[doc = "Values that can be written to the field `LOM`"] pub enum LOMW { - #[doc = "Listen-Only mode is deactivated."] - _0, - #[doc = "FlexCAN module operates in Listen-Only mode."] - _1, + #[doc = "Listen-Only mode is deactivated."] _0, + #[doc = "FlexCAN module operates in Listen-Only mode."] _1, } impl LOMW { #[allow(missing_docs)] @@ -687,10 +667,8 @@ impl<'a> _LOMW<'a> { } #[doc = "Values that can be written to the field `LBUF`"] pub enum LBUFW { - #[doc = "Buffer with highest priority is transmitted first."] - _0, - #[doc = "Lowest number buffer is transmitted first."] - _1, + #[doc = "Buffer with highest priority is transmitted first."] _0, + #[doc = "Lowest number buffer is transmitted first."] _1, } impl LBUFW { #[allow(missing_docs)] @@ -745,10 +723,8 @@ impl<'a> _LBUFW<'a> { } #[doc = "Values that can be written to the field `TSYN`"] pub enum TSYNW { - #[doc = "Timer Sync feature disabled"] - _0, - #[doc = "Timer Sync feature enabled"] - _1, + #[doc = "Timer Sync feature disabled"] _0, + #[doc = "Timer Sync feature enabled"] _1, } impl TSYNW { #[allow(missing_docs)] @@ -803,10 +779,8 @@ impl<'a> _TSYNW<'a> { } #[doc = "Values that can be written to the field `BOFFREC`"] pub enum BOFFRECW { - #[doc = "Automatic recovering from Bus Off state enabled."] - _0, - #[doc = "Automatic recovering from Bus Off state disabled."] - _1, + #[doc = "Automatic recovering from Bus Off state enabled."] _0, + #[doc = "Automatic recovering from Bus Off state disabled."] _1, } impl BOFFRECW { #[allow(missing_docs)] @@ -861,8 +835,7 @@ impl<'a> _BOFFRECW<'a> { } #[doc = "Values that can be written to the field `SMP`"] pub enum SMPW { - #[doc = "Just one sample is used to determine the bit value."] - _0, + #[doc = "Just one sample is used to determine the bit value."] _0, #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."] _1, } @@ -919,10 +892,8 @@ impl<'a> _SMPW<'a> { } #[doc = "Values that can be written to the field `RWRNMSK`"] pub enum RWRNMSKW { - #[doc = "Rx Warning Interrupt disabled."] - _0, - #[doc = "Rx Warning Interrupt enabled."] - _1, + #[doc = "Rx Warning Interrupt disabled."] _0, + #[doc = "Rx Warning Interrupt enabled."] _1, } impl RWRNMSKW { #[allow(missing_docs)] @@ -977,10 +948,8 @@ impl<'a> _RWRNMSKW<'a> { } #[doc = "Values that can be written to the field `TWRNMSK`"] pub enum TWRNMSKW { - #[doc = "Tx Warning Interrupt disabled."] - _0, - #[doc = "Tx Warning Interrupt enabled."] - _1, + #[doc = "Tx Warning Interrupt disabled."] _0, + #[doc = "Tx Warning Interrupt enabled."] _1, } impl TWRNMSKW { #[allow(missing_docs)] @@ -1035,10 +1004,8 @@ impl<'a> _TWRNMSKW<'a> { } #[doc = "Values that can be written to the field `LPB`"] pub enum LPBW { - #[doc = "Loop Back disabled."] - _0, - #[doc = "Loop Back enabled."] - _1, + #[doc = "Loop Back disabled."] _0, + #[doc = "Loop Back enabled."] _1, } impl LPBW { #[allow(missing_docs)] @@ -1095,8 +1062,7 @@ impl<'a> _LPBW<'a> { pub enum CLKSRCW { #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."] _0, - #[doc = "The CAN engine clock source is the peripheral clock."] - _1, + #[doc = "The CAN engine clock source is the peripheral clock."] _1, } impl CLKSRCW { #[allow(missing_docs)] @@ -1151,10 +1117,8 @@ impl<'a> _CLKSRCW<'a> { } #[doc = "Values that can be written to the field `ERRMSK`"] pub enum ERRMSKW { - #[doc = "Error interrupt disabled."] - _0, - #[doc = "Error interrupt enabled."] - _1, + #[doc = "Error interrupt disabled."] _0, + #[doc = "Error interrupt enabled."] _1, } impl ERRMSKW { #[allow(missing_docs)] @@ -1209,10 +1173,8 @@ impl<'a> _ERRMSKW<'a> { } #[doc = "Values that can be written to the field `BOFFMSK`"] pub enum BOFFMSKW { - #[doc = "Bus Off interrupt disabled."] - _0, - #[doc = "Bus Off interrupt enabled."] - _1, + #[doc = "Bus Off interrupt disabled."] _0, + #[doc = "Bus Off interrupt enabled."] _1, } impl BOFFMSKW { #[allow(missing_docs)] diff --git a/src/can2/ctrl1_pn/mod.rs b/src/can2/ctrl1_pn/mod.rs index 0fe8a14..dc76bb4 100644 --- a/src/can2/ctrl1_pn/mod.rs +++ b/src/can2/ctrl1_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL1_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CTRL1_PN { #[doc = "Possible values of the field `FCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCSR { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSR { #[doc = r" Value of the field as raw bits"] @@ -99,12 +97,9 @@ impl FCSR { #[doc = "Possible values of the field `IDFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDFSR { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -155,12 +150,9 @@ impl IDFSR { #[doc = "Possible values of the field `PLFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLFSR { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -217,8 +209,7 @@ pub enum NMATCHR { _00000010, #[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."] _11111111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl NMATCHR { #[doc = r" Value of the field as raw bits"] @@ -261,10 +252,8 @@ impl NMATCHR { #[doc = "Possible values of the field `WUMF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMF_MSKR { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -308,10 +297,8 @@ impl WUMF_MSKR { #[doc = "Possible values of the field `WTOF_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOF_MSKR { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -354,14 +341,10 @@ impl WTOF_MSKR { } #[doc = "Values that can be written to the field `FCS`"] pub enum FCSW { - #[doc = "Message ID filtering only"] - _00, - #[doc = "Message ID filtering and payload filtering"] - _01, - #[doc = "Message ID filtering occurring a specified number of times."] - _10, - #[doc = "Message ID filtering and payload filtering a specified number of times"] - _11, + #[doc = "Message ID filtering only"] _00, + #[doc = "Message ID filtering and payload filtering"] _01, + #[doc = "Message ID filtering occurring a specified number of times."] _10, + #[doc = "Message ID filtering and payload filtering a specified number of times"] _11, } impl FCSW { #[allow(missing_docs)] @@ -420,12 +403,9 @@ impl<'a> _FCSW<'a> { } #[doc = "Values that can be written to the field `IDFS`"] pub enum IDFSW { - #[doc = "Match upon a ID contents against an exact target value"] - _00, - #[doc = "Match upon a ID value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a ID value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a ID contents against an exact target value"] _00, + #[doc = "Match upon a ID value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -486,12 +466,9 @@ impl<'a> _IDFSW<'a> { } #[doc = "Values that can be written to the field `PLFS`"] pub enum PLFSW { - #[doc = "Match upon a payload contents against an exact target value"] - _00, - #[doc = "Match upon a payload value greater than or equal to a specified target value"] - _01, - #[doc = "Match upon a payload value smaller than or equal to a specified target value"] - _10, + #[doc = "Match upon a payload contents against an exact target value"] _00, + #[doc = "Match upon a payload value greater than or equal to a specified target value"] _01, + #[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10, #[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"] _11, } @@ -608,10 +585,8 @@ impl<'a> _NMATCHW<'a> { } #[doc = "Values that can be written to the field `WUMF_MSK`"] pub enum WUMF_MSKW { - #[doc = "Wake up match event is disabled"] - _0, - #[doc = "Wake up match event is enabled"] - _1, + #[doc = "Wake up match event is disabled"] _0, + #[doc = "Wake up match event is enabled"] _1, } impl WUMF_MSKW { #[allow(missing_docs)] @@ -666,10 +641,8 @@ impl<'a> _WUMF_MSKW<'a> { } #[doc = "Values that can be written to the field `WTOF_MSK`"] pub enum WTOF_MSKW { - #[doc = "Timeout wake up event is disabled"] - _0, - #[doc = "Timeout wake up event is enabled"] - _1, + #[doc = "Timeout wake up event is disabled"] _0, + #[doc = "Timeout wake up event is enabled"] _1, } impl WTOF_MSKW { #[allow(missing_docs)] diff --git a/src/can2/ctrl2/mod.rs b/src/can2/ctrl2/mod.rs index fcb2804..dfec61f 100644 --- a/src/can2/ctrl2/mod.rs +++ b/src/can2/ctrl2/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL2 { #[doc = "Possible values of the field `EDFLTDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDFLTDISR { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EDFLTDISR { #[doc = "Possible values of the field `ISOCANFDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISOCANFDENR { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ISOCANFDENR { #[doc = "Possible values of the field `PREXCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PREXCENR { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +274,8 @@ impl EACENR { #[doc = "Possible values of the field `RRS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RRSR { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +319,8 @@ impl RRSR { #[doc = "Possible values of the field `MRP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MRPR { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +386,8 @@ impl RFFNR { #[doc = "Possible values of the field `BOFFDONEMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEMSKR { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +431,8 @@ impl BOFFDONEMSKR { #[doc = "Possible values of the field `ERRMSK_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRMSK_FASTR { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -487,10 +475,8 @@ impl ERRMSK_FASTR { } #[doc = "Values that can be written to the field `EDFLTDIS`"] pub enum EDFLTDISW { - #[doc = "Edge Filter is enabled."] - _0, - #[doc = "Edge Filter is disabled."] - _1, + #[doc = "Edge Filter is enabled."] _0, + #[doc = "Edge Filter is disabled."] _1, } impl EDFLTDISW { #[allow(missing_docs)] @@ -545,10 +531,8 @@ impl<'a> _EDFLTDISW<'a> { } #[doc = "Values that can be written to the field `ISOCANFDEN`"] pub enum ISOCANFDENW { - #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] - _0, - #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] - _1, + #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0, + #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1, } impl ISOCANFDENW { #[allow(missing_docs)] @@ -603,10 +587,8 @@ impl<'a> _ISOCANFDENW<'a> { } #[doc = "Values that can be written to the field `PREXCEN`"] pub enum PREXCENW { - #[doc = "Protocol Exception is disabled."] - _0, - #[doc = "Protocol Exception is enabled."] - _1, + #[doc = "Protocol Exception is disabled."] _0, + #[doc = "Protocol Exception is enabled."] _1, } impl PREXCENW { #[allow(missing_docs)] @@ -777,10 +759,8 @@ impl<'a> _EACENW<'a> { } #[doc = "Values that can be written to the field `RRS`"] pub enum RRSW { - #[doc = "Remote Response Frame is generated."] - _0, - #[doc = "Remote Request Frame is stored."] - _1, + #[doc = "Remote Response Frame is generated."] _0, + #[doc = "Remote Request Frame is stored."] _1, } impl RRSW { #[allow(missing_docs)] @@ -835,10 +815,8 @@ impl<'a> _RRSW<'a> { } #[doc = "Values that can be written to the field `MRP`"] pub enum MRPW { - #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] - _0, - #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] - _1, + #[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0, + #[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1, } impl MRPW { #[allow(missing_docs)] @@ -923,10 +901,8 @@ impl<'a> _RFFNW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEMSK`"] pub enum BOFFDONEMSKW { - #[doc = "Bus Off Done interrupt disabled."] - _0, - #[doc = "Bus Off Done interrupt enabled."] - _1, + #[doc = "Bus Off Done interrupt disabled."] _0, + #[doc = "Bus Off Done interrupt enabled."] _1, } impl BOFFDONEMSKW { #[allow(missing_docs)] @@ -981,10 +957,8 @@ impl<'a> _BOFFDONEMSKW<'a> { } #[doc = "Values that can be written to the field `ERRMSK_FAST`"] pub enum ERRMSK_FASTW { - #[doc = "ERRINT_FAST Error interrupt disabled."] - _0, - #[doc = "ERRINT_FAST Error interrupt enabled."] - _1, + #[doc = "ERRINT_FAST Error interrupt disabled."] _0, + #[doc = "ERRINT_FAST Error interrupt enabled."] _1, } impl ERRMSK_FASTW { #[allow(missing_docs)] diff --git a/src/can2/ctrl2_pn/mod.rs b/src/can2/ctrl2_pn/mod.rs index 01029c8..7831ff2 100644 --- a/src/can2/ctrl2_pn/mod.rs +++ b/src/can2/ctrl2_pn/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL2_PN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/ecr/mod.rs b/src/can2/ecr/mod.rs index ab42b4e..22c7322 100644 --- a/src/can2/ecr/mod.rs +++ b/src/can2/ecr/mod.rs @@ -22,7 +22,9 @@ impl super::ECR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/embedded_ram/mod.rs b/src/can2/embedded_ram/mod.rs index 91a2c94..5fe0f4f 100644 --- a/src/can2/embedded_ram/mod.rs +++ b/src/can2/embedded_ram/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/esr1/mod.rs b/src/can2/esr1/mod.rs index f1f6be4..4798194 100644 --- a/src/can2/esr1/mod.rs +++ b/src/can2/esr1/mod.rs @@ -22,7 +22,9 @@ impl super::ESR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ESR1 { #[doc = "Possible values of the field `ERRINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERRINTR { #[doc = "Possible values of the field `BOFFINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl BOFFINTR { #[doc = "Possible values of the field `RX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXR { - #[doc = "FlexCAN is not receiving a message."] - _0, - #[doc = "FlexCAN is receiving a message."] - _1, + #[doc = "FlexCAN is not receiving a message."] _0, + #[doc = "FlexCAN is receiving a message."] _1, } impl RXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,14 +180,10 @@ impl RXR { #[doc = "Possible values of the field `FLTCONF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTCONFR { - #[doc = "Error Active"] - _00, - #[doc = "Error Passive"] - _01, - #[doc = "Bus Off"] - _1X, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Error Active"] _00, + #[doc = "Error Passive"] _01, + #[doc = "Bus Off"] _1X, + #[doc = r" Reserved"] _Reserved(u8), } impl FLTCONFR { #[doc = r" Value of the field as raw bits"] @@ -234,10 +226,8 @@ impl FLTCONFR { #[doc = "Possible values of the field `TX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXR { - #[doc = "FlexCAN is not transmitting a message."] - _0, - #[doc = "FlexCAN is transmitting a message."] - _1, + #[doc = "FlexCAN is not transmitting a message."] _0, + #[doc = "FlexCAN is transmitting a message."] _1, } impl TXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -281,10 +271,8 @@ impl TXR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No such occurrence."] - _0, - #[doc = "CAN bus is now IDLE."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "CAN bus is now IDLE."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -328,10 +316,8 @@ impl IDLER { #[doc = "Possible values of the field `RXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "RXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "RXERRCNT is greater than or equal to 96."] _1, } impl RXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -375,10 +361,8 @@ impl RXWRNR { #[doc = "Possible values of the field `TXWRN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXWRNR { - #[doc = "No such occurrence."] - _0, - #[doc = "TXERRCNT is greater than or equal to 96."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "TXERRCNT is greater than or equal to 96."] _1, } impl TXWRNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -422,10 +406,8 @@ impl TXWRNR { #[doc = "Possible values of the field `STFERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -469,10 +451,8 @@ impl STFERRR { #[doc = "Possible values of the field `FRMERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -516,10 +496,8 @@ impl FRMERRR { #[doc = "Possible values of the field `CRCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -563,10 +541,8 @@ impl CRCERRR { #[doc = "Possible values of the field `ACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACKERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "An ACK error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "An ACK error occurred since last read of this register."] _1, } impl ACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -610,10 +586,8 @@ impl ACKERRR { #[doc = "Possible values of the field `BIT0ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -657,10 +631,8 @@ impl BIT0ERRR { #[doc = "Possible values of the field `BIT1ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERRR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -704,8 +676,7 @@ impl BIT1ERRR { #[doc = "Possible values of the field `RWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -751,8 +722,7 @@ impl RWRNINTR { #[doc = "Possible values of the field `TWRNINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TWRNINTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -798,10 +768,8 @@ impl TWRNINTR { #[doc = "Possible values of the field `SYNCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCHR { - #[doc = "FlexCAN is not synchronized to the CAN bus."] - _0, - #[doc = "FlexCAN is synchronized to the CAN bus."] - _1, + #[doc = "FlexCAN is not synchronized to the CAN bus."] _0, + #[doc = "FlexCAN is synchronized to the CAN bus."] _1, } impl SYNCHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -845,10 +813,8 @@ impl SYNCHR { #[doc = "Possible values of the field `BOFFDONEINT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOFFDONEINTR { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,8 +858,7 @@ impl BOFFDONEINTR { #[doc = "Possible values of the field `ERRINT_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRINT_FASTR { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -939,10 +904,8 @@ impl ERRINT_FASTR { #[doc = "Possible values of the field `ERROVR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERROVRR { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -986,10 +949,8 @@ impl ERROVRR { #[doc = "Possible values of the field `STFERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STFERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Stuffing Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Stuffing Error occurred since last read of this register."] _1, } impl STFERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1033,10 +994,8 @@ impl STFERR_FASTR { #[doc = "Possible values of the field `FRMERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRMERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A Form Error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A Form Error occurred since last read of this register."] _1, } impl FRMERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1080,10 +1039,8 @@ impl FRMERR_FASTR { #[doc = "Possible values of the field `CRCERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRCERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "A CRC error occurred since last read of this register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "A CRC error occurred since last read of this register."] _1, } impl CRCERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1127,10 +1084,8 @@ impl CRCERR_FASTR { #[doc = "Possible values of the field `BIT0ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT0ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as dominant is received as recessive."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as dominant is received as recessive."] _1, } impl BIT0ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1174,10 +1129,8 @@ impl BIT0ERR_FASTR { #[doc = "Possible values of the field `BIT1ERR_FAST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIT1ERR_FASTR { - #[doc = "No such occurrence."] - _0, - #[doc = "At least one bit sent as recessive is received as dominant."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "At least one bit sent as recessive is received as dominant."] _1, } impl BIT1ERR_FASTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1220,10 +1173,8 @@ impl BIT1ERR_FASTR { } #[doc = "Values that can be written to the field `ERRINT`"] pub enum ERRINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1, } impl ERRINTW { #[allow(missing_docs)] @@ -1278,10 +1229,8 @@ impl<'a> _ERRINTW<'a> { } #[doc = "Values that can be written to the field `BOFFINT`"] pub enum BOFFINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module entered Bus Off state."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module entered Bus Off state."] _1, } impl BOFFINTW { #[allow(missing_docs)] @@ -1336,8 +1285,7 @@ impl<'a> _BOFFINTW<'a> { } #[doc = "Values that can be written to the field `RWRNINT`"] pub enum RWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1394,8 +1342,7 @@ impl<'a> _RWRNINTW<'a> { } #[doc = "Values that can be written to the field `TWRNINT`"] pub enum TWRNINTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."] _1, } @@ -1452,10 +1399,8 @@ impl<'a> _TWRNINTW<'a> { } #[doc = "Values that can be written to the field `BOFFDONEINT`"] pub enum BOFFDONEINTW { - #[doc = "No such occurrence."] - _0, - #[doc = "FlexCAN module has completed Bus Off process."] - _1, + #[doc = "No such occurrence."] _0, + #[doc = "FlexCAN module has completed Bus Off process."] _1, } impl BOFFDONEINTW { #[allow(missing_docs)] @@ -1510,8 +1455,7 @@ impl<'a> _BOFFDONEINTW<'a> { } #[doc = "Values that can be written to the field `ERRINT_FAST`"] pub enum ERRINT_FASTW { - #[doc = "No such occurrence."] - _0, + #[doc = "No such occurrence."] _0, #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."] _1, } @@ -1568,10 +1512,8 @@ impl<'a> _ERRINT_FASTW<'a> { } #[doc = "Values that can be written to the field `ERROVR`"] pub enum ERROVRW { - #[doc = "Overrun has not occurred."] - _0, - #[doc = "Overrun has occurred."] - _1, + #[doc = "Overrun has not occurred."] _0, + #[doc = "Overrun has occurred."] _1, } impl ERROVRW { #[allow(missing_docs)] diff --git a/src/can2/esr2/mod.rs b/src/can2/esr2/mod.rs index d4f29f2..8f2635b 100644 --- a/src/can2/esr2/mod.rs +++ b/src/can2/esr2/mod.rs @@ -6,14 +6,15 @@ impl super::ESR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `IMB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IMBR { - #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] - _0, + #[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] _0, #[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."] _1, } @@ -59,10 +60,8 @@ impl IMBR { #[doc = "Possible values of the field `VPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VPSR { - #[doc = "Contents of IMB and LPTM are invalid."] - _0, - #[doc = "Contents of IMB and LPTM are valid."] - _1, + #[doc = "Contents of IMB and LPTM are invalid."] _0, + #[doc = "Contents of IMB and LPTM are valid."] _1, } impl VPSR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can2/fdcbt/mod.rs b/src/can2/fdcbt/mod.rs index d5b4147..0ddab6e 100644 --- a/src/can2/fdcbt/mod.rs +++ b/src/can2/fdcbt/mod.rs @@ -22,7 +22,9 @@ impl super::FDCBT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/fdcrc/mod.rs b/src/can2/fdcrc/mod.rs index b213def..d0da073 100644 --- a/src/can2/fdcrc/mod.rs +++ b/src/can2/fdcrc/mod.rs @@ -6,7 +6,9 @@ impl super::FDCRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/fdctrl/mod.rs b/src/can2/fdctrl/mod.rs index e337ada..cf39ab2 100644 --- a/src/can2/fdctrl/mod.rs +++ b/src/can2/fdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl TDCOFFR { #[doc = "Possible values of the field `TDCFAIL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCFAILR { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl TDCFAILR { #[doc = "Possible values of the field `TDCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDCENR { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -159,14 +157,10 @@ impl TDCENR { #[doc = "Possible values of the field `MBDSR0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBDSR0R { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0R { #[doc = r" Value of the field as raw bits"] @@ -215,10 +209,8 @@ impl MBDSR0R { #[doc = "Possible values of the field `FDRATE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FDRATER { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -276,10 +268,8 @@ impl<'a> _TDCOFFW<'a> { } #[doc = "Values that can be written to the field `TDCFAIL`"] pub enum TDCFAILW { - #[doc = "Measured loop delay is in range."] - _0, - #[doc = "Measured loop delay is out of range."] - _1, + #[doc = "Measured loop delay is in range."] _0, + #[doc = "Measured loop delay is out of range."] _1, } impl TDCFAILW { #[allow(missing_docs)] @@ -334,10 +324,8 @@ impl<'a> _TDCFAILW<'a> { } #[doc = "Values that can be written to the field `TDCEN`"] pub enum TDCENW { - #[doc = "TDC is disabled"] - _0, - #[doc = "TDC is enabled"] - _1, + #[doc = "TDC is disabled"] _0, + #[doc = "TDC is enabled"] _1, } impl TDCENW { #[allow(missing_docs)] @@ -392,14 +380,10 @@ impl<'a> _TDCENW<'a> { } #[doc = "Values that can be written to the field `MBDSR0`"] pub enum MBDSR0W { - #[doc = "Selects 8 bytes per Message Buffer."] - _00, - #[doc = "Selects 16 bytes per Message Buffer."] - _01, - #[doc = "Selects 32 bytes per Message Buffer."] - _10, - #[doc = "Selects 64 bytes per Message Buffer."] - _11, + #[doc = "Selects 8 bytes per Message Buffer."] _00, + #[doc = "Selects 16 bytes per Message Buffer."] _01, + #[doc = "Selects 32 bytes per Message Buffer."] _10, + #[doc = "Selects 64 bytes per Message Buffer."] _11, } impl MBDSR0W { #[allow(missing_docs)] @@ -458,10 +442,8 @@ impl<'a> _MBDSR0W<'a> { } #[doc = "Values that can be written to the field `FDRATE`"] pub enum FDRATEW { - #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] - _0, - #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] - _1, + #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0, + #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1, } impl FDRATEW { #[allow(missing_docs)] diff --git a/src/can2/flt_dlc/mod.rs b/src/can2/flt_dlc/mod.rs index 74c52b5..db8cb41 100644 --- a/src/can2/flt_dlc/mod.rs +++ b/src/can2/flt_dlc/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_DLC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/flt_id1/mod.rs b/src/can2/flt_id1/mod.rs index 7af09e6..528a567 100644 --- a/src/can2/flt_id1/mod.rs +++ b/src/can2/flt_id1/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID1R { #[doc = "Possible values of the field `FLT_RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_RTRR { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl FLT_RTRR { #[doc = "Possible values of the field `FLT_IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT_IDER { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID1W<'a> { } #[doc = "Values that can be written to the field `FLT_RTR`"] pub enum FLT_RTRW { - #[doc = "Reject remote frame (accept data frame)"] - _0, - #[doc = "Accept remote frame"] - _1, + #[doc = "Reject remote frame (accept data frame)"] _0, + #[doc = "Accept remote frame"] _1, } impl FLT_RTRW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _FLT_RTRW<'a> { } #[doc = "Values that can be written to the field `FLT_IDE`"] pub enum FLT_IDEW { - #[doc = "Accept standard frame format"] - _0, - #[doc = "Accept extended frame format"] - _1, + #[doc = "Accept standard frame format"] _0, + #[doc = "Accept extended frame format"] _1, } impl FLT_IDEW { #[allow(missing_docs)] diff --git a/src/can2/flt_id2_idmask/mod.rs b/src/can2/flt_id2_idmask/mod.rs index e836809..66cd275 100644 --- a/src/can2/flt_id2_idmask/mod.rs +++ b/src/can2/flt_id2_idmask/mod.rs @@ -22,7 +22,9 @@ impl super::FLT_ID2_IDMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl FLT_ID2_IDMASKR { #[doc = "Possible values of the field `RTR_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTR_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl RTR_MSKR { #[doc = "Possible values of the field `IDE_MSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDE_MSKR { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _FLT_ID2_IDMASKW<'a> { } #[doc = "Values that can be written to the field `RTR_MSK`"] pub enum RTR_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl RTR_MSKW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _RTR_MSKW<'a> { } #[doc = "Values that can be written to the field `IDE_MSK`"] pub enum IDE_MSKW { - #[doc = "The corresponding bit in the filter is \"don't care\""] - _0, - #[doc = "The corresponding bit in the filter is checked"] - _1, + #[doc = "The corresponding bit in the filter is \"don't care\""] _0, + #[doc = "The corresponding bit in the filter is checked"] _1, } impl IDE_MSKW { #[allow(missing_docs)] diff --git a/src/can2/iflag1/mod.rs b/src/can2/iflag1/mod.rs index 62b4c8f..20a7322 100644 --- a/src/can2/iflag1/mod.rs +++ b/src/can2/iflag1/mod.rs @@ -22,7 +22,9 @@ impl super::IFLAG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/imask1/mod.rs b/src/can2/imask1/mod.rs index b6debac..1f67ed9 100644 --- a/src/can2/imask1/mod.rs +++ b/src/can2/imask1/mod.rs @@ -22,7 +22,9 @@ impl super::IMASK1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/mcr/mod.rs b/src/can2/mcr/mod.rs index 0f6af62..3c5653b 100644 --- a/src/can2/mcr/mod.rs +++ b/src/can2/mcr/mod.rs @@ -22,7 +22,9 @@ impl super::MCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,11 @@ impl MAXMBR { #[doc = "Possible values of the field `IDAM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDAMR { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMR { #[doc = r" Value of the field as raw bits"] @@ -157,10 +156,8 @@ impl FDENR { #[doc = "Possible values of the field `AEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AENR { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -204,10 +201,8 @@ impl AENR { #[doc = "Possible values of the field `LPRIOEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPRIOENR { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -251,10 +246,8 @@ impl LPRIOENR { #[doc = "Possible values of the field `PNET_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PNET_ENR { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -298,10 +291,8 @@ impl PNET_ENR { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -347,8 +338,7 @@ impl DMAR { pub enum IRMQR { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -392,10 +382,8 @@ impl IRMQR { #[doc = "Possible values of the field `SRXDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRXDISR { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -439,10 +427,8 @@ impl SRXDISR { #[doc = "Possible values of the field `LPMACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPMACKR { - #[doc = "FlexCAN is not in a low-power mode."] - _0, - #[doc = "FlexCAN is in a low-power mode."] - _1, + #[doc = "FlexCAN is not in a low-power mode."] _0, + #[doc = "FlexCAN is in a low-power mode."] _1, } impl LPMACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -554,10 +540,8 @@ impl SUPVR { #[doc = "Possible values of the field `FRZACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZACKR { - #[doc = "FlexCAN not in Freeze mode, prescaler running."] - _0, - #[doc = "FlexCAN in Freeze mode, prescaler stopped."] - _1, + #[doc = "FlexCAN not in Freeze mode, prescaler running."] _0, + #[doc = "FlexCAN in Freeze mode, prescaler stopped."] _1, } impl FRZACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -601,10 +585,8 @@ impl FRZACKR { #[doc = "Possible values of the field `SOFTRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFTRSTR { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +630,8 @@ impl SOFTRSTR { #[doc = "Possible values of the field `NOTRDY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOTRDYR { - #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl NOTRDYR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -690,10 +670,8 @@ impl NOTRDYR { #[doc = "Possible values of the field `HALT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HALTR { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -737,10 +715,8 @@ impl HALTR { #[doc = "Possible values of the field `RFEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFENR { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -784,10 +760,8 @@ impl RFENR { #[doc = "Possible values of the field `FRZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRZR { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -831,10 +805,8 @@ impl FRZR { #[doc = "Possible values of the field `MDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MDISR { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -892,14 +864,11 @@ impl<'a> _MAXMBW<'a> { } #[doc = "Values that can be written to the field `IDAM`"] pub enum IDAMW { - #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] - _00, + #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00, #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."] _01, - #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] - _10, - #[doc = "Format D: All frames rejected."] - _11, + #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10, + #[doc = "Format D: All frames rejected."] _11, } impl IDAMW { #[allow(missing_docs)] @@ -1016,10 +985,8 @@ impl<'a> _FDENW<'a> { } #[doc = "Values that can be written to the field `AEN`"] pub enum AENW { - #[doc = "Abort disabled."] - _0, - #[doc = "Abort enabled."] - _1, + #[doc = "Abort disabled."] _0, + #[doc = "Abort enabled."] _1, } impl AENW { #[allow(missing_docs)] @@ -1074,10 +1041,8 @@ impl<'a> _AENW<'a> { } #[doc = "Values that can be written to the field `LPRIOEN`"] pub enum LPRIOENW { - #[doc = "Local Priority disabled."] - _0, - #[doc = "Local Priority enabled."] - _1, + #[doc = "Local Priority disabled."] _0, + #[doc = "Local Priority enabled."] _1, } impl LPRIOENW { #[allow(missing_docs)] @@ -1132,10 +1097,8 @@ impl<'a> _LPRIOENW<'a> { } #[doc = "Values that can be written to the field `PNET_EN`"] pub enum PNET_ENW { - #[doc = "Pretended Networking mode is disabled."] - _0, - #[doc = "Pretended Networking mode is enabled."] - _1, + #[doc = "Pretended Networking mode is disabled."] _0, + #[doc = "Pretended Networking mode is enabled."] _1, } impl PNET_ENW { #[allow(missing_docs)] @@ -1190,10 +1153,8 @@ impl<'a> _PNET_ENW<'a> { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "DMA feature for RX FIFO disabled."] - _0, - #[doc = "DMA feature for RX FIFO enabled."] - _1, + #[doc = "DMA feature for RX FIFO disabled."] _0, + #[doc = "DMA feature for RX FIFO enabled."] _1, } impl DMAW { #[allow(missing_docs)] @@ -1250,8 +1211,7 @@ impl<'a> _DMAW<'a> { pub enum IRMQW { #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."] _0, - #[doc = "Individual Rx masking and queue feature are enabled."] - _1, + #[doc = "Individual Rx masking and queue feature are enabled."] _1, } impl IRMQW { #[allow(missing_docs)] @@ -1306,10 +1266,8 @@ impl<'a> _IRMQW<'a> { } #[doc = "Values that can be written to the field `SRXDIS`"] pub enum SRXDISW { - #[doc = "Self reception enabled."] - _0, - #[doc = "Self reception disabled."] - _1, + #[doc = "Self reception enabled."] _0, + #[doc = "Self reception disabled."] _1, } impl SRXDISW { #[allow(missing_docs)] @@ -1445,10 +1403,8 @@ impl<'a> _SUPVW<'a> { } #[doc = "Values that can be written to the field `SOFTRST`"] pub enum SOFTRSTW { - #[doc = "No reset request."] - _0, - #[doc = "Resets the registers affected by soft reset."] - _1, + #[doc = "No reset request."] _0, + #[doc = "Resets the registers affected by soft reset."] _1, } impl SOFTRSTW { #[allow(missing_docs)] @@ -1503,10 +1459,8 @@ impl<'a> _SOFTRSTW<'a> { } #[doc = "Values that can be written to the field `HALT`"] pub enum HALTW { - #[doc = "No Freeze mode request."] - _0, - #[doc = "Enters Freeze mode if the FRZ bit is asserted."] - _1, + #[doc = "No Freeze mode request."] _0, + #[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1, } impl HALTW { #[allow(missing_docs)] @@ -1561,10 +1515,8 @@ impl<'a> _HALTW<'a> { } #[doc = "Values that can be written to the field `RFEN`"] pub enum RFENW { - #[doc = "Rx FIFO not enabled."] - _0, - #[doc = "Rx FIFO enabled."] - _1, + #[doc = "Rx FIFO not enabled."] _0, + #[doc = "Rx FIFO enabled."] _1, } impl RFENW { #[allow(missing_docs)] @@ -1619,10 +1571,8 @@ impl<'a> _RFENW<'a> { } #[doc = "Values that can be written to the field `FRZ`"] pub enum FRZW { - #[doc = "Not enabled to enter Freeze mode."] - _0, - #[doc = "Enabled to enter Freeze mode."] - _1, + #[doc = "Not enabled to enter Freeze mode."] _0, + #[doc = "Enabled to enter Freeze mode."] _1, } impl FRZW { #[allow(missing_docs)] @@ -1677,10 +1627,8 @@ impl<'a> _FRZW<'a> { } #[doc = "Values that can be written to the field `MDIS`"] pub enum MDISW { - #[doc = "Enable the FlexCAN module."] - _0, - #[doc = "Disable the FlexCAN module."] - _1, + #[doc = "Enable the FlexCAN module."] _0, + #[doc = "Disable the FlexCAN module."] _1, } impl MDISW { #[allow(missing_docs)] diff --git a/src/can2/mod.rs b/src/can2/mod.rs index bd086bc..054059d 100644 --- a/src/can2/mod.rs +++ b/src/can2/mod.rs @@ -2,93 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Module Configuration Register"] - pub mcr: MCR, - #[doc = "0x04 - Control 1 register"] - pub ctrl1: CTRL1, - #[doc = "0x08 - Free Running Timer"] - pub timer: TIMER, + #[doc = "0x00 - Module Configuration Register"] pub mcr: MCR, + #[doc = "0x04 - Control 1 register"] pub ctrl1: CTRL1, + #[doc = "0x08 - Free Running Timer"] pub timer: TIMER, _reserved0: [u8; 4usize], - #[doc = "0x10 - Rx Mailboxes Global Mask Register"] - pub rxmgmask: RXMGMASK, - #[doc = "0x14 - Rx 14 Mask register"] - pub rx14mask: RX14MASK, - #[doc = "0x18 - Rx 15 Mask register"] - pub rx15mask: RX15MASK, - #[doc = "0x1c - Error Counter"] - pub ecr: ECR, - #[doc = "0x20 - Error and Status 1 register"] - pub esr1: ESR1, + #[doc = "0x10 - Rx Mailboxes Global Mask Register"] pub rxmgmask: RXMGMASK, + #[doc = "0x14 - Rx 14 Mask register"] pub rx14mask: RX14MASK, + #[doc = "0x18 - Rx 15 Mask register"] pub rx15mask: RX15MASK, + #[doc = "0x1c - Error Counter"] pub ecr: ECR, + #[doc = "0x20 - Error and Status 1 register"] pub esr1: ESR1, _reserved1: [u8; 4usize], - #[doc = "0x28 - Interrupt Masks 1 register"] - pub imask1: IMASK1, + #[doc = "0x28 - Interrupt Masks 1 register"] pub imask1: IMASK1, _reserved2: [u8; 4usize], - #[doc = "0x30 - Interrupt Flags 1 register"] - pub iflag1: IFLAG1, - #[doc = "0x34 - Control 2 register"] - pub ctrl2: CTRL2, - #[doc = "0x38 - Error and Status 2 register"] - pub esr2: ESR2, + #[doc = "0x30 - Interrupt Flags 1 register"] pub iflag1: IFLAG1, + #[doc = "0x34 - Control 2 register"] pub ctrl2: CTRL2, + #[doc = "0x38 - Error and Status 2 register"] pub esr2: ESR2, _reserved3: [u8; 8usize], - #[doc = "0x44 - CRC Register"] - pub crcr: CRCR, - #[doc = "0x48 - Rx FIFO Global Mask register"] - pub rxfgmask: RXFGMASK, - #[doc = "0x4c - Rx FIFO Information Register"] - pub rxfir: RXFIR, - #[doc = "0x50 - CAN Bit Timing Register"] - pub cbt: CBT, + #[doc = "0x44 - CRC Register"] pub crcr: CRCR, + #[doc = "0x48 - Rx FIFO Global Mask register"] pub rxfgmask: RXFGMASK, + #[doc = "0x4c - Rx FIFO Information Register"] pub rxfir: RXFIR, + #[doc = "0x50 - CAN Bit Timing Register"] pub cbt: CBT, _reserved4: [u8; 44usize], - #[doc = "0x80 - Embedded RAM"] - pub embedded_ram: [EMBEDDEDRAM; 128], + #[doc = "0x80 - Embedded RAM"] pub embedded_ram: [EMBEDDEDRAM; 128], _reserved5: [u8; 1536usize], - #[doc = "0x880 - Rx Individual Mask Registers"] - pub rximr0: RXIMR0, - #[doc = "0x884 - Rx Individual Mask Registers"] - pub rximr1: RXIMR1, - #[doc = "0x888 - Rx Individual Mask Registers"] - pub rximr2: RXIMR2, - #[doc = "0x88c - Rx Individual Mask Registers"] - pub rximr3: RXIMR3, - #[doc = "0x890 - Rx Individual Mask Registers"] - pub rximr4: RXIMR4, - #[doc = "0x894 - Rx Individual Mask Registers"] - pub rximr5: RXIMR5, - #[doc = "0x898 - Rx Individual Mask Registers"] - pub rximr6: RXIMR6, - #[doc = "0x89c - Rx Individual Mask Registers"] - pub rximr7: RXIMR7, - #[doc = "0x8a0 - Rx Individual Mask Registers"] - pub rximr8: RXIMR8, - #[doc = "0x8a4 - Rx Individual Mask Registers"] - pub rximr9: RXIMR9, - #[doc = "0x8a8 - Rx Individual Mask Registers"] - pub rximr10: RXIMR10, - #[doc = "0x8ac - Rx Individual Mask Registers"] - pub rximr11: RXIMR11, - #[doc = "0x8b0 - Rx Individual Mask Registers"] - pub rximr12: RXIMR12, - #[doc = "0x8b4 - Rx Individual Mask Registers"] - pub rximr13: RXIMR13, - #[doc = "0x8b8 - Rx Individual Mask Registers"] - pub rximr14: RXIMR14, - #[doc = "0x8bc - Rx Individual Mask Registers"] - pub rximr15: RXIMR15, + #[doc = "0x880 - Rx Individual Mask Registers"] pub rximr0: RXIMR0, + #[doc = "0x884 - Rx Individual Mask Registers"] pub rximr1: RXIMR1, + #[doc = "0x888 - Rx Individual Mask Registers"] pub rximr2: RXIMR2, + #[doc = "0x88c - Rx Individual Mask Registers"] pub rximr3: RXIMR3, + #[doc = "0x890 - Rx Individual Mask Registers"] pub rximr4: RXIMR4, + #[doc = "0x894 - Rx Individual Mask Registers"] pub rximr5: RXIMR5, + #[doc = "0x898 - Rx Individual Mask Registers"] pub rximr6: RXIMR6, + #[doc = "0x89c - Rx Individual Mask Registers"] pub rximr7: RXIMR7, + #[doc = "0x8a0 - Rx Individual Mask Registers"] pub rximr8: RXIMR8, + #[doc = "0x8a4 - Rx Individual Mask Registers"] pub rximr9: RXIMR9, + #[doc = "0x8a8 - Rx Individual Mask Registers"] pub rximr10: RXIMR10, + #[doc = "0x8ac - Rx Individual Mask Registers"] pub rximr11: RXIMR11, + #[doc = "0x8b0 - Rx Individual Mask Registers"] pub rximr12: RXIMR12, + #[doc = "0x8b4 - Rx Individual Mask Registers"] pub rximr13: RXIMR13, + #[doc = "0x8b8 - Rx Individual Mask Registers"] pub rximr14: RXIMR14, + #[doc = "0x8bc - Rx Individual Mask Registers"] pub rximr15: RXIMR15, _reserved6: [u8; 576usize], - #[doc = "0xb00 - Pretended Networking Control 1 Register"] - pub ctrl1_pn: CTRL1_PN, - #[doc = "0xb04 - Pretended Networking Control 2 Register"] - pub ctrl2_pn: CTRL2_PN, - #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] - pub wu_mtc: WU_MTC, - #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] - pub flt_id1: FLT_ID1, - #[doc = "0xb10 - Pretended Networking DLC Filter Register"] - pub flt_dlc: FLT_DLC, - #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] - pub pl1_lo: PL1_LO, - #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] - pub pl1_hi: PL1_HI, + #[doc = "0xb00 - Pretended Networking Control 1 Register"] pub ctrl1_pn: CTRL1_PN, + #[doc = "0xb04 - Pretended Networking Control 2 Register"] pub ctrl2_pn: CTRL2_PN, + #[doc = "0xb08 - Pretended Networking Wake Up Match Register"] pub wu_mtc: WU_MTC, + #[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] pub flt_id1: FLT_ID1, + #[doc = "0xb10 - Pretended Networking DLC Filter Register"] pub flt_dlc: FLT_DLC, + #[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] pub pl1_lo: PL1_LO, + #[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] pub pl1_hi: PL1_HI, #[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"] pub flt_id2_idmask: FLT_ID2_IDMASK, #[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"] @@ -96,45 +56,26 @@ pub struct RegisterBlock { #[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"] pub pl2_plmask_hi: PL2_PLMASK_HI, _reserved7: [u8; 24usize], - #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] - pub wmb0_cs: WMB0_CS, - #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] - pub wmb0_id: WMB0_ID, - #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb0_d03: WMB0_D03, - #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] - pub wmb0_d47: WMB0_D47, - #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] - pub wmb1_cs: WMB1_CS, - #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] - pub wmb1_id: WMB1_ID, - #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb1_d03: WMB1_D03, - #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] - pub wmb1_d47: WMB1_D47, - #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] - pub wmb2_cs: WMB2_CS, - #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] - pub wmb2_id: WMB2_ID, - #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb2_d03: WMB2_D03, - #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] - pub wmb2_d47: WMB2_D47, - #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] - pub wmb3_cs: WMB3_CS, - #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] - pub wmb3_id: WMB3_ID, - #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] - pub wmb3_d03: WMB3_D03, - #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] - pub wmb3_d47: WMB3_D47, + #[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] pub wmb0_cs: WMB0_CS, + #[doc = "0xb44 - Wake Up Message Buffer Register for ID"] pub wmb0_id: WMB0_ID, + #[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] pub wmb0_d03: WMB0_D03, + #[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] pub wmb0_d47: WMB0_D47, + #[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] pub wmb1_cs: WMB1_CS, + #[doc = "0xb54 - Wake Up Message Buffer Register for ID"] pub wmb1_id: WMB1_ID, + #[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] pub wmb1_d03: WMB1_D03, + #[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] pub wmb1_d47: WMB1_D47, + #[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] pub wmb2_cs: WMB2_CS, + #[doc = "0xb64 - Wake Up Message Buffer Register for ID"] pub wmb2_id: WMB2_ID, + #[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] pub wmb2_d03: WMB2_D03, + #[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] pub wmb2_d47: WMB2_D47, + #[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] pub wmb3_cs: WMB3_CS, + #[doc = "0xb74 - Wake Up Message Buffer Register for ID"] pub wmb3_id: WMB3_ID, + #[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] pub wmb3_d03: WMB3_D03, + #[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] pub wmb3_d47: WMB3_D47, _reserved8: [u8; 128usize], - #[doc = "0xc00 - CAN FD Control Register"] - pub fdctrl: FDCTRL, - #[doc = "0xc04 - CAN FD Bit Timing Register"] - pub fdcbt: FDCBT, - #[doc = "0xc08 - CAN FD CRC Register"] - pub fdcrc: FDCRC, + #[doc = "0xc00 - CAN FD Control Register"] pub fdctrl: FDCTRL, + #[doc = "0xc04 - CAN FD Bit Timing Register"] pub fdcbt: FDCBT, + #[doc = "0xc08 - CAN FD CRC Register"] pub fdcrc: FDCRC, } #[doc = "Module Configuration Register"] pub struct MCR { diff --git a/src/can2/pl1_hi/mod.rs b/src/can2/pl1_hi/mod.rs index 7b090b3..ab431b7 100644 --- a/src/can2/pl1_hi/mod.rs +++ b/src/can2/pl1_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/pl1_lo/mod.rs b/src/can2/pl1_lo/mod.rs index 363ae74..6e07f19 100644 --- a/src/can2/pl1_lo/mod.rs +++ b/src/can2/pl1_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL1_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/pl2_plmask_hi/mod.rs b/src/can2/pl2_plmask_hi/mod.rs index f4943ba..32cc6bd 100644 --- a/src/can2/pl2_plmask_hi/mod.rs +++ b/src/can2/pl2_plmask_hi/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_HI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/pl2_plmask_lo/mod.rs b/src/can2/pl2_plmask_lo/mod.rs index eb939de..358d16f 100644 --- a/src/can2/pl2_plmask_lo/mod.rs +++ b/src/can2/pl2_plmask_lo/mod.rs @@ -22,7 +22,9 @@ impl super::PL2_PLMASK_LO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rx14mask/mod.rs b/src/can2/rx14mask/mod.rs index 068409e..5670ed6 100644 --- a/src/can2/rx14mask/mod.rs +++ b/src/can2/rx14mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX14MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rx15mask/mod.rs b/src/can2/rx15mask/mod.rs index 5f05ad1..e97bce8 100644 --- a/src/can2/rx15mask/mod.rs +++ b/src/can2/rx15mask/mod.rs @@ -22,7 +22,9 @@ impl super::RX15MASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rxfgmask/mod.rs b/src/can2/rxfgmask/mod.rs index 2cafbce..db4555e 100644 --- a/src/can2/rxfgmask/mod.rs +++ b/src/can2/rxfgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXFGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rxfir/mod.rs b/src/can2/rxfir/mod.rs index 50db283..2221db3 100644 --- a/src/can2/rxfir/mod.rs +++ b/src/can2/rxfir/mod.rs @@ -6,7 +6,9 @@ impl super::RXFIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/rximr0/mod.rs b/src/can2/rximr0/mod.rs index 9632744..301c690 100644 --- a/src/can2/rximr0/mod.rs +++ b/src/can2/rximr0/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr1/mod.rs b/src/can2/rximr1/mod.rs index f9c8ab4..fb71a89 100644 --- a/src/can2/rximr1/mod.rs +++ b/src/can2/rximr1/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr10/mod.rs b/src/can2/rximr10/mod.rs index 7f61429..b43cc60 100644 --- a/src/can2/rximr10/mod.rs +++ b/src/can2/rximr10/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr11/mod.rs b/src/can2/rximr11/mod.rs index 20d5cdb..644a727 100644 --- a/src/can2/rximr11/mod.rs +++ b/src/can2/rximr11/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr12/mod.rs b/src/can2/rximr12/mod.rs index a3a94dd..779cda3 100644 --- a/src/can2/rximr12/mod.rs +++ b/src/can2/rximr12/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr13/mod.rs b/src/can2/rximr13/mod.rs index 974628a..b457c29 100644 --- a/src/can2/rximr13/mod.rs +++ b/src/can2/rximr13/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr14/mod.rs b/src/can2/rximr14/mod.rs index 193e9ae..d637965 100644 --- a/src/can2/rximr14/mod.rs +++ b/src/can2/rximr14/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr15/mod.rs b/src/can2/rximr15/mod.rs index 899ec96..8b60538 100644 --- a/src/can2/rximr15/mod.rs +++ b/src/can2/rximr15/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr2/mod.rs b/src/can2/rximr2/mod.rs index bffb2eb..b79c370 100644 --- a/src/can2/rximr2/mod.rs +++ b/src/can2/rximr2/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr3/mod.rs b/src/can2/rximr3/mod.rs index df84bb2..dc21ee1 100644 --- a/src/can2/rximr3/mod.rs +++ b/src/can2/rximr3/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr4/mod.rs b/src/can2/rximr4/mod.rs index d1ffc2a..2a5d5a7 100644 --- a/src/can2/rximr4/mod.rs +++ b/src/can2/rximr4/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr5/mod.rs b/src/can2/rximr5/mod.rs index 2d67f95..7500c7a 100644 --- a/src/can2/rximr5/mod.rs +++ b/src/can2/rximr5/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr6/mod.rs b/src/can2/rximr6/mod.rs index b5879da..c7582e2 100644 --- a/src/can2/rximr6/mod.rs +++ b/src/can2/rximr6/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr7/mod.rs b/src/can2/rximr7/mod.rs index 674dc6b..a5de575 100644 --- a/src/can2/rximr7/mod.rs +++ b/src/can2/rximr7/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr8/mod.rs b/src/can2/rximr8/mod.rs index 6fac312..626ec56 100644 --- a/src/can2/rximr8/mod.rs +++ b/src/can2/rximr8/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rximr9/mod.rs b/src/can2/rximr9/mod.rs index b21a830..4acd2f7 100644 --- a/src/can2/rximr9/mod.rs +++ b/src/can2/rximr9/mod.rs @@ -22,7 +22,9 @@ impl super::RXIMR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/rxmgmask/mod.rs b/src/can2/rxmgmask/mod.rs index da42c27..dc87f29 100644 --- a/src/can2/rxmgmask/mod.rs +++ b/src/can2/rxmgmask/mod.rs @@ -22,7 +22,9 @@ impl super::RXMGMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/timer/mod.rs b/src/can2/timer/mod.rs index c5d0eb6..7a46bca 100644 --- a/src/can2/timer/mod.rs +++ b/src/can2/timer/mod.rs @@ -22,7 +22,9 @@ impl super::TIMER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/can2/wmb0_cs/mod.rs b/src/can2/wmb0_cs/mod.rs index 4562128..fa731f4 100644 --- a/src/can2/wmb0_cs/mod.rs +++ b/src/can2/wmb0_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can2/wmb0_d03/mod.rs b/src/can2/wmb0_d03/mod.rs index 4d5dc99..90e28be 100644 --- a/src/can2/wmb0_d03/mod.rs +++ b/src/can2/wmb0_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb0_d47/mod.rs b/src/can2/wmb0_d47/mod.rs index b074c72..f567362 100644 --- a/src/can2/wmb0_d47/mod.rs +++ b/src/can2/wmb0_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb0_id/mod.rs b/src/can2/wmb0_id/mod.rs index 9621d2c..e76a1a5 100644 --- a/src/can2/wmb0_id/mod.rs +++ b/src/can2/wmb0_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB0_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb1_cs/mod.rs b/src/can2/wmb1_cs/mod.rs index 4c426aa..f54e732 100644 --- a/src/can2/wmb1_cs/mod.rs +++ b/src/can2/wmb1_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can2/wmb1_d03/mod.rs b/src/can2/wmb1_d03/mod.rs index 78d7079..7eb5aeb 100644 --- a/src/can2/wmb1_d03/mod.rs +++ b/src/can2/wmb1_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb1_d47/mod.rs b/src/can2/wmb1_d47/mod.rs index 3499051..b4df930 100644 --- a/src/can2/wmb1_d47/mod.rs +++ b/src/can2/wmb1_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb1_id/mod.rs b/src/can2/wmb1_id/mod.rs index c1e4593..5466ab1 100644 --- a/src/can2/wmb1_id/mod.rs +++ b/src/can2/wmb1_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB1_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb2_cs/mod.rs b/src/can2/wmb2_cs/mod.rs index df6e9c2..f37b0a2 100644 --- a/src/can2/wmb2_cs/mod.rs +++ b/src/can2/wmb2_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can2/wmb2_d03/mod.rs b/src/can2/wmb2_d03/mod.rs index 83ad28a..15406c4 100644 --- a/src/can2/wmb2_d03/mod.rs +++ b/src/can2/wmb2_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb2_d47/mod.rs b/src/can2/wmb2_d47/mod.rs index 0d57550..30b3c6b 100644 --- a/src/can2/wmb2_d47/mod.rs +++ b/src/can2/wmb2_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb2_id/mod.rs b/src/can2/wmb2_id/mod.rs index a4c67b3..c421aa6 100644 --- a/src/can2/wmb2_id/mod.rs +++ b/src/can2/wmb2_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB2_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb3_cs/mod.rs b/src/can2/wmb3_cs/mod.rs index 92c6dd9..05b7b1f 100644 --- a/src/can2/wmb3_cs/mod.rs +++ b/src/can2/wmb3_cs/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DLCR { #[doc = "Possible values of the field `RTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTRR { - #[doc = "Frame is data one (not remote)"] - _0, - #[doc = "Frame is a remote one"] - _1, + #[doc = "Frame is data one (not remote)"] _0, + #[doc = "Frame is a remote one"] _1, } impl RTRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -70,10 +70,8 @@ impl RTRR { #[doc = "Possible values of the field `IDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDER { - #[doc = "Frame format is standard"] - _0, - #[doc = "Frame format is extended"] - _1, + #[doc = "Frame format is standard"] _0, + #[doc = "Frame format is extended"] _1, } impl IDER { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/can2/wmb3_d03/mod.rs b/src/can2/wmb3_d03/mod.rs index 064dfa5..64f4c8f 100644 --- a/src/can2/wmb3_d03/mod.rs +++ b/src/can2/wmb3_d03/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D03 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb3_d47/mod.rs b/src/can2/wmb3_d47/mod.rs index 494d46c..a60b2ae 100644 --- a/src/can2/wmb3_d47/mod.rs +++ b/src/can2/wmb3_d47/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_D47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wmb3_id/mod.rs b/src/can2/wmb3_id/mod.rs index 25d4e25..6b7ac79 100644 --- a/src/can2/wmb3_id/mod.rs +++ b/src/can2/wmb3_id/mod.rs @@ -6,7 +6,9 @@ impl super::WMB3_ID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/can2/wu_mtc/mod.rs b/src/can2/wu_mtc/mod.rs index 30239c5..04c03ba 100644 --- a/src/can2/wu_mtc/mod.rs +++ b/src/can2/wu_mtc/mod.rs @@ -22,7 +22,9 @@ impl super::WU_MTC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl MCOUNTERR { #[doc = "Possible values of the field `WUMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WUMFR { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl WUMFR { #[doc = "Possible values of the field `WTOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WTOFR { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -147,10 +145,8 @@ impl WTOFR { } #[doc = "Values that can be written to the field `WUMF`"] pub enum WUMFW { - #[doc = "No wake up by match event detected"] - _0, - #[doc = "Wake up by match event detected"] - _1, + #[doc = "No wake up by match event detected"] _0, + #[doc = "Wake up by match event detected"] _1, } impl WUMFW { #[allow(missing_docs)] @@ -205,10 +201,8 @@ impl<'a> _WUMFW<'a> { } #[doc = "Values that can be written to the field `WTOF`"] pub enum WTOFW { - #[doc = "No wake up by timeout event detected"] - _0, - #[doc = "Wake up by timeout event detected"] - _1, + #[doc = "No wake up by timeout event detected"] _0, + #[doc = "Wake up by timeout event detected"] _1, } impl WTOFW { #[allow(missing_docs)] diff --git a/src/cmp0/c0/mod.rs b/src/cmp0/c0/mod.rs index 36cc8a6..81b8fc0 100644 --- a/src/cmp0/c0/mod.rs +++ b/src/cmp0/c0/mod.rs @@ -22,7 +22,9 @@ impl super::C0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::C0 { #[doc = "Possible values of the field `HYSTCTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HYSTCTRR { - #[doc = "The hard block output has level 0 hysteresis internally."] - _00, - #[doc = "The hard block output has level 1 hysteresis internally."] - _01, - #[doc = "The hard block output has level 2 hysteresis internally."] - _10, - #[doc = "The hard block output has level 3 hysteresis internally."] - _11, + #[doc = "The hard block output has level 0 hysteresis internally."] _00, + #[doc = "The hard block output has level 1 hysteresis internally."] _01, + #[doc = "The hard block output has level 2 hysteresis internally."] _10, + #[doc = "The hard block output has level 3 hysteresis internally."] _11, } impl HYSTCTRR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl HYSTCTRR { #[doc = "Possible values of the field `OFFSET`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OFFSETR { - #[doc = "The comparator hard block output has level 0 offset internally."] - _0, - #[doc = "The comparator hard block output has level 1 offset internally."] - _1, + #[doc = "The comparator hard block output has level 0 offset internally."] _0, + #[doc = "The comparator hard block output has level 1 offset internally."] _1, } impl OFFSETR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,20 +144,13 @@ impl OFFSETR { pub enum FILTER_CNTR { #[doc = "Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA."] _000, - #[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] - _001, - #[doc = "2 consecutive samples must agree."] - _010, - #[doc = "3 consecutive samples must agree."] - _011, - #[doc = "4 consecutive samples must agree."] - _100, - #[doc = "5 consecutive samples must agree."] - _101, - #[doc = "6 consecutive samples must agree."] - _110, - #[doc = "7 consecutive samples must agree."] - _111, + #[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] _001, + #[doc = "2 consecutive samples must agree."] _010, + #[doc = "3 consecutive samples must agree."] _011, + #[doc = "4 consecutive samples must agree."] _100, + #[doc = "5 consecutive samples must agree."] _101, + #[doc = "6 consecutive samples must agree."] _110, + #[doc = "7 consecutive samples must agree."] _111, } impl FILTER_CNTR { #[doc = r" Value of the field as raw bits"] @@ -238,10 +227,8 @@ impl FILTER_CNTR { #[doc = "Possible values of the field `EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENR { - #[doc = "Analog Comparator is disabled."] - _0, - #[doc = "Analog Comparator is enabled."] - _1, + #[doc = "Analog Comparator is disabled."] _0, + #[doc = "Analog Comparator is enabled."] _1, } impl ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -332,10 +319,8 @@ impl OPER { #[doc = "Possible values of the field `COS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COSR { - #[doc = "Set CMPO to equal COUT (filtered comparator output)."] - _0, - #[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] - _1, + #[doc = "Set CMPO to equal COUT (filtered comparator output)."] _0, + #[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] _1, } impl COSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -379,10 +364,8 @@ impl COSR { #[doc = "Possible values of the field `INVT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INVTR { - #[doc = "Does not invert the comparator output."] - _0, - #[doc = "Inverts the comparator output."] - _1, + #[doc = "Does not invert the comparator output."] _0, + #[doc = "Inverts the comparator output."] _1, } impl INVTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -426,8 +409,7 @@ impl INVTR { #[doc = "Possible values of the field `PMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PMODER { - #[doc = "Low Speed (LS) comparison mode is selected."] - _0, + #[doc = "Low Speed (LS) comparison mode is selected."] _0, #[doc = "High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode."] _1, } @@ -473,10 +455,8 @@ impl PMODER { #[doc = "Possible values of the field `WE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WER { - #[doc = "Windowing mode is not selected."] - _0, - #[doc = "Windowing mode is selected."] - _1, + #[doc = "Windowing mode is not selected."] _0, + #[doc = "Windowing mode is selected."] _1, } impl WER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -520,10 +500,8 @@ impl WER { #[doc = "Possible values of the field `SE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SER { - #[doc = "Sampling mode is not selected."] - _0, - #[doc = "Sampling mode is selected."] - _1, + #[doc = "Sampling mode is not selected."] _0, + #[doc = "Sampling mode is selected."] _1, } impl SER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -599,10 +577,8 @@ impl COUTR { #[doc = "Possible values of the field `CFF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CFFR { - #[doc = "A falling edge has not been detected on COUT."] - _0, - #[doc = "A falling edge on COUT has occurred."] - _1, + #[doc = "A falling edge has not been detected on COUT."] _0, + #[doc = "A falling edge on COUT has occurred."] _1, } impl CFFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -646,10 +622,8 @@ impl CFFR { #[doc = "Possible values of the field `CFR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CFRR { - #[doc = "A rising edge has not been detected on COUT."] - _0, - #[doc = "A rising edge on COUT has occurred."] - _1, + #[doc = "A rising edge has not been detected on COUT."] _0, + #[doc = "A rising edge on COUT has occurred."] _1, } impl CFRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -693,10 +667,8 @@ impl CFRR { #[doc = "Possible values of the field `IEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IEFR { - #[doc = "Interrupt is disabled."] - _0, - #[doc = "Interrupt is enabled."] - _1, + #[doc = "Interrupt is disabled."] _0, + #[doc = "Interrupt is enabled."] _1, } impl IEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -740,10 +712,8 @@ impl IEFR { #[doc = "Possible values of the field `IER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IERR { - #[doc = "Interrupt is disabled."] - _0, - #[doc = "Interrupt is enabled."] - _1, + #[doc = "Interrupt is disabled."] _0, + #[doc = "Interrupt is enabled."] _1, } impl IERR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -787,10 +757,8 @@ impl IERR { #[doc = "Possible values of the field `DMAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAENR { - #[doc = "DMA is disabled."] - _0, - #[doc = "DMA is enabled."] - _1, + #[doc = "DMA is disabled."] _0, + #[doc = "DMA is enabled."] _1, } impl DMAENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -833,14 +801,10 @@ impl DMAENR { } #[doc = "Values that can be written to the field `HYSTCTR`"] pub enum HYSTCTRW { - #[doc = "The hard block output has level 0 hysteresis internally."] - _00, - #[doc = "The hard block output has level 1 hysteresis internally."] - _01, - #[doc = "The hard block output has level 2 hysteresis internally."] - _10, - #[doc = "The hard block output has level 3 hysteresis internally."] - _11, + #[doc = "The hard block output has level 0 hysteresis internally."] _00, + #[doc = "The hard block output has level 1 hysteresis internally."] _01, + #[doc = "The hard block output has level 2 hysteresis internally."] _10, + #[doc = "The hard block output has level 3 hysteresis internally."] _11, } impl HYSTCTRW { #[allow(missing_docs)] @@ -899,10 +863,8 @@ impl<'a> _HYSTCTRW<'a> { } #[doc = "Values that can be written to the field `OFFSET`"] pub enum OFFSETW { - #[doc = "The comparator hard block output has level 0 offset internally."] - _0, - #[doc = "The comparator hard block output has level 1 offset internally."] - _1, + #[doc = "The comparator hard block output has level 0 offset internally."] _0, + #[doc = "The comparator hard block output has level 1 offset internally."] _1, } impl OFFSETW { #[allow(missing_docs)] @@ -959,20 +921,13 @@ impl<'a> _OFFSETW<'a> { pub enum FILTER_CNTW { #[doc = "Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA."] _000, - #[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] - _001, - #[doc = "2 consecutive samples must agree."] - _010, - #[doc = "3 consecutive samples must agree."] - _011, - #[doc = "4 consecutive samples must agree."] - _100, - #[doc = "5 consecutive samples must agree."] - _101, - #[doc = "6 consecutive samples must agree."] - _110, - #[doc = "7 consecutive samples must agree."] - _111, + #[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] _001, + #[doc = "2 consecutive samples must agree."] _010, + #[doc = "3 consecutive samples must agree."] _011, + #[doc = "4 consecutive samples must agree."] _100, + #[doc = "5 consecutive samples must agree."] _101, + #[doc = "6 consecutive samples must agree."] _110, + #[doc = "7 consecutive samples must agree."] _111, } impl FILTER_CNTW { #[allow(missing_docs)] @@ -1055,10 +1010,8 @@ impl<'a> _FILTER_CNTW<'a> { } #[doc = "Values that can be written to the field `EN`"] pub enum ENW { - #[doc = "Analog Comparator is disabled."] - _0, - #[doc = "Analog Comparator is enabled."] - _1, + #[doc = "Analog Comparator is disabled."] _0, + #[doc = "Analog Comparator is enabled."] _1, } impl ENW { #[allow(missing_docs)] @@ -1171,10 +1124,8 @@ impl<'a> _OPEW<'a> { } #[doc = "Values that can be written to the field `COS`"] pub enum COSW { - #[doc = "Set CMPO to equal COUT (filtered comparator output)."] - _0, - #[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] - _1, + #[doc = "Set CMPO to equal COUT (filtered comparator output)."] _0, + #[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] _1, } impl COSW { #[allow(missing_docs)] @@ -1229,10 +1180,8 @@ impl<'a> _COSW<'a> { } #[doc = "Values that can be written to the field `INVT`"] pub enum INVTW { - #[doc = "Does not invert the comparator output."] - _0, - #[doc = "Inverts the comparator output."] - _1, + #[doc = "Does not invert the comparator output."] _0, + #[doc = "Inverts the comparator output."] _1, } impl INVTW { #[allow(missing_docs)] @@ -1287,8 +1236,7 @@ impl<'a> _INVTW<'a> { } #[doc = "Values that can be written to the field `PMODE`"] pub enum PMODEW { - #[doc = "Low Speed (LS) comparison mode is selected."] - _0, + #[doc = "Low Speed (LS) comparison mode is selected."] _0, #[doc = "High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode."] _1, } @@ -1345,10 +1293,8 @@ impl<'a> _PMODEW<'a> { } #[doc = "Values that can be written to the field `WE`"] pub enum WEW { - #[doc = "Windowing mode is not selected."] - _0, - #[doc = "Windowing mode is selected."] - _1, + #[doc = "Windowing mode is not selected."] _0, + #[doc = "Windowing mode is selected."] _1, } impl WEW { #[allow(missing_docs)] @@ -1403,10 +1349,8 @@ impl<'a> _WEW<'a> { } #[doc = "Values that can be written to the field `SE`"] pub enum SEW { - #[doc = "Sampling mode is not selected."] - _0, - #[doc = "Sampling mode is selected."] - _1, + #[doc = "Sampling mode is not selected."] _0, + #[doc = "Sampling mode is selected."] _1, } impl SEW { #[allow(missing_docs)] @@ -1476,10 +1420,8 @@ impl<'a> _FPRW<'a> { } #[doc = "Values that can be written to the field `CFF`"] pub enum CFFW { - #[doc = "A falling edge has not been detected on COUT."] - _0, - #[doc = "A falling edge on COUT has occurred."] - _1, + #[doc = "A falling edge has not been detected on COUT."] _0, + #[doc = "A falling edge on COUT has occurred."] _1, } impl CFFW { #[allow(missing_docs)] @@ -1534,10 +1476,8 @@ impl<'a> _CFFW<'a> { } #[doc = "Values that can be written to the field `CFR`"] pub enum CFRW { - #[doc = "A rising edge has not been detected on COUT."] - _0, - #[doc = "A rising edge on COUT has occurred."] - _1, + #[doc = "A rising edge has not been detected on COUT."] _0, + #[doc = "A rising edge on COUT has occurred."] _1, } impl CFRW { #[allow(missing_docs)] @@ -1592,10 +1532,8 @@ impl<'a> _CFRW<'a> { } #[doc = "Values that can be written to the field `IEF`"] pub enum IEFW { - #[doc = "Interrupt is disabled."] - _0, - #[doc = "Interrupt is enabled."] - _1, + #[doc = "Interrupt is disabled."] _0, + #[doc = "Interrupt is enabled."] _1, } impl IEFW { #[allow(missing_docs)] @@ -1650,10 +1588,8 @@ impl<'a> _IEFW<'a> { } #[doc = "Values that can be written to the field `IER`"] pub enum IERW { - #[doc = "Interrupt is disabled."] - _0, - #[doc = "Interrupt is enabled."] - _1, + #[doc = "Interrupt is disabled."] _0, + #[doc = "Interrupt is enabled."] _1, } impl IERW { #[allow(missing_docs)] @@ -1708,10 +1644,8 @@ impl<'a> _IERW<'a> { } #[doc = "Values that can be written to the field `DMAEN`"] pub enum DMAENW { - #[doc = "DMA is disabled."] - _0, - #[doc = "DMA is enabled."] - _1, + #[doc = "DMA is disabled."] _0, + #[doc = "DMA is enabled."] _1, } impl DMAENW { #[allow(missing_docs)] diff --git a/src/cmp0/c1/mod.rs b/src/cmp0/c1/mod.rs index 6a047b6..06a6e37 100644 --- a/src/cmp0/c1/mod.rs +++ b/src/cmp0/c1/mod.rs @@ -22,7 +22,9 @@ impl super::C1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,22 +56,14 @@ impl VOSELR { #[doc = "Possible values of the field `MSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MSELR { - #[doc = "IN0"] - _000, - #[doc = "IN1"] - _001, - #[doc = "IN2"] - _010, - #[doc = "IN3"] - _011, - #[doc = "IN4"] - _100, - #[doc = "IN5"] - _101, - #[doc = "IN6"] - _110, - #[doc = "IN7"] - _111, + #[doc = "IN0"] _000, + #[doc = "IN1"] _001, + #[doc = "IN2"] _010, + #[doc = "IN3"] _011, + #[doc = "IN4"] _100, + #[doc = "IN5"] _101, + #[doc = "IN6"] _110, + #[doc = "IN7"] _111, } impl MSELR { #[doc = r" Value of the field as raw bits"] @@ -146,22 +140,14 @@ impl MSELR { #[doc = "Possible values of the field `PSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PSELR { - #[doc = "IN0"] - _000, - #[doc = "IN1"] - _001, - #[doc = "IN2"] - _010, - #[doc = "IN3"] - _011, - #[doc = "IN4"] - _100, - #[doc = "IN5"] - _101, - #[doc = "IN6"] - _110, - #[doc = "IN7"] - _111, + #[doc = "IN0"] _000, + #[doc = "IN1"] _001, + #[doc = "IN2"] _010, + #[doc = "IN3"] _011, + #[doc = "IN4"] _100, + #[doc = "IN5"] _101, + #[doc = "IN6"] _110, + #[doc = "IN7"] _111, } impl PSELR { #[doc = r" Value of the field as raw bits"] @@ -238,10 +224,8 @@ impl PSELR { #[doc = "Possible values of the field `VRSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VRSELR { - #[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] - _0, - #[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] - _1, + #[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] _0, + #[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] _1, } impl VRSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -285,10 +269,8 @@ impl VRSELR { #[doc = "Possible values of the field `DACEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DACENR { - #[doc = "DAC is disabled."] - _0, - #[doc = "DAC is enabled."] - _1, + #[doc = "DAC is disabled."] _0, + #[doc = "DAC is enabled."] _1, } impl DACENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -500,12 +482,9 @@ impl CHN7R { #[doc = "Possible values of the field `INNSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INNSELR { - #[doc = "IN0, from the 8-bit DAC output"] - _00, - #[doc = "IN1, from the analog 8-1 mux"] - _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "IN0, from the 8-bit DAC output"] _00, + #[doc = "IN1, from the analog 8-1 mux"] _01, + #[doc = r" Reserved"] _Reserved(u8), } impl INNSELR { #[doc = r" Value of the field as raw bits"] @@ -541,12 +520,9 @@ impl INNSELR { #[doc = "Possible values of the field `INPSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INPSELR { - #[doc = "IN0, from the 8-bit DAC output"] - _00, - #[doc = "IN1, from the analog 8-1 mux"] - _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "IN0, from the 8-bit DAC output"] _00, + #[doc = "IN1, from the analog 8-1 mux"] _01, + #[doc = r" Reserved"] _Reserved(u8), } impl INPSELR { #[doc = r" Value of the field as raw bits"] @@ -596,22 +572,14 @@ impl<'a> _VOSELW<'a> { } #[doc = "Values that can be written to the field `MSEL`"] pub enum MSELW { - #[doc = "IN0"] - _000, - #[doc = "IN1"] - _001, - #[doc = "IN2"] - _010, - #[doc = "IN3"] - _011, - #[doc = "IN4"] - _100, - #[doc = "IN5"] - _101, - #[doc = "IN6"] - _110, - #[doc = "IN7"] - _111, + #[doc = "IN0"] _000, + #[doc = "IN1"] _001, + #[doc = "IN2"] _010, + #[doc = "IN3"] _011, + #[doc = "IN4"] _100, + #[doc = "IN5"] _101, + #[doc = "IN6"] _110, + #[doc = "IN7"] _111, } impl MSELW { #[allow(missing_docs)] @@ -694,22 +662,14 @@ impl<'a> _MSELW<'a> { } #[doc = "Values that can be written to the field `PSEL`"] pub enum PSELW { - #[doc = "IN0"] - _000, - #[doc = "IN1"] - _001, - #[doc = "IN2"] - _010, - #[doc = "IN3"] - _011, - #[doc = "IN4"] - _100, - #[doc = "IN5"] - _101, - #[doc = "IN6"] - _110, - #[doc = "IN7"] - _111, + #[doc = "IN0"] _000, + #[doc = "IN1"] _001, + #[doc = "IN2"] _010, + #[doc = "IN3"] _011, + #[doc = "IN4"] _100, + #[doc = "IN5"] _101, + #[doc = "IN6"] _110, + #[doc = "IN7"] _111, } impl PSELW { #[allow(missing_docs)] @@ -792,10 +752,8 @@ impl<'a> _PSELW<'a> { } #[doc = "Values that can be written to the field `VRSEL`"] pub enum VRSELW { - #[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] - _0, - #[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] - _1, + #[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] _0, + #[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] _1, } impl VRSELW { #[allow(missing_docs)] @@ -850,10 +808,8 @@ impl<'a> _VRSELW<'a> { } #[doc = "Values that can be written to the field `DACEN`"] pub enum DACENW { - #[doc = "DAC is disabled."] - _0, - #[doc = "DAC is enabled."] - _1, + #[doc = "DAC is disabled."] _0, + #[doc = "DAC is enabled."] _1, } impl DACENW { #[allow(missing_docs)] @@ -1092,10 +1048,8 @@ impl<'a> _CHN7W<'a> { } #[doc = "Values that can be written to the field `INNSEL`"] pub enum INNSELW { - #[doc = "IN0, from the 8-bit DAC output"] - _00, - #[doc = "IN1, from the analog 8-1 mux"] - _01, + #[doc = "IN0, from the 8-bit DAC output"] _00, + #[doc = "IN1, from the analog 8-1 mux"] _01, } impl INNSELW { #[allow(missing_docs)] @@ -1140,10 +1094,8 @@ impl<'a> _INNSELW<'a> { } #[doc = "Values that can be written to the field `INPSEL`"] pub enum INPSELW { - #[doc = "IN0, from the 8-bit DAC output"] - _00, - #[doc = "IN1, from the analog 8-1 mux"] - _01, + #[doc = "IN0, from the 8-bit DAC output"] _00, + #[doc = "IN1, from the analog 8-1 mux"] _01, } impl INPSELW { #[allow(missing_docs)] diff --git a/src/cmp0/c2/mod.rs b/src/cmp0/c2/mod.rs index 050c583..eb9392f 100644 --- a/src/cmp0/c2/mod.rs +++ b/src/cmp0/c2/mod.rs @@ -22,7 +22,9 @@ impl super::C2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl ACONR { #[doc = "Possible values of the field `INITMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INITMODR { - #[doc = "The modulus is set to 64(same with 111111)."] - _000000, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "The modulus is set to 64(same with 111111)."] _000000, + #[doc = r" Reserved"] _Reserved(u8), } impl INITMODR { #[doc = r" Value of the field as raw bits"] @@ -310,22 +310,14 @@ impl CH7FR { #[doc = "Possible values of the field `FXMXCH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FXMXCHR { - #[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] - _000, - #[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] - _001, - #[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] - _010, - #[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] - _011, - #[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] - _100, - #[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] - _101, - #[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] - _110, - #[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] - _111, + #[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] _000, + #[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] _001, + #[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] _010, + #[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] _011, + #[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] _100, + #[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] _101, + #[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] _110, + #[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] _111, } impl FXMXCHR { #[doc = r" Value of the field as raw bits"] @@ -402,10 +394,8 @@ impl FXMXCHR { #[doc = "Possible values of the field `FXMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FXMPR { - #[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] - _0, - #[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] - _1, + #[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] _0, + #[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] _1, } impl FXMPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -449,8 +439,7 @@ impl FXMPR { #[doc = "Possible values of the field `RRIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RRIER { - #[doc = "The round-robin interrupt is disabled."] - _0, + #[doc = "The round-robin interrupt is disabled."] _0, #[doc = "The round-robin interrupt is enabled when a comparison result changes from the last sample."] _1, } @@ -496,10 +485,8 @@ impl RRIER { #[doc = "Possible values of the field `RRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RRER { - #[doc = "Round-robin operation is disabled."] - _0, - #[doc = "Round-robin operation is enabled."] - _1, + #[doc = "Round-robin operation is disabled."] _0, + #[doc = "Round-robin operation is enabled."] _1, } impl RRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -557,8 +544,7 @@ impl<'a> _ACONW<'a> { } #[doc = "Values that can be written to the field `INITMOD`"] pub enum INITMODW { - #[doc = "The modulus is set to 64(same with 111111)."] - _000000, + #[doc = "The modulus is set to 64(same with 111111)."] _000000, } impl INITMODW { #[allow(missing_docs)] @@ -847,22 +833,14 @@ impl<'a> _CH7FW<'a> { } #[doc = "Values that can be written to the field `FXMXCH`"] pub enum FXMXCHW { - #[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] - _000, - #[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] - _001, - #[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] - _010, - #[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] - _011, - #[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] - _100, - #[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] - _101, - #[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] - _110, - #[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] - _111, + #[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] _000, + #[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] _001, + #[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] _010, + #[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] _011, + #[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] _100, + #[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] _101, + #[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] _110, + #[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] _111, } impl FXMXCHW { #[allow(missing_docs)] @@ -945,10 +923,8 @@ impl<'a> _FXMXCHW<'a> { } #[doc = "Values that can be written to the field `FXMP`"] pub enum FXMPW { - #[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] - _0, - #[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] - _1, + #[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] _0, + #[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] _1, } impl FXMPW { #[allow(missing_docs)] @@ -1003,8 +979,7 @@ impl<'a> _FXMPW<'a> { } #[doc = "Values that can be written to the field `RRIE`"] pub enum RRIEW { - #[doc = "The round-robin interrupt is disabled."] - _0, + #[doc = "The round-robin interrupt is disabled."] _0, #[doc = "The round-robin interrupt is enabled when a comparison result changes from the last sample."] _1, } @@ -1061,10 +1036,8 @@ impl<'a> _RRIEW<'a> { } #[doc = "Values that can be written to the field `RRE`"] pub enum RREW { - #[doc = "Round-robin operation is disabled."] - _0, - #[doc = "Round-robin operation is enabled."] - _1, + #[doc = "Round-robin operation is disabled."] _0, + #[doc = "Round-robin operation is enabled."] _1, } impl RREW { #[allow(missing_docs)] diff --git a/src/cmp0/mod.rs b/src/cmp0/mod.rs index a3f50e2..82938d2 100644 --- a/src/cmp0/mod.rs +++ b/src/cmp0/mod.rs @@ -2,12 +2,9 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - CMP Control Register 0"] - pub c0: C0, - #[doc = "0x04 - CMP Control Register 1"] - pub c1: C1, - #[doc = "0x08 - CMP Control Register 2"] - pub c2: C2, + #[doc = "0x00 - CMP Control Register 0"] pub c0: C0, + #[doc = "0x04 - CMP Control Register 1"] pub c1: C1, + #[doc = "0x08 - CMP Control Register 2"] pub c2: C2, } #[doc = "CMP Control Register 0"] pub struct C0 { diff --git a/src/crc/ctrl/mod.rs b/src/crc/ctrl/mod.rs index 70feb16..1102e8a 100644 --- a/src/crc/ctrl/mod.rs +++ b/src/crc/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL { #[doc = "Possible values of the field `TCRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCRCR { - #[doc = "16-bit CRC protocol."] - _0, - #[doc = "32-bit CRC protocol."] - _1, + #[doc = "16-bit CRC protocol."] _0, + #[doc = "32-bit CRC protocol."] _1, } impl TCRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TCRCR { #[doc = "Possible values of the field `WAS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WASR { - #[doc = "Writes to the CRC data register are data values."] - _0, - #[doc = "Writes to the CRC data register are seed values."] - _1, + #[doc = "Writes to the CRC data register are data values."] _0, + #[doc = "Writes to the CRC data register are seed values."] _1, } impl WASR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WASR { #[doc = "Possible values of the field `FXOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FXORR { - #[doc = "No XOR on reading."] - _0, - #[doc = "Invert or complement the read value of the CRC Data register."] - _1, + #[doc = "No XOR on reading."] _0, + #[doc = "Invert or complement the read value of the CRC Data register."] _1, } impl FXORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,14 +180,10 @@ impl FXORR { #[doc = "Possible values of the field `TOTR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOTRR { - #[doc = "No transposition."] - _00, - #[doc = "Bits in bytes are transposed; bytes are not transposed."] - _01, - #[doc = "Both bits in bytes and bytes are transposed."] - _10, - #[doc = "Only bytes are transposed; no bits in a byte are transposed."] - _11, + #[doc = "No transposition."] _00, + #[doc = "Bits in bytes are transposed; bytes are not transposed."] _01, + #[doc = "Both bits in bytes and bytes are transposed."] _10, + #[doc = "Only bytes are transposed; no bits in a byte are transposed."] _11, } impl TOTRR { #[doc = r" Value of the field as raw bits"] @@ -240,14 +232,10 @@ impl TOTRR { #[doc = "Possible values of the field `TOT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOTR { - #[doc = "No transposition."] - _00, - #[doc = "Bits in bytes are transposed; bytes are not transposed."] - _01, - #[doc = "Both bits in bytes and bytes are transposed."] - _10, - #[doc = "Only bytes are transposed; no bits in a byte are transposed."] - _11, + #[doc = "No transposition."] _00, + #[doc = "Bits in bytes are transposed; bytes are not transposed."] _01, + #[doc = "Both bits in bytes and bytes are transposed."] _10, + #[doc = "Only bytes are transposed; no bits in a byte are transposed."] _11, } impl TOTR { #[doc = r" Value of the field as raw bits"] @@ -295,10 +283,8 @@ impl TOTR { } #[doc = "Values that can be written to the field `TCRC`"] pub enum TCRCW { - #[doc = "16-bit CRC protocol."] - _0, - #[doc = "32-bit CRC protocol."] - _1, + #[doc = "16-bit CRC protocol."] _0, + #[doc = "32-bit CRC protocol."] _1, } impl TCRCW { #[allow(missing_docs)] @@ -353,10 +339,8 @@ impl<'a> _TCRCW<'a> { } #[doc = "Values that can be written to the field `WAS`"] pub enum WASW { - #[doc = "Writes to the CRC data register are data values."] - _0, - #[doc = "Writes to the CRC data register are seed values."] - _1, + #[doc = "Writes to the CRC data register are data values."] _0, + #[doc = "Writes to the CRC data register are seed values."] _1, } impl WASW { #[allow(missing_docs)] @@ -411,10 +395,8 @@ impl<'a> _WASW<'a> { } #[doc = "Values that can be written to the field `FXOR`"] pub enum FXORW { - #[doc = "No XOR on reading."] - _0, - #[doc = "Invert or complement the read value of the CRC Data register."] - _1, + #[doc = "No XOR on reading."] _0, + #[doc = "Invert or complement the read value of the CRC Data register."] _1, } impl FXORW { #[allow(missing_docs)] @@ -469,14 +451,10 @@ impl<'a> _FXORW<'a> { } #[doc = "Values that can be written to the field `TOTR`"] pub enum TOTRW { - #[doc = "No transposition."] - _00, - #[doc = "Bits in bytes are transposed; bytes are not transposed."] - _01, - #[doc = "Both bits in bytes and bytes are transposed."] - _10, - #[doc = "Only bytes are transposed; no bits in a byte are transposed."] - _11, + #[doc = "No transposition."] _00, + #[doc = "Bits in bytes are transposed; bytes are not transposed."] _01, + #[doc = "Both bits in bytes and bytes are transposed."] _10, + #[doc = "Only bytes are transposed; no bits in a byte are transposed."] _11, } impl TOTRW { #[allow(missing_docs)] @@ -535,14 +513,10 @@ impl<'a> _TOTRW<'a> { } #[doc = "Values that can be written to the field `TOT`"] pub enum TOTW { - #[doc = "No transposition."] - _00, - #[doc = "Bits in bytes are transposed; bytes are not transposed."] - _01, - #[doc = "Both bits in bytes and bytes are transposed."] - _10, - #[doc = "Only bytes are transposed; no bits in a byte are transposed."] - _11, + #[doc = "No transposition."] _00, + #[doc = "Bits in bytes are transposed; bytes are not transposed."] _01, + #[doc = "Both bits in bytes and bytes are transposed."] _10, + #[doc = "Only bytes are transposed; no bits in a byte are transposed."] _11, } impl TOTW { #[allow(missing_docs)] diff --git a/src/crc/data/mod.rs b/src/crc/data/mod.rs index 3432b94..96d41c0 100644 --- a/src/crc/data/mod.rs +++ b/src/crc/data/mod.rs @@ -22,7 +22,9 @@ impl super::DATA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datah/mod.rs b/src/crc/datah/mod.rs index 573cb0e..9ef80c8 100644 --- a/src/crc/datah/mod.rs +++ b/src/crc/datah/mod.rs @@ -22,7 +22,9 @@ impl super::DATAH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datahl/mod.rs b/src/crc/datahl/mod.rs index f963127..8d307a2 100644 --- a/src/crc/datahl/mod.rs +++ b/src/crc/datahl/mod.rs @@ -22,7 +22,9 @@ impl super::DATAHL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datahu/mod.rs b/src/crc/datahu/mod.rs index 5e641f4..c45a502 100644 --- a/src/crc/datahu/mod.rs +++ b/src/crc/datahu/mod.rs @@ -22,7 +22,9 @@ impl super::DATAHU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datal/mod.rs b/src/crc/datal/mod.rs index 7d266ac..3bb61b6 100644 --- a/src/crc/datal/mod.rs +++ b/src/crc/datal/mod.rs @@ -22,7 +22,9 @@ impl super::DATAL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datall/mod.rs b/src/crc/datall/mod.rs index c8389e4..68c84e3 100644 --- a/src/crc/datall/mod.rs +++ b/src/crc/datall/mod.rs @@ -22,7 +22,9 @@ impl super::DATALL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/datalu/mod.rs b/src/crc/datalu/mod.rs index 7f637aa..cd560ec 100644 --- a/src/crc/datalu/mod.rs +++ b/src/crc/datalu/mod.rs @@ -22,7 +22,9 @@ impl super::DATALU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/gpoly/mod.rs b/src/crc/gpoly/mod.rs index 66d0724..7260c73 100644 --- a/src/crc/gpoly/mod.rs +++ b/src/crc/gpoly/mod.rs @@ -22,7 +22,9 @@ impl super::GPOLY { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/crc/mod.rs b/src/crc/mod.rs index 746c376..d7be0fb 100644 --- a/src/crc/mod.rs +++ b/src/crc/mod.rs @@ -2,12 +2,9 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - CRC Data register"] - pub data: DATA, - #[doc = "0x04 - CRC Polynomial register"] - pub gpoly: GPOLY, - #[doc = "0x08 - CRC Control register"] - pub ctrl: CTRL, + #[doc = "0x00 - CRC Data register"] pub data: DATA, + #[doc = "0x04 - CRC Polynomial register"] pub gpoly: GPOLY, + #[doc = "0x08 - CRC Control register"] pub ctrl: CTRL, } #[doc = "CRC Data register"] pub struct DATA { diff --git a/src/cse_pram/embedded_ram0/mod.rs b/src/cse_pram/embedded_ram0/mod.rs index 25a8a44..ca2ce32 100644 --- a/src/cse_pram/embedded_ram0/mod.rs +++ b/src/cse_pram/embedded_ram0/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram0hl/mod.rs b/src/cse_pram/embedded_ram0hl/mod.rs index 3513dd7..395820c 100644 --- a/src/cse_pram/embedded_ram0hl/mod.rs +++ b/src/cse_pram/embedded_ram0hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM0HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram0hu/mod.rs b/src/cse_pram/embedded_ram0hu/mod.rs index ca3ee0f..f0841b0 100644 --- a/src/cse_pram/embedded_ram0hu/mod.rs +++ b/src/cse_pram/embedded_ram0hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM0HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram0ll/mod.rs b/src/cse_pram/embedded_ram0ll/mod.rs index 86ad6ae..de8e7b2 100644 --- a/src/cse_pram/embedded_ram0ll/mod.rs +++ b/src/cse_pram/embedded_ram0ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM0LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram0lu/mod.rs b/src/cse_pram/embedded_ram0lu/mod.rs index a55d412..563ac07 100644 --- a/src/cse_pram/embedded_ram0lu/mod.rs +++ b/src/cse_pram/embedded_ram0lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM0LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram1/mod.rs b/src/cse_pram/embedded_ram1/mod.rs index 4ae8406..ca403ca 100644 --- a/src/cse_pram/embedded_ram1/mod.rs +++ b/src/cse_pram/embedded_ram1/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram10/mod.rs b/src/cse_pram/embedded_ram10/mod.rs index 90787ab..fdaea4f 100644 --- a/src/cse_pram/embedded_ram10/mod.rs +++ b/src/cse_pram/embedded_ram10/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram10hl/mod.rs b/src/cse_pram/embedded_ram10hl/mod.rs index 56aa0d0..ff13238 100644 --- a/src/cse_pram/embedded_ram10hl/mod.rs +++ b/src/cse_pram/embedded_ram10hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM10HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram10hu/mod.rs b/src/cse_pram/embedded_ram10hu/mod.rs index 968116f..11f6b86 100644 --- a/src/cse_pram/embedded_ram10hu/mod.rs +++ b/src/cse_pram/embedded_ram10hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM10HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram10ll/mod.rs b/src/cse_pram/embedded_ram10ll/mod.rs index 6ef8092..194a371 100644 --- a/src/cse_pram/embedded_ram10ll/mod.rs +++ b/src/cse_pram/embedded_ram10ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM10LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram10lu/mod.rs b/src/cse_pram/embedded_ram10lu/mod.rs index f25bda4..7674263 100644 --- a/src/cse_pram/embedded_ram10lu/mod.rs +++ b/src/cse_pram/embedded_ram10lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM10LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram11/mod.rs b/src/cse_pram/embedded_ram11/mod.rs index b500ffc..c5bc10b 100644 --- a/src/cse_pram/embedded_ram11/mod.rs +++ b/src/cse_pram/embedded_ram11/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram11hl/mod.rs b/src/cse_pram/embedded_ram11hl/mod.rs index b562c66..c073af4 100644 --- a/src/cse_pram/embedded_ram11hl/mod.rs +++ b/src/cse_pram/embedded_ram11hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM11HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram11hu/mod.rs b/src/cse_pram/embedded_ram11hu/mod.rs index 20edc8d..f093edc 100644 --- a/src/cse_pram/embedded_ram11hu/mod.rs +++ b/src/cse_pram/embedded_ram11hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM11HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram11ll/mod.rs b/src/cse_pram/embedded_ram11ll/mod.rs index beda45a..e1a40fe 100644 --- a/src/cse_pram/embedded_ram11ll/mod.rs +++ b/src/cse_pram/embedded_ram11ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM11LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram11lu/mod.rs b/src/cse_pram/embedded_ram11lu/mod.rs index b0bdbc9..2d0539f 100644 --- a/src/cse_pram/embedded_ram11lu/mod.rs +++ b/src/cse_pram/embedded_ram11lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM11LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram12/mod.rs b/src/cse_pram/embedded_ram12/mod.rs index 66ec08c..6aed891 100644 --- a/src/cse_pram/embedded_ram12/mod.rs +++ b/src/cse_pram/embedded_ram12/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram12hl/mod.rs b/src/cse_pram/embedded_ram12hl/mod.rs index e214913..0e7d289 100644 --- a/src/cse_pram/embedded_ram12hl/mod.rs +++ b/src/cse_pram/embedded_ram12hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM12HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram12hu/mod.rs b/src/cse_pram/embedded_ram12hu/mod.rs index 2bef523..d1c94e2 100644 --- a/src/cse_pram/embedded_ram12hu/mod.rs +++ b/src/cse_pram/embedded_ram12hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM12HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram12ll/mod.rs b/src/cse_pram/embedded_ram12ll/mod.rs index 38deb3f..09e2741 100644 --- a/src/cse_pram/embedded_ram12ll/mod.rs +++ b/src/cse_pram/embedded_ram12ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM12LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram12lu/mod.rs b/src/cse_pram/embedded_ram12lu/mod.rs index 203968d..8528a81 100644 --- a/src/cse_pram/embedded_ram12lu/mod.rs +++ b/src/cse_pram/embedded_ram12lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM12LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram13/mod.rs b/src/cse_pram/embedded_ram13/mod.rs index 070d94d..1e040bb 100644 --- a/src/cse_pram/embedded_ram13/mod.rs +++ b/src/cse_pram/embedded_ram13/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram13hl/mod.rs b/src/cse_pram/embedded_ram13hl/mod.rs index 2798370..59a66d6 100644 --- a/src/cse_pram/embedded_ram13hl/mod.rs +++ b/src/cse_pram/embedded_ram13hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM13HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram13hu/mod.rs b/src/cse_pram/embedded_ram13hu/mod.rs index c9de7d7..5d39958 100644 --- a/src/cse_pram/embedded_ram13hu/mod.rs +++ b/src/cse_pram/embedded_ram13hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM13HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram13ll/mod.rs b/src/cse_pram/embedded_ram13ll/mod.rs index 577b12a..af01e41 100644 --- a/src/cse_pram/embedded_ram13ll/mod.rs +++ b/src/cse_pram/embedded_ram13ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM13LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram13lu/mod.rs b/src/cse_pram/embedded_ram13lu/mod.rs index fde825c..dd8f0f6 100644 --- a/src/cse_pram/embedded_ram13lu/mod.rs +++ b/src/cse_pram/embedded_ram13lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM13LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram14/mod.rs b/src/cse_pram/embedded_ram14/mod.rs index d699b12..a654031 100644 --- a/src/cse_pram/embedded_ram14/mod.rs +++ b/src/cse_pram/embedded_ram14/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram14hl/mod.rs b/src/cse_pram/embedded_ram14hl/mod.rs index bcfdb2b..f01c90f 100644 --- a/src/cse_pram/embedded_ram14hl/mod.rs +++ b/src/cse_pram/embedded_ram14hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM14HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram14hu/mod.rs b/src/cse_pram/embedded_ram14hu/mod.rs index ae9ca40..8cfd90d 100644 --- a/src/cse_pram/embedded_ram14hu/mod.rs +++ b/src/cse_pram/embedded_ram14hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM14HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram14ll/mod.rs b/src/cse_pram/embedded_ram14ll/mod.rs index e145622..6a0e0ad 100644 --- a/src/cse_pram/embedded_ram14ll/mod.rs +++ b/src/cse_pram/embedded_ram14ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM14LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram14lu/mod.rs b/src/cse_pram/embedded_ram14lu/mod.rs index d68ecbd..97bfbf5 100644 --- a/src/cse_pram/embedded_ram14lu/mod.rs +++ b/src/cse_pram/embedded_ram14lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM14LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram15/mod.rs b/src/cse_pram/embedded_ram15/mod.rs index 2abd779..112a088 100644 --- a/src/cse_pram/embedded_ram15/mod.rs +++ b/src/cse_pram/embedded_ram15/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram15hl/mod.rs b/src/cse_pram/embedded_ram15hl/mod.rs index 658bf89..655eee5 100644 --- a/src/cse_pram/embedded_ram15hl/mod.rs +++ b/src/cse_pram/embedded_ram15hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM15HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram15hu/mod.rs b/src/cse_pram/embedded_ram15hu/mod.rs index b3ab366..ad5d314 100644 --- a/src/cse_pram/embedded_ram15hu/mod.rs +++ b/src/cse_pram/embedded_ram15hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM15HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram15ll/mod.rs b/src/cse_pram/embedded_ram15ll/mod.rs index 224e056..033928c 100644 --- a/src/cse_pram/embedded_ram15ll/mod.rs +++ b/src/cse_pram/embedded_ram15ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM15LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram15lu/mod.rs b/src/cse_pram/embedded_ram15lu/mod.rs index 23ac151..e1854b2 100644 --- a/src/cse_pram/embedded_ram15lu/mod.rs +++ b/src/cse_pram/embedded_ram15lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM15LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram16/mod.rs b/src/cse_pram/embedded_ram16/mod.rs index d7f9c1d..88a7816 100644 --- a/src/cse_pram/embedded_ram16/mod.rs +++ b/src/cse_pram/embedded_ram16/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram16hl/mod.rs b/src/cse_pram/embedded_ram16hl/mod.rs index 57fa89d..c83dc11 100644 --- a/src/cse_pram/embedded_ram16hl/mod.rs +++ b/src/cse_pram/embedded_ram16hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM16HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram16hu/mod.rs b/src/cse_pram/embedded_ram16hu/mod.rs index 9f226ba..4df93e9 100644 --- a/src/cse_pram/embedded_ram16hu/mod.rs +++ b/src/cse_pram/embedded_ram16hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM16HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram16ll/mod.rs b/src/cse_pram/embedded_ram16ll/mod.rs index 01151a7..295d6ef 100644 --- a/src/cse_pram/embedded_ram16ll/mod.rs +++ b/src/cse_pram/embedded_ram16ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM16LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram16lu/mod.rs b/src/cse_pram/embedded_ram16lu/mod.rs index daffadf..fe0283a 100644 --- a/src/cse_pram/embedded_ram16lu/mod.rs +++ b/src/cse_pram/embedded_ram16lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM16LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram17/mod.rs b/src/cse_pram/embedded_ram17/mod.rs index bc5ce5e..36613de 100644 --- a/src/cse_pram/embedded_ram17/mod.rs +++ b/src/cse_pram/embedded_ram17/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram17hl/mod.rs b/src/cse_pram/embedded_ram17hl/mod.rs index 5c61294..6681efc 100644 --- a/src/cse_pram/embedded_ram17hl/mod.rs +++ b/src/cse_pram/embedded_ram17hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM17HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram17hu/mod.rs b/src/cse_pram/embedded_ram17hu/mod.rs index 9793b06..ace3e09 100644 --- a/src/cse_pram/embedded_ram17hu/mod.rs +++ b/src/cse_pram/embedded_ram17hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM17HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram17ll/mod.rs b/src/cse_pram/embedded_ram17ll/mod.rs index 1e6cdde..8819cb8 100644 --- a/src/cse_pram/embedded_ram17ll/mod.rs +++ b/src/cse_pram/embedded_ram17ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM17LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram17lu/mod.rs b/src/cse_pram/embedded_ram17lu/mod.rs index 3370785..063ca54 100644 --- a/src/cse_pram/embedded_ram17lu/mod.rs +++ b/src/cse_pram/embedded_ram17lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM17LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram18/mod.rs b/src/cse_pram/embedded_ram18/mod.rs index e462d53..7dc8d23 100644 --- a/src/cse_pram/embedded_ram18/mod.rs +++ b/src/cse_pram/embedded_ram18/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram18hl/mod.rs b/src/cse_pram/embedded_ram18hl/mod.rs index 1c63018..a9e3952 100644 --- a/src/cse_pram/embedded_ram18hl/mod.rs +++ b/src/cse_pram/embedded_ram18hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM18HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram18hu/mod.rs b/src/cse_pram/embedded_ram18hu/mod.rs index 0a91d72..a50e909 100644 --- a/src/cse_pram/embedded_ram18hu/mod.rs +++ b/src/cse_pram/embedded_ram18hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM18HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram18ll/mod.rs b/src/cse_pram/embedded_ram18ll/mod.rs index e5edbac..e624c62 100644 --- a/src/cse_pram/embedded_ram18ll/mod.rs +++ b/src/cse_pram/embedded_ram18ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM18LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram18lu/mod.rs b/src/cse_pram/embedded_ram18lu/mod.rs index 7365f81..ac79d7e 100644 --- a/src/cse_pram/embedded_ram18lu/mod.rs +++ b/src/cse_pram/embedded_ram18lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM18LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram19/mod.rs b/src/cse_pram/embedded_ram19/mod.rs index 1aea636..3df2331 100644 --- a/src/cse_pram/embedded_ram19/mod.rs +++ b/src/cse_pram/embedded_ram19/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram19hl/mod.rs b/src/cse_pram/embedded_ram19hl/mod.rs index 84b3089..a81806e 100644 --- a/src/cse_pram/embedded_ram19hl/mod.rs +++ b/src/cse_pram/embedded_ram19hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM19HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram19hu/mod.rs b/src/cse_pram/embedded_ram19hu/mod.rs index ddb5fe5..30a48c0 100644 --- a/src/cse_pram/embedded_ram19hu/mod.rs +++ b/src/cse_pram/embedded_ram19hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM19HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram19ll/mod.rs b/src/cse_pram/embedded_ram19ll/mod.rs index 1e18709..28ae264 100644 --- a/src/cse_pram/embedded_ram19ll/mod.rs +++ b/src/cse_pram/embedded_ram19ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM19LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram19lu/mod.rs b/src/cse_pram/embedded_ram19lu/mod.rs index 39c8eb5..bda0257 100644 --- a/src/cse_pram/embedded_ram19lu/mod.rs +++ b/src/cse_pram/embedded_ram19lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM19LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram1hl/mod.rs b/src/cse_pram/embedded_ram1hl/mod.rs index 899a3ca..1ac5244 100644 --- a/src/cse_pram/embedded_ram1hl/mod.rs +++ b/src/cse_pram/embedded_ram1hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM1HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram1hu/mod.rs b/src/cse_pram/embedded_ram1hu/mod.rs index ad52210..8c34a78 100644 --- a/src/cse_pram/embedded_ram1hu/mod.rs +++ b/src/cse_pram/embedded_ram1hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM1HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram1ll/mod.rs b/src/cse_pram/embedded_ram1ll/mod.rs index 88f3034..ca427b9 100644 --- a/src/cse_pram/embedded_ram1ll/mod.rs +++ b/src/cse_pram/embedded_ram1ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM1LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram1lu/mod.rs b/src/cse_pram/embedded_ram1lu/mod.rs index 1f83c2f..173edab 100644 --- a/src/cse_pram/embedded_ram1lu/mod.rs +++ b/src/cse_pram/embedded_ram1lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM1LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram2/mod.rs b/src/cse_pram/embedded_ram2/mod.rs index d46b896..05c0c4a 100644 --- a/src/cse_pram/embedded_ram2/mod.rs +++ b/src/cse_pram/embedded_ram2/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram20/mod.rs b/src/cse_pram/embedded_ram20/mod.rs index 6cfa901..88d83c7 100644 --- a/src/cse_pram/embedded_ram20/mod.rs +++ b/src/cse_pram/embedded_ram20/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram20hl/mod.rs b/src/cse_pram/embedded_ram20hl/mod.rs index c6f2aa3..b9bc014 100644 --- a/src/cse_pram/embedded_ram20hl/mod.rs +++ b/src/cse_pram/embedded_ram20hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM20HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram20hu/mod.rs b/src/cse_pram/embedded_ram20hu/mod.rs index f68414b..5f901a2 100644 --- a/src/cse_pram/embedded_ram20hu/mod.rs +++ b/src/cse_pram/embedded_ram20hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM20HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram20ll/mod.rs b/src/cse_pram/embedded_ram20ll/mod.rs index 854f0c3..5b46cf7 100644 --- a/src/cse_pram/embedded_ram20ll/mod.rs +++ b/src/cse_pram/embedded_ram20ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM20LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram20lu/mod.rs b/src/cse_pram/embedded_ram20lu/mod.rs index 27dc7a8..ef0cef1 100644 --- a/src/cse_pram/embedded_ram20lu/mod.rs +++ b/src/cse_pram/embedded_ram20lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM20LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram21/mod.rs b/src/cse_pram/embedded_ram21/mod.rs index 893512a..5b7c7bb 100644 --- a/src/cse_pram/embedded_ram21/mod.rs +++ b/src/cse_pram/embedded_ram21/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram21hl/mod.rs b/src/cse_pram/embedded_ram21hl/mod.rs index 1297a56..c87d777 100644 --- a/src/cse_pram/embedded_ram21hl/mod.rs +++ b/src/cse_pram/embedded_ram21hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM21HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram21hu/mod.rs b/src/cse_pram/embedded_ram21hu/mod.rs index 442a4a3..414139f 100644 --- a/src/cse_pram/embedded_ram21hu/mod.rs +++ b/src/cse_pram/embedded_ram21hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM21HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram21ll/mod.rs b/src/cse_pram/embedded_ram21ll/mod.rs index c31dd05..0230730 100644 --- a/src/cse_pram/embedded_ram21ll/mod.rs +++ b/src/cse_pram/embedded_ram21ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM21LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram21lu/mod.rs b/src/cse_pram/embedded_ram21lu/mod.rs index 4110b35..efa87b8 100644 --- a/src/cse_pram/embedded_ram21lu/mod.rs +++ b/src/cse_pram/embedded_ram21lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM21LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram22/mod.rs b/src/cse_pram/embedded_ram22/mod.rs index fecc08f..75ba88a 100644 --- a/src/cse_pram/embedded_ram22/mod.rs +++ b/src/cse_pram/embedded_ram22/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram22hl/mod.rs b/src/cse_pram/embedded_ram22hl/mod.rs index dbfd9de..679da49 100644 --- a/src/cse_pram/embedded_ram22hl/mod.rs +++ b/src/cse_pram/embedded_ram22hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM22HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram22hu/mod.rs b/src/cse_pram/embedded_ram22hu/mod.rs index 3b24259..d1bed22 100644 --- a/src/cse_pram/embedded_ram22hu/mod.rs +++ b/src/cse_pram/embedded_ram22hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM22HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram22ll/mod.rs b/src/cse_pram/embedded_ram22ll/mod.rs index 12c5b4f..a48f0b9 100644 --- a/src/cse_pram/embedded_ram22ll/mod.rs +++ b/src/cse_pram/embedded_ram22ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM22LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram22lu/mod.rs b/src/cse_pram/embedded_ram22lu/mod.rs index 23781bc..8ea2d86 100644 --- a/src/cse_pram/embedded_ram22lu/mod.rs +++ b/src/cse_pram/embedded_ram22lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM22LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram23/mod.rs b/src/cse_pram/embedded_ram23/mod.rs index 18c8d83..c2e7c6e 100644 --- a/src/cse_pram/embedded_ram23/mod.rs +++ b/src/cse_pram/embedded_ram23/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram23hl/mod.rs b/src/cse_pram/embedded_ram23hl/mod.rs index 1ec51f0..fc412ee 100644 --- a/src/cse_pram/embedded_ram23hl/mod.rs +++ b/src/cse_pram/embedded_ram23hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM23HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram23hu/mod.rs b/src/cse_pram/embedded_ram23hu/mod.rs index 1423916..ff2f9a3 100644 --- a/src/cse_pram/embedded_ram23hu/mod.rs +++ b/src/cse_pram/embedded_ram23hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM23HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram23ll/mod.rs b/src/cse_pram/embedded_ram23ll/mod.rs index 3b3dad6..b5c45f6 100644 --- a/src/cse_pram/embedded_ram23ll/mod.rs +++ b/src/cse_pram/embedded_ram23ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM23LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram23lu/mod.rs b/src/cse_pram/embedded_ram23lu/mod.rs index 112270b..3bac0fc 100644 --- a/src/cse_pram/embedded_ram23lu/mod.rs +++ b/src/cse_pram/embedded_ram23lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM23LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram24/mod.rs b/src/cse_pram/embedded_ram24/mod.rs index b1143e7..ffcc81e 100644 --- a/src/cse_pram/embedded_ram24/mod.rs +++ b/src/cse_pram/embedded_ram24/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram24hl/mod.rs b/src/cse_pram/embedded_ram24hl/mod.rs index 5d28818..f00c4e1 100644 --- a/src/cse_pram/embedded_ram24hl/mod.rs +++ b/src/cse_pram/embedded_ram24hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM24HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram24hu/mod.rs b/src/cse_pram/embedded_ram24hu/mod.rs index 52cf174..ebc109d 100644 --- a/src/cse_pram/embedded_ram24hu/mod.rs +++ b/src/cse_pram/embedded_ram24hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM24HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram24ll/mod.rs b/src/cse_pram/embedded_ram24ll/mod.rs index 9e4054a..aeffac4 100644 --- a/src/cse_pram/embedded_ram24ll/mod.rs +++ b/src/cse_pram/embedded_ram24ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM24LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram24lu/mod.rs b/src/cse_pram/embedded_ram24lu/mod.rs index 584dabd..31ea011 100644 --- a/src/cse_pram/embedded_ram24lu/mod.rs +++ b/src/cse_pram/embedded_ram24lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM24LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram25/mod.rs b/src/cse_pram/embedded_ram25/mod.rs index 2d83e19..d98c45c 100644 --- a/src/cse_pram/embedded_ram25/mod.rs +++ b/src/cse_pram/embedded_ram25/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram25hl/mod.rs b/src/cse_pram/embedded_ram25hl/mod.rs index 7abcdc4..718cc1f 100644 --- a/src/cse_pram/embedded_ram25hl/mod.rs +++ b/src/cse_pram/embedded_ram25hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM25HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram25hu/mod.rs b/src/cse_pram/embedded_ram25hu/mod.rs index 7c7101b..f01b992 100644 --- a/src/cse_pram/embedded_ram25hu/mod.rs +++ b/src/cse_pram/embedded_ram25hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM25HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram25ll/mod.rs b/src/cse_pram/embedded_ram25ll/mod.rs index f07a994..6233c95 100644 --- a/src/cse_pram/embedded_ram25ll/mod.rs +++ b/src/cse_pram/embedded_ram25ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM25LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram25lu/mod.rs b/src/cse_pram/embedded_ram25lu/mod.rs index 3c21090..0337f96 100644 --- a/src/cse_pram/embedded_ram25lu/mod.rs +++ b/src/cse_pram/embedded_ram25lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM25LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram26/mod.rs b/src/cse_pram/embedded_ram26/mod.rs index 06b3825..c81777d 100644 --- a/src/cse_pram/embedded_ram26/mod.rs +++ b/src/cse_pram/embedded_ram26/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram26hl/mod.rs b/src/cse_pram/embedded_ram26hl/mod.rs index c0d0a95..1f9d77e 100644 --- a/src/cse_pram/embedded_ram26hl/mod.rs +++ b/src/cse_pram/embedded_ram26hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM26HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram26hu/mod.rs b/src/cse_pram/embedded_ram26hu/mod.rs index e13b987..3d00c54 100644 --- a/src/cse_pram/embedded_ram26hu/mod.rs +++ b/src/cse_pram/embedded_ram26hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM26HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram26ll/mod.rs b/src/cse_pram/embedded_ram26ll/mod.rs index c3c6c81..d28d498 100644 --- a/src/cse_pram/embedded_ram26ll/mod.rs +++ b/src/cse_pram/embedded_ram26ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM26LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram26lu/mod.rs b/src/cse_pram/embedded_ram26lu/mod.rs index 2360945..e27ddbe 100644 --- a/src/cse_pram/embedded_ram26lu/mod.rs +++ b/src/cse_pram/embedded_ram26lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM26LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram27/mod.rs b/src/cse_pram/embedded_ram27/mod.rs index b55091b..c3c7e65 100644 --- a/src/cse_pram/embedded_ram27/mod.rs +++ b/src/cse_pram/embedded_ram27/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram27hl/mod.rs b/src/cse_pram/embedded_ram27hl/mod.rs index e888cd3..3541de1 100644 --- a/src/cse_pram/embedded_ram27hl/mod.rs +++ b/src/cse_pram/embedded_ram27hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM27HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram27hu/mod.rs b/src/cse_pram/embedded_ram27hu/mod.rs index 01b70d5..5cb8706 100644 --- a/src/cse_pram/embedded_ram27hu/mod.rs +++ b/src/cse_pram/embedded_ram27hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM27HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram27ll/mod.rs b/src/cse_pram/embedded_ram27ll/mod.rs index 776f24c..485cdfa 100644 --- a/src/cse_pram/embedded_ram27ll/mod.rs +++ b/src/cse_pram/embedded_ram27ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM27LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram27lu/mod.rs b/src/cse_pram/embedded_ram27lu/mod.rs index a7cd338..0c244db 100644 --- a/src/cse_pram/embedded_ram27lu/mod.rs +++ b/src/cse_pram/embedded_ram27lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM27LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram28/mod.rs b/src/cse_pram/embedded_ram28/mod.rs index ea874bc..3b2bf5b 100644 --- a/src/cse_pram/embedded_ram28/mod.rs +++ b/src/cse_pram/embedded_ram28/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram28hl/mod.rs b/src/cse_pram/embedded_ram28hl/mod.rs index c08f769..ee8db78 100644 --- a/src/cse_pram/embedded_ram28hl/mod.rs +++ b/src/cse_pram/embedded_ram28hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM28HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram28hu/mod.rs b/src/cse_pram/embedded_ram28hu/mod.rs index bda3469..d1f04fc 100644 --- a/src/cse_pram/embedded_ram28hu/mod.rs +++ b/src/cse_pram/embedded_ram28hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM28HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram28ll/mod.rs b/src/cse_pram/embedded_ram28ll/mod.rs index 5fac9df..ed5a411 100644 --- a/src/cse_pram/embedded_ram28ll/mod.rs +++ b/src/cse_pram/embedded_ram28ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM28LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram28lu/mod.rs b/src/cse_pram/embedded_ram28lu/mod.rs index 580297a..749ade7 100644 --- a/src/cse_pram/embedded_ram28lu/mod.rs +++ b/src/cse_pram/embedded_ram28lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM28LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram29/mod.rs b/src/cse_pram/embedded_ram29/mod.rs index e0a7956..217abf5 100644 --- a/src/cse_pram/embedded_ram29/mod.rs +++ b/src/cse_pram/embedded_ram29/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram29hl/mod.rs b/src/cse_pram/embedded_ram29hl/mod.rs index b3a9dad..cd2af71 100644 --- a/src/cse_pram/embedded_ram29hl/mod.rs +++ b/src/cse_pram/embedded_ram29hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM29HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram29hu/mod.rs b/src/cse_pram/embedded_ram29hu/mod.rs index 2221b8b..7a6f2dd 100644 --- a/src/cse_pram/embedded_ram29hu/mod.rs +++ b/src/cse_pram/embedded_ram29hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM29HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram29ll/mod.rs b/src/cse_pram/embedded_ram29ll/mod.rs index 834681b..e392c07 100644 --- a/src/cse_pram/embedded_ram29ll/mod.rs +++ b/src/cse_pram/embedded_ram29ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM29LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram29lu/mod.rs b/src/cse_pram/embedded_ram29lu/mod.rs index 3480b05..80e7632 100644 --- a/src/cse_pram/embedded_ram29lu/mod.rs +++ b/src/cse_pram/embedded_ram29lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM29LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram2hl/mod.rs b/src/cse_pram/embedded_ram2hl/mod.rs index 58bab1a..f5b5c37 100644 --- a/src/cse_pram/embedded_ram2hl/mod.rs +++ b/src/cse_pram/embedded_ram2hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM2HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram2hu/mod.rs b/src/cse_pram/embedded_ram2hu/mod.rs index f11e9f7..47d9676 100644 --- a/src/cse_pram/embedded_ram2hu/mod.rs +++ b/src/cse_pram/embedded_ram2hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM2HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram2ll/mod.rs b/src/cse_pram/embedded_ram2ll/mod.rs index 0fa746d..b61e514 100644 --- a/src/cse_pram/embedded_ram2ll/mod.rs +++ b/src/cse_pram/embedded_ram2ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM2LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram2lu/mod.rs b/src/cse_pram/embedded_ram2lu/mod.rs index 2cf37bf..2b92cc9 100644 --- a/src/cse_pram/embedded_ram2lu/mod.rs +++ b/src/cse_pram/embedded_ram2lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM2LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram3/mod.rs b/src/cse_pram/embedded_ram3/mod.rs index 8e721cf..043849f 100644 --- a/src/cse_pram/embedded_ram3/mod.rs +++ b/src/cse_pram/embedded_ram3/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram30/mod.rs b/src/cse_pram/embedded_ram30/mod.rs index ea3aa52..13baf58 100644 --- a/src/cse_pram/embedded_ram30/mod.rs +++ b/src/cse_pram/embedded_ram30/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram30hl/mod.rs b/src/cse_pram/embedded_ram30hl/mod.rs index 6d0c3e2..ab97707 100644 --- a/src/cse_pram/embedded_ram30hl/mod.rs +++ b/src/cse_pram/embedded_ram30hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM30HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram30hu/mod.rs b/src/cse_pram/embedded_ram30hu/mod.rs index ade2de9..88937d6 100644 --- a/src/cse_pram/embedded_ram30hu/mod.rs +++ b/src/cse_pram/embedded_ram30hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM30HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram30ll/mod.rs b/src/cse_pram/embedded_ram30ll/mod.rs index f6d6d1f..6bff31e 100644 --- a/src/cse_pram/embedded_ram30ll/mod.rs +++ b/src/cse_pram/embedded_ram30ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM30LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram30lu/mod.rs b/src/cse_pram/embedded_ram30lu/mod.rs index b8b4eb7..ba7c9d5 100644 --- a/src/cse_pram/embedded_ram30lu/mod.rs +++ b/src/cse_pram/embedded_ram30lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM30LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram31/mod.rs b/src/cse_pram/embedded_ram31/mod.rs index 809c836..f7f51c0 100644 --- a/src/cse_pram/embedded_ram31/mod.rs +++ b/src/cse_pram/embedded_ram31/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram31hl/mod.rs b/src/cse_pram/embedded_ram31hl/mod.rs index 45937a1..efc310a 100644 --- a/src/cse_pram/embedded_ram31hl/mod.rs +++ b/src/cse_pram/embedded_ram31hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM31HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram31hu/mod.rs b/src/cse_pram/embedded_ram31hu/mod.rs index 7155528..8a78c42 100644 --- a/src/cse_pram/embedded_ram31hu/mod.rs +++ b/src/cse_pram/embedded_ram31hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM31HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram31ll/mod.rs b/src/cse_pram/embedded_ram31ll/mod.rs index 744c7a0..c5e8501 100644 --- a/src/cse_pram/embedded_ram31ll/mod.rs +++ b/src/cse_pram/embedded_ram31ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM31LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram31lu/mod.rs b/src/cse_pram/embedded_ram31lu/mod.rs index a7fe87c..79a6383 100644 --- a/src/cse_pram/embedded_ram31lu/mod.rs +++ b/src/cse_pram/embedded_ram31lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM31LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram3hl/mod.rs b/src/cse_pram/embedded_ram3hl/mod.rs index 6251e28..e2bb4d2 100644 --- a/src/cse_pram/embedded_ram3hl/mod.rs +++ b/src/cse_pram/embedded_ram3hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM3HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram3hu/mod.rs b/src/cse_pram/embedded_ram3hu/mod.rs index 07545cf..ab019e2 100644 --- a/src/cse_pram/embedded_ram3hu/mod.rs +++ b/src/cse_pram/embedded_ram3hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM3HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram3ll/mod.rs b/src/cse_pram/embedded_ram3ll/mod.rs index ae2a23e..a0d2f9a 100644 --- a/src/cse_pram/embedded_ram3ll/mod.rs +++ b/src/cse_pram/embedded_ram3ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM3LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram3lu/mod.rs b/src/cse_pram/embedded_ram3lu/mod.rs index 9f34caa..4d81141 100644 --- a/src/cse_pram/embedded_ram3lu/mod.rs +++ b/src/cse_pram/embedded_ram3lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM3LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram4/mod.rs b/src/cse_pram/embedded_ram4/mod.rs index 07a788b..82edc95 100644 --- a/src/cse_pram/embedded_ram4/mod.rs +++ b/src/cse_pram/embedded_ram4/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram4hl/mod.rs b/src/cse_pram/embedded_ram4hl/mod.rs index 4334df1..8883ea4 100644 --- a/src/cse_pram/embedded_ram4hl/mod.rs +++ b/src/cse_pram/embedded_ram4hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM4HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram4hu/mod.rs b/src/cse_pram/embedded_ram4hu/mod.rs index 8bc4e63..aa33f6a 100644 --- a/src/cse_pram/embedded_ram4hu/mod.rs +++ b/src/cse_pram/embedded_ram4hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM4HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram4ll/mod.rs b/src/cse_pram/embedded_ram4ll/mod.rs index bb0d626..78059b9 100644 --- a/src/cse_pram/embedded_ram4ll/mod.rs +++ b/src/cse_pram/embedded_ram4ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM4LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram4lu/mod.rs b/src/cse_pram/embedded_ram4lu/mod.rs index 115d7e6..3797084 100644 --- a/src/cse_pram/embedded_ram4lu/mod.rs +++ b/src/cse_pram/embedded_ram4lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM4LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram5/mod.rs b/src/cse_pram/embedded_ram5/mod.rs index d47038c..e48542b 100644 --- a/src/cse_pram/embedded_ram5/mod.rs +++ b/src/cse_pram/embedded_ram5/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram5hl/mod.rs b/src/cse_pram/embedded_ram5hl/mod.rs index f29846e..61044b3 100644 --- a/src/cse_pram/embedded_ram5hl/mod.rs +++ b/src/cse_pram/embedded_ram5hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM5HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram5hu/mod.rs b/src/cse_pram/embedded_ram5hu/mod.rs index 737a160..5210c37 100644 --- a/src/cse_pram/embedded_ram5hu/mod.rs +++ b/src/cse_pram/embedded_ram5hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM5HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram5ll/mod.rs b/src/cse_pram/embedded_ram5ll/mod.rs index 00159eb..218f3d8 100644 --- a/src/cse_pram/embedded_ram5ll/mod.rs +++ b/src/cse_pram/embedded_ram5ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM5LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram5lu/mod.rs b/src/cse_pram/embedded_ram5lu/mod.rs index 46a98ec..18e61f2 100644 --- a/src/cse_pram/embedded_ram5lu/mod.rs +++ b/src/cse_pram/embedded_ram5lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM5LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram6/mod.rs b/src/cse_pram/embedded_ram6/mod.rs index 57964b1..fa7c44c 100644 --- a/src/cse_pram/embedded_ram6/mod.rs +++ b/src/cse_pram/embedded_ram6/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram6hl/mod.rs b/src/cse_pram/embedded_ram6hl/mod.rs index 8931791..ebdf3fa 100644 --- a/src/cse_pram/embedded_ram6hl/mod.rs +++ b/src/cse_pram/embedded_ram6hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM6HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram6hu/mod.rs b/src/cse_pram/embedded_ram6hu/mod.rs index 211afdf..a5151a8 100644 --- a/src/cse_pram/embedded_ram6hu/mod.rs +++ b/src/cse_pram/embedded_ram6hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM6HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram6ll/mod.rs b/src/cse_pram/embedded_ram6ll/mod.rs index 6695d85..c855b6f 100644 --- a/src/cse_pram/embedded_ram6ll/mod.rs +++ b/src/cse_pram/embedded_ram6ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM6LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram6lu/mod.rs b/src/cse_pram/embedded_ram6lu/mod.rs index 450e8c5..c9576c8 100644 --- a/src/cse_pram/embedded_ram6lu/mod.rs +++ b/src/cse_pram/embedded_ram6lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM6LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram7/mod.rs b/src/cse_pram/embedded_ram7/mod.rs index c6be3a4..517505d 100644 --- a/src/cse_pram/embedded_ram7/mod.rs +++ b/src/cse_pram/embedded_ram7/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram7hl/mod.rs b/src/cse_pram/embedded_ram7hl/mod.rs index e94642f..644a68f 100644 --- a/src/cse_pram/embedded_ram7hl/mod.rs +++ b/src/cse_pram/embedded_ram7hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM7HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram7hu/mod.rs b/src/cse_pram/embedded_ram7hu/mod.rs index 2c73510..d4a5471 100644 --- a/src/cse_pram/embedded_ram7hu/mod.rs +++ b/src/cse_pram/embedded_ram7hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM7HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram7ll/mod.rs b/src/cse_pram/embedded_ram7ll/mod.rs index ac59f40..5d2d955 100644 --- a/src/cse_pram/embedded_ram7ll/mod.rs +++ b/src/cse_pram/embedded_ram7ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM7LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram7lu/mod.rs b/src/cse_pram/embedded_ram7lu/mod.rs index 80311f5..dcff6cd 100644 --- a/src/cse_pram/embedded_ram7lu/mod.rs +++ b/src/cse_pram/embedded_ram7lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM7LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram8/mod.rs b/src/cse_pram/embedded_ram8/mod.rs index 37fbc47..d87f9c9 100644 --- a/src/cse_pram/embedded_ram8/mod.rs +++ b/src/cse_pram/embedded_ram8/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram8hl/mod.rs b/src/cse_pram/embedded_ram8hl/mod.rs index 89478e1..37813c6 100644 --- a/src/cse_pram/embedded_ram8hl/mod.rs +++ b/src/cse_pram/embedded_ram8hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM8HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram8hu/mod.rs b/src/cse_pram/embedded_ram8hu/mod.rs index dc389c2..cd870f2 100644 --- a/src/cse_pram/embedded_ram8hu/mod.rs +++ b/src/cse_pram/embedded_ram8hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM8HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram8ll/mod.rs b/src/cse_pram/embedded_ram8ll/mod.rs index 0af860b..8a06ce7 100644 --- a/src/cse_pram/embedded_ram8ll/mod.rs +++ b/src/cse_pram/embedded_ram8ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM8LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram8lu/mod.rs b/src/cse_pram/embedded_ram8lu/mod.rs index e86a024..4021109 100644 --- a/src/cse_pram/embedded_ram8lu/mod.rs +++ b/src/cse_pram/embedded_ram8lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM8LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram9/mod.rs b/src/cse_pram/embedded_ram9/mod.rs index 7951980..4ee4652 100644 --- a/src/cse_pram/embedded_ram9/mod.rs +++ b/src/cse_pram/embedded_ram9/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram9hl/mod.rs b/src/cse_pram/embedded_ram9hl/mod.rs index 20907dd..1ab948f 100644 --- a/src/cse_pram/embedded_ram9hl/mod.rs +++ b/src/cse_pram/embedded_ram9hl/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM9HL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram9hu/mod.rs b/src/cse_pram/embedded_ram9hu/mod.rs index 366367c..e7383a9 100644 --- a/src/cse_pram/embedded_ram9hu/mod.rs +++ b/src/cse_pram/embedded_ram9hu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM9HU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram9ll/mod.rs b/src/cse_pram/embedded_ram9ll/mod.rs index 502d140..5d43a10 100644 --- a/src/cse_pram/embedded_ram9ll/mod.rs +++ b/src/cse_pram/embedded_ram9ll/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM9LL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/embedded_ram9lu/mod.rs b/src/cse_pram/embedded_ram9lu/mod.rs index 8f120af..fbe2686 100644 --- a/src/cse_pram/embedded_ram9lu/mod.rs +++ b/src/cse_pram/embedded_ram9lu/mod.rs @@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM9LU { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/cse_pram/mod.rs b/src/cse_pram/mod.rs index be26683..7febef0 100644 --- a/src/cse_pram/mod.rs +++ b/src/cse_pram/mod.rs @@ -2,70 +2,38 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - CSE PRAM 0 Register"] - pub embedded_ram0: EMBEDDEDRAM0, - #[doc = "0x04 - CSE PRAM 1 Register"] - pub embedded_ram1: EMBEDDEDRAM1, - #[doc = "0x08 - CSE PRAM 2 Register"] - pub embedded_ram2: EMBEDDEDRAM2, - #[doc = "0x0c - CSE PRAM 3 Register"] - pub embedded_ram3: EMBEDDEDRAM3, - #[doc = "0x10 - CSE PRAM 4 Register"] - pub embedded_ram4: EMBEDDEDRAM4, - #[doc = "0x14 - CSE PRAM 5 Register"] - pub embedded_ram5: EMBEDDEDRAM5, - #[doc = "0x18 - CSE PRAM 6 Register"] - pub embedded_ram6: EMBEDDEDRAM6, - #[doc = "0x1c - CSE PRAM 7 Register"] - pub embedded_ram7: EMBEDDEDRAM7, - #[doc = "0x20 - CSE PRAM 8 Register"] - pub embedded_ram8: EMBEDDEDRAM8, - #[doc = "0x24 - CSE PRAM 9 Register"] - pub embedded_ram9: EMBEDDEDRAM9, - #[doc = "0x28 - CSE PRAM 10 Register"] - pub embedded_ram10: EMBEDDEDRAM10, - #[doc = "0x2c - CSE PRAM 11 Register"] - pub embedded_ram11: EMBEDDEDRAM11, - #[doc = "0x30 - CSE PRAM 12 Register"] - pub embedded_ram12: EMBEDDEDRAM12, - #[doc = "0x34 - CSE PRAM 13 Register"] - pub embedded_ram13: EMBEDDEDRAM13, - #[doc = "0x38 - CSE PRAM 14 Register"] - pub embedded_ram14: EMBEDDEDRAM14, - #[doc = "0x3c - CSE PRAM 15 Register"] - pub embedded_ram15: EMBEDDEDRAM15, - #[doc = "0x40 - CSE PRAM 16 Register"] - pub embedded_ram16: EMBEDDEDRAM16, - #[doc = "0x44 - CSE PRAM 17 Register"] - pub embedded_ram17: EMBEDDEDRAM17, - #[doc = "0x48 - CSE PRAM 18 Register"] - pub embedded_ram18: EMBEDDEDRAM18, - #[doc = "0x4c - CSE PRAM 19 Register"] - pub embedded_ram19: EMBEDDEDRAM19, - #[doc = "0x50 - CSE PRAM 20 Register"] - pub embedded_ram20: EMBEDDEDRAM20, - #[doc = "0x54 - CSE PRAM 21 Register"] - pub embedded_ram21: EMBEDDEDRAM21, - #[doc = "0x58 - CSE PRAM 22 Register"] - pub embedded_ram22: EMBEDDEDRAM22, - #[doc = "0x5c - CSE PRAM 23 Register"] - pub embedded_ram23: EMBEDDEDRAM23, - #[doc = "0x60 - CSE PRAM 24 Register"] - pub embedded_ram24: EMBEDDEDRAM24, - #[doc = "0x64 - CSE PRAM 25 Register"] - pub embedded_ram25: EMBEDDEDRAM25, - #[doc = "0x68 - CSE PRAM 26 Register"] - pub embedded_ram26: EMBEDDEDRAM26, - #[doc = "0x6c - CSE PRAM 27 Register"] - pub embedded_ram27: EMBEDDEDRAM27, - #[doc = "0x70 - CSE PRAM 28 Register"] - pub embedded_ram28: EMBEDDEDRAM28, - #[doc = "0x74 - CSE PRAM 29 Register"] - pub embedded_ram29: EMBEDDEDRAM29, - #[doc = "0x78 - CSE PRAM 30 Register"] - pub embedded_ram30: EMBEDDEDRAM30, - #[doc = "0x7c - CSE PRAM 31 Register"] - pub embedded_ram31: EMBEDDEDRAM31, + #[doc = "0x00 - CSE PRAM 0 Register"] pub embedded_ram0: EMBEDDEDRAM0, + #[doc = "0x04 - CSE PRAM 1 Register"] pub embedded_ram1: EMBEDDEDRAM1, + #[doc = "0x08 - CSE PRAM 2 Register"] pub embedded_ram2: EMBEDDEDRAM2, + #[doc = "0x0c - CSE PRAM 3 Register"] pub embedded_ram3: EMBEDDEDRAM3, + #[doc = "0x10 - CSE PRAM 4 Register"] pub embedded_ram4: EMBEDDEDRAM4, + #[doc = "0x14 - CSE PRAM 5 Register"] pub embedded_ram5: EMBEDDEDRAM5, + #[doc = "0x18 - CSE PRAM 6 Register"] pub embedded_ram6: EMBEDDEDRAM6, + #[doc = "0x1c - CSE PRAM 7 Register"] pub embedded_ram7: EMBEDDEDRAM7, + #[doc = "0x20 - CSE PRAM 8 Register"] pub embedded_ram8: EMBEDDEDRAM8, + #[doc = "0x24 - CSE PRAM 9 Register"] pub embedded_ram9: EMBEDDEDRAM9, + #[doc = "0x28 - CSE PRAM 10 Register"] pub embedded_ram10: EMBEDDEDRAM10, + #[doc = "0x2c - CSE PRAM 11 Register"] pub embedded_ram11: EMBEDDEDRAM11, + #[doc = "0x30 - CSE PRAM 12 Register"] pub embedded_ram12: EMBEDDEDRAM12, + #[doc = "0x34 - CSE PRAM 13 Register"] pub embedded_ram13: EMBEDDEDRAM13, + #[doc = "0x38 - CSE PRAM 14 Register"] pub embedded_ram14: EMBEDDEDRAM14, + #[doc = "0x3c - CSE PRAM 15 Register"] pub embedded_ram15: EMBEDDEDRAM15, + #[doc = "0x40 - CSE PRAM 16 Register"] pub embedded_ram16: EMBEDDEDRAM16, + #[doc = "0x44 - CSE PRAM 17 Register"] pub embedded_ram17: EMBEDDEDRAM17, + #[doc = "0x48 - CSE PRAM 18 Register"] pub embedded_ram18: EMBEDDEDRAM18, + #[doc = "0x4c - CSE PRAM 19 Register"] pub embedded_ram19: EMBEDDEDRAM19, + #[doc = "0x50 - CSE PRAM 20 Register"] pub embedded_ram20: EMBEDDEDRAM20, + #[doc = "0x54 - CSE PRAM 21 Register"] pub embedded_ram21: EMBEDDEDRAM21, + #[doc = "0x58 - CSE PRAM 22 Register"] pub embedded_ram22: EMBEDDEDRAM22, + #[doc = "0x5c - CSE PRAM 23 Register"] pub embedded_ram23: EMBEDDEDRAM23, + #[doc = "0x60 - CSE PRAM 24 Register"] pub embedded_ram24: EMBEDDEDRAM24, + #[doc = "0x64 - CSE PRAM 25 Register"] pub embedded_ram25: EMBEDDEDRAM25, + #[doc = "0x68 - CSE PRAM 26 Register"] pub embedded_ram26: EMBEDDEDRAM26, + #[doc = "0x6c - CSE PRAM 27 Register"] pub embedded_ram27: EMBEDDEDRAM27, + #[doc = "0x70 - CSE PRAM 28 Register"] pub embedded_ram28: EMBEDDEDRAM28, + #[doc = "0x74 - CSE PRAM 29 Register"] pub embedded_ram29: EMBEDDEDRAM29, + #[doc = "0x78 - CSE PRAM 30 Register"] pub embedded_ram30: EMBEDDEDRAM30, + #[doc = "0x7c - CSE PRAM 31 Register"] pub embedded_ram31: EMBEDDEDRAM31, } #[doc = "CSE PRAM 0 Register"] pub struct EMBEDDEDRAM0 { diff --git a/src/dma/cdne/mod.rs b/src/dma/cdne/mod.rs index 2b40b33..1f51480 100644 --- a/src/dma/cdne/mod.rs +++ b/src/dma/cdne/mod.rs @@ -31,10 +31,8 @@ impl<'a> _CDNEW<'a> { } #[doc = "Values that can be written to the field `CADN`"] pub enum CADNW { - #[doc = "Clears only the TCDn_CSR[DONE] bit specified in the CDNE field"] - _0, - #[doc = "Clears all bits in TCDn_CSR[DONE]"] - _1, + #[doc = "Clears only the TCDn_CSR[DONE] bit specified in the CDNE field"] _0, + #[doc = "Clears all bits in TCDn_CSR[DONE]"] _1, } impl CADNW { #[allow(missing_docs)] @@ -89,10 +87,8 @@ impl<'a> _CADNW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/ceei/mod.rs b/src/dma/ceei/mod.rs index 4248fa1..9a39526 100644 --- a/src/dma/ceei/mod.rs +++ b/src/dma/ceei/mod.rs @@ -54,10 +54,8 @@ impl<'a> _CAEEW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/cerq/mod.rs b/src/dma/cerq/mod.rs index cd33130..27601d2 100644 --- a/src/dma/cerq/mod.rs +++ b/src/dma/cerq/mod.rs @@ -54,10 +54,8 @@ impl<'a> _CAERW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/cerr/mod.rs b/src/dma/cerr/mod.rs index 0776ec2..e7f3669 100644 --- a/src/dma/cerr/mod.rs +++ b/src/dma/cerr/mod.rs @@ -54,10 +54,8 @@ impl<'a> _CAEIW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/cint/mod.rs b/src/dma/cint/mod.rs index 52701eb..9d4d06b 100644 --- a/src/dma/cint/mod.rs +++ b/src/dma/cint/mod.rs @@ -54,10 +54,8 @@ impl<'a> _CAIRW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/cr/mod.rs b/src/dma/cr/mod.rs index 908aff9..32f049f 100644 --- a/src/dma/cr/mod.rs +++ b/src/dma/cr/mod.rs @@ -22,7 +22,9 @@ impl super::CR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -85,8 +87,7 @@ impl ERCAR { #[doc = "Possible values of the field `HOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HOER { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."] _1, } @@ -132,8 +133,7 @@ impl HOER { #[doc = "Possible values of the field `HALT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HALTR { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."] _1, } @@ -226,8 +226,7 @@ impl CLMR { #[doc = "Possible values of the field `EMLM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EMLMR { - #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."] - _0, + #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."] _0, #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."] _1, } @@ -273,8 +272,7 @@ impl EMLMR { #[doc = "Possible values of the field `ECX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECXR { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt."] _1, } @@ -320,8 +318,7 @@ impl ECXR { #[doc = "Possible values of the field `CX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CXR { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."] _1, } @@ -412,8 +409,7 @@ impl<'a> _ERCAW<'a> { } #[doc = "Values that can be written to the field `HOE`"] pub enum HOEW { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."] _1, } @@ -470,8 +466,7 @@ impl<'a> _HOEW<'a> { } #[doc = "Values that can be written to the field `HALT`"] pub enum HALTW { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."] _1, } @@ -586,8 +581,7 @@ impl<'a> _CLMW<'a> { } #[doc = "Values that can be written to the field `EMLM`"] pub enum EMLMW { - #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."] - _0, + #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."] _0, #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."] _1, } @@ -644,8 +638,7 @@ impl<'a> _EMLMW<'a> { } #[doc = "Values that can be written to the field `ECX`"] pub enum ECXW { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt."] _1, } @@ -702,8 +695,7 @@ impl<'a> _ECXW<'a> { } #[doc = "Values that can be written to the field `CX`"] pub enum CXW { - #[doc = "Normal operation"] - _0, + #[doc = "Normal operation"] _0, #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."] _1, } diff --git a/src/dma/dchpri0/mod.rs b/src/dma/dchpri0/mod.rs index fbc4ed3..02701a4 100644 --- a/src/dma/dchpri0/mod.rs +++ b/src/dma/dchpri0/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri1/mod.rs b/src/dma/dchpri1/mod.rs index 2e2fe62..6113118 100644 --- a/src/dma/dchpri1/mod.rs +++ b/src/dma/dchpri1/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri10/mod.rs b/src/dma/dchpri10/mod.rs index 686c0c1..68bc82b 100644 --- a/src/dma/dchpri10/mod.rs +++ b/src/dma/dchpri10/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri11/mod.rs b/src/dma/dchpri11/mod.rs index 208678f..167eaef 100644 --- a/src/dma/dchpri11/mod.rs +++ b/src/dma/dchpri11/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri12/mod.rs b/src/dma/dchpri12/mod.rs index aa120bc..9187a24 100644 --- a/src/dma/dchpri12/mod.rs +++ b/src/dma/dchpri12/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri13/mod.rs b/src/dma/dchpri13/mod.rs index 78c9158..d62a397 100644 --- a/src/dma/dchpri13/mod.rs +++ b/src/dma/dchpri13/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri14/mod.rs b/src/dma/dchpri14/mod.rs index b32afac..10efcbb 100644 --- a/src/dma/dchpri14/mod.rs +++ b/src/dma/dchpri14/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri15/mod.rs b/src/dma/dchpri15/mod.rs index 87246bf..3c8f1f8 100644 --- a/src/dma/dchpri15/mod.rs +++ b/src/dma/dchpri15/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri2/mod.rs b/src/dma/dchpri2/mod.rs index d274779..2c2aff5 100644 --- a/src/dma/dchpri2/mod.rs +++ b/src/dma/dchpri2/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri3/mod.rs b/src/dma/dchpri3/mod.rs index e30bb41..afb96a1 100644 --- a/src/dma/dchpri3/mod.rs +++ b/src/dma/dchpri3/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri4/mod.rs b/src/dma/dchpri4/mod.rs index 7fb790f..9b8b05a 100644 --- a/src/dma/dchpri4/mod.rs +++ b/src/dma/dchpri4/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri5/mod.rs b/src/dma/dchpri5/mod.rs index ffc06c4..654e765 100644 --- a/src/dma/dchpri5/mod.rs +++ b/src/dma/dchpri5/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri6/mod.rs b/src/dma/dchpri6/mod.rs index 0ccde05..3658686 100644 --- a/src/dma/dchpri6/mod.rs +++ b/src/dma/dchpri6/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri7/mod.rs b/src/dma/dchpri7/mod.rs index 843b802..93f82d7 100644 --- a/src/dma/dchpri7/mod.rs +++ b/src/dma/dchpri7/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri8/mod.rs b/src/dma/dchpri8/mod.rs index b164f6c..8417420 100644 --- a/src/dma/dchpri8/mod.rs +++ b/src/dma/dchpri8/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/dchpri9/mod.rs b/src/dma/dchpri9/mod.rs index e1920e4..1e64015 100644 --- a/src/dma/dchpri9/mod.rs +++ b/src/dma/dchpri9/mod.rs @@ -22,7 +22,9 @@ impl super::DCHPRI9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CHPRIR { #[doc = "Possible values of the field `DPA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPAR { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,8 +101,7 @@ impl DPAR { #[doc = "Possible values of the field `ECP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPR { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } @@ -162,10 +161,8 @@ impl<'a> _CHPRIW<'a> { } #[doc = "Values that can be written to the field `DPA`"] pub enum DPAW { - #[doc = "Channel n can suspend a lower priority channel."] - _0, - #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] - _1, + #[doc = "Channel n can suspend a lower priority channel."] _0, + #[doc = "Channel n cannot suspend any channel, regardless of channel priority."] _1, } impl DPAW { #[allow(missing_docs)] @@ -220,8 +217,7 @@ impl<'a> _DPAW<'a> { } #[doc = "Values that can be written to the field `ECP`"] pub enum ECPW { - #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] - _0, + #[doc = "Channel n cannot be suspended by a higher priority channel's service request."] _0, #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."] _1, } diff --git a/src/dma/ears/mod.rs b/src/dma/ears/mod.rs index 661714d..c1a6325 100644 --- a/src/dma/ears/mod.rs +++ b/src/dma/ears/mod.rs @@ -22,7 +22,9 @@ impl super::EARS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EARS { #[doc = "Possible values of the field `EDREQ_0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_0R { - #[doc = "Disable asynchronous DMA request for channel 0."] - _0, - #[doc = "Enable asynchronous DMA request for channel 0."] - _1, + #[doc = "Disable asynchronous DMA request for channel 0."] _0, + #[doc = "Enable asynchronous DMA request for channel 0."] _1, } impl EDREQ_0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EDREQ_0R { #[doc = "Possible values of the field `EDREQ_1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_1R { - #[doc = "Disable asynchronous DMA request for channel 1"] - _0, - #[doc = "Enable asynchronous DMA request for channel 1."] - _1, + #[doc = "Disable asynchronous DMA request for channel 1"] _0, + #[doc = "Enable asynchronous DMA request for channel 1."] _1, } impl EDREQ_1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl EDREQ_1R { #[doc = "Possible values of the field `EDREQ_2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_2R { - #[doc = "Disable asynchronous DMA request for channel 2."] - _0, - #[doc = "Enable asynchronous DMA request for channel 2."] - _1, + #[doc = "Disable asynchronous DMA request for channel 2."] _0, + #[doc = "Enable asynchronous DMA request for channel 2."] _1, } impl EDREQ_2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl EDREQ_2R { #[doc = "Possible values of the field `EDREQ_3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_3R { - #[doc = "Disable asynchronous DMA request for channel 3."] - _0, - #[doc = "Enable asynchronous DMA request for channel 3."] - _1, + #[doc = "Disable asynchronous DMA request for channel 3."] _0, + #[doc = "Enable asynchronous DMA request for channel 3."] _1, } impl EDREQ_3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl EDREQ_3R { #[doc = "Possible values of the field `EDREQ_4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_4R { - #[doc = "Disable asynchronous DMA request for channel 4."] - _0, - #[doc = "Enable asynchronous DMA request for channel 4."] - _1, + #[doc = "Disable asynchronous DMA request for channel 4."] _0, + #[doc = "Enable asynchronous DMA request for channel 4."] _1, } impl EDREQ_4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl EDREQ_4R { #[doc = "Possible values of the field `EDREQ_5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_5R { - #[doc = "Disable asynchronous DMA request for channel 5."] - _0, - #[doc = "Enable asynchronous DMA request for channel 5."] - _1, + #[doc = "Disable asynchronous DMA request for channel 5."] _0, + #[doc = "Enable asynchronous DMA request for channel 5."] _1, } impl EDREQ_5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl EDREQ_5R { #[doc = "Possible values of the field `EDREQ_6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_6R { - #[doc = "Disable asynchronous DMA request for channel 6."] - _0, - #[doc = "Enable asynchronous DMA request for channel 6."] - _1, + #[doc = "Disable asynchronous DMA request for channel 6."] _0, + #[doc = "Enable asynchronous DMA request for channel 6."] _1, } impl EDREQ_6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl EDREQ_6R { #[doc = "Possible values of the field `EDREQ_7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_7R { - #[doc = "Disable asynchronous DMA request for channel 7."] - _0, - #[doc = "Enable asynchronous DMA request for channel 7."] - _1, + #[doc = "Disable asynchronous DMA request for channel 7."] _0, + #[doc = "Enable asynchronous DMA request for channel 7."] _1, } impl EDREQ_7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl EDREQ_7R { #[doc = "Possible values of the field `EDREQ_8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_8R { - #[doc = "Disable asynchronous DMA request for channel 8."] - _0, - #[doc = "Enable asynchronous DMA request for channel 8."] - _1, + #[doc = "Disable asynchronous DMA request for channel 8."] _0, + #[doc = "Enable asynchronous DMA request for channel 8."] _1, } impl EDREQ_8R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl EDREQ_8R { #[doc = "Possible values of the field `EDREQ_9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_9R { - #[doc = "Disable asynchronous DMA request for channel 9."] - _0, - #[doc = "Enable asynchronous DMA request for channel 9."] - _1, + #[doc = "Disable asynchronous DMA request for channel 9."] _0, + #[doc = "Enable asynchronous DMA request for channel 9."] _1, } impl EDREQ_9R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl EDREQ_9R { #[doc = "Possible values of the field `EDREQ_10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_10R { - #[doc = "Disable asynchronous DMA request for channel 10."] - _0, - #[doc = "Enable asynchronous DMA request for channel 10."] - _1, + #[doc = "Disable asynchronous DMA request for channel 10."] _0, + #[doc = "Enable asynchronous DMA request for channel 10."] _1, } impl EDREQ_10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl EDREQ_10R { #[doc = "Possible values of the field `EDREQ_11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_11R { - #[doc = "Disable asynchronous DMA request for channel 11."] - _0, - #[doc = "Enable asynchronous DMA request for channel 11."] - _1, + #[doc = "Disable asynchronous DMA request for channel 11."] _0, + #[doc = "Enable asynchronous DMA request for channel 11."] _1, } impl EDREQ_11R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl EDREQ_11R { #[doc = "Possible values of the field `EDREQ_12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_12R { - #[doc = "Disable asynchronous DMA request for channel 12."] - _0, - #[doc = "Enable asynchronous DMA request for channel 12."] - _1, + #[doc = "Disable asynchronous DMA request for channel 12."] _0, + #[doc = "Enable asynchronous DMA request for channel 12."] _1, } impl EDREQ_12R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl EDREQ_12R { #[doc = "Possible values of the field `EDREQ_13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_13R { - #[doc = "Disable asynchronous DMA request for channel 13."] - _0, - #[doc = "Enable asynchronous DMA request for channel 13."] - _1, + #[doc = "Disable asynchronous DMA request for channel 13."] _0, + #[doc = "Enable asynchronous DMA request for channel 13."] _1, } impl EDREQ_13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl EDREQ_13R { #[doc = "Possible values of the field `EDREQ_14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_14R { - #[doc = "Disable asynchronous DMA request for channel 14."] - _0, - #[doc = "Enable asynchronous DMA request for channel 14."] - _1, + #[doc = "Disable asynchronous DMA request for channel 14."] _0, + #[doc = "Enable asynchronous DMA request for channel 14."] _1, } impl EDREQ_14R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl EDREQ_14R { #[doc = "Possible values of the field `EDREQ_15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EDREQ_15R { - #[doc = "Disable asynchronous DMA request for channel 15."] - _0, - #[doc = "Enable asynchronous DMA request for channel 15."] - _1, + #[doc = "Disable asynchronous DMA request for channel 15."] _0, + #[doc = "Enable asynchronous DMA request for channel 15."] _1, } impl EDREQ_15R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl EDREQ_15R { } #[doc = "Values that can be written to the field `EDREQ_0`"] pub enum EDREQ_0W { - #[doc = "Disable asynchronous DMA request for channel 0."] - _0, - #[doc = "Enable asynchronous DMA request for channel 0."] - _1, + #[doc = "Disable asynchronous DMA request for channel 0."] _0, + #[doc = "Enable asynchronous DMA request for channel 0."] _1, } impl EDREQ_0W { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _EDREQ_0W<'a> { } #[doc = "Values that can be written to the field `EDREQ_1`"] pub enum EDREQ_1W { - #[doc = "Disable asynchronous DMA request for channel 1"] - _0, - #[doc = "Enable asynchronous DMA request for channel 1."] - _1, + #[doc = "Disable asynchronous DMA request for channel 1"] _0, + #[doc = "Enable asynchronous DMA request for channel 1."] _1, } impl EDREQ_1W { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _EDREQ_1W<'a> { } #[doc = "Values that can be written to the field `EDREQ_2`"] pub enum EDREQ_2W { - #[doc = "Disable asynchronous DMA request for channel 2."] - _0, - #[doc = "Enable asynchronous DMA request for channel 2."] - _1, + #[doc = "Disable asynchronous DMA request for channel 2."] _0, + #[doc = "Enable asynchronous DMA request for channel 2."] _1, } impl EDREQ_2W { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _EDREQ_2W<'a> { } #[doc = "Values that can be written to the field `EDREQ_3`"] pub enum EDREQ_3W { - #[doc = "Disable asynchronous DMA request for channel 3."] - _0, - #[doc = "Enable asynchronous DMA request for channel 3."] - _1, + #[doc = "Disable asynchronous DMA request for channel 3."] _0, + #[doc = "Enable asynchronous DMA request for channel 3."] _1, } impl EDREQ_3W { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _EDREQ_3W<'a> { } #[doc = "Values that can be written to the field `EDREQ_4`"] pub enum EDREQ_4W { - #[doc = "Disable asynchronous DMA request for channel 4."] - _0, - #[doc = "Enable asynchronous DMA request for channel 4."] - _1, + #[doc = "Disable asynchronous DMA request for channel 4."] _0, + #[doc = "Enable asynchronous DMA request for channel 4."] _1, } impl EDREQ_4W { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _EDREQ_4W<'a> { } #[doc = "Values that can be written to the field `EDREQ_5`"] pub enum EDREQ_5W { - #[doc = "Disable asynchronous DMA request for channel 5."] - _0, - #[doc = "Enable asynchronous DMA request for channel 5."] - _1, + #[doc = "Disable asynchronous DMA request for channel 5."] _0, + #[doc = "Enable asynchronous DMA request for channel 5."] _1, } impl EDREQ_5W { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _EDREQ_5W<'a> { } #[doc = "Values that can be written to the field `EDREQ_6`"] pub enum EDREQ_6W { - #[doc = "Disable asynchronous DMA request for channel 6."] - _0, - #[doc = "Enable asynchronous DMA request for channel 6."] - _1, + #[doc = "Disable asynchronous DMA request for channel 6."] _0, + #[doc = "Enable asynchronous DMA request for channel 6."] _1, } impl EDREQ_6W { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _EDREQ_6W<'a> { } #[doc = "Values that can be written to the field `EDREQ_7`"] pub enum EDREQ_7W { - #[doc = "Disable asynchronous DMA request for channel 7."] - _0, - #[doc = "Enable asynchronous DMA request for channel 7."] - _1, + #[doc = "Disable asynchronous DMA request for channel 7."] _0, + #[doc = "Enable asynchronous DMA request for channel 7."] _1, } impl EDREQ_7W { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _EDREQ_7W<'a> { } #[doc = "Values that can be written to the field `EDREQ_8`"] pub enum EDREQ_8W { - #[doc = "Disable asynchronous DMA request for channel 8."] - _0, - #[doc = "Enable asynchronous DMA request for channel 8."] - _1, + #[doc = "Disable asynchronous DMA request for channel 8."] _0, + #[doc = "Enable asynchronous DMA request for channel 8."] _1, } impl EDREQ_8W { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _EDREQ_8W<'a> { } #[doc = "Values that can be written to the field `EDREQ_9`"] pub enum EDREQ_9W { - #[doc = "Disable asynchronous DMA request for channel 9."] - _0, - #[doc = "Enable asynchronous DMA request for channel 9."] - _1, + #[doc = "Disable asynchronous DMA request for channel 9."] _0, + #[doc = "Enable asynchronous DMA request for channel 9."] _1, } impl EDREQ_9W { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _EDREQ_9W<'a> { } #[doc = "Values that can be written to the field `EDREQ_10`"] pub enum EDREQ_10W { - #[doc = "Disable asynchronous DMA request for channel 10."] - _0, - #[doc = "Enable asynchronous DMA request for channel 10."] - _1, + #[doc = "Disable asynchronous DMA request for channel 10."] _0, + #[doc = "Enable asynchronous DMA request for channel 10."] _1, } impl EDREQ_10W { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _EDREQ_10W<'a> { } #[doc = "Values that can be written to the field `EDREQ_11`"] pub enum EDREQ_11W { - #[doc = "Disable asynchronous DMA request for channel 11."] - _0, - #[doc = "Enable asynchronous DMA request for channel 11."] - _1, + #[doc = "Disable asynchronous DMA request for channel 11."] _0, + #[doc = "Enable asynchronous DMA request for channel 11."] _1, } impl EDREQ_11W { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _EDREQ_11W<'a> { } #[doc = "Values that can be written to the field `EDREQ_12`"] pub enum EDREQ_12W { - #[doc = "Disable asynchronous DMA request for channel 12."] - _0, - #[doc = "Enable asynchronous DMA request for channel 12."] - _1, + #[doc = "Disable asynchronous DMA request for channel 12."] _0, + #[doc = "Enable asynchronous DMA request for channel 12."] _1, } impl EDREQ_12W { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _EDREQ_12W<'a> { } #[doc = "Values that can be written to the field `EDREQ_13`"] pub enum EDREQ_13W { - #[doc = "Disable asynchronous DMA request for channel 13."] - _0, - #[doc = "Enable asynchronous DMA request for channel 13."] - _1, + #[doc = "Disable asynchronous DMA request for channel 13."] _0, + #[doc = "Enable asynchronous DMA request for channel 13."] _1, } impl EDREQ_13W { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _EDREQ_13W<'a> { } #[doc = "Values that can be written to the field `EDREQ_14`"] pub enum EDREQ_14W { - #[doc = "Disable asynchronous DMA request for channel 14."] - _0, - #[doc = "Enable asynchronous DMA request for channel 14."] - _1, + #[doc = "Disable asynchronous DMA request for channel 14."] _0, + #[doc = "Enable asynchronous DMA request for channel 14."] _1, } impl EDREQ_14W { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _EDREQ_14W<'a> { } #[doc = "Values that can be written to the field `EDREQ_15`"] pub enum EDREQ_15W { - #[doc = "Disable asynchronous DMA request for channel 15."] - _0, - #[doc = "Enable asynchronous DMA request for channel 15."] - _1, + #[doc = "Disable asynchronous DMA request for channel 15."] _0, + #[doc = "Enable asynchronous DMA request for channel 15."] _1, } impl EDREQ_15W { #[allow(missing_docs)] diff --git a/src/dma/eei/mod.rs b/src/dma/eei/mod.rs index 980ad9e..6f2d35a 100644 --- a/src/dma/eei/mod.rs +++ b/src/dma/eei/mod.rs @@ -22,7 +22,9 @@ impl super::EEI { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::EEI { #[doc = "Possible values of the field `EEI0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI0R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -90,8 +91,7 @@ impl EEI0R { #[doc = "Possible values of the field `EEI1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI1R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -137,8 +137,7 @@ impl EEI1R { #[doc = "Possible values of the field `EEI2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI2R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -184,8 +183,7 @@ impl EEI2R { #[doc = "Possible values of the field `EEI3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI3R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -231,8 +229,7 @@ impl EEI3R { #[doc = "Possible values of the field `EEI4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI4R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -278,8 +275,7 @@ impl EEI4R { #[doc = "Possible values of the field `EEI5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI5R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -325,8 +321,7 @@ impl EEI5R { #[doc = "Possible values of the field `EEI6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI6R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -372,8 +367,7 @@ impl EEI6R { #[doc = "Possible values of the field `EEI7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI7R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -419,8 +413,7 @@ impl EEI7R { #[doc = "Possible values of the field `EEI8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI8R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -466,8 +459,7 @@ impl EEI8R { #[doc = "Possible values of the field `EEI9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI9R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -513,8 +505,7 @@ impl EEI9R { #[doc = "Possible values of the field `EEI10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI10R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -560,8 +551,7 @@ impl EEI10R { #[doc = "Possible values of the field `EEI11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI11R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -607,8 +597,7 @@ impl EEI11R { #[doc = "Possible values of the field `EEI12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI12R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -654,8 +643,7 @@ impl EEI12R { #[doc = "Possible values of the field `EEI13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI13R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -701,8 +689,7 @@ impl EEI13R { #[doc = "Possible values of the field `EEI14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI14R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -748,8 +735,7 @@ impl EEI14R { #[doc = "Possible values of the field `EEI15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEI15R { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -794,8 +780,7 @@ impl EEI15R { } #[doc = "Values that can be written to the field `EEI0`"] pub enum EEI0W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -852,8 +837,7 @@ impl<'a> _EEI0W<'a> { } #[doc = "Values that can be written to the field `EEI1`"] pub enum EEI1W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -910,8 +894,7 @@ impl<'a> _EEI1W<'a> { } #[doc = "Values that can be written to the field `EEI2`"] pub enum EEI2W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -968,8 +951,7 @@ impl<'a> _EEI2W<'a> { } #[doc = "Values that can be written to the field `EEI3`"] pub enum EEI3W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1026,8 +1008,7 @@ impl<'a> _EEI3W<'a> { } #[doc = "Values that can be written to the field `EEI4`"] pub enum EEI4W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1084,8 +1065,7 @@ impl<'a> _EEI4W<'a> { } #[doc = "Values that can be written to the field `EEI5`"] pub enum EEI5W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1142,8 +1122,7 @@ impl<'a> _EEI5W<'a> { } #[doc = "Values that can be written to the field `EEI6`"] pub enum EEI6W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1200,8 +1179,7 @@ impl<'a> _EEI6W<'a> { } #[doc = "Values that can be written to the field `EEI7`"] pub enum EEI7W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1258,8 +1236,7 @@ impl<'a> _EEI7W<'a> { } #[doc = "Values that can be written to the field `EEI8`"] pub enum EEI8W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1316,8 +1293,7 @@ impl<'a> _EEI8W<'a> { } #[doc = "Values that can be written to the field `EEI9`"] pub enum EEI9W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1374,8 +1350,7 @@ impl<'a> _EEI9W<'a> { } #[doc = "Values that can be written to the field `EEI10`"] pub enum EEI10W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1432,8 +1407,7 @@ impl<'a> _EEI10W<'a> { } #[doc = "Values that can be written to the field `EEI11`"] pub enum EEI11W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1490,8 +1464,7 @@ impl<'a> _EEI11W<'a> { } #[doc = "Values that can be written to the field `EEI12`"] pub enum EEI12W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1548,8 +1521,7 @@ impl<'a> _EEI12W<'a> { } #[doc = "Values that can be written to the field `EEI13`"] pub enum EEI13W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1606,8 +1578,7 @@ impl<'a> _EEI13W<'a> { } #[doc = "Values that can be written to the field `EEI14`"] pub enum EEI14W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } @@ -1664,8 +1635,7 @@ impl<'a> _EEI14W<'a> { } #[doc = "Values that can be written to the field `EEI15`"] pub enum EEI15W { - #[doc = "The error signal for corresponding channel does not generate an error interrupt"] - _0, + #[doc = "The error signal for corresponding channel does not generate an error interrupt"] _0, #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"] _1, } diff --git a/src/dma/erq/mod.rs b/src/dma/erq/mod.rs index 144b481..3346a8a 100644 --- a/src/dma/erq/mod.rs +++ b/src/dma/erq/mod.rs @@ -22,7 +22,9 @@ impl super::ERQ { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ERQ { #[doc = "Possible values of the field `ERQ0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ0R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERQ0R { #[doc = "Possible values of the field `ERQ1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ1R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ERQ1R { #[doc = "Possible values of the field `ERQ2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ2R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ERQ2R { #[doc = "Possible values of the field `ERQ3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ3R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl ERQ3R { #[doc = "Possible values of the field `ERQ4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ4R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl ERQ4R { #[doc = "Possible values of the field `ERQ5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ5R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ERQ5R { #[doc = "Possible values of the field `ERQ6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ6R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl ERQ6R { #[doc = "Possible values of the field `ERQ7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ7R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl ERQ7R { #[doc = "Possible values of the field `ERQ8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ8R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ8R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl ERQ8R { #[doc = "Possible values of the field `ERQ9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ9R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ9R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl ERQ9R { #[doc = "Possible values of the field `ERQ10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ10R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl ERQ10R { #[doc = "Possible values of the field `ERQ11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ11R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ11R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl ERQ11R { #[doc = "Possible values of the field `ERQ12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ12R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ12R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl ERQ12R { #[doc = "Possible values of the field `ERQ13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ13R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl ERQ13R { #[doc = "Possible values of the field `ERQ14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ14R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ14R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl ERQ14R { #[doc = "Possible values of the field `ERQ15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERQ15R { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ15R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl ERQ15R { } #[doc = "Values that can be written to the field `ERQ0`"] pub enum ERQ0W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ0W { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _ERQ0W<'a> { } #[doc = "Values that can be written to the field `ERQ1`"] pub enum ERQ1W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ1W { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _ERQ1W<'a> { } #[doc = "Values that can be written to the field `ERQ2`"] pub enum ERQ2W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ2W { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _ERQ2W<'a> { } #[doc = "Values that can be written to the field `ERQ3`"] pub enum ERQ3W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ3W { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _ERQ3W<'a> { } #[doc = "Values that can be written to the field `ERQ4`"] pub enum ERQ4W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ4W { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _ERQ4W<'a> { } #[doc = "Values that can be written to the field `ERQ5`"] pub enum ERQ5W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ5W { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _ERQ5W<'a> { } #[doc = "Values that can be written to the field `ERQ6`"] pub enum ERQ6W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ6W { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _ERQ6W<'a> { } #[doc = "Values that can be written to the field `ERQ7`"] pub enum ERQ7W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ7W { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _ERQ7W<'a> { } #[doc = "Values that can be written to the field `ERQ8`"] pub enum ERQ8W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ8W { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _ERQ8W<'a> { } #[doc = "Values that can be written to the field `ERQ9`"] pub enum ERQ9W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ9W { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _ERQ9W<'a> { } #[doc = "Values that can be written to the field `ERQ10`"] pub enum ERQ10W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ10W { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _ERQ10W<'a> { } #[doc = "Values that can be written to the field `ERQ11`"] pub enum ERQ11W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ11W { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _ERQ11W<'a> { } #[doc = "Values that can be written to the field `ERQ12`"] pub enum ERQ12W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ12W { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _ERQ12W<'a> { } #[doc = "Values that can be written to the field `ERQ13`"] pub enum ERQ13W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ13W { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _ERQ13W<'a> { } #[doc = "Values that can be written to the field `ERQ14`"] pub enum ERQ14W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ14W { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _ERQ14W<'a> { } #[doc = "Values that can be written to the field `ERQ15`"] pub enum ERQ15W { - #[doc = "The DMA request signal for the corresponding channel is disabled"] - _0, - #[doc = "The DMA request signal for the corresponding channel is enabled"] - _1, + #[doc = "The DMA request signal for the corresponding channel is disabled"] _0, + #[doc = "The DMA request signal for the corresponding channel is enabled"] _1, } impl ERQ15W { #[allow(missing_docs)] diff --git a/src/dma/err/mod.rs b/src/dma/err/mod.rs index cdf94a6..bf84639 100644 --- a/src/dma/err/mod.rs +++ b/src/dma/err/mod.rs @@ -22,7 +22,9 @@ impl super::ERR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ERR { #[doc = "Possible values of the field `ERR0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR0R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERR0R { #[doc = "Possible values of the field `ERR1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR1R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ERR1R { #[doc = "Possible values of the field `ERR2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR2R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ERR2R { #[doc = "Possible values of the field `ERR3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR3R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl ERR3R { #[doc = "Possible values of the field `ERR4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR4R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl ERR4R { #[doc = "Possible values of the field `ERR5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR5R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ERR5R { #[doc = "Possible values of the field `ERR6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR6R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl ERR6R { #[doc = "Possible values of the field `ERR7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR7R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl ERR7R { #[doc = "Possible values of the field `ERR8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR8R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR8R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl ERR8R { #[doc = "Possible values of the field `ERR9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR9R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR9R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl ERR9R { #[doc = "Possible values of the field `ERR10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR10R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl ERR10R { #[doc = "Possible values of the field `ERR11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR11R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR11R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl ERR11R { #[doc = "Possible values of the field `ERR12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR12R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR12R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl ERR12R { #[doc = "Possible values of the field `ERR13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR13R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl ERR13R { #[doc = "Possible values of the field `ERR14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR14R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR14R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl ERR14R { #[doc = "Possible values of the field `ERR15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERR15R { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR15R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl ERR15R { } #[doc = "Values that can be written to the field `ERR0`"] pub enum ERR0W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR0W { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _ERR0W<'a> { } #[doc = "Values that can be written to the field `ERR1`"] pub enum ERR1W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR1W { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _ERR1W<'a> { } #[doc = "Values that can be written to the field `ERR2`"] pub enum ERR2W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR2W { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _ERR2W<'a> { } #[doc = "Values that can be written to the field `ERR3`"] pub enum ERR3W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR3W { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _ERR3W<'a> { } #[doc = "Values that can be written to the field `ERR4`"] pub enum ERR4W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR4W { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _ERR4W<'a> { } #[doc = "Values that can be written to the field `ERR5`"] pub enum ERR5W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR5W { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _ERR5W<'a> { } #[doc = "Values that can be written to the field `ERR6`"] pub enum ERR6W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR6W { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _ERR6W<'a> { } #[doc = "Values that can be written to the field `ERR7`"] pub enum ERR7W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR7W { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _ERR7W<'a> { } #[doc = "Values that can be written to the field `ERR8`"] pub enum ERR8W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR8W { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _ERR8W<'a> { } #[doc = "Values that can be written to the field `ERR9`"] pub enum ERR9W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR9W { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _ERR9W<'a> { } #[doc = "Values that can be written to the field `ERR10`"] pub enum ERR10W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR10W { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _ERR10W<'a> { } #[doc = "Values that can be written to the field `ERR11`"] pub enum ERR11W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR11W { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _ERR11W<'a> { } #[doc = "Values that can be written to the field `ERR12`"] pub enum ERR12W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR12W { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _ERR12W<'a> { } #[doc = "Values that can be written to the field `ERR13`"] pub enum ERR13W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR13W { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _ERR13W<'a> { } #[doc = "Values that can be written to the field `ERR14`"] pub enum ERR14W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR14W { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _ERR14W<'a> { } #[doc = "Values that can be written to the field `ERR15`"] pub enum ERR15W { - #[doc = "An error in this channel has not occurred"] - _0, - #[doc = "An error in this channel has occurred"] - _1, + #[doc = "An error in this channel has not occurred"] _0, + #[doc = "An error in this channel has occurred"] _1, } impl ERR15W { #[allow(missing_docs)] diff --git a/src/dma/es/mod.rs b/src/dma/es/mod.rs index a27218a..009b94e 100644 --- a/src/dma/es/mod.rs +++ b/src/dma/es/mod.rs @@ -6,16 +6,16 @@ impl super::ES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `DBE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBER { - #[doc = "No destination bus error"] - _0, - #[doc = "The last recorded error was a bus error on a destination write"] - _1, + #[doc = "No destination bus error"] _0, + #[doc = "The last recorded error was a bus error on a destination write"] _1, } impl DBER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl DBER { #[doc = "Possible values of the field `SBE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBER { - #[doc = "No source bus error"] - _0, - #[doc = "The last recorded error was a bus error on a source read"] - _1, + #[doc = "No source bus error"] _0, + #[doc = "The last recorded error was a bus error on a source read"] _1, } impl SBER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,8 +104,7 @@ impl SBER { #[doc = "Possible values of the field `SGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SGER { - #[doc = "No scatter/gather configuration error"] - _0, + #[doc = "No scatter/gather configuration error"] _0, #[doc = "The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary."] _1, } @@ -153,10 +150,8 @@ impl SGER { #[doc = "Possible values of the field `NCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NCER { - #[doc = "No NBYTES/CITER configuration error"] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "No NBYTES/CITER configuration error"] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl NCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,8 +190,7 @@ impl NCER { #[doc = "Possible values of the field `DOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOER { - #[doc = "No destination offset configuration error"] - _0, + #[doc = "No destination offset configuration error"] _0, #[doc = "The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]."] _1, } @@ -242,8 +236,7 @@ impl DOER { #[doc = "Possible values of the field `DAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DAER { - #[doc = "No destination address configuration error"] - _0, + #[doc = "No destination address configuration error"] _0, #[doc = "The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]."] _1, } @@ -289,8 +282,7 @@ impl DAER { #[doc = "Possible values of the field `SOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOER { - #[doc = "No source offset configuration error"] - _0, + #[doc = "No source offset configuration error"] _0, #[doc = "The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]."] _1, } @@ -336,8 +328,7 @@ impl SOER { #[doc = "Possible values of the field `SAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SAER { - #[doc = "No source address configuration error."] - _0, + #[doc = "No source address configuration error."] _0, #[doc = "The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]."] _1, } @@ -394,10 +385,8 @@ impl ERRCHNR { #[doc = "Possible values of the field `CPE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPER { - #[doc = "No channel priority error"] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "No channel priority error"] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl CPER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -436,10 +425,8 @@ impl CPER { #[doc = "Possible values of the field `ECX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECXR { - #[doc = "No canceled transfers"] - _0, - #[doc = "The last recorded entry was a canceled transfer by the error cancel transfer input"] - _1, + #[doc = "No canceled transfers"] _0, + #[doc = "The last recorded entry was a canceled transfer by the error cancel transfer input"] _1, } impl ECXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -483,8 +470,7 @@ impl ECXR { #[doc = "Possible values of the field `VLD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VLDR { - #[doc = "No ERR bits are set."] - _0, + #[doc = "No ERR bits are set."] _0, #[doc = "At least one ERR bit is set indicating a valid error exists that has not been cleared."] _1, } diff --git a/src/dma/hrs/mod.rs b/src/dma/hrs/mod.rs index f599ce7..d3d801a 100644 --- a/src/dma/hrs/mod.rs +++ b/src/dma/hrs/mod.rs @@ -6,16 +6,16 @@ impl super::HRS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `HRS0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS0R { - #[doc = "A hardware service request for channel 0 is not present"] - _0, - #[doc = "A hardware service request for channel 0 is present"] - _1, + #[doc = "A hardware service request for channel 0 is not present"] _0, + #[doc = "A hardware service request for channel 0 is present"] _1, } impl HRS0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl HRS0R { #[doc = "Possible values of the field `HRS1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS1R { - #[doc = "A hardware service request for channel 1 is not present"] - _0, - #[doc = "A hardware service request for channel 1 is present"] - _1, + #[doc = "A hardware service request for channel 1 is not present"] _0, + #[doc = "A hardware service request for channel 1 is present"] _1, } impl HRS1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl HRS1R { #[doc = "Possible values of the field `HRS2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS2R { - #[doc = "A hardware service request for channel 2 is not present"] - _0, - #[doc = "A hardware service request for channel 2 is present"] - _1, + #[doc = "A hardware service request for channel 2 is not present"] _0, + #[doc = "A hardware service request for channel 2 is present"] _1, } impl HRS2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl HRS2R { #[doc = "Possible values of the field `HRS3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS3R { - #[doc = "A hardware service request for channel 3 is not present"] - _0, - #[doc = "A hardware service request for channel 3 is present"] - _1, + #[doc = "A hardware service request for channel 3 is not present"] _0, + #[doc = "A hardware service request for channel 3 is present"] _1, } impl HRS3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl HRS3R { #[doc = "Possible values of the field `HRS4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS4R { - #[doc = "A hardware service request for channel 4 is not present"] - _0, - #[doc = "A hardware service request for channel 4 is present"] - _1, + #[doc = "A hardware service request for channel 4 is not present"] _0, + #[doc = "A hardware service request for channel 4 is present"] _1, } impl HRS4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl HRS4R { #[doc = "Possible values of the field `HRS5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS5R { - #[doc = "A hardware service request for channel 5 is not present"] - _0, - #[doc = "A hardware service request for channel 5 is present"] - _1, + #[doc = "A hardware service request for channel 5 is not present"] _0, + #[doc = "A hardware service request for channel 5 is present"] _1, } impl HRS5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl HRS5R { #[doc = "Possible values of the field `HRS6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS6R { - #[doc = "A hardware service request for channel 6 is not present"] - _0, - #[doc = "A hardware service request for channel 6 is present"] - _1, + #[doc = "A hardware service request for channel 6 is not present"] _0, + #[doc = "A hardware service request for channel 6 is present"] _1, } impl HRS6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl HRS6R { #[doc = "Possible values of the field `HRS7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS7R { - #[doc = "A hardware service request for channel 7 is not present"] - _0, - #[doc = "A hardware service request for channel 7 is present"] - _1, + #[doc = "A hardware service request for channel 7 is not present"] _0, + #[doc = "A hardware service request for channel 7 is present"] _1, } impl HRS7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -388,10 +374,8 @@ impl HRS7R { #[doc = "Possible values of the field `HRS8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS8R { - #[doc = "A hardware service request for channel 8 is not present"] - _0, - #[doc = "A hardware service request for channel 8 is present"] - _1, + #[doc = "A hardware service request for channel 8 is not present"] _0, + #[doc = "A hardware service request for channel 8 is present"] _1, } impl HRS8R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -435,10 +419,8 @@ impl HRS8R { #[doc = "Possible values of the field `HRS9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS9R { - #[doc = "A hardware service request for channel 9 is not present"] - _0, - #[doc = "A hardware service request for channel 9 is present"] - _1, + #[doc = "A hardware service request for channel 9 is not present"] _0, + #[doc = "A hardware service request for channel 9 is present"] _1, } impl HRS9R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -482,10 +464,8 @@ impl HRS9R { #[doc = "Possible values of the field `HRS10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS10R { - #[doc = "A hardware service request for channel 10 is not present"] - _0, - #[doc = "A hardware service request for channel 10 is present"] - _1, + #[doc = "A hardware service request for channel 10 is not present"] _0, + #[doc = "A hardware service request for channel 10 is present"] _1, } impl HRS10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -529,10 +509,8 @@ impl HRS10R { #[doc = "Possible values of the field `HRS11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS11R { - #[doc = "A hardware service request for channel 11 is not present"] - _0, - #[doc = "A hardware service request for channel 11 is present"] - _1, + #[doc = "A hardware service request for channel 11 is not present"] _0, + #[doc = "A hardware service request for channel 11 is present"] _1, } impl HRS11R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -576,10 +554,8 @@ impl HRS11R { #[doc = "Possible values of the field `HRS12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS12R { - #[doc = "A hardware service request for channel 12 is not present"] - _0, - #[doc = "A hardware service request for channel 12 is present"] - _1, + #[doc = "A hardware service request for channel 12 is not present"] _0, + #[doc = "A hardware service request for channel 12 is present"] _1, } impl HRS12R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -623,10 +599,8 @@ impl HRS12R { #[doc = "Possible values of the field `HRS13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS13R { - #[doc = "A hardware service request for channel 13 is not present"] - _0, - #[doc = "A hardware service request for channel 13 is present"] - _1, + #[doc = "A hardware service request for channel 13 is not present"] _0, + #[doc = "A hardware service request for channel 13 is present"] _1, } impl HRS13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -670,10 +644,8 @@ impl HRS13R { #[doc = "Possible values of the field `HRS14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS14R { - #[doc = "A hardware service request for channel 14 is not present"] - _0, - #[doc = "A hardware service request for channel 14 is present"] - _1, + #[doc = "A hardware service request for channel 14 is not present"] _0, + #[doc = "A hardware service request for channel 14 is present"] _1, } impl HRS14R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -717,10 +689,8 @@ impl HRS14R { #[doc = "Possible values of the field `HRS15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRS15R { - #[doc = "A hardware service request for channel 15 is not present"] - _0, - #[doc = "A hardware service request for channel 15 is present"] - _1, + #[doc = "A hardware service request for channel 15 is not present"] _0, + #[doc = "A hardware service request for channel 15 is present"] _1, } impl HRS15R { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/dma/int/mod.rs b/src/dma/int/mod.rs index 94f8bd7..4af8240 100644 --- a/src/dma/int/mod.rs +++ b/src/dma/int/mod.rs @@ -22,7 +22,9 @@ impl super::INT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::INT { #[doc = "Possible values of the field `INT0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT0R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl INT0R { #[doc = "Possible values of the field `INT1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT1R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INT1R { #[doc = "Possible values of the field `INT2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT2R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl INT2R { #[doc = "Possible values of the field `INT3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT3R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl INT3R { #[doc = "Possible values of the field `INT4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT4R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl INT4R { #[doc = "Possible values of the field `INT5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT5R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl INT5R { #[doc = "Possible values of the field `INT6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT6R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl INT6R { #[doc = "Possible values of the field `INT7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT7R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl INT7R { #[doc = "Possible values of the field `INT8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT8R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT8R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl INT8R { #[doc = "Possible values of the field `INT9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT9R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT9R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl INT9R { #[doc = "Possible values of the field `INT10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT10R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl INT10R { #[doc = "Possible values of the field `INT11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT11R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT11R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl INT11R { #[doc = "Possible values of the field `INT12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT12R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT12R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl INT12R { #[doc = "Possible values of the field `INT13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT13R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl INT13R { #[doc = "Possible values of the field `INT14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT14R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT14R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl INT14R { #[doc = "Possible values of the field `INT15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INT15R { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT15R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl INT15R { } #[doc = "Values that can be written to the field `INT0`"] pub enum INT0W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT0W { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _INT0W<'a> { } #[doc = "Values that can be written to the field `INT1`"] pub enum INT1W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT1W { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _INT1W<'a> { } #[doc = "Values that can be written to the field `INT2`"] pub enum INT2W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT2W { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _INT2W<'a> { } #[doc = "Values that can be written to the field `INT3`"] pub enum INT3W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT3W { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _INT3W<'a> { } #[doc = "Values that can be written to the field `INT4`"] pub enum INT4W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT4W { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _INT4W<'a> { } #[doc = "Values that can be written to the field `INT5`"] pub enum INT5W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT5W { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _INT5W<'a> { } #[doc = "Values that can be written to the field `INT6`"] pub enum INT6W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT6W { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _INT6W<'a> { } #[doc = "Values that can be written to the field `INT7`"] pub enum INT7W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT7W { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _INT7W<'a> { } #[doc = "Values that can be written to the field `INT8`"] pub enum INT8W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT8W { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _INT8W<'a> { } #[doc = "Values that can be written to the field `INT9`"] pub enum INT9W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT9W { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _INT9W<'a> { } #[doc = "Values that can be written to the field `INT10`"] pub enum INT10W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT10W { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _INT10W<'a> { } #[doc = "Values that can be written to the field `INT11`"] pub enum INT11W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT11W { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _INT11W<'a> { } #[doc = "Values that can be written to the field `INT12`"] pub enum INT12W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT12W { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _INT12W<'a> { } #[doc = "Values that can be written to the field `INT13`"] pub enum INT13W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT13W { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _INT13W<'a> { } #[doc = "Values that can be written to the field `INT14`"] pub enum INT14W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT14W { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _INT14W<'a> { } #[doc = "Values that can be written to the field `INT15`"] pub enum INT15W { - #[doc = "The interrupt request for corresponding channel is cleared"] - _0, - #[doc = "The interrupt request for corresponding channel is active"] - _1, + #[doc = "The interrupt request for corresponding channel is cleared"] _0, + #[doc = "The interrupt request for corresponding channel is active"] _1, } impl INT15W { #[allow(missing_docs)] diff --git a/src/dma/mod.rs b/src/dma/mod.rs index f53d957..c74efb7 100644 --- a/src/dma/mod.rs +++ b/src/dma/mod.rs @@ -2,428 +2,300 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Control Register"] - pub cr: CR, - #[doc = "0x04 - Error Status Register"] - pub es: ES, + #[doc = "0x00 - Control Register"] pub cr: CR, + #[doc = "0x04 - Error Status Register"] pub es: ES, _reserved0: [u8; 4usize], - #[doc = "0x0c - Enable Request Register"] - pub erq: ERQ, + #[doc = "0x0c - Enable Request Register"] pub erq: ERQ, _reserved1: [u8; 4usize], - #[doc = "0x14 - Enable Error Interrupt Register"] - pub eei: EEI, - #[doc = "0x18 - Clear Enable Error Interrupt Register"] - pub ceei: CEEI, - #[doc = "0x19 - Set Enable Error Interrupt Register"] - pub seei: SEEI, - #[doc = "0x1a - Clear Enable Request Register"] - pub cerq: CERQ, - #[doc = "0x1b - Set Enable Request Register"] - pub serq: SERQ, - #[doc = "0x1c - Clear DONE Status Bit Register"] - pub cdne: CDNE, - #[doc = "0x1d - Set START Bit Register"] - pub ssrt: SSRT, - #[doc = "0x1e - Clear Error Register"] - pub cerr: CERR, - #[doc = "0x1f - Clear Interrupt Request Register"] - pub cint: CINT, + #[doc = "0x14 - Enable Error Interrupt Register"] pub eei: EEI, + #[doc = "0x18 - Clear Enable Error Interrupt Register"] pub ceei: CEEI, + #[doc = "0x19 - Set Enable Error Interrupt Register"] pub seei: SEEI, + #[doc = "0x1a - Clear Enable Request Register"] pub cerq: CERQ, + #[doc = "0x1b - Set Enable Request Register"] pub serq: SERQ, + #[doc = "0x1c - Clear DONE Status Bit Register"] pub cdne: CDNE, + #[doc = "0x1d - Set START Bit Register"] pub ssrt: SSRT, + #[doc = "0x1e - Clear Error Register"] pub cerr: CERR, + #[doc = "0x1f - Clear Interrupt Request Register"] pub cint: CINT, _reserved2: [u8; 4usize], - #[doc = "0x24 - Interrupt Request Register"] - pub int: INT, + #[doc = "0x24 - Interrupt Request Register"] pub int: INT, _reserved3: [u8; 4usize], - #[doc = "0x2c - Error Register"] - pub err: ERR, + #[doc = "0x2c - Error Register"] pub err: ERR, _reserved4: [u8; 4usize], - #[doc = "0x34 - Hardware Request Status Register"] - pub hrs: HRS, + #[doc = "0x34 - Hardware Request Status Register"] pub hrs: HRS, _reserved5: [u8; 12usize], - #[doc = "0x44 - Enable Asynchronous Request in Stop Register"] - pub ears: EARS, + #[doc = "0x44 - Enable Asynchronous Request in Stop Register"] pub ears: EARS, _reserved6: [u8; 184usize], - #[doc = "0x100 - Channel n Priority Register"] - pub dchpri3: DCHPRI3, - #[doc = "0x101 - Channel n Priority Register"] - pub dchpri2: DCHPRI2, - #[doc = "0x102 - Channel n Priority Register"] - pub dchpri1: DCHPRI1, - #[doc = "0x103 - Channel n Priority Register"] - pub dchpri0: DCHPRI0, - #[doc = "0x104 - Channel n Priority Register"] - pub dchpri7: DCHPRI7, - #[doc = "0x105 - Channel n Priority Register"] - pub dchpri6: DCHPRI6, - #[doc = "0x106 - Channel n Priority Register"] - pub dchpri5: DCHPRI5, - #[doc = "0x107 - Channel n Priority Register"] - pub dchpri4: DCHPRI4, - #[doc = "0x108 - Channel n Priority Register"] - pub dchpri11: DCHPRI11, - #[doc = "0x109 - Channel n Priority Register"] - pub dchpri10: DCHPRI10, - #[doc = "0x10a - Channel n Priority Register"] - pub dchpri9: DCHPRI9, - #[doc = "0x10b - Channel n Priority Register"] - pub dchpri8: DCHPRI8, - #[doc = "0x10c - Channel n Priority Register"] - pub dchpri15: DCHPRI15, - #[doc = "0x10d - Channel n Priority Register"] - pub dchpri14: DCHPRI14, - #[doc = "0x10e - Channel n Priority Register"] - pub dchpri13: DCHPRI13, - #[doc = "0x10f - Channel n Priority Register"] - pub dchpri12: DCHPRI12, + #[doc = "0x100 - Channel n Priority Register"] pub dchpri3: DCHPRI3, + #[doc = "0x101 - Channel n Priority Register"] pub dchpri2: DCHPRI2, + #[doc = "0x102 - Channel n Priority Register"] pub dchpri1: DCHPRI1, + #[doc = "0x103 - Channel n Priority Register"] pub dchpri0: DCHPRI0, + #[doc = "0x104 - Channel n Priority Register"] pub dchpri7: DCHPRI7, + #[doc = "0x105 - Channel n Priority Register"] pub dchpri6: DCHPRI6, + #[doc = "0x106 - Channel n Priority Register"] pub dchpri5: DCHPRI5, + #[doc = "0x107 - Channel n Priority Register"] pub dchpri4: DCHPRI4, + #[doc = "0x108 - Channel n Priority Register"] pub dchpri11: DCHPRI11, + #[doc = "0x109 - Channel n Priority Register"] pub dchpri10: DCHPRI10, + #[doc = "0x10a - Channel n Priority Register"] pub dchpri9: DCHPRI9, + #[doc = "0x10b - Channel n Priority Register"] pub dchpri8: DCHPRI8, + #[doc = "0x10c - Channel n Priority Register"] pub dchpri15: DCHPRI15, + #[doc = "0x10d - Channel n Priority Register"] pub dchpri14: DCHPRI14, + #[doc = "0x10e - Channel n Priority Register"] pub dchpri13: DCHPRI13, + #[doc = "0x10f - Channel n Priority Register"] pub dchpri12: DCHPRI12, _reserved7: [u8; 3824usize], - #[doc = "0x1000 - TCD Source Address"] - pub tcd0_saddr: TCD0_SADDR, - #[doc = "0x1004 - TCD Signed Source Address Offset"] - pub tcd0_soff: TCD0_SOFF, - #[doc = "0x1006 - TCD Transfer Attributes"] - pub tcd0_attr: TCD0_ATTR, + #[doc = "0x1000 - TCD Source Address"] pub tcd0_saddr: TCD0_SADDR, + #[doc = "0x1004 - TCD Signed Source Address Offset"] pub tcd0_soff: TCD0_SOFF, + #[doc = "0x1006 - TCD Transfer Attributes"] pub tcd0_attr: TCD0_ATTR, #[doc = "0x1008 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd0_nbytes_mlno: TCD0_NBYTES_MLNO, - #[doc = "0x100c - TCD Last Source Address Adjustment"] - pub tcd0_slast: TCD0_SLAST, - #[doc = "0x1010 - TCD Destination Address"] - pub tcd0_daddr: TCD0_DADDR, - #[doc = "0x1014 - TCD Signed Destination Address Offset"] - pub tcd0_doff: TCD0_DOFF, + pub tcd0_nbytes_mlno: + TCD0_NBYTES_MLNO, + #[doc = "0x100c - TCD Last Source Address Adjustment"] pub tcd0_slast: TCD0_SLAST, + #[doc = "0x1010 - TCD Destination Address"] pub tcd0_daddr: TCD0_DADDR, + #[doc = "0x1014 - TCD Signed Destination Address Offset"] pub tcd0_doff: TCD0_DOFF, #[doc = "0x1016 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd0_citer_elinkno: TCD0_CITER_ELINKNO, #[doc = "0x1018 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd0_dlastsga: TCD0_DLASTSGA, - #[doc = "0x101c - TCD Control and Status"] - pub tcd0_csr: TCD0_CSR, + #[doc = "0x101c - TCD Control and Status"] pub tcd0_csr: TCD0_CSR, #[doc = "0x101e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd0_biter_elinkno: TCD0_BITER_ELINKNO, - #[doc = "0x1020 - TCD Source Address"] - pub tcd1_saddr: TCD1_SADDR, - #[doc = "0x1024 - TCD Signed Source Address Offset"] - pub tcd1_soff: TCD1_SOFF, - #[doc = "0x1026 - TCD Transfer Attributes"] - pub tcd1_attr: TCD1_ATTR, + #[doc = "0x1020 - TCD Source Address"] pub tcd1_saddr: TCD1_SADDR, + #[doc = "0x1024 - TCD Signed Source Address Offset"] pub tcd1_soff: TCD1_SOFF, + #[doc = "0x1026 - TCD Transfer Attributes"] pub tcd1_attr: TCD1_ATTR, #[doc = "0x1028 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd1_nbytes_mlno: TCD1_NBYTES_MLNO, - #[doc = "0x102c - TCD Last Source Address Adjustment"] - pub tcd1_slast: TCD1_SLAST, - #[doc = "0x1030 - TCD Destination Address"] - pub tcd1_daddr: TCD1_DADDR, - #[doc = "0x1034 - TCD Signed Destination Address Offset"] - pub tcd1_doff: TCD1_DOFF, + pub tcd1_nbytes_mlno: + TCD1_NBYTES_MLNO, + #[doc = "0x102c - TCD Last Source Address Adjustment"] pub tcd1_slast: TCD1_SLAST, + #[doc = "0x1030 - TCD Destination Address"] pub tcd1_daddr: TCD1_DADDR, + #[doc = "0x1034 - TCD Signed Destination Address Offset"] pub tcd1_doff: TCD1_DOFF, #[doc = "0x1036 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd1_citer_elinkno: TCD1_CITER_ELINKNO, #[doc = "0x1038 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd1_dlastsga: TCD1_DLASTSGA, - #[doc = "0x103c - TCD Control and Status"] - pub tcd1_csr: TCD1_CSR, + #[doc = "0x103c - TCD Control and Status"] pub tcd1_csr: TCD1_CSR, #[doc = "0x103e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd1_biter_elinkno: TCD1_BITER_ELINKNO, - #[doc = "0x1040 - TCD Source Address"] - pub tcd2_saddr: TCD2_SADDR, - #[doc = "0x1044 - TCD Signed Source Address Offset"] - pub tcd2_soff: TCD2_SOFF, - #[doc = "0x1046 - TCD Transfer Attributes"] - pub tcd2_attr: TCD2_ATTR, + #[doc = "0x1040 - TCD Source Address"] pub tcd2_saddr: TCD2_SADDR, + #[doc = "0x1044 - TCD Signed Source Address Offset"] pub tcd2_soff: TCD2_SOFF, + #[doc = "0x1046 - TCD Transfer Attributes"] pub tcd2_attr: TCD2_ATTR, #[doc = "0x1048 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd2_nbytes_mlno: TCD2_NBYTES_MLNO, - #[doc = "0x104c - TCD Last Source Address Adjustment"] - pub tcd2_slast: TCD2_SLAST, - #[doc = "0x1050 - TCD Destination Address"] - pub tcd2_daddr: TCD2_DADDR, - #[doc = "0x1054 - TCD Signed Destination Address Offset"] - pub tcd2_doff: TCD2_DOFF, + pub tcd2_nbytes_mlno: + TCD2_NBYTES_MLNO, + #[doc = "0x104c - TCD Last Source Address Adjustment"] pub tcd2_slast: TCD2_SLAST, + #[doc = "0x1050 - TCD Destination Address"] pub tcd2_daddr: TCD2_DADDR, + #[doc = "0x1054 - TCD Signed Destination Address Offset"] pub tcd2_doff: TCD2_DOFF, #[doc = "0x1056 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd2_citer_elinkno: TCD2_CITER_ELINKNO, #[doc = "0x1058 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd2_dlastsga: TCD2_DLASTSGA, - #[doc = "0x105c - TCD Control and Status"] - pub tcd2_csr: TCD2_CSR, + #[doc = "0x105c - TCD Control and Status"] pub tcd2_csr: TCD2_CSR, #[doc = "0x105e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd2_biter_elinkno: TCD2_BITER_ELINKNO, - #[doc = "0x1060 - TCD Source Address"] - pub tcd3_saddr: TCD3_SADDR, - #[doc = "0x1064 - TCD Signed Source Address Offset"] - pub tcd3_soff: TCD3_SOFF, - #[doc = "0x1066 - TCD Transfer Attributes"] - pub tcd3_attr: TCD3_ATTR, + #[doc = "0x1060 - TCD Source Address"] pub tcd3_saddr: TCD3_SADDR, + #[doc = "0x1064 - TCD Signed Source Address Offset"] pub tcd3_soff: TCD3_SOFF, + #[doc = "0x1066 - TCD Transfer Attributes"] pub tcd3_attr: TCD3_ATTR, #[doc = "0x1068 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd3_nbytes_mlno: TCD3_NBYTES_MLNO, - #[doc = "0x106c - TCD Last Source Address Adjustment"] - pub tcd3_slast: TCD3_SLAST, - #[doc = "0x1070 - TCD Destination Address"] - pub tcd3_daddr: TCD3_DADDR, - #[doc = "0x1074 - TCD Signed Destination Address Offset"] - pub tcd3_doff: TCD3_DOFF, + pub tcd3_nbytes_mlno: + TCD3_NBYTES_MLNO, + #[doc = "0x106c - TCD Last Source Address Adjustment"] pub tcd3_slast: TCD3_SLAST, + #[doc = "0x1070 - TCD Destination Address"] pub tcd3_daddr: TCD3_DADDR, + #[doc = "0x1074 - TCD Signed Destination Address Offset"] pub tcd3_doff: TCD3_DOFF, #[doc = "0x1076 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd3_citer_elinkno: TCD3_CITER_ELINKNO, #[doc = "0x1078 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd3_dlastsga: TCD3_DLASTSGA, - #[doc = "0x107c - TCD Control and Status"] - pub tcd3_csr: TCD3_CSR, + #[doc = "0x107c - TCD Control and Status"] pub tcd3_csr: TCD3_CSR, #[doc = "0x107e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd3_biter_elinkno: TCD3_BITER_ELINKNO, - #[doc = "0x1080 - TCD Source Address"] - pub tcd4_saddr: TCD4_SADDR, - #[doc = "0x1084 - TCD Signed Source Address Offset"] - pub tcd4_soff: TCD4_SOFF, - #[doc = "0x1086 - TCD Transfer Attributes"] - pub tcd4_attr: TCD4_ATTR, + #[doc = "0x1080 - TCD Source Address"] pub tcd4_saddr: TCD4_SADDR, + #[doc = "0x1084 - TCD Signed Source Address Offset"] pub tcd4_soff: TCD4_SOFF, + #[doc = "0x1086 - TCD Transfer Attributes"] pub tcd4_attr: TCD4_ATTR, #[doc = "0x1088 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd4_nbytes_mlno: TCD4_NBYTES_MLNO, - #[doc = "0x108c - TCD Last Source Address Adjustment"] - pub tcd4_slast: TCD4_SLAST, - #[doc = "0x1090 - TCD Destination Address"] - pub tcd4_daddr: TCD4_DADDR, - #[doc = "0x1094 - TCD Signed Destination Address Offset"] - pub tcd4_doff: TCD4_DOFF, + pub tcd4_nbytes_mlno: + TCD4_NBYTES_MLNO, + #[doc = "0x108c - TCD Last Source Address Adjustment"] pub tcd4_slast: TCD4_SLAST, + #[doc = "0x1090 - TCD Destination Address"] pub tcd4_daddr: TCD4_DADDR, + #[doc = "0x1094 - TCD Signed Destination Address Offset"] pub tcd4_doff: TCD4_DOFF, #[doc = "0x1096 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd4_citer_elinkno: TCD4_CITER_ELINKNO, #[doc = "0x1098 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd4_dlastsga: TCD4_DLASTSGA, - #[doc = "0x109c - TCD Control and Status"] - pub tcd4_csr: TCD4_CSR, + #[doc = "0x109c - TCD Control and Status"] pub tcd4_csr: TCD4_CSR, #[doc = "0x109e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd4_biter_elinkno: TCD4_BITER_ELINKNO, - #[doc = "0x10a0 - TCD Source Address"] - pub tcd5_saddr: TCD5_SADDR, - #[doc = "0x10a4 - TCD Signed Source Address Offset"] - pub tcd5_soff: TCD5_SOFF, - #[doc = "0x10a6 - TCD Transfer Attributes"] - pub tcd5_attr: TCD5_ATTR, + #[doc = "0x10a0 - TCD Source Address"] pub tcd5_saddr: TCD5_SADDR, + #[doc = "0x10a4 - TCD Signed Source Address Offset"] pub tcd5_soff: TCD5_SOFF, + #[doc = "0x10a6 - TCD Transfer Attributes"] pub tcd5_attr: TCD5_ATTR, #[doc = "0x10a8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd5_nbytes_mlno: TCD5_NBYTES_MLNO, - #[doc = "0x10ac - TCD Last Source Address Adjustment"] - pub tcd5_slast: TCD5_SLAST, - #[doc = "0x10b0 - TCD Destination Address"] - pub tcd5_daddr: TCD5_DADDR, - #[doc = "0x10b4 - TCD Signed Destination Address Offset"] - pub tcd5_doff: TCD5_DOFF, + pub tcd5_nbytes_mlno: + TCD5_NBYTES_MLNO, + #[doc = "0x10ac - TCD Last Source Address Adjustment"] pub tcd5_slast: TCD5_SLAST, + #[doc = "0x10b0 - TCD Destination Address"] pub tcd5_daddr: TCD5_DADDR, + #[doc = "0x10b4 - TCD Signed Destination Address Offset"] pub tcd5_doff: TCD5_DOFF, #[doc = "0x10b6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd5_citer_elinkno: TCD5_CITER_ELINKNO, #[doc = "0x10b8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd5_dlastsga: TCD5_DLASTSGA, - #[doc = "0x10bc - TCD Control and Status"] - pub tcd5_csr: TCD5_CSR, + #[doc = "0x10bc - TCD Control and Status"] pub tcd5_csr: TCD5_CSR, #[doc = "0x10be - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd5_biter_elinkno: TCD5_BITER_ELINKNO, - #[doc = "0x10c0 - TCD Source Address"] - pub tcd6_saddr: TCD6_SADDR, - #[doc = "0x10c4 - TCD Signed Source Address Offset"] - pub tcd6_soff: TCD6_SOFF, - #[doc = "0x10c6 - TCD Transfer Attributes"] - pub tcd6_attr: TCD6_ATTR, + #[doc = "0x10c0 - TCD Source Address"] pub tcd6_saddr: TCD6_SADDR, + #[doc = "0x10c4 - TCD Signed Source Address Offset"] pub tcd6_soff: TCD6_SOFF, + #[doc = "0x10c6 - TCD Transfer Attributes"] pub tcd6_attr: TCD6_ATTR, #[doc = "0x10c8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd6_nbytes_mlno: TCD6_NBYTES_MLNO, - #[doc = "0x10cc - TCD Last Source Address Adjustment"] - pub tcd6_slast: TCD6_SLAST, - #[doc = "0x10d0 - TCD Destination Address"] - pub tcd6_daddr: TCD6_DADDR, - #[doc = "0x10d4 - TCD Signed Destination Address Offset"] - pub tcd6_doff: TCD6_DOFF, + pub tcd6_nbytes_mlno: + TCD6_NBYTES_MLNO, + #[doc = "0x10cc - TCD Last Source Address Adjustment"] pub tcd6_slast: TCD6_SLAST, + #[doc = "0x10d0 - TCD Destination Address"] pub tcd6_daddr: TCD6_DADDR, + #[doc = "0x10d4 - TCD Signed Destination Address Offset"] pub tcd6_doff: TCD6_DOFF, #[doc = "0x10d6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd6_citer_elinkno: TCD6_CITER_ELINKNO, #[doc = "0x10d8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd6_dlastsga: TCD6_DLASTSGA, - #[doc = "0x10dc - TCD Control and Status"] - pub tcd6_csr: TCD6_CSR, + #[doc = "0x10dc - TCD Control and Status"] pub tcd6_csr: TCD6_CSR, #[doc = "0x10de - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd6_biter_elinkno: TCD6_BITER_ELINKNO, - #[doc = "0x10e0 - TCD Source Address"] - pub tcd7_saddr: TCD7_SADDR, - #[doc = "0x10e4 - TCD Signed Source Address Offset"] - pub tcd7_soff: TCD7_SOFF, - #[doc = "0x10e6 - TCD Transfer Attributes"] - pub tcd7_attr: TCD7_ATTR, + #[doc = "0x10e0 - TCD Source Address"] pub tcd7_saddr: TCD7_SADDR, + #[doc = "0x10e4 - TCD Signed Source Address Offset"] pub tcd7_soff: TCD7_SOFF, + #[doc = "0x10e6 - TCD Transfer Attributes"] pub tcd7_attr: TCD7_ATTR, #[doc = "0x10e8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd7_nbytes_mlno: TCD7_NBYTES_MLNO, - #[doc = "0x10ec - TCD Last Source Address Adjustment"] - pub tcd7_slast: TCD7_SLAST, - #[doc = "0x10f0 - TCD Destination Address"] - pub tcd7_daddr: TCD7_DADDR, - #[doc = "0x10f4 - TCD Signed Destination Address Offset"] - pub tcd7_doff: TCD7_DOFF, + pub tcd7_nbytes_mlno: + TCD7_NBYTES_MLNO, + #[doc = "0x10ec - TCD Last Source Address Adjustment"] pub tcd7_slast: TCD7_SLAST, + #[doc = "0x10f0 - TCD Destination Address"] pub tcd7_daddr: TCD7_DADDR, + #[doc = "0x10f4 - TCD Signed Destination Address Offset"] pub tcd7_doff: TCD7_DOFF, #[doc = "0x10f6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd7_citer_elinkno: TCD7_CITER_ELINKNO, #[doc = "0x10f8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd7_dlastsga: TCD7_DLASTSGA, - #[doc = "0x10fc - TCD Control and Status"] - pub tcd7_csr: TCD7_CSR, + #[doc = "0x10fc - TCD Control and Status"] pub tcd7_csr: TCD7_CSR, #[doc = "0x10fe - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd7_biter_elinkno: TCD7_BITER_ELINKNO, - #[doc = "0x1100 - TCD Source Address"] - pub tcd8_saddr: TCD8_SADDR, - #[doc = "0x1104 - TCD Signed Source Address Offset"] - pub tcd8_soff: TCD8_SOFF, - #[doc = "0x1106 - TCD Transfer Attributes"] - pub tcd8_attr: TCD8_ATTR, + #[doc = "0x1100 - TCD Source Address"] pub tcd8_saddr: TCD8_SADDR, + #[doc = "0x1104 - TCD Signed Source Address Offset"] pub tcd8_soff: TCD8_SOFF, + #[doc = "0x1106 - TCD Transfer Attributes"] pub tcd8_attr: TCD8_ATTR, #[doc = "0x1108 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd8_nbytes_mlno: TCD8_NBYTES_MLNO, - #[doc = "0x110c - TCD Last Source Address Adjustment"] - pub tcd8_slast: TCD8_SLAST, - #[doc = "0x1110 - TCD Destination Address"] - pub tcd8_daddr: TCD8_DADDR, - #[doc = "0x1114 - TCD Signed Destination Address Offset"] - pub tcd8_doff: TCD8_DOFF, + pub tcd8_nbytes_mlno: + TCD8_NBYTES_MLNO, + #[doc = "0x110c - TCD Last Source Address Adjustment"] pub tcd8_slast: TCD8_SLAST, + #[doc = "0x1110 - TCD Destination Address"] pub tcd8_daddr: TCD8_DADDR, + #[doc = "0x1114 - TCD Signed Destination Address Offset"] pub tcd8_doff: TCD8_DOFF, #[doc = "0x1116 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd8_citer_elinkno: TCD8_CITER_ELINKNO, #[doc = "0x1118 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd8_dlastsga: TCD8_DLASTSGA, - #[doc = "0x111c - TCD Control and Status"] - pub tcd8_csr: TCD8_CSR, + #[doc = "0x111c - TCD Control and Status"] pub tcd8_csr: TCD8_CSR, #[doc = "0x111e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd8_biter_elinkno: TCD8_BITER_ELINKNO, - #[doc = "0x1120 - TCD Source Address"] - pub tcd9_saddr: TCD9_SADDR, - #[doc = "0x1124 - TCD Signed Source Address Offset"] - pub tcd9_soff: TCD9_SOFF, - #[doc = "0x1126 - TCD Transfer Attributes"] - pub tcd9_attr: TCD9_ATTR, + #[doc = "0x1120 - TCD Source Address"] pub tcd9_saddr: TCD9_SADDR, + #[doc = "0x1124 - TCD Signed Source Address Offset"] pub tcd9_soff: TCD9_SOFF, + #[doc = "0x1126 - TCD Transfer Attributes"] pub tcd9_attr: TCD9_ATTR, #[doc = "0x1128 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd9_nbytes_mlno: TCD9_NBYTES_MLNO, - #[doc = "0x112c - TCD Last Source Address Adjustment"] - pub tcd9_slast: TCD9_SLAST, - #[doc = "0x1130 - TCD Destination Address"] - pub tcd9_daddr: TCD9_DADDR, - #[doc = "0x1134 - TCD Signed Destination Address Offset"] - pub tcd9_doff: TCD9_DOFF, + pub tcd9_nbytes_mlno: + TCD9_NBYTES_MLNO, + #[doc = "0x112c - TCD Last Source Address Adjustment"] pub tcd9_slast: TCD9_SLAST, + #[doc = "0x1130 - TCD Destination Address"] pub tcd9_daddr: TCD9_DADDR, + #[doc = "0x1134 - TCD Signed Destination Address Offset"] pub tcd9_doff: TCD9_DOFF, #[doc = "0x1136 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd9_citer_elinkno: TCD9_CITER_ELINKNO, #[doc = "0x1138 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd9_dlastsga: TCD9_DLASTSGA, - #[doc = "0x113c - TCD Control and Status"] - pub tcd9_csr: TCD9_CSR, + #[doc = "0x113c - TCD Control and Status"] pub tcd9_csr: TCD9_CSR, #[doc = "0x113e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd9_biter_elinkno: TCD9_BITER_ELINKNO, - #[doc = "0x1140 - TCD Source Address"] - pub tcd10_saddr: TCD10_SADDR, - #[doc = "0x1144 - TCD Signed Source Address Offset"] - pub tcd10_soff: TCD10_SOFF, - #[doc = "0x1146 - TCD Transfer Attributes"] - pub tcd10_attr: TCD10_ATTR, + #[doc = "0x1140 - TCD Source Address"] pub tcd10_saddr: TCD10_SADDR, + #[doc = "0x1144 - TCD Signed Source Address Offset"] pub tcd10_soff: TCD10_SOFF, + #[doc = "0x1146 - TCD Transfer Attributes"] pub tcd10_attr: TCD10_ATTR, #[doc = "0x1148 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd10_nbytes_mlno: TCD10_NBYTES_MLNO, - #[doc = "0x114c - TCD Last Source Address Adjustment"] - pub tcd10_slast: TCD10_SLAST, - #[doc = "0x1150 - TCD Destination Address"] - pub tcd10_daddr: TCD10_DADDR, - #[doc = "0x1154 - TCD Signed Destination Address Offset"] - pub tcd10_doff: TCD10_DOFF, + pub tcd10_nbytes_mlno: + TCD10_NBYTES_MLNO, + #[doc = "0x114c - TCD Last Source Address Adjustment"] pub tcd10_slast: TCD10_SLAST, + #[doc = "0x1150 - TCD Destination Address"] pub tcd10_daddr: TCD10_DADDR, + #[doc = "0x1154 - TCD Signed Destination Address Offset"] pub tcd10_doff: TCD10_DOFF, #[doc = "0x1156 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd10_citer_elinkno: TCD10_CITER_ELINKNO, #[doc = "0x1158 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd10_dlastsga: TCD10_DLASTSGA, - #[doc = "0x115c - TCD Control and Status"] - pub tcd10_csr: TCD10_CSR, + #[doc = "0x115c - TCD Control and Status"] pub tcd10_csr: TCD10_CSR, #[doc = "0x115e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd10_biter_elinkno: TCD10_BITER_ELINKNO, - #[doc = "0x1160 - TCD Source Address"] - pub tcd11_saddr: TCD11_SADDR, - #[doc = "0x1164 - TCD Signed Source Address Offset"] - pub tcd11_soff: TCD11_SOFF, - #[doc = "0x1166 - TCD Transfer Attributes"] - pub tcd11_attr: TCD11_ATTR, + #[doc = "0x1160 - TCD Source Address"] pub tcd11_saddr: TCD11_SADDR, + #[doc = "0x1164 - TCD Signed Source Address Offset"] pub tcd11_soff: TCD11_SOFF, + #[doc = "0x1166 - TCD Transfer Attributes"] pub tcd11_attr: TCD11_ATTR, #[doc = "0x1168 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd11_nbytes_mlno: TCD11_NBYTES_MLNO, - #[doc = "0x116c - TCD Last Source Address Adjustment"] - pub tcd11_slast: TCD11_SLAST, - #[doc = "0x1170 - TCD Destination Address"] - pub tcd11_daddr: TCD11_DADDR, - #[doc = "0x1174 - TCD Signed Destination Address Offset"] - pub tcd11_doff: TCD11_DOFF, + pub tcd11_nbytes_mlno: + TCD11_NBYTES_MLNO, + #[doc = "0x116c - TCD Last Source Address Adjustment"] pub tcd11_slast: TCD11_SLAST, + #[doc = "0x1170 - TCD Destination Address"] pub tcd11_daddr: TCD11_DADDR, + #[doc = "0x1174 - TCD Signed Destination Address Offset"] pub tcd11_doff: TCD11_DOFF, #[doc = "0x1176 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd11_citer_elinkno: TCD11_CITER_ELINKNO, #[doc = "0x1178 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd11_dlastsga: TCD11_DLASTSGA, - #[doc = "0x117c - TCD Control and Status"] - pub tcd11_csr: TCD11_CSR, + #[doc = "0x117c - TCD Control and Status"] pub tcd11_csr: TCD11_CSR, #[doc = "0x117e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd11_biter_elinkno: TCD11_BITER_ELINKNO, - #[doc = "0x1180 - TCD Source Address"] - pub tcd12_saddr: TCD12_SADDR, - #[doc = "0x1184 - TCD Signed Source Address Offset"] - pub tcd12_soff: TCD12_SOFF, - #[doc = "0x1186 - TCD Transfer Attributes"] - pub tcd12_attr: TCD12_ATTR, + #[doc = "0x1180 - TCD Source Address"] pub tcd12_saddr: TCD12_SADDR, + #[doc = "0x1184 - TCD Signed Source Address Offset"] pub tcd12_soff: TCD12_SOFF, + #[doc = "0x1186 - TCD Transfer Attributes"] pub tcd12_attr: TCD12_ATTR, #[doc = "0x1188 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd12_nbytes_mlno: TCD12_NBYTES_MLNO, - #[doc = "0x118c - TCD Last Source Address Adjustment"] - pub tcd12_slast: TCD12_SLAST, - #[doc = "0x1190 - TCD Destination Address"] - pub tcd12_daddr: TCD12_DADDR, - #[doc = "0x1194 - TCD Signed Destination Address Offset"] - pub tcd12_doff: TCD12_DOFF, + pub tcd12_nbytes_mlno: + TCD12_NBYTES_MLNO, + #[doc = "0x118c - TCD Last Source Address Adjustment"] pub tcd12_slast: TCD12_SLAST, + #[doc = "0x1190 - TCD Destination Address"] pub tcd12_daddr: TCD12_DADDR, + #[doc = "0x1194 - TCD Signed Destination Address Offset"] pub tcd12_doff: TCD12_DOFF, #[doc = "0x1196 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd12_citer_elinkno: TCD12_CITER_ELINKNO, #[doc = "0x1198 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd12_dlastsga: TCD12_DLASTSGA, - #[doc = "0x119c - TCD Control and Status"] - pub tcd12_csr: TCD12_CSR, + #[doc = "0x119c - TCD Control and Status"] pub tcd12_csr: TCD12_CSR, #[doc = "0x119e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd12_biter_elinkno: TCD12_BITER_ELINKNO, - #[doc = "0x11a0 - TCD Source Address"] - pub tcd13_saddr: TCD13_SADDR, - #[doc = "0x11a4 - TCD Signed Source Address Offset"] - pub tcd13_soff: TCD13_SOFF, - #[doc = "0x11a6 - TCD Transfer Attributes"] - pub tcd13_attr: TCD13_ATTR, + #[doc = "0x11a0 - TCD Source Address"] pub tcd13_saddr: TCD13_SADDR, + #[doc = "0x11a4 - TCD Signed Source Address Offset"] pub tcd13_soff: TCD13_SOFF, + #[doc = "0x11a6 - TCD Transfer Attributes"] pub tcd13_attr: TCD13_ATTR, #[doc = "0x11a8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd13_nbytes_mlno: TCD13_NBYTES_MLNO, - #[doc = "0x11ac - TCD Last Source Address Adjustment"] - pub tcd13_slast: TCD13_SLAST, - #[doc = "0x11b0 - TCD Destination Address"] - pub tcd13_daddr: TCD13_DADDR, - #[doc = "0x11b4 - TCD Signed Destination Address Offset"] - pub tcd13_doff: TCD13_DOFF, + pub tcd13_nbytes_mlno: + TCD13_NBYTES_MLNO, + #[doc = "0x11ac - TCD Last Source Address Adjustment"] pub tcd13_slast: TCD13_SLAST, + #[doc = "0x11b0 - TCD Destination Address"] pub tcd13_daddr: TCD13_DADDR, + #[doc = "0x11b4 - TCD Signed Destination Address Offset"] pub tcd13_doff: TCD13_DOFF, #[doc = "0x11b6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd13_citer_elinkno: TCD13_CITER_ELINKNO, #[doc = "0x11b8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd13_dlastsga: TCD13_DLASTSGA, - #[doc = "0x11bc - TCD Control and Status"] - pub tcd13_csr: TCD13_CSR, + #[doc = "0x11bc - TCD Control and Status"] pub tcd13_csr: TCD13_CSR, #[doc = "0x11be - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd13_biter_elinkno: TCD13_BITER_ELINKNO, - #[doc = "0x11c0 - TCD Source Address"] - pub tcd14_saddr: TCD14_SADDR, - #[doc = "0x11c4 - TCD Signed Source Address Offset"] - pub tcd14_soff: TCD14_SOFF, - #[doc = "0x11c6 - TCD Transfer Attributes"] - pub tcd14_attr: TCD14_ATTR, + #[doc = "0x11c0 - TCD Source Address"] pub tcd14_saddr: TCD14_SADDR, + #[doc = "0x11c4 - TCD Signed Source Address Offset"] pub tcd14_soff: TCD14_SOFF, + #[doc = "0x11c6 - TCD Transfer Attributes"] pub tcd14_attr: TCD14_ATTR, #[doc = "0x11c8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd14_nbytes_mlno: TCD14_NBYTES_MLNO, - #[doc = "0x11cc - TCD Last Source Address Adjustment"] - pub tcd14_slast: TCD14_SLAST, - #[doc = "0x11d0 - TCD Destination Address"] - pub tcd14_daddr: TCD14_DADDR, - #[doc = "0x11d4 - TCD Signed Destination Address Offset"] - pub tcd14_doff: TCD14_DOFF, + pub tcd14_nbytes_mlno: + TCD14_NBYTES_MLNO, + #[doc = "0x11cc - TCD Last Source Address Adjustment"] pub tcd14_slast: TCD14_SLAST, + #[doc = "0x11d0 - TCD Destination Address"] pub tcd14_daddr: TCD14_DADDR, + #[doc = "0x11d4 - TCD Signed Destination Address Offset"] pub tcd14_doff: TCD14_DOFF, #[doc = "0x11d6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd14_citer_elinkno: TCD14_CITER_ELINKNO, #[doc = "0x11d8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd14_dlastsga: TCD14_DLASTSGA, - #[doc = "0x11dc - TCD Control and Status"] - pub tcd14_csr: TCD14_CSR, + #[doc = "0x11dc - TCD Control and Status"] pub tcd14_csr: TCD14_CSR, #[doc = "0x11de - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd14_biter_elinkno: TCD14_BITER_ELINKNO, - #[doc = "0x11e0 - TCD Source Address"] - pub tcd15_saddr: TCD15_SADDR, - #[doc = "0x11e4 - TCD Signed Source Address Offset"] - pub tcd15_soff: TCD15_SOFF, - #[doc = "0x11e6 - TCD Transfer Attributes"] - pub tcd15_attr: TCD15_ATTR, + #[doc = "0x11e0 - TCD Source Address"] pub tcd15_saddr: TCD15_SADDR, + #[doc = "0x11e4 - TCD Signed Source Address Offset"] pub tcd15_soff: TCD15_SOFF, + #[doc = "0x11e6 - TCD Transfer Attributes"] pub tcd15_attr: TCD15_ATTR, #[doc = "0x11e8 - TCD Minor Byte Count (Minor Loop Mapping Disabled)"] - pub tcd15_nbytes_mlno: TCD15_NBYTES_MLNO, - #[doc = "0x11ec - TCD Last Source Address Adjustment"] - pub tcd15_slast: TCD15_SLAST, - #[doc = "0x11f0 - TCD Destination Address"] - pub tcd15_daddr: TCD15_DADDR, - #[doc = "0x11f4 - TCD Signed Destination Address Offset"] - pub tcd15_doff: TCD15_DOFF, + pub tcd15_nbytes_mlno: + TCD15_NBYTES_MLNO, + #[doc = "0x11ec - TCD Last Source Address Adjustment"] pub tcd15_slast: TCD15_SLAST, + #[doc = "0x11f0 - TCD Destination Address"] pub tcd15_daddr: TCD15_DADDR, + #[doc = "0x11f4 - TCD Signed Destination Address Offset"] pub tcd15_doff: TCD15_DOFF, #[doc = "0x11f6 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd15_citer_elinkno: TCD15_CITER_ELINKNO, #[doc = "0x11f8 - TCD Last Destination Address Adjustment/Scatter Gather Address"] pub tcd15_dlastsga: TCD15_DLASTSGA, - #[doc = "0x11fc - TCD Control and Status"] - pub tcd15_csr: TCD15_CSR, + #[doc = "0x11fc - TCD Control and Status"] pub tcd15_csr: TCD15_CSR, #[doc = "0x11fe - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"] pub tcd15_biter_elinkno: TCD15_BITER_ELINKNO, } diff --git a/src/dma/seei/mod.rs b/src/dma/seei/mod.rs index e8a8b0e..5fb8382 100644 --- a/src/dma/seei/mod.rs +++ b/src/dma/seei/mod.rs @@ -54,10 +54,8 @@ impl<'a> _SAEEW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/serq/mod.rs b/src/dma/serq/mod.rs index 0daf3ed..ebcc924 100644 --- a/src/dma/serq/mod.rs +++ b/src/dma/serq/mod.rs @@ -54,10 +54,8 @@ impl<'a> _SAERW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/ssrt/mod.rs b/src/dma/ssrt/mod.rs index f2d03f3..370e6e6 100644 --- a/src/dma/ssrt/mod.rs +++ b/src/dma/ssrt/mod.rs @@ -31,10 +31,8 @@ impl<'a> _SSRTW<'a> { } #[doc = "Values that can be written to the field `SAST`"] pub enum SASTW { - #[doc = "Set only the TCDn_CSR[START] bit specified in the SSRT field"] - _0, - #[doc = "Set all bits in TCDn_CSR[START]"] - _1, + #[doc = "Set only the TCDn_CSR[START] bit specified in the SSRT field"] _0, + #[doc = "Set all bits in TCDn_CSR[START]"] _1, } impl SASTW { #[allow(missing_docs)] @@ -89,10 +87,8 @@ impl<'a> _SASTW<'a> { } #[doc = "Values that can be written to the field `NOP`"] pub enum NOPW { - #[doc = "Normal operation"] - _0, - #[doc = "No operation, ignore the other bits in this register"] - _1, + #[doc = "Normal operation"] _0, + #[doc = "No operation, ignore the other bits in this register"] _1, } impl NOPW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_attr/mod.rs b/src/dma/tcd0_attr/mod.rs index 7f566c1..406c151 100644 --- a/src/dma/tcd0_attr/mod.rs +++ b/src/dma/tcd0_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_biter_elinkno/mod.rs b/src/dma/tcd0_biter_elinkno/mod.rs index e1f26b6..6713a8d 100644 --- a/src/dma/tcd0_biter_elinkno/mod.rs +++ b/src/dma/tcd0_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_biter_elinkyes/mod.rs b/src/dma/tcd0_biter_elinkyes/mod.rs index 6c11111..392b657 100644 --- a/src/dma/tcd0_biter_elinkyes/mod.rs +++ b/src/dma/tcd0_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_citer_elinkno/mod.rs b/src/dma/tcd0_citer_elinkno/mod.rs index 4138240..0ddb105 100644 --- a/src/dma/tcd0_citer_elinkno/mod.rs +++ b/src/dma/tcd0_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_citer_elinkyes/mod.rs b/src/dma/tcd0_citer_elinkyes/mod.rs index 5374a47..4f32490 100644 --- a/src/dma/tcd0_citer_elinkyes/mod.rs +++ b/src/dma/tcd0_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_csr/mod.rs b/src/dma/tcd0_csr/mod.rs index b56c051..9ea031d 100644 --- a/src/dma/tcd0_csr/mod.rs +++ b/src/dma/tcd0_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD0_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_daddr/mod.rs b/src/dma/tcd0_daddr/mod.rs index 35a64b5..c40e1b7 100644 --- a/src/dma/tcd0_daddr/mod.rs +++ b/src/dma/tcd0_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_dlastsga/mod.rs b/src/dma/tcd0_dlastsga/mod.rs index 5791b2b..568f241 100644 --- a/src/dma/tcd0_dlastsga/mod.rs +++ b/src/dma/tcd0_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_doff/mod.rs b/src/dma/tcd0_doff/mod.rs index 87b33f3..376601f 100644 --- a/src/dma/tcd0_doff/mod.rs +++ b/src/dma/tcd0_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_nbytes_mlno/mod.rs b/src/dma/tcd0_nbytes_mlno/mod.rs index dc571ef..da2949c 100644 --- a/src/dma/tcd0_nbytes_mlno/mod.rs +++ b/src/dma/tcd0_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_nbytes_mloffno/mod.rs b/src/dma/tcd0_nbytes_mloffno/mod.rs index 6f68f88..1fed331 100644 --- a/src/dma/tcd0_nbytes_mloffno/mod.rs +++ b/src/dma/tcd0_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_nbytes_mloffyes/mod.rs b/src/dma/tcd0_nbytes_mloffyes/mod.rs index 7daeb24..7548da1 100644 --- a/src/dma/tcd0_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd0_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd0_saddr/mod.rs b/src/dma/tcd0_saddr/mod.rs index 92c7122..ab5e1b5 100644 --- a/src/dma/tcd0_saddr/mod.rs +++ b/src/dma/tcd0_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_slast/mod.rs b/src/dma/tcd0_slast/mod.rs index bae998b..9f7bc80 100644 --- a/src/dma/tcd0_slast/mod.rs +++ b/src/dma/tcd0_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd0_soff/mod.rs b/src/dma/tcd0_soff/mod.rs index 9fda1d2..9c39006 100644 --- a/src/dma/tcd0_soff/mod.rs +++ b/src/dma/tcd0_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD0_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_attr/mod.rs b/src/dma/tcd10_attr/mod.rs index f842980..349542b 100644 --- a/src/dma/tcd10_attr/mod.rs +++ b/src/dma/tcd10_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_biter_elinkno/mod.rs b/src/dma/tcd10_biter_elinkno/mod.rs index 13f7ff1..3cc24ce 100644 --- a/src/dma/tcd10_biter_elinkno/mod.rs +++ b/src/dma/tcd10_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_biter_elinkyes/mod.rs b/src/dma/tcd10_biter_elinkyes/mod.rs index 22ff837..7d21f0f 100644 --- a/src/dma/tcd10_biter_elinkyes/mod.rs +++ b/src/dma/tcd10_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_citer_elinkno/mod.rs b/src/dma/tcd10_citer_elinkno/mod.rs index 17293b1..877fe05 100644 --- a/src/dma/tcd10_citer_elinkno/mod.rs +++ b/src/dma/tcd10_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_citer_elinkyes/mod.rs b/src/dma/tcd10_citer_elinkyes/mod.rs index b1a186e..d5529fd 100644 --- a/src/dma/tcd10_citer_elinkyes/mod.rs +++ b/src/dma/tcd10_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_csr/mod.rs b/src/dma/tcd10_csr/mod.rs index 6154e0f..d6640be 100644 --- a/src/dma/tcd10_csr/mod.rs +++ b/src/dma/tcd10_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD10_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_daddr/mod.rs b/src/dma/tcd10_daddr/mod.rs index 791847e..7fb9983 100644 --- a/src/dma/tcd10_daddr/mod.rs +++ b/src/dma/tcd10_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_dlastsga/mod.rs b/src/dma/tcd10_dlastsga/mod.rs index ddde2ac..2aa37c9 100644 --- a/src/dma/tcd10_dlastsga/mod.rs +++ b/src/dma/tcd10_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_doff/mod.rs b/src/dma/tcd10_doff/mod.rs index a454609..ce612a9 100644 --- a/src/dma/tcd10_doff/mod.rs +++ b/src/dma/tcd10_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_nbytes_mlno/mod.rs b/src/dma/tcd10_nbytes_mlno/mod.rs index 779d02c..666d2c6 100644 --- a/src/dma/tcd10_nbytes_mlno/mod.rs +++ b/src/dma/tcd10_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_nbytes_mloffno/mod.rs b/src/dma/tcd10_nbytes_mloffno/mod.rs index f598bc4..ae14425 100644 --- a/src/dma/tcd10_nbytes_mloffno/mod.rs +++ b/src/dma/tcd10_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_nbytes_mloffyes/mod.rs b/src/dma/tcd10_nbytes_mloffyes/mod.rs index 193f777..a9d3140 100644 --- a/src/dma/tcd10_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd10_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd10_saddr/mod.rs b/src/dma/tcd10_saddr/mod.rs index c868fda..aa9c22b 100644 --- a/src/dma/tcd10_saddr/mod.rs +++ b/src/dma/tcd10_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_slast/mod.rs b/src/dma/tcd10_slast/mod.rs index e5a86fd..2d331a2 100644 --- a/src/dma/tcd10_slast/mod.rs +++ b/src/dma/tcd10_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd10_soff/mod.rs b/src/dma/tcd10_soff/mod.rs index a872558..df0788a 100644 --- a/src/dma/tcd10_soff/mod.rs +++ b/src/dma/tcd10_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD10_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_attr/mod.rs b/src/dma/tcd11_attr/mod.rs index e7b0e7e..34a8207 100644 --- a/src/dma/tcd11_attr/mod.rs +++ b/src/dma/tcd11_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_biter_elinkno/mod.rs b/src/dma/tcd11_biter_elinkno/mod.rs index 2171b40..dfee09b 100644 --- a/src/dma/tcd11_biter_elinkno/mod.rs +++ b/src/dma/tcd11_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_biter_elinkyes/mod.rs b/src/dma/tcd11_biter_elinkyes/mod.rs index d4cc09e..e9a811e 100644 --- a/src/dma/tcd11_biter_elinkyes/mod.rs +++ b/src/dma/tcd11_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_citer_elinkno/mod.rs b/src/dma/tcd11_citer_elinkno/mod.rs index 64a922e..9ac5266 100644 --- a/src/dma/tcd11_citer_elinkno/mod.rs +++ b/src/dma/tcd11_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_citer_elinkyes/mod.rs b/src/dma/tcd11_citer_elinkyes/mod.rs index f967b9e..a0c4942 100644 --- a/src/dma/tcd11_citer_elinkyes/mod.rs +++ b/src/dma/tcd11_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_csr/mod.rs b/src/dma/tcd11_csr/mod.rs index 38896ef..98a2b9b 100644 --- a/src/dma/tcd11_csr/mod.rs +++ b/src/dma/tcd11_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD11_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_daddr/mod.rs b/src/dma/tcd11_daddr/mod.rs index eec4fe7..f464151 100644 --- a/src/dma/tcd11_daddr/mod.rs +++ b/src/dma/tcd11_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_dlastsga/mod.rs b/src/dma/tcd11_dlastsga/mod.rs index e68617a..a20f5df 100644 --- a/src/dma/tcd11_dlastsga/mod.rs +++ b/src/dma/tcd11_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_doff/mod.rs b/src/dma/tcd11_doff/mod.rs index d5455f8..91a33e5 100644 --- a/src/dma/tcd11_doff/mod.rs +++ b/src/dma/tcd11_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_nbytes_mlno/mod.rs b/src/dma/tcd11_nbytes_mlno/mod.rs index 92158ff..fffb26f 100644 --- a/src/dma/tcd11_nbytes_mlno/mod.rs +++ b/src/dma/tcd11_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_nbytes_mloffno/mod.rs b/src/dma/tcd11_nbytes_mloffno/mod.rs index 331fb07..7075b6b 100644 --- a/src/dma/tcd11_nbytes_mloffno/mod.rs +++ b/src/dma/tcd11_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_nbytes_mloffyes/mod.rs b/src/dma/tcd11_nbytes_mloffyes/mod.rs index 641c7f4..cb05604 100644 --- a/src/dma/tcd11_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd11_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd11_saddr/mod.rs b/src/dma/tcd11_saddr/mod.rs index 667f753..3cabc19 100644 --- a/src/dma/tcd11_saddr/mod.rs +++ b/src/dma/tcd11_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_slast/mod.rs b/src/dma/tcd11_slast/mod.rs index 7c04db6..369ae92 100644 --- a/src/dma/tcd11_slast/mod.rs +++ b/src/dma/tcd11_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd11_soff/mod.rs b/src/dma/tcd11_soff/mod.rs index bfc267e..4296626 100644 --- a/src/dma/tcd11_soff/mod.rs +++ b/src/dma/tcd11_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD11_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_attr/mod.rs b/src/dma/tcd12_attr/mod.rs index 4237127..e8e2fbc 100644 --- a/src/dma/tcd12_attr/mod.rs +++ b/src/dma/tcd12_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_biter_elinkno/mod.rs b/src/dma/tcd12_biter_elinkno/mod.rs index c2a5954..ab51220 100644 --- a/src/dma/tcd12_biter_elinkno/mod.rs +++ b/src/dma/tcd12_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_biter_elinkyes/mod.rs b/src/dma/tcd12_biter_elinkyes/mod.rs index 0255336..2edb2fd 100644 --- a/src/dma/tcd12_biter_elinkyes/mod.rs +++ b/src/dma/tcd12_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_citer_elinkno/mod.rs b/src/dma/tcd12_citer_elinkno/mod.rs index 4ee7710..2b405ad 100644 --- a/src/dma/tcd12_citer_elinkno/mod.rs +++ b/src/dma/tcd12_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_citer_elinkyes/mod.rs b/src/dma/tcd12_citer_elinkyes/mod.rs index 1ae88ae..cc121e1 100644 --- a/src/dma/tcd12_citer_elinkyes/mod.rs +++ b/src/dma/tcd12_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_csr/mod.rs b/src/dma/tcd12_csr/mod.rs index 210e325..2bfeb8e 100644 --- a/src/dma/tcd12_csr/mod.rs +++ b/src/dma/tcd12_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD12_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_daddr/mod.rs b/src/dma/tcd12_daddr/mod.rs index f099c78..c277d5b 100644 --- a/src/dma/tcd12_daddr/mod.rs +++ b/src/dma/tcd12_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_dlastsga/mod.rs b/src/dma/tcd12_dlastsga/mod.rs index ceae21d..048679b 100644 --- a/src/dma/tcd12_dlastsga/mod.rs +++ b/src/dma/tcd12_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_doff/mod.rs b/src/dma/tcd12_doff/mod.rs index d759881..29f606d 100644 --- a/src/dma/tcd12_doff/mod.rs +++ b/src/dma/tcd12_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_nbytes_mlno/mod.rs b/src/dma/tcd12_nbytes_mlno/mod.rs index 7405cf9..1eedd09 100644 --- a/src/dma/tcd12_nbytes_mlno/mod.rs +++ b/src/dma/tcd12_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_nbytes_mloffno/mod.rs b/src/dma/tcd12_nbytes_mloffno/mod.rs index 2530ab1..6f2d646 100644 --- a/src/dma/tcd12_nbytes_mloffno/mod.rs +++ b/src/dma/tcd12_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_nbytes_mloffyes/mod.rs b/src/dma/tcd12_nbytes_mloffyes/mod.rs index c55aba7..2e9c52d 100644 --- a/src/dma/tcd12_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd12_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd12_saddr/mod.rs b/src/dma/tcd12_saddr/mod.rs index aa4e466..cbbef29 100644 --- a/src/dma/tcd12_saddr/mod.rs +++ b/src/dma/tcd12_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_slast/mod.rs b/src/dma/tcd12_slast/mod.rs index 62d0aad..5bbf711 100644 --- a/src/dma/tcd12_slast/mod.rs +++ b/src/dma/tcd12_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd12_soff/mod.rs b/src/dma/tcd12_soff/mod.rs index a6dc44e..6ea9d33 100644 --- a/src/dma/tcd12_soff/mod.rs +++ b/src/dma/tcd12_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD12_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_attr/mod.rs b/src/dma/tcd13_attr/mod.rs index 1f14db8..7592cab 100644 --- a/src/dma/tcd13_attr/mod.rs +++ b/src/dma/tcd13_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_biter_elinkno/mod.rs b/src/dma/tcd13_biter_elinkno/mod.rs index 36028bc..a1c8b4e 100644 --- a/src/dma/tcd13_biter_elinkno/mod.rs +++ b/src/dma/tcd13_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_biter_elinkyes/mod.rs b/src/dma/tcd13_biter_elinkyes/mod.rs index 0fb8fdb..93a6f05 100644 --- a/src/dma/tcd13_biter_elinkyes/mod.rs +++ b/src/dma/tcd13_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_citer_elinkno/mod.rs b/src/dma/tcd13_citer_elinkno/mod.rs index e4e80ed..62d60d9 100644 --- a/src/dma/tcd13_citer_elinkno/mod.rs +++ b/src/dma/tcd13_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_citer_elinkyes/mod.rs b/src/dma/tcd13_citer_elinkyes/mod.rs index 44c401f..a4809c0 100644 --- a/src/dma/tcd13_citer_elinkyes/mod.rs +++ b/src/dma/tcd13_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_csr/mod.rs b/src/dma/tcd13_csr/mod.rs index 124d654..4353678 100644 --- a/src/dma/tcd13_csr/mod.rs +++ b/src/dma/tcd13_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD13_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_daddr/mod.rs b/src/dma/tcd13_daddr/mod.rs index 559ca9c..bfbee4d 100644 --- a/src/dma/tcd13_daddr/mod.rs +++ b/src/dma/tcd13_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_dlastsga/mod.rs b/src/dma/tcd13_dlastsga/mod.rs index 3013170..7eea584 100644 --- a/src/dma/tcd13_dlastsga/mod.rs +++ b/src/dma/tcd13_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_doff/mod.rs b/src/dma/tcd13_doff/mod.rs index bd5147f..eb1d880 100644 --- a/src/dma/tcd13_doff/mod.rs +++ b/src/dma/tcd13_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_nbytes_mlno/mod.rs b/src/dma/tcd13_nbytes_mlno/mod.rs index e352e87..96893b9 100644 --- a/src/dma/tcd13_nbytes_mlno/mod.rs +++ b/src/dma/tcd13_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_nbytes_mloffno/mod.rs b/src/dma/tcd13_nbytes_mloffno/mod.rs index 30ec818..d25ee11 100644 --- a/src/dma/tcd13_nbytes_mloffno/mod.rs +++ b/src/dma/tcd13_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_nbytes_mloffyes/mod.rs b/src/dma/tcd13_nbytes_mloffyes/mod.rs index b9091bb..9399b55 100644 --- a/src/dma/tcd13_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd13_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd13_saddr/mod.rs b/src/dma/tcd13_saddr/mod.rs index 6cb64a2..2a11fdf 100644 --- a/src/dma/tcd13_saddr/mod.rs +++ b/src/dma/tcd13_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_slast/mod.rs b/src/dma/tcd13_slast/mod.rs index 0d91c38..5206c4f 100644 --- a/src/dma/tcd13_slast/mod.rs +++ b/src/dma/tcd13_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd13_soff/mod.rs b/src/dma/tcd13_soff/mod.rs index ef30297..c2c3638 100644 --- a/src/dma/tcd13_soff/mod.rs +++ b/src/dma/tcd13_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD13_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_attr/mod.rs b/src/dma/tcd14_attr/mod.rs index beb6808..cd19419 100644 --- a/src/dma/tcd14_attr/mod.rs +++ b/src/dma/tcd14_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_biter_elinkno/mod.rs b/src/dma/tcd14_biter_elinkno/mod.rs index b150db8..e1bd79d 100644 --- a/src/dma/tcd14_biter_elinkno/mod.rs +++ b/src/dma/tcd14_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_biter_elinkyes/mod.rs b/src/dma/tcd14_biter_elinkyes/mod.rs index bd3ae99..42eadbf 100644 --- a/src/dma/tcd14_biter_elinkyes/mod.rs +++ b/src/dma/tcd14_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_citer_elinkno/mod.rs b/src/dma/tcd14_citer_elinkno/mod.rs index dd25789..0631210 100644 --- a/src/dma/tcd14_citer_elinkno/mod.rs +++ b/src/dma/tcd14_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_citer_elinkyes/mod.rs b/src/dma/tcd14_citer_elinkyes/mod.rs index a72370f..57f50eb 100644 --- a/src/dma/tcd14_citer_elinkyes/mod.rs +++ b/src/dma/tcd14_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_csr/mod.rs b/src/dma/tcd14_csr/mod.rs index 0b4feb0..dbbe037 100644 --- a/src/dma/tcd14_csr/mod.rs +++ b/src/dma/tcd14_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD14_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_daddr/mod.rs b/src/dma/tcd14_daddr/mod.rs index a0d1ac8..8cdb734 100644 --- a/src/dma/tcd14_daddr/mod.rs +++ b/src/dma/tcd14_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_dlastsga/mod.rs b/src/dma/tcd14_dlastsga/mod.rs index 0e03435..bb35dca 100644 --- a/src/dma/tcd14_dlastsga/mod.rs +++ b/src/dma/tcd14_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_doff/mod.rs b/src/dma/tcd14_doff/mod.rs index c04b428..1c25313 100644 --- a/src/dma/tcd14_doff/mod.rs +++ b/src/dma/tcd14_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_nbytes_mlno/mod.rs b/src/dma/tcd14_nbytes_mlno/mod.rs index f77e772..aeae2e1 100644 --- a/src/dma/tcd14_nbytes_mlno/mod.rs +++ b/src/dma/tcd14_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_nbytes_mloffno/mod.rs b/src/dma/tcd14_nbytes_mloffno/mod.rs index f3b2e00..453f946 100644 --- a/src/dma/tcd14_nbytes_mloffno/mod.rs +++ b/src/dma/tcd14_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_nbytes_mloffyes/mod.rs b/src/dma/tcd14_nbytes_mloffyes/mod.rs index d666b3b..6307776 100644 --- a/src/dma/tcd14_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd14_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd14_saddr/mod.rs b/src/dma/tcd14_saddr/mod.rs index bb949ad..d52639a 100644 --- a/src/dma/tcd14_saddr/mod.rs +++ b/src/dma/tcd14_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_slast/mod.rs b/src/dma/tcd14_slast/mod.rs index 058d4a2..ea4d379 100644 --- a/src/dma/tcd14_slast/mod.rs +++ b/src/dma/tcd14_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd14_soff/mod.rs b/src/dma/tcd14_soff/mod.rs index cbf32bb..6e77555 100644 --- a/src/dma/tcd14_soff/mod.rs +++ b/src/dma/tcd14_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD14_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_attr/mod.rs b/src/dma/tcd15_attr/mod.rs index 3a37f7b..e16ea9c 100644 --- a/src/dma/tcd15_attr/mod.rs +++ b/src/dma/tcd15_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_biter_elinkno/mod.rs b/src/dma/tcd15_biter_elinkno/mod.rs index 6242bf5..313016f 100644 --- a/src/dma/tcd15_biter_elinkno/mod.rs +++ b/src/dma/tcd15_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_biter_elinkyes/mod.rs b/src/dma/tcd15_biter_elinkyes/mod.rs index dc27f67..53402f4 100644 --- a/src/dma/tcd15_biter_elinkyes/mod.rs +++ b/src/dma/tcd15_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_citer_elinkno/mod.rs b/src/dma/tcd15_citer_elinkno/mod.rs index 8ac5686..4077aff 100644 --- a/src/dma/tcd15_citer_elinkno/mod.rs +++ b/src/dma/tcd15_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_citer_elinkyes/mod.rs b/src/dma/tcd15_citer_elinkyes/mod.rs index 07c3a3c..d2526b7 100644 --- a/src/dma/tcd15_citer_elinkyes/mod.rs +++ b/src/dma/tcd15_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_csr/mod.rs b/src/dma/tcd15_csr/mod.rs index 6650ef4..e7556da 100644 --- a/src/dma/tcd15_csr/mod.rs +++ b/src/dma/tcd15_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD15_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_daddr/mod.rs b/src/dma/tcd15_daddr/mod.rs index 4e98529..8e21256 100644 --- a/src/dma/tcd15_daddr/mod.rs +++ b/src/dma/tcd15_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_dlastsga/mod.rs b/src/dma/tcd15_dlastsga/mod.rs index f675dfc..67ab058 100644 --- a/src/dma/tcd15_dlastsga/mod.rs +++ b/src/dma/tcd15_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_doff/mod.rs b/src/dma/tcd15_doff/mod.rs index 47af429..d46bde3 100644 --- a/src/dma/tcd15_doff/mod.rs +++ b/src/dma/tcd15_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_nbytes_mlno/mod.rs b/src/dma/tcd15_nbytes_mlno/mod.rs index 23b420b..6057bc4 100644 --- a/src/dma/tcd15_nbytes_mlno/mod.rs +++ b/src/dma/tcd15_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_nbytes_mloffno/mod.rs b/src/dma/tcd15_nbytes_mloffno/mod.rs index 12ebe0f..f3d9fe9 100644 --- a/src/dma/tcd15_nbytes_mloffno/mod.rs +++ b/src/dma/tcd15_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_nbytes_mloffyes/mod.rs b/src/dma/tcd15_nbytes_mloffyes/mod.rs index 91bc704..e5989e3 100644 --- a/src/dma/tcd15_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd15_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd15_saddr/mod.rs b/src/dma/tcd15_saddr/mod.rs index b35c752..8511acc 100644 --- a/src/dma/tcd15_saddr/mod.rs +++ b/src/dma/tcd15_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_slast/mod.rs b/src/dma/tcd15_slast/mod.rs index 971138f..9d8245e 100644 --- a/src/dma/tcd15_slast/mod.rs +++ b/src/dma/tcd15_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd15_soff/mod.rs b/src/dma/tcd15_soff/mod.rs index e96b231..73ced40 100644 --- a/src/dma/tcd15_soff/mod.rs +++ b/src/dma/tcd15_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD15_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_attr/mod.rs b/src/dma/tcd1_attr/mod.rs index b6f7607..c6d22d4 100644 --- a/src/dma/tcd1_attr/mod.rs +++ b/src/dma/tcd1_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_biter_elinkno/mod.rs b/src/dma/tcd1_biter_elinkno/mod.rs index 0be79c5..d03c561 100644 --- a/src/dma/tcd1_biter_elinkno/mod.rs +++ b/src/dma/tcd1_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_biter_elinkyes/mod.rs b/src/dma/tcd1_biter_elinkyes/mod.rs index 6112b13..88c6ca0 100644 --- a/src/dma/tcd1_biter_elinkyes/mod.rs +++ b/src/dma/tcd1_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_citer_elinkno/mod.rs b/src/dma/tcd1_citer_elinkno/mod.rs index dd7679d..e2a9bbb 100644 --- a/src/dma/tcd1_citer_elinkno/mod.rs +++ b/src/dma/tcd1_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_citer_elinkyes/mod.rs b/src/dma/tcd1_citer_elinkyes/mod.rs index 9fc2ff6..d3d83de 100644 --- a/src/dma/tcd1_citer_elinkyes/mod.rs +++ b/src/dma/tcd1_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_csr/mod.rs b/src/dma/tcd1_csr/mod.rs index fd652ae..305731f 100644 --- a/src/dma/tcd1_csr/mod.rs +++ b/src/dma/tcd1_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD1_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_daddr/mod.rs b/src/dma/tcd1_daddr/mod.rs index c720174..4122050 100644 --- a/src/dma/tcd1_daddr/mod.rs +++ b/src/dma/tcd1_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_dlastsga/mod.rs b/src/dma/tcd1_dlastsga/mod.rs index 77f4977..ec31b6f 100644 --- a/src/dma/tcd1_dlastsga/mod.rs +++ b/src/dma/tcd1_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_doff/mod.rs b/src/dma/tcd1_doff/mod.rs index 208614f..d1d2aa1 100644 --- a/src/dma/tcd1_doff/mod.rs +++ b/src/dma/tcd1_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_nbytes_mlno/mod.rs b/src/dma/tcd1_nbytes_mlno/mod.rs index 4d7f139..4250da5 100644 --- a/src/dma/tcd1_nbytes_mlno/mod.rs +++ b/src/dma/tcd1_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_nbytes_mloffno/mod.rs b/src/dma/tcd1_nbytes_mloffno/mod.rs index 82aabb6..16fe0d9 100644 --- a/src/dma/tcd1_nbytes_mloffno/mod.rs +++ b/src/dma/tcd1_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_nbytes_mloffyes/mod.rs b/src/dma/tcd1_nbytes_mloffyes/mod.rs index 68a3902..6dd8d88 100644 --- a/src/dma/tcd1_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd1_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd1_saddr/mod.rs b/src/dma/tcd1_saddr/mod.rs index 41d1086..cd0555b 100644 --- a/src/dma/tcd1_saddr/mod.rs +++ b/src/dma/tcd1_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_slast/mod.rs b/src/dma/tcd1_slast/mod.rs index c72fb44..2fe3d74 100644 --- a/src/dma/tcd1_slast/mod.rs +++ b/src/dma/tcd1_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd1_soff/mod.rs b/src/dma/tcd1_soff/mod.rs index dd74e4d..973a3cd 100644 --- a/src/dma/tcd1_soff/mod.rs +++ b/src/dma/tcd1_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD1_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_attr/mod.rs b/src/dma/tcd2_attr/mod.rs index 908e521..8c348a5 100644 --- a/src/dma/tcd2_attr/mod.rs +++ b/src/dma/tcd2_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_biter_elinkno/mod.rs b/src/dma/tcd2_biter_elinkno/mod.rs index 0526460..51be44e 100644 --- a/src/dma/tcd2_biter_elinkno/mod.rs +++ b/src/dma/tcd2_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_biter_elinkyes/mod.rs b/src/dma/tcd2_biter_elinkyes/mod.rs index f1a6cc5..d87550e 100644 --- a/src/dma/tcd2_biter_elinkyes/mod.rs +++ b/src/dma/tcd2_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_citer_elinkno/mod.rs b/src/dma/tcd2_citer_elinkno/mod.rs index 0860260..bbfd565 100644 --- a/src/dma/tcd2_citer_elinkno/mod.rs +++ b/src/dma/tcd2_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_citer_elinkyes/mod.rs b/src/dma/tcd2_citer_elinkyes/mod.rs index f37b880..558609d 100644 --- a/src/dma/tcd2_citer_elinkyes/mod.rs +++ b/src/dma/tcd2_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_csr/mod.rs b/src/dma/tcd2_csr/mod.rs index 03b219a..f916e9d 100644 --- a/src/dma/tcd2_csr/mod.rs +++ b/src/dma/tcd2_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD2_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_daddr/mod.rs b/src/dma/tcd2_daddr/mod.rs index 221ec0e..1bd3993 100644 --- a/src/dma/tcd2_daddr/mod.rs +++ b/src/dma/tcd2_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_dlastsga/mod.rs b/src/dma/tcd2_dlastsga/mod.rs index 5cde74d..892f983 100644 --- a/src/dma/tcd2_dlastsga/mod.rs +++ b/src/dma/tcd2_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_doff/mod.rs b/src/dma/tcd2_doff/mod.rs index 7370517..56613c9 100644 --- a/src/dma/tcd2_doff/mod.rs +++ b/src/dma/tcd2_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_nbytes_mlno/mod.rs b/src/dma/tcd2_nbytes_mlno/mod.rs index e8a7655..79489c8 100644 --- a/src/dma/tcd2_nbytes_mlno/mod.rs +++ b/src/dma/tcd2_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_nbytes_mloffno/mod.rs b/src/dma/tcd2_nbytes_mloffno/mod.rs index 7e599e2..91e1a9b 100644 --- a/src/dma/tcd2_nbytes_mloffno/mod.rs +++ b/src/dma/tcd2_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_nbytes_mloffyes/mod.rs b/src/dma/tcd2_nbytes_mloffyes/mod.rs index 05b68fe..6ee5023 100644 --- a/src/dma/tcd2_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd2_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd2_saddr/mod.rs b/src/dma/tcd2_saddr/mod.rs index 16dbdf7..0628b55 100644 --- a/src/dma/tcd2_saddr/mod.rs +++ b/src/dma/tcd2_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_slast/mod.rs b/src/dma/tcd2_slast/mod.rs index d20b82f..2641685 100644 --- a/src/dma/tcd2_slast/mod.rs +++ b/src/dma/tcd2_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd2_soff/mod.rs b/src/dma/tcd2_soff/mod.rs index db667bd..ae5af29 100644 --- a/src/dma/tcd2_soff/mod.rs +++ b/src/dma/tcd2_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD2_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_attr/mod.rs b/src/dma/tcd3_attr/mod.rs index a223bcf..a4d0bc5 100644 --- a/src/dma/tcd3_attr/mod.rs +++ b/src/dma/tcd3_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_biter_elinkno/mod.rs b/src/dma/tcd3_biter_elinkno/mod.rs index abeb6cc..ae1a4b1 100644 --- a/src/dma/tcd3_biter_elinkno/mod.rs +++ b/src/dma/tcd3_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_biter_elinkyes/mod.rs b/src/dma/tcd3_biter_elinkyes/mod.rs index b82e64a..d64a0d5 100644 --- a/src/dma/tcd3_biter_elinkyes/mod.rs +++ b/src/dma/tcd3_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_citer_elinkno/mod.rs b/src/dma/tcd3_citer_elinkno/mod.rs index 5c05cf6..8c54a2c 100644 --- a/src/dma/tcd3_citer_elinkno/mod.rs +++ b/src/dma/tcd3_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_citer_elinkyes/mod.rs b/src/dma/tcd3_citer_elinkyes/mod.rs index 0fe0b04..b17a0c7 100644 --- a/src/dma/tcd3_citer_elinkyes/mod.rs +++ b/src/dma/tcd3_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_csr/mod.rs b/src/dma/tcd3_csr/mod.rs index 2fb2f5b..5a63a44 100644 --- a/src/dma/tcd3_csr/mod.rs +++ b/src/dma/tcd3_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD3_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_daddr/mod.rs b/src/dma/tcd3_daddr/mod.rs index 2f0e1a0..22cef56 100644 --- a/src/dma/tcd3_daddr/mod.rs +++ b/src/dma/tcd3_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_dlastsga/mod.rs b/src/dma/tcd3_dlastsga/mod.rs index 62e18f5..550adb7 100644 --- a/src/dma/tcd3_dlastsga/mod.rs +++ b/src/dma/tcd3_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_doff/mod.rs b/src/dma/tcd3_doff/mod.rs index 697b83e..e4593cc 100644 --- a/src/dma/tcd3_doff/mod.rs +++ b/src/dma/tcd3_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_nbytes_mlno/mod.rs b/src/dma/tcd3_nbytes_mlno/mod.rs index 2eed344..279190e 100644 --- a/src/dma/tcd3_nbytes_mlno/mod.rs +++ b/src/dma/tcd3_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_nbytes_mloffno/mod.rs b/src/dma/tcd3_nbytes_mloffno/mod.rs index 98bdfab..09f57bd 100644 --- a/src/dma/tcd3_nbytes_mloffno/mod.rs +++ b/src/dma/tcd3_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_nbytes_mloffyes/mod.rs b/src/dma/tcd3_nbytes_mloffyes/mod.rs index ec376fb..8bea5a4 100644 --- a/src/dma/tcd3_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd3_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd3_saddr/mod.rs b/src/dma/tcd3_saddr/mod.rs index 82f913a..22aaf4f 100644 --- a/src/dma/tcd3_saddr/mod.rs +++ b/src/dma/tcd3_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_slast/mod.rs b/src/dma/tcd3_slast/mod.rs index d4f21ed..155f307 100644 --- a/src/dma/tcd3_slast/mod.rs +++ b/src/dma/tcd3_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd3_soff/mod.rs b/src/dma/tcd3_soff/mod.rs index d8c3740..06221fb 100644 --- a/src/dma/tcd3_soff/mod.rs +++ b/src/dma/tcd3_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD3_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_attr/mod.rs b/src/dma/tcd4_attr/mod.rs index ac164fb..487d386 100644 --- a/src/dma/tcd4_attr/mod.rs +++ b/src/dma/tcd4_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_biter_elinkno/mod.rs b/src/dma/tcd4_biter_elinkno/mod.rs index 595ab07..b6ef4b2 100644 --- a/src/dma/tcd4_biter_elinkno/mod.rs +++ b/src/dma/tcd4_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_biter_elinkyes/mod.rs b/src/dma/tcd4_biter_elinkyes/mod.rs index 5f57c52..99ac218 100644 --- a/src/dma/tcd4_biter_elinkyes/mod.rs +++ b/src/dma/tcd4_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_citer_elinkno/mod.rs b/src/dma/tcd4_citer_elinkno/mod.rs index 21b12a3..eca417b 100644 --- a/src/dma/tcd4_citer_elinkno/mod.rs +++ b/src/dma/tcd4_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_citer_elinkyes/mod.rs b/src/dma/tcd4_citer_elinkyes/mod.rs index 47db411..657ec4c 100644 --- a/src/dma/tcd4_citer_elinkyes/mod.rs +++ b/src/dma/tcd4_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_csr/mod.rs b/src/dma/tcd4_csr/mod.rs index 6a0b523..e312e60 100644 --- a/src/dma/tcd4_csr/mod.rs +++ b/src/dma/tcd4_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD4_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_daddr/mod.rs b/src/dma/tcd4_daddr/mod.rs index b765d74..4be26da 100644 --- a/src/dma/tcd4_daddr/mod.rs +++ b/src/dma/tcd4_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_dlastsga/mod.rs b/src/dma/tcd4_dlastsga/mod.rs index 9b1d68a..defdb2c 100644 --- a/src/dma/tcd4_dlastsga/mod.rs +++ b/src/dma/tcd4_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_doff/mod.rs b/src/dma/tcd4_doff/mod.rs index 93c8e8d..96908ba 100644 --- a/src/dma/tcd4_doff/mod.rs +++ b/src/dma/tcd4_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_nbytes_mlno/mod.rs b/src/dma/tcd4_nbytes_mlno/mod.rs index 858f9a5..f53d3fc 100644 --- a/src/dma/tcd4_nbytes_mlno/mod.rs +++ b/src/dma/tcd4_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_nbytes_mloffno/mod.rs b/src/dma/tcd4_nbytes_mloffno/mod.rs index 1364607..398be8d 100644 --- a/src/dma/tcd4_nbytes_mloffno/mod.rs +++ b/src/dma/tcd4_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_nbytes_mloffyes/mod.rs b/src/dma/tcd4_nbytes_mloffyes/mod.rs index 97fdaef..13a6eaf 100644 --- a/src/dma/tcd4_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd4_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd4_saddr/mod.rs b/src/dma/tcd4_saddr/mod.rs index e2e91f3..cb053c3 100644 --- a/src/dma/tcd4_saddr/mod.rs +++ b/src/dma/tcd4_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_slast/mod.rs b/src/dma/tcd4_slast/mod.rs index 14ebb2f..2e191cf 100644 --- a/src/dma/tcd4_slast/mod.rs +++ b/src/dma/tcd4_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd4_soff/mod.rs b/src/dma/tcd4_soff/mod.rs index 90ccf23..de13ab5 100644 --- a/src/dma/tcd4_soff/mod.rs +++ b/src/dma/tcd4_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD4_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_attr/mod.rs b/src/dma/tcd5_attr/mod.rs index 7e9d8a2..01d1799 100644 --- a/src/dma/tcd5_attr/mod.rs +++ b/src/dma/tcd5_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_biter_elinkno/mod.rs b/src/dma/tcd5_biter_elinkno/mod.rs index 95837a5..9c49b1f 100644 --- a/src/dma/tcd5_biter_elinkno/mod.rs +++ b/src/dma/tcd5_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_biter_elinkyes/mod.rs b/src/dma/tcd5_biter_elinkyes/mod.rs index 0844c6d..1b58231 100644 --- a/src/dma/tcd5_biter_elinkyes/mod.rs +++ b/src/dma/tcd5_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_citer_elinkno/mod.rs b/src/dma/tcd5_citer_elinkno/mod.rs index 1fda980..aa287f6 100644 --- a/src/dma/tcd5_citer_elinkno/mod.rs +++ b/src/dma/tcd5_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_citer_elinkyes/mod.rs b/src/dma/tcd5_citer_elinkyes/mod.rs index 9725547..e46136e 100644 --- a/src/dma/tcd5_citer_elinkyes/mod.rs +++ b/src/dma/tcd5_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_csr/mod.rs b/src/dma/tcd5_csr/mod.rs index 39a762c..669cf9e 100644 --- a/src/dma/tcd5_csr/mod.rs +++ b/src/dma/tcd5_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD5_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_daddr/mod.rs b/src/dma/tcd5_daddr/mod.rs index 860a10e..3aee344 100644 --- a/src/dma/tcd5_daddr/mod.rs +++ b/src/dma/tcd5_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_dlastsga/mod.rs b/src/dma/tcd5_dlastsga/mod.rs index 91abcc2..4479cdf 100644 --- a/src/dma/tcd5_dlastsga/mod.rs +++ b/src/dma/tcd5_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_doff/mod.rs b/src/dma/tcd5_doff/mod.rs index e16e251..8e47dca 100644 --- a/src/dma/tcd5_doff/mod.rs +++ b/src/dma/tcd5_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_nbytes_mlno/mod.rs b/src/dma/tcd5_nbytes_mlno/mod.rs index fb61d80..f9751ba 100644 --- a/src/dma/tcd5_nbytes_mlno/mod.rs +++ b/src/dma/tcd5_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_nbytes_mloffno/mod.rs b/src/dma/tcd5_nbytes_mloffno/mod.rs index dd41e38..4d24d58 100644 --- a/src/dma/tcd5_nbytes_mloffno/mod.rs +++ b/src/dma/tcd5_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_nbytes_mloffyes/mod.rs b/src/dma/tcd5_nbytes_mloffyes/mod.rs index c8e2a35..9bfeae3 100644 --- a/src/dma/tcd5_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd5_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd5_saddr/mod.rs b/src/dma/tcd5_saddr/mod.rs index 36ec7b1..19745dd 100644 --- a/src/dma/tcd5_saddr/mod.rs +++ b/src/dma/tcd5_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_slast/mod.rs b/src/dma/tcd5_slast/mod.rs index 2316230..3bc67c9 100644 --- a/src/dma/tcd5_slast/mod.rs +++ b/src/dma/tcd5_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd5_soff/mod.rs b/src/dma/tcd5_soff/mod.rs index bf8ef0d..bdb2086 100644 --- a/src/dma/tcd5_soff/mod.rs +++ b/src/dma/tcd5_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD5_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_attr/mod.rs b/src/dma/tcd6_attr/mod.rs index b7f4cc2..faf7fd1 100644 --- a/src/dma/tcd6_attr/mod.rs +++ b/src/dma/tcd6_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_biter_elinkno/mod.rs b/src/dma/tcd6_biter_elinkno/mod.rs index 9d8ac57..a023080 100644 --- a/src/dma/tcd6_biter_elinkno/mod.rs +++ b/src/dma/tcd6_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_biter_elinkyes/mod.rs b/src/dma/tcd6_biter_elinkyes/mod.rs index 17c04a5..f468074 100644 --- a/src/dma/tcd6_biter_elinkyes/mod.rs +++ b/src/dma/tcd6_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_citer_elinkno/mod.rs b/src/dma/tcd6_citer_elinkno/mod.rs index 555aafe..01b5e0c 100644 --- a/src/dma/tcd6_citer_elinkno/mod.rs +++ b/src/dma/tcd6_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_citer_elinkyes/mod.rs b/src/dma/tcd6_citer_elinkyes/mod.rs index 339c991..bc715f8 100644 --- a/src/dma/tcd6_citer_elinkyes/mod.rs +++ b/src/dma/tcd6_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_csr/mod.rs b/src/dma/tcd6_csr/mod.rs index 3b33f42..b26ea53 100644 --- a/src/dma/tcd6_csr/mod.rs +++ b/src/dma/tcd6_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD6_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_daddr/mod.rs b/src/dma/tcd6_daddr/mod.rs index 7e31ee3..2a65efd 100644 --- a/src/dma/tcd6_daddr/mod.rs +++ b/src/dma/tcd6_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_dlastsga/mod.rs b/src/dma/tcd6_dlastsga/mod.rs index 59bace3..4b89df7 100644 --- a/src/dma/tcd6_dlastsga/mod.rs +++ b/src/dma/tcd6_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_doff/mod.rs b/src/dma/tcd6_doff/mod.rs index a9bc051..6bc19da 100644 --- a/src/dma/tcd6_doff/mod.rs +++ b/src/dma/tcd6_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_nbytes_mlno/mod.rs b/src/dma/tcd6_nbytes_mlno/mod.rs index 4a9f01e..2d7e96c 100644 --- a/src/dma/tcd6_nbytes_mlno/mod.rs +++ b/src/dma/tcd6_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_nbytes_mloffno/mod.rs b/src/dma/tcd6_nbytes_mloffno/mod.rs index 0933484..4da1990 100644 --- a/src/dma/tcd6_nbytes_mloffno/mod.rs +++ b/src/dma/tcd6_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_nbytes_mloffyes/mod.rs b/src/dma/tcd6_nbytes_mloffyes/mod.rs index be4a1fb..91c1018 100644 --- a/src/dma/tcd6_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd6_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd6_saddr/mod.rs b/src/dma/tcd6_saddr/mod.rs index fbf6b0a..eda7c15 100644 --- a/src/dma/tcd6_saddr/mod.rs +++ b/src/dma/tcd6_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_slast/mod.rs b/src/dma/tcd6_slast/mod.rs index 7807d00..cd8ab29 100644 --- a/src/dma/tcd6_slast/mod.rs +++ b/src/dma/tcd6_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd6_soff/mod.rs b/src/dma/tcd6_soff/mod.rs index b2a6699..fb3be28 100644 --- a/src/dma/tcd6_soff/mod.rs +++ b/src/dma/tcd6_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD6_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_attr/mod.rs b/src/dma/tcd7_attr/mod.rs index a3fd391..4f06cfb 100644 --- a/src/dma/tcd7_attr/mod.rs +++ b/src/dma/tcd7_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_biter_elinkno/mod.rs b/src/dma/tcd7_biter_elinkno/mod.rs index 1b5c9b6..b5cc83f 100644 --- a/src/dma/tcd7_biter_elinkno/mod.rs +++ b/src/dma/tcd7_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_biter_elinkyes/mod.rs b/src/dma/tcd7_biter_elinkyes/mod.rs index 8591825..cf392ae 100644 --- a/src/dma/tcd7_biter_elinkyes/mod.rs +++ b/src/dma/tcd7_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_citer_elinkno/mod.rs b/src/dma/tcd7_citer_elinkno/mod.rs index 10913e9..da87f5c 100644 --- a/src/dma/tcd7_citer_elinkno/mod.rs +++ b/src/dma/tcd7_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_citer_elinkyes/mod.rs b/src/dma/tcd7_citer_elinkyes/mod.rs index e4c0e70..e9dca66 100644 --- a/src/dma/tcd7_citer_elinkyes/mod.rs +++ b/src/dma/tcd7_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_csr/mod.rs b/src/dma/tcd7_csr/mod.rs index bc2aa83..688f33a 100644 --- a/src/dma/tcd7_csr/mod.rs +++ b/src/dma/tcd7_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD7_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_daddr/mod.rs b/src/dma/tcd7_daddr/mod.rs index 5e565bd..64592e2 100644 --- a/src/dma/tcd7_daddr/mod.rs +++ b/src/dma/tcd7_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_dlastsga/mod.rs b/src/dma/tcd7_dlastsga/mod.rs index 301db92..2410676 100644 --- a/src/dma/tcd7_dlastsga/mod.rs +++ b/src/dma/tcd7_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_doff/mod.rs b/src/dma/tcd7_doff/mod.rs index 940d0db..030d1cf 100644 --- a/src/dma/tcd7_doff/mod.rs +++ b/src/dma/tcd7_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_nbytes_mlno/mod.rs b/src/dma/tcd7_nbytes_mlno/mod.rs index 1839a20..d60c973 100644 --- a/src/dma/tcd7_nbytes_mlno/mod.rs +++ b/src/dma/tcd7_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_nbytes_mloffno/mod.rs b/src/dma/tcd7_nbytes_mloffno/mod.rs index 9ab9975..e4a6457 100644 --- a/src/dma/tcd7_nbytes_mloffno/mod.rs +++ b/src/dma/tcd7_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_nbytes_mloffyes/mod.rs b/src/dma/tcd7_nbytes_mloffyes/mod.rs index baa8794..728f3c8 100644 --- a/src/dma/tcd7_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd7_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd7_saddr/mod.rs b/src/dma/tcd7_saddr/mod.rs index cf2ea9a..9cab50c 100644 --- a/src/dma/tcd7_saddr/mod.rs +++ b/src/dma/tcd7_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_slast/mod.rs b/src/dma/tcd7_slast/mod.rs index d4981fd..90c9a78 100644 --- a/src/dma/tcd7_slast/mod.rs +++ b/src/dma/tcd7_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd7_soff/mod.rs b/src/dma/tcd7_soff/mod.rs index cfab57a..213f533 100644 --- a/src/dma/tcd7_soff/mod.rs +++ b/src/dma/tcd7_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD7_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_attr/mod.rs b/src/dma/tcd8_attr/mod.rs index 5b9fadd..a92eb89 100644 --- a/src/dma/tcd8_attr/mod.rs +++ b/src/dma/tcd8_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_biter_elinkno/mod.rs b/src/dma/tcd8_biter_elinkno/mod.rs index 5b4b7cb..7006e8a 100644 --- a/src/dma/tcd8_biter_elinkno/mod.rs +++ b/src/dma/tcd8_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_biter_elinkyes/mod.rs b/src/dma/tcd8_biter_elinkyes/mod.rs index ad1f623..d2bce42 100644 --- a/src/dma/tcd8_biter_elinkyes/mod.rs +++ b/src/dma/tcd8_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_citer_elinkno/mod.rs b/src/dma/tcd8_citer_elinkno/mod.rs index 40afc1e..a5a567b 100644 --- a/src/dma/tcd8_citer_elinkno/mod.rs +++ b/src/dma/tcd8_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_citer_elinkyes/mod.rs b/src/dma/tcd8_citer_elinkyes/mod.rs index dc29896..79eb209 100644 --- a/src/dma/tcd8_citer_elinkyes/mod.rs +++ b/src/dma/tcd8_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_csr/mod.rs b/src/dma/tcd8_csr/mod.rs index dcf9e56..8978db1 100644 --- a/src/dma/tcd8_csr/mod.rs +++ b/src/dma/tcd8_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD8_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_daddr/mod.rs b/src/dma/tcd8_daddr/mod.rs index 39301c6..7192bf1 100644 --- a/src/dma/tcd8_daddr/mod.rs +++ b/src/dma/tcd8_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_dlastsga/mod.rs b/src/dma/tcd8_dlastsga/mod.rs index ab4e8e2..8095387 100644 --- a/src/dma/tcd8_dlastsga/mod.rs +++ b/src/dma/tcd8_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_doff/mod.rs b/src/dma/tcd8_doff/mod.rs index a1b15af..d4c1fa3 100644 --- a/src/dma/tcd8_doff/mod.rs +++ b/src/dma/tcd8_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_nbytes_mlno/mod.rs b/src/dma/tcd8_nbytes_mlno/mod.rs index 48c80c1..f7627de 100644 --- a/src/dma/tcd8_nbytes_mlno/mod.rs +++ b/src/dma/tcd8_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_nbytes_mloffno/mod.rs b/src/dma/tcd8_nbytes_mloffno/mod.rs index 8cbe295..69fa57e 100644 --- a/src/dma/tcd8_nbytes_mloffno/mod.rs +++ b/src/dma/tcd8_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_nbytes_mloffyes/mod.rs b/src/dma/tcd8_nbytes_mloffyes/mod.rs index 0afb652..5adcd8d 100644 --- a/src/dma/tcd8_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd8_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd8_saddr/mod.rs b/src/dma/tcd8_saddr/mod.rs index 84a5abe..53e953a 100644 --- a/src/dma/tcd8_saddr/mod.rs +++ b/src/dma/tcd8_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_slast/mod.rs b/src/dma/tcd8_slast/mod.rs index 7163c3c..51ccd3f 100644 --- a/src/dma/tcd8_slast/mod.rs +++ b/src/dma/tcd8_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd8_soff/mod.rs b/src/dma/tcd8_soff/mod.rs index 3f7fc93..f4ae7fa 100644 --- a/src/dma/tcd8_soff/mod.rs +++ b/src/dma/tcd8_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD8_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_attr/mod.rs b/src/dma/tcd9_attr/mod.rs index daec273..299c062 100644 --- a/src/dma/tcd9_attr/mod.rs +++ b/src/dma/tcd9_attr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_ATTR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,14 +67,10 @@ impl DMODR { #[doc = "Possible values of the field `SSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSIZER { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl SSIZER { #[doc = r" Value of the field as raw bits"] @@ -115,10 +113,8 @@ impl SSIZER { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Source address modulo feature is disabled"] - _0, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Source address modulo feature is disabled"] _0, + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -176,12 +172,9 @@ impl<'a> _DMODW<'a> { } #[doc = "Values that can be written to the field `SSIZE`"] pub enum SSIZEW { - #[doc = "8-bit"] - _0, - #[doc = "16-bit"] - _1, - #[doc = "32-bit"] - _10, + #[doc = "8-bit"] _0, + #[doc = "16-bit"] _1, + #[doc = "32-bit"] _10, } impl SSIZEW { #[allow(missing_docs)] @@ -232,8 +225,7 @@ impl<'a> _SSIZEW<'a> { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Source address modulo feature is disabled"] - _0, + #[doc = "Source address modulo feature is disabled"] _0, } impl SMODW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_biter_elinkno/mod.rs b/src/dma/tcd9_biter_elinkno/mod.rs index 2c513a1..a0fd169 100644 --- a/src/dma/tcd9_biter_elinkno/mod.rs +++ b/src/dma/tcd9_biter_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_BITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl BITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _BITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_biter_elinkyes/mod.rs b/src/dma/tcd9_biter_elinkyes/mod.rs index 4c59675..e241219 100644 --- a/src/dma/tcd9_biter_elinkyes/mod.rs +++ b/src/dma/tcd9_biter_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_BITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_citer_elinkno/mod.rs b/src/dma/tcd9_citer_elinkno/mod.rs index dc5f646..0ff10bf 100644 --- a/src/dma/tcd9_citer_elinkno/mod.rs +++ b/src/dma/tcd9_citer_elinkno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_CITER_ELINKNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CITERR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _CITERW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_citer_elinkyes/mod.rs b/src/dma/tcd9_citer_elinkyes/mod.rs index 498bf2f..08a6beb 100644 --- a/src/dma/tcd9_citer_elinkyes/mod.rs +++ b/src/dma/tcd9_citer_elinkyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_CITER_ELINKYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl LINKCHR { #[doc = "Possible values of the field `ELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELINKR { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -141,10 +141,8 @@ impl<'a> _LINKCHW<'a> { } #[doc = "Values that can be written to the field `ELINK`"] pub enum ELINKW { - #[doc = "The channel-to-channel linking is disabled"] - _0, - #[doc = "The channel-to-channel linking is enabled"] - _1, + #[doc = "The channel-to-channel linking is disabled"] _0, + #[doc = "The channel-to-channel linking is enabled"] _1, } impl ELINKW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_csr/mod.rs b/src/dma/tcd9_csr/mod.rs index 4f3538b..dfdbd17 100644 --- a/src/dma/tcd9_csr/mod.rs +++ b/src/dma/tcd9_csr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCD9_CSR { #[doc = "Possible values of the field `START`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STARTR { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STARTR { #[doc = "Possible values of the field `INTMAJOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTMAJORR { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INTMAJORR { #[doc = "Possible values of the field `INTHALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTHALFR { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -205,8 +201,7 @@ impl DREQR { #[doc = "Possible values of the field `ESG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESGR { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -252,10 +247,8 @@ impl ESGR { #[doc = "Possible values of the field `MAJORELINK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAJORELINKR { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -352,14 +345,10 @@ impl MAJORLINKCHR { #[doc = "Possible values of the field `BWC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BWCR { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl BWCR { #[doc = r" Value of the field as raw bits"] @@ -401,10 +390,8 @@ impl BWCR { } #[doc = "Values that can be written to the field `START`"] pub enum STARTW { - #[doc = "The channel is not explicitly started."] - _0, - #[doc = "The channel is explicitly started via a software initiated service request."] - _1, + #[doc = "The channel is not explicitly started."] _0, + #[doc = "The channel is explicitly started via a software initiated service request."] _1, } impl STARTW { #[allow(missing_docs)] @@ -459,10 +446,8 @@ impl<'a> _STARTW<'a> { } #[doc = "Values that can be written to the field `INTMAJOR`"] pub enum INTMAJORW { - #[doc = "The end-of-major loop interrupt is disabled."] - _0, - #[doc = "The end-of-major loop interrupt is enabled."] - _1, + #[doc = "The end-of-major loop interrupt is disabled."] _0, + #[doc = "The end-of-major loop interrupt is enabled."] _1, } impl INTMAJORW { #[allow(missing_docs)] @@ -517,10 +502,8 @@ impl<'a> _INTMAJORW<'a> { } #[doc = "Values that can be written to the field `INTHALF`"] pub enum INTHALFW { - #[doc = "The half-point interrupt is disabled."] - _0, - #[doc = "The half-point interrupt is enabled."] - _1, + #[doc = "The half-point interrupt is disabled."] _0, + #[doc = "The half-point interrupt is enabled."] _1, } impl INTHALFW { #[allow(missing_docs)] @@ -598,8 +581,7 @@ impl<'a> _DREQW<'a> { } #[doc = "Values that can be written to the field `ESG`"] pub enum ESGW { - #[doc = "The current channel's TCD is normal format."] - _0, + #[doc = "The current channel's TCD is normal format."] _0, #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."] _1, } @@ -656,10 +638,8 @@ impl<'a> _ESGW<'a> { } #[doc = "Values that can be written to the field `MAJORELINK`"] pub enum MAJORELINKW { - #[doc = "The channel-to-channel linking is disabled."] - _0, - #[doc = "The channel-to-channel linking is enabled."] - _1, + #[doc = "The channel-to-channel linking is disabled."] _0, + #[doc = "The channel-to-channel linking is enabled."] _1, } impl MAJORELINKW { #[allow(missing_docs)] @@ -775,12 +755,9 @@ impl<'a> _MAJORLINKCHW<'a> { } #[doc = "Values that can be written to the field `BWC`"] pub enum BWCW { - #[doc = "No eDMA engine stalls."] - _0, - #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - _10, - #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - _11, + #[doc = "No eDMA engine stalls."] _0, + #[doc = "eDMA engine stalls for 4 cycles after each R/W."] _10, + #[doc = "eDMA engine stalls for 8 cycles after each R/W."] _11, } impl BWCW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_daddr/mod.rs b/src/dma/tcd9_daddr/mod.rs index fbd88e6..f710ee2 100644 --- a/src/dma/tcd9_daddr/mod.rs +++ b/src/dma/tcd9_daddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_DADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_dlastsga/mod.rs b/src/dma/tcd9_dlastsga/mod.rs index 1810ca3..79628a7 100644 --- a/src/dma/tcd9_dlastsga/mod.rs +++ b/src/dma/tcd9_dlastsga/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_DLASTSGA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_doff/mod.rs b/src/dma/tcd9_doff/mod.rs index 80e63d4..7a8e6d2 100644 --- a/src/dma/tcd9_doff/mod.rs +++ b/src/dma/tcd9_doff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_DOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_nbytes_mlno/mod.rs b/src/dma/tcd9_nbytes_mlno/mod.rs index 02d8cb8..a64ad6b 100644 --- a/src/dma/tcd9_nbytes_mlno/mod.rs +++ b/src/dma/tcd9_nbytes_mlno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_NBYTES_MLNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_nbytes_mloffno/mod.rs b/src/dma/tcd9_nbytes_mloffno/mod.rs index 29b06bf..520a5c0 100644 --- a/src/dma/tcd9_nbytes_mloffno/mod.rs +++ b/src/dma/tcd9_nbytes_mloffno/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_NBYTES_MLOFFNO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl NBYTESR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -162,10 +160,8 @@ impl<'a> _NBYTESW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -220,10 +216,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_nbytes_mloffyes/mod.rs b/src/dma/tcd9_nbytes_mloffyes/mod.rs index c6d5529..d03ca0b 100644 --- a/src/dma/tcd9_nbytes_mloffyes/mod.rs +++ b/src/dma/tcd9_nbytes_mloffyes/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_NBYTES_MLOFFYES { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,10 +67,8 @@ impl MLOFFR { #[doc = "Possible values of the field `DMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMLOER { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -112,10 +112,8 @@ impl DMLOER { #[doc = "Possible values of the field `SMLOE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMLOER { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -188,10 +186,8 @@ impl<'a> _MLOFFW<'a> { } #[doc = "Values that can be written to the field `DMLOE`"] pub enum DMLOEW { - #[doc = "The minor loop offset is not applied to the DADDR"] - _0, - #[doc = "The minor loop offset is applied to the DADDR"] - _1, + #[doc = "The minor loop offset is not applied to the DADDR"] _0, + #[doc = "The minor loop offset is applied to the DADDR"] _1, } impl DMLOEW { #[allow(missing_docs)] @@ -246,10 +242,8 @@ impl<'a> _DMLOEW<'a> { } #[doc = "Values that can be written to the field `SMLOE`"] pub enum SMLOEW { - #[doc = "The minor loop offset is not applied to the SADDR"] - _0, - #[doc = "The minor loop offset is applied to the SADDR"] - _1, + #[doc = "The minor loop offset is not applied to the SADDR"] _0, + #[doc = "The minor loop offset is applied to the SADDR"] _1, } impl SMLOEW { #[allow(missing_docs)] diff --git a/src/dma/tcd9_saddr/mod.rs b/src/dma/tcd9_saddr/mod.rs index 38b5392..fc546cf 100644 --- a/src/dma/tcd9_saddr/mod.rs +++ b/src/dma/tcd9_saddr/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_SADDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_slast/mod.rs b/src/dma/tcd9_slast/mod.rs index bcbd09f..2adc374 100644 --- a/src/dma/tcd9_slast/mod.rs +++ b/src/dma/tcd9_slast/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_SLAST { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dma/tcd9_soff/mod.rs b/src/dma/tcd9_soff/mod.rs index 48f98c6..7f70ca8 100644 --- a/src/dma/tcd9_soff/mod.rs +++ b/src/dma/tcd9_soff/mod.rs @@ -22,7 +22,9 @@ impl super::TCD9_SOFF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/dmamux/chcfg0/mod.rs b/src/dmamux/chcfg0/mod.rs index d2a715a..f9f3f82 100644 --- a/src/dmamux/chcfg0/mod.rs +++ b/src/dmamux/chcfg0/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg1/mod.rs b/src/dmamux/chcfg1/mod.rs index 8bed2da..06b20fa 100644 --- a/src/dmamux/chcfg1/mod.rs +++ b/src/dmamux/chcfg1/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg10/mod.rs b/src/dmamux/chcfg10/mod.rs index 1552b44..13be465 100644 --- a/src/dmamux/chcfg10/mod.rs +++ b/src/dmamux/chcfg10/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg11/mod.rs b/src/dmamux/chcfg11/mod.rs index 3ff1437..793b184 100644 --- a/src/dmamux/chcfg11/mod.rs +++ b/src/dmamux/chcfg11/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg12/mod.rs b/src/dmamux/chcfg12/mod.rs index e29531e..4170d64 100644 --- a/src/dmamux/chcfg12/mod.rs +++ b/src/dmamux/chcfg12/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg13/mod.rs b/src/dmamux/chcfg13/mod.rs index 7924d75..cf6f630 100644 --- a/src/dmamux/chcfg13/mod.rs +++ b/src/dmamux/chcfg13/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg14/mod.rs b/src/dmamux/chcfg14/mod.rs index ccccc58..22be284 100644 --- a/src/dmamux/chcfg14/mod.rs +++ b/src/dmamux/chcfg14/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg15/mod.rs b/src/dmamux/chcfg15/mod.rs index 07d078f..10d548d 100644 --- a/src/dmamux/chcfg15/mod.rs +++ b/src/dmamux/chcfg15/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg2/mod.rs b/src/dmamux/chcfg2/mod.rs index e066e99..95f5063 100644 --- a/src/dmamux/chcfg2/mod.rs +++ b/src/dmamux/chcfg2/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg3/mod.rs b/src/dmamux/chcfg3/mod.rs index 1104a5f..088df26 100644 --- a/src/dmamux/chcfg3/mod.rs +++ b/src/dmamux/chcfg3/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg4/mod.rs b/src/dmamux/chcfg4/mod.rs index e791bcc..8af782f 100644 --- a/src/dmamux/chcfg4/mod.rs +++ b/src/dmamux/chcfg4/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg5/mod.rs b/src/dmamux/chcfg5/mod.rs index 5bace2d..79d2d2e 100644 --- a/src/dmamux/chcfg5/mod.rs +++ b/src/dmamux/chcfg5/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg6/mod.rs b/src/dmamux/chcfg6/mod.rs index 0d6bf25..bc26ae3 100644 --- a/src/dmamux/chcfg6/mod.rs +++ b/src/dmamux/chcfg6/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg7/mod.rs b/src/dmamux/chcfg7/mod.rs index 9af3017..abc8d3f 100644 --- a/src/dmamux/chcfg7/mod.rs +++ b/src/dmamux/chcfg7/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg8/mod.rs b/src/dmamux/chcfg8/mod.rs index 4182236..1e0d06c 100644 --- a/src/dmamux/chcfg8/mod.rs +++ b/src/dmamux/chcfg8/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/chcfg9/mod.rs b/src/dmamux/chcfg9/mod.rs index 60df8ae..82a07e6 100644 --- a/src/dmamux/chcfg9/mod.rs +++ b/src/dmamux/chcfg9/mod.rs @@ -22,7 +22,9 @@ impl super::CHCFG9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -103,8 +105,7 @@ impl TRIGR { pub enum ENBLR { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -222,8 +223,7 @@ impl<'a> _TRIGW<'a> { pub enum ENBLW { #[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."] _0, - #[doc = "DMA channel is enabled"] - _1, + #[doc = "DMA channel is enabled"] _1, } impl ENBLW { #[allow(missing_docs)] diff --git a/src/dmamux/mod.rs b/src/dmamux/mod.rs index b87a68c..9664f0a 100644 --- a/src/dmamux/mod.rs +++ b/src/dmamux/mod.rs @@ -2,38 +2,22 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Channel Configuration register"] - pub chcfg0: CHCFG0, - #[doc = "0x01 - Channel Configuration register"] - pub chcfg1: CHCFG1, - #[doc = "0x02 - Channel Configuration register"] - pub chcfg2: CHCFG2, - #[doc = "0x03 - Channel Configuration register"] - pub chcfg3: CHCFG3, - #[doc = "0x04 - Channel Configuration register"] - pub chcfg4: CHCFG4, - #[doc = "0x05 - Channel Configuration register"] - pub chcfg5: CHCFG5, - #[doc = "0x06 - Channel Configuration register"] - pub chcfg6: CHCFG6, - #[doc = "0x07 - Channel Configuration register"] - pub chcfg7: CHCFG7, - #[doc = "0x08 - Channel Configuration register"] - pub chcfg8: CHCFG8, - #[doc = "0x09 - Channel Configuration register"] - pub chcfg9: CHCFG9, - #[doc = "0x0a - Channel Configuration register"] - pub chcfg10: CHCFG10, - #[doc = "0x0b - Channel Configuration register"] - pub chcfg11: CHCFG11, - #[doc = "0x0c - Channel Configuration register"] - pub chcfg12: CHCFG12, - #[doc = "0x0d - Channel Configuration register"] - pub chcfg13: CHCFG13, - #[doc = "0x0e - Channel Configuration register"] - pub chcfg14: CHCFG14, - #[doc = "0x0f - Channel Configuration register"] - pub chcfg15: CHCFG15, + #[doc = "0x00 - Channel Configuration register"] pub chcfg0: CHCFG0, + #[doc = "0x01 - Channel Configuration register"] pub chcfg1: CHCFG1, + #[doc = "0x02 - Channel Configuration register"] pub chcfg2: CHCFG2, + #[doc = "0x03 - Channel Configuration register"] pub chcfg3: CHCFG3, + #[doc = "0x04 - Channel Configuration register"] pub chcfg4: CHCFG4, + #[doc = "0x05 - Channel Configuration register"] pub chcfg5: CHCFG5, + #[doc = "0x06 - Channel Configuration register"] pub chcfg6: CHCFG6, + #[doc = "0x07 - Channel Configuration register"] pub chcfg7: CHCFG7, + #[doc = "0x08 - Channel Configuration register"] pub chcfg8: CHCFG8, + #[doc = "0x09 - Channel Configuration register"] pub chcfg9: CHCFG9, + #[doc = "0x0a - Channel Configuration register"] pub chcfg10: CHCFG10, + #[doc = "0x0b - Channel Configuration register"] pub chcfg11: CHCFG11, + #[doc = "0x0c - Channel Configuration register"] pub chcfg12: CHCFG12, + #[doc = "0x0d - Channel Configuration register"] pub chcfg13: CHCFG13, + #[doc = "0x0e - Channel Configuration register"] pub chcfg14: CHCFG14, + #[doc = "0x0f - Channel Configuration register"] pub chcfg15: CHCFG15, } #[doc = "Channel Configuration register"] pub struct CHCFG0 { diff --git a/src/eim/eichd0_word0/mod.rs b/src/eim/eichd0_word0/mod.rs index f95a2f9..7a82980 100644 --- a/src/eim/eichd0_word0/mod.rs +++ b/src/eim/eichd0_word0/mod.rs @@ -22,7 +22,9 @@ impl super::EICHD0_WORD0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/eim/eichd0_word1/mod.rs b/src/eim/eichd0_word1/mod.rs index 614c138..87ad730 100644 --- a/src/eim/eichd0_word1/mod.rs +++ b/src/eim/eichd0_word1/mod.rs @@ -22,7 +22,9 @@ impl super::EICHD0_WORD1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/eim/eichd1_word0/mod.rs b/src/eim/eichd1_word0/mod.rs index 98ca30b..ec9b843 100644 --- a/src/eim/eichd1_word0/mod.rs +++ b/src/eim/eichd1_word0/mod.rs @@ -22,7 +22,9 @@ impl super::EICHD1_WORD0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/eim/eichd1_word1/mod.rs b/src/eim/eichd1_word1/mod.rs index 275f573..2e00f90 100644 --- a/src/eim/eichd1_word1/mod.rs +++ b/src/eim/eichd1_word1/mod.rs @@ -22,7 +22,9 @@ impl super::EICHD1_WORD1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/eim/eichen/mod.rs b/src/eim/eichen/mod.rs index be2fd5e..7e16138 100644 --- a/src/eim/eichen/mod.rs +++ b/src/eim/eichen/mod.rs @@ -22,7 +22,9 @@ impl super::EICHEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EICHEN { #[doc = "Possible values of the field `EICH1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EICH1ENR { - #[doc = "Error injection is disabled on Error Injection Channel 1"] - _0, - #[doc = "Error injection is enabled on Error Injection Channel 1"] - _1, + #[doc = "Error injection is disabled on Error Injection Channel 1"] _0, + #[doc = "Error injection is enabled on Error Injection Channel 1"] _1, } impl EICH1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EICH1ENR { #[doc = "Possible values of the field `EICH0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EICH0ENR { - #[doc = "Error injection is disabled on Error Injection Channel 0"] - _0, - #[doc = "Error injection is enabled on Error Injection Channel 0"] - _1, + #[doc = "Error injection is disabled on Error Injection Channel 0"] _0, + #[doc = "Error injection is enabled on Error Injection Channel 0"] _1, } impl EICH0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl EICH0ENR { } #[doc = "Values that can be written to the field `EICH1EN`"] pub enum EICH1ENW { - #[doc = "Error injection is disabled on Error Injection Channel 1"] - _0, - #[doc = "Error injection is enabled on Error Injection Channel 1"] - _1, + #[doc = "Error injection is disabled on Error Injection Channel 1"] _0, + #[doc = "Error injection is enabled on Error Injection Channel 1"] _1, } impl EICH1ENW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _EICH1ENW<'a> { } #[doc = "Values that can be written to the field `EICH0EN`"] pub enum EICH0ENW { - #[doc = "Error injection is disabled on Error Injection Channel 0"] - _0, - #[doc = "Error injection is enabled on Error Injection Channel 0"] - _1, + #[doc = "Error injection is disabled on Error Injection Channel 0"] _0, + #[doc = "Error injection is enabled on Error Injection Channel 0"] _1, } impl EICH0ENW { #[allow(missing_docs)] diff --git a/src/eim/eimcr/mod.rs b/src/eim/eimcr/mod.rs index c3a3c35..6379790 100644 --- a/src/eim/eimcr/mod.rs +++ b/src/eim/eimcr/mod.rs @@ -22,7 +22,9 @@ impl super::EIMCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EIMCR { #[doc = "Possible values of the field `GEIEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GEIENR { - #[doc = "Disabled"] - _0, - #[doc = "Enabled"] - _1, + #[doc = "Disabled"] _0, + #[doc = "Enabled"] _1, } impl GEIENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl GEIENR { } #[doc = "Values that can be written to the field `GEIEN`"] pub enum GEIENW { - #[doc = "Disabled"] - _0, - #[doc = "Enabled"] - _1, + #[doc = "Disabled"] _0, + #[doc = "Enabled"] _1, } impl GEIENW { #[allow(missing_docs)] diff --git a/src/eim/mod.rs b/src/eim/mod.rs index d859736..7b406b5 100644 --- a/src/eim/mod.rs +++ b/src/eim/mod.rs @@ -2,20 +2,14 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Error Injection Module Configuration Register"] - pub eimcr: EIMCR, - #[doc = "0x04 - Error Injection Channel Enable register"] - pub eichen: EICHEN, + #[doc = "0x00 - Error Injection Module Configuration Register"] pub eimcr: EIMCR, + #[doc = "0x04 - Error Injection Channel Enable register"] pub eichen: EICHEN, _reserved0: [u8; 248usize], - #[doc = "0x100 - Error Injection Channel Descriptor n, Word0"] - pub eichd0_word0: EICHD0_WORD0, - #[doc = "0x104 - Error Injection Channel Descriptor n, Word1"] - pub eichd0_word1: EICHD0_WORD1, + #[doc = "0x100 - Error Injection Channel Descriptor n, Word0"] pub eichd0_word0: EICHD0_WORD0, + #[doc = "0x104 - Error Injection Channel Descriptor n, Word1"] pub eichd0_word1: EICHD0_WORD1, _reserved1: [u8; 248usize], - #[doc = "0x200 - Error Injection Channel Descriptor n, Word0"] - pub eichd1_word0: EICHD1_WORD0, - #[doc = "0x204 - Error Injection Channel Descriptor n, Word1"] - pub eichd1_word1: EICHD1_WORD1, + #[doc = "0x200 - Error Injection Channel Descriptor n, Word0"] pub eichd1_word0: EICHD1_WORD0, + #[doc = "0x204 - Error Injection Channel Descriptor n, Word1"] pub eichd1_word1: EICHD1_WORD1, } #[doc = "Error Injection Module Configuration Register"] pub struct EIMCR { diff --git a/src/erm/cr0/mod.rs b/src/erm/cr0/mod.rs index 137065d..380ea77 100644 --- a/src/erm/cr0/mod.rs +++ b/src/erm/cr0/mod.rs @@ -22,7 +22,9 @@ impl super::CR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CR0 { #[doc = "Possible values of the field `ENCIE1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENCIE1R { - #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] _0, + #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] _1, } impl ENCIE1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ENCIE1R { #[doc = "Possible values of the field `ESCIE1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESCIE1R { - #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] _0, + #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] _1, } impl ESCIE1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ESCIE1R { #[doc = "Possible values of the field `ENCIE0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENCIE0R { - #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] _0, + #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] _1, } impl ENCIE0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ENCIE0R { #[doc = "Possible values of the field `ESCIE0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESCIE0R { - #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] _0, + #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] _1, } impl ESCIE0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl ESCIE0R { } #[doc = "Values that can be written to the field `ENCIE1`"] pub enum ENCIE1W { - #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] _0, + #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] _1, } impl ENCIE1W { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _ENCIE1W<'a> { } #[doc = "Values that can be written to the field `ESCIE1`"] pub enum ESCIE1W { - #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] _0, + #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] _1, } impl ESCIE1W { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _ESCIE1W<'a> { } #[doc = "Values that can be written to the field `ENCIE0`"] pub enum ENCIE0W { - #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] _0, + #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] _1, } impl ENCIE0W { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _ENCIE0W<'a> { } #[doc = "Values that can be written to the field `ESCIE0`"] pub enum ESCIE0W { - #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] - _0, - #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] - _1, + #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] _0, + #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] _1, } impl ESCIE0W { #[allow(missing_docs)] diff --git a/src/erm/ear0/mod.rs b/src/erm/ear0/mod.rs index 349589b..be0cee9 100644 --- a/src/erm/ear0/mod.rs +++ b/src/erm/ear0/mod.rs @@ -6,7 +6,9 @@ impl super::EAR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/erm/ear1/mod.rs b/src/erm/ear1/mod.rs index 76b9b64..cf9fd90 100644 --- a/src/erm/ear1/mod.rs +++ b/src/erm/ear1/mod.rs @@ -6,7 +6,9 @@ impl super::EAR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/erm/mod.rs b/src/erm/mod.rs index 89dac73..18f202c 100644 --- a/src/erm/mod.rs +++ b/src/erm/mod.rs @@ -2,17 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - ERM Configuration Register 0"] - pub cr0: CR0, + #[doc = "0x00 - ERM Configuration Register 0"] pub cr0: CR0, _reserved0: [u8; 12usize], - #[doc = "0x10 - ERM Status Register 0"] - pub sr0: SR0, + #[doc = "0x10 - ERM Status Register 0"] pub sr0: SR0, _reserved1: [u8; 236usize], - #[doc = "0x100 - ERM Memory n Error Address Register"] - pub ear0: EAR0, + #[doc = "0x100 - ERM Memory n Error Address Register"] pub ear0: EAR0, _reserved2: [u8; 12usize], - #[doc = "0x110 - ERM Memory n Error Address Register"] - pub ear1: EAR1, + #[doc = "0x110 - ERM Memory n Error Address Register"] pub ear1: EAR1, } #[doc = "ERM Configuration Register 0"] pub struct CR0 { diff --git a/src/erm/sr0/mod.rs b/src/erm/sr0/mod.rs index d65e519..15bcba3 100644 --- a/src/erm/sr0/mod.rs +++ b/src/erm/sr0/mod.rs @@ -22,7 +22,9 @@ impl super::SR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SR0 { #[doc = "Possible values of the field `NCE1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NCE1R { - #[doc = "No non-correctable error event on Memory 1 detected"] - _0, - #[doc = "Non-correctable error event on Memory 1 detected"] - _1, + #[doc = "No non-correctable error event on Memory 1 detected"] _0, + #[doc = "Non-correctable error event on Memory 1 detected"] _1, } impl NCE1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl NCE1R { #[doc = "Possible values of the field `SBC1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBC1R { - #[doc = "No single-bit correction event on Memory 1 detected"] - _0, - #[doc = "Single-bit correction event on Memory 1 detected"] - _1, + #[doc = "No single-bit correction event on Memory 1 detected"] _0, + #[doc = "Single-bit correction event on Memory 1 detected"] _1, } impl SBC1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SBC1R { #[doc = "Possible values of the field `NCE0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NCE0R { - #[doc = "No non-correctable error event on Memory 0 detected"] - _0, - #[doc = "Non-correctable error event on Memory 0 detected"] - _1, + #[doc = "No non-correctable error event on Memory 0 detected"] _0, + #[doc = "Non-correctable error event on Memory 0 detected"] _1, } impl NCE0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl NCE0R { #[doc = "Possible values of the field `SBC0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBC0R { - #[doc = "No single-bit correction event on Memory 0 detected"] - _0, - #[doc = "Single-bit correction event on Memory 0 detected"] - _1, + #[doc = "No single-bit correction event on Memory 0 detected"] _0, + #[doc = "Single-bit correction event on Memory 0 detected"] _1, } impl SBC0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl SBC0R { } #[doc = "Values that can be written to the field `NCE1`"] pub enum NCE1W { - #[doc = "No non-correctable error event on Memory 1 detected"] - _0, - #[doc = "Non-correctable error event on Memory 1 detected"] - _1, + #[doc = "No non-correctable error event on Memory 1 detected"] _0, + #[doc = "Non-correctable error event on Memory 1 detected"] _1, } impl NCE1W { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _NCE1W<'a> { } #[doc = "Values that can be written to the field `SBC1`"] pub enum SBC1W { - #[doc = "No single-bit correction event on Memory 1 detected"] - _0, - #[doc = "Single-bit correction event on Memory 1 detected"] - _1, + #[doc = "No single-bit correction event on Memory 1 detected"] _0, + #[doc = "Single-bit correction event on Memory 1 detected"] _1, } impl SBC1W { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _SBC1W<'a> { } #[doc = "Values that can be written to the field `NCE0`"] pub enum NCE0W { - #[doc = "No non-correctable error event on Memory 0 detected"] - _0, - #[doc = "Non-correctable error event on Memory 0 detected"] - _1, + #[doc = "No non-correctable error event on Memory 0 detected"] _0, + #[doc = "Non-correctable error event on Memory 0 detected"] _1, } impl NCE0W { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _NCE0W<'a> { } #[doc = "Values that can be written to the field `SBC0`"] pub enum SBC0W { - #[doc = "No single-bit correction event on Memory 0 detected"] - _0, - #[doc = "Single-bit correction event on Memory 0 detected"] - _1, + #[doc = "No single-bit correction event on Memory 0 detected"] _0, + #[doc = "Single-bit correction event on Memory 0 detected"] _1, } impl SBC0W { #[allow(missing_docs)] diff --git a/src/ewm/ctrl/mod.rs b/src/ewm/ctrl/mod.rs index 32a7205..752a077 100644 --- a/src/ewm/ctrl/mod.rs +++ b/src/ewm/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ewm/mod.rs b/src/ewm/mod.rs index 73bf6c4..159ff4c 100644 --- a/src/ewm/mod.rs +++ b/src/ewm/mod.rs @@ -2,17 +2,12 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Control Register"] - pub ctrl: CTRL, - #[doc = "0x01 - Service Register"] - pub serv: SERV, - #[doc = "0x02 - Compare Low Register"] - pub cmpl: CMPL, - #[doc = "0x03 - Compare High Register"] - pub cmph: CMPH, + #[doc = "0x00 - Control Register"] pub ctrl: CTRL, + #[doc = "0x01 - Service Register"] pub serv: SERV, + #[doc = "0x02 - Compare Low Register"] pub cmpl: CMPL, + #[doc = "0x03 - Compare High Register"] pub cmph: CMPH, _reserved0: [u8; 1usize], - #[doc = "0x05 - Clock Prescaler Register"] - pub clkprescaler: CLKPRESCALER, + #[doc = "0x05 - Clock Prescaler Register"] pub clkprescaler: CLKPRESCALER, } #[doc = "Control Register"] pub struct CTRL { diff --git a/src/flexio/ctrl/mod.rs b/src/flexio/ctrl/mod.rs index 697b7c6..7614743 100644 --- a/src/flexio/ctrl/mod.rs +++ b/src/flexio/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL { #[doc = "Possible values of the field `FLEXEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLEXENR { - #[doc = "FlexIO module is disabled."] - _0, - #[doc = "FlexIO module is enabled."] - _1, + #[doc = "FlexIO module is disabled."] _0, + #[doc = "FlexIO module is enabled."] _1, } impl FLEXENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,8 +90,7 @@ impl FLEXENR { #[doc = "Possible values of the field `SWRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRSTR { - #[doc = "Software reset is disabled"] - _0, + #[doc = "Software reset is disabled"] _0, #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."] _1, } @@ -137,10 +136,8 @@ impl SWRSTR { #[doc = "Possible values of the field `FASTACC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FASTACCR { - #[doc = "Configures for normal register accesses to FlexIO"] - _0, - #[doc = "Configures for fast register accesses to FlexIO"] - _1, + #[doc = "Configures for normal register accesses to FlexIO"] _0, + #[doc = "Configures for fast register accesses to FlexIO"] _1, } impl FASTACCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +181,8 @@ impl FASTACCR { #[doc = "Possible values of the field `DBGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGER { - #[doc = "FlexIO is disabled in debug modes."] - _0, - #[doc = "FlexIO is enabled in debug modes"] - _1, + #[doc = "FlexIO is disabled in debug modes."] _0, + #[doc = "FlexIO is enabled in debug modes"] _1, } impl DBGER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +226,8 @@ impl DBGER { #[doc = "Possible values of the field `DOZEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZENR { - #[doc = "FlexIO enabled in Doze modes."] - _0, - #[doc = "FlexIO disabled in Doze modes."] - _1, + #[doc = "FlexIO enabled in Doze modes."] _0, + #[doc = "FlexIO disabled in Doze modes."] _1, } impl DOZENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +270,8 @@ impl DOZENR { } #[doc = "Values that can be written to the field `FLEXEN`"] pub enum FLEXENW { - #[doc = "FlexIO module is disabled."] - _0, - #[doc = "FlexIO module is enabled."] - _1, + #[doc = "FlexIO module is disabled."] _0, + #[doc = "FlexIO module is enabled."] _1, } impl FLEXENW { #[allow(missing_docs)] @@ -335,8 +326,7 @@ impl<'a> _FLEXENW<'a> { } #[doc = "Values that can be written to the field `SWRST`"] pub enum SWRSTW { - #[doc = "Software reset is disabled"] - _0, + #[doc = "Software reset is disabled"] _0, #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."] _1, } @@ -393,10 +383,8 @@ impl<'a> _SWRSTW<'a> { } #[doc = "Values that can be written to the field `FASTACC`"] pub enum FASTACCW { - #[doc = "Configures for normal register accesses to FlexIO"] - _0, - #[doc = "Configures for fast register accesses to FlexIO"] - _1, + #[doc = "Configures for normal register accesses to FlexIO"] _0, + #[doc = "Configures for fast register accesses to FlexIO"] _1, } impl FASTACCW { #[allow(missing_docs)] @@ -451,10 +439,8 @@ impl<'a> _FASTACCW<'a> { } #[doc = "Values that can be written to the field `DBGE`"] pub enum DBGEW { - #[doc = "FlexIO is disabled in debug modes."] - _0, - #[doc = "FlexIO is enabled in debug modes"] - _1, + #[doc = "FlexIO is disabled in debug modes."] _0, + #[doc = "FlexIO is enabled in debug modes"] _1, } impl DBGEW { #[allow(missing_docs)] @@ -509,10 +495,8 @@ impl<'a> _DBGEW<'a> { } #[doc = "Values that can be written to the field `DOZEN`"] pub enum DOZENW { - #[doc = "FlexIO enabled in Doze modes."] - _0, - #[doc = "FlexIO disabled in Doze modes."] - _1, + #[doc = "FlexIO enabled in Doze modes."] _0, + #[doc = "FlexIO disabled in Doze modes."] _1, } impl DOZENW { #[allow(missing_docs)] diff --git a/src/flexio/mod.rs b/src/flexio/mod.rs index f2b1dbc..b133afb 100644 --- a/src/flexio/mod.rs +++ b/src/flexio/mod.rs @@ -2,111 +2,64 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - FlexIO Control Register"] - pub ctrl: CTRL, - #[doc = "0x0c - Pin State Register"] - pub pin: PIN, - #[doc = "0x10 - Shifter Status Register"] - pub shiftstat: SHIFTSTAT, - #[doc = "0x14 - Shifter Error Register"] - pub shifterr: SHIFTERR, - #[doc = "0x18 - Timer Status Register"] - pub timstat: TIMSTAT, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - FlexIO Control Register"] pub ctrl: CTRL, + #[doc = "0x0c - Pin State Register"] pub pin: PIN, + #[doc = "0x10 - Shifter Status Register"] pub shiftstat: SHIFTSTAT, + #[doc = "0x14 - Shifter Error Register"] pub shifterr: SHIFTERR, + #[doc = "0x18 - Timer Status Register"] pub timstat: TIMSTAT, _reserved0: [u8; 4usize], - #[doc = "0x20 - Shifter Status Interrupt Enable"] - pub shiftsien: SHIFTSIEN, - #[doc = "0x24 - Shifter Error Interrupt Enable"] - pub shifteien: SHIFTEIEN, - #[doc = "0x28 - Timer Interrupt Enable Register"] - pub timien: TIMIEN, + #[doc = "0x20 - Shifter Status Interrupt Enable"] pub shiftsien: SHIFTSIEN, + #[doc = "0x24 - Shifter Error Interrupt Enable"] pub shifteien: SHIFTEIEN, + #[doc = "0x28 - Timer Interrupt Enable Register"] pub timien: TIMIEN, _reserved1: [u8; 4usize], - #[doc = "0x30 - Shifter Status DMA Enable"] - pub shiftsden: SHIFTSDEN, + #[doc = "0x30 - Shifter Status DMA Enable"] pub shiftsden: SHIFTSDEN, _reserved2: [u8; 76usize], - #[doc = "0x80 - Shifter Control N Register"] - pub shiftctl0: SHIFTCTL0, - #[doc = "0x84 - Shifter Control N Register"] - pub shiftctl1: SHIFTCTL1, - #[doc = "0x88 - Shifter Control N Register"] - pub shiftctl2: SHIFTCTL2, - #[doc = "0x8c - Shifter Control N Register"] - pub shiftctl3: SHIFTCTL3, + #[doc = "0x80 - Shifter Control N Register"] pub shiftctl0: SHIFTCTL0, + #[doc = "0x84 - Shifter Control N Register"] pub shiftctl1: SHIFTCTL1, + #[doc = "0x88 - Shifter Control N Register"] pub shiftctl2: SHIFTCTL2, + #[doc = "0x8c - Shifter Control N Register"] pub shiftctl3: SHIFTCTL3, _reserved3: [u8; 112usize], - #[doc = "0x100 - Shifter Configuration N Register"] - pub shiftcfg0: SHIFTCFG0, - #[doc = "0x104 - Shifter Configuration N Register"] - pub shiftcfg1: SHIFTCFG1, - #[doc = "0x108 - Shifter Configuration N Register"] - pub shiftcfg2: SHIFTCFG2, - #[doc = "0x10c - Shifter Configuration N Register"] - pub shiftcfg3: SHIFTCFG3, + #[doc = "0x100 - Shifter Configuration N Register"] pub shiftcfg0: SHIFTCFG0, + #[doc = "0x104 - Shifter Configuration N Register"] pub shiftcfg1: SHIFTCFG1, + #[doc = "0x108 - Shifter Configuration N Register"] pub shiftcfg2: SHIFTCFG2, + #[doc = "0x10c - Shifter Configuration N Register"] pub shiftcfg3: SHIFTCFG3, _reserved4: [u8; 240usize], - #[doc = "0x200 - Shifter Buffer N Register"] - pub shiftbuf0: SHIFTBUF0, - #[doc = "0x204 - Shifter Buffer N Register"] - pub shiftbuf1: SHIFTBUF1, - #[doc = "0x208 - Shifter Buffer N Register"] - pub shiftbuf2: SHIFTBUF2, - #[doc = "0x20c - Shifter Buffer N Register"] - pub shiftbuf3: SHIFTBUF3, + #[doc = "0x200 - Shifter Buffer N Register"] pub shiftbuf0: SHIFTBUF0, + #[doc = "0x204 - Shifter Buffer N Register"] pub shiftbuf1: SHIFTBUF1, + #[doc = "0x208 - Shifter Buffer N Register"] pub shiftbuf2: SHIFTBUF2, + #[doc = "0x20c - Shifter Buffer N Register"] pub shiftbuf3: SHIFTBUF3, _reserved5: [u8; 112usize], - #[doc = "0x280 - Shifter Buffer N Bit Swapped Register"] - pub shiftbufbis0: SHIFTBUFBIS0, - #[doc = "0x284 - Shifter Buffer N Bit Swapped Register"] - pub shiftbufbis1: SHIFTBUFBIS1, - #[doc = "0x288 - Shifter Buffer N Bit Swapped Register"] - pub shiftbufbis2: SHIFTBUFBIS2, - #[doc = "0x28c - Shifter Buffer N Bit Swapped Register"] - pub shiftbufbis3: SHIFTBUFBIS3, + #[doc = "0x280 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis0: SHIFTBUFBIS0, + #[doc = "0x284 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis1: SHIFTBUFBIS1, + #[doc = "0x288 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis2: SHIFTBUFBIS2, + #[doc = "0x28c - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis3: SHIFTBUFBIS3, _reserved6: [u8; 112usize], - #[doc = "0x300 - Shifter Buffer N Byte Swapped Register"] - pub shiftbufbys0: SHIFTBUFBYS0, - #[doc = "0x304 - Shifter Buffer N Byte Swapped Register"] - pub shiftbufbys1: SHIFTBUFBYS1, - #[doc = "0x308 - Shifter Buffer N Byte Swapped Register"] - pub shiftbufbys2: SHIFTBUFBYS2, - #[doc = "0x30c - Shifter Buffer N Byte Swapped Register"] - pub shiftbufbys3: SHIFTBUFBYS3, + #[doc = "0x300 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys0: SHIFTBUFBYS0, + #[doc = "0x304 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys1: SHIFTBUFBYS1, + #[doc = "0x308 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys2: SHIFTBUFBYS2, + #[doc = "0x30c - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys3: SHIFTBUFBYS3, _reserved7: [u8; 112usize], - #[doc = "0x380 - Shifter Buffer N Bit Byte Swapped Register"] - pub shiftbufbbs0: SHIFTBUFBBS0, - #[doc = "0x384 - Shifter Buffer N Bit Byte Swapped Register"] - pub shiftbufbbs1: SHIFTBUFBBS1, - #[doc = "0x388 - Shifter Buffer N Bit Byte Swapped Register"] - pub shiftbufbbs2: SHIFTBUFBBS2, - #[doc = "0x38c - Shifter Buffer N Bit Byte Swapped Register"] - pub shiftbufbbs3: SHIFTBUFBBS3, + #[doc = "0x380 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs0: SHIFTBUFBBS0, + #[doc = "0x384 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs1: SHIFTBUFBBS1, + #[doc = "0x388 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs2: SHIFTBUFBBS2, + #[doc = "0x38c - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs3: SHIFTBUFBBS3, _reserved8: [u8; 112usize], - #[doc = "0x400 - Timer Control N Register"] - pub timctl0: TIMCTL0, - #[doc = "0x404 - Timer Control N Register"] - pub timctl1: TIMCTL1, - #[doc = "0x408 - Timer Control N Register"] - pub timctl2: TIMCTL2, - #[doc = "0x40c - Timer Control N Register"] - pub timctl3: TIMCTL3, + #[doc = "0x400 - Timer Control N Register"] pub timctl0: TIMCTL0, + #[doc = "0x404 - Timer Control N Register"] pub timctl1: TIMCTL1, + #[doc = "0x408 - Timer Control N Register"] pub timctl2: TIMCTL2, + #[doc = "0x40c - Timer Control N Register"] pub timctl3: TIMCTL3, _reserved9: [u8; 112usize], - #[doc = "0x480 - Timer Configuration N Register"] - pub timcfg0: TIMCFG0, - #[doc = "0x484 - Timer Configuration N Register"] - pub timcfg1: TIMCFG1, - #[doc = "0x488 - Timer Configuration N Register"] - pub timcfg2: TIMCFG2, - #[doc = "0x48c - Timer Configuration N Register"] - pub timcfg3: TIMCFG3, + #[doc = "0x480 - Timer Configuration N Register"] pub timcfg0: TIMCFG0, + #[doc = "0x484 - Timer Configuration N Register"] pub timcfg1: TIMCFG1, + #[doc = "0x488 - Timer Configuration N Register"] pub timcfg2: TIMCFG2, + #[doc = "0x48c - Timer Configuration N Register"] pub timcfg3: TIMCFG3, _reserved10: [u8; 112usize], - #[doc = "0x500 - Timer Compare N Register"] - pub timcmp0: TIMCMP0, - #[doc = "0x504 - Timer Compare N Register"] - pub timcmp1: TIMCMP1, - #[doc = "0x508 - Timer Compare N Register"] - pub timcmp2: TIMCMP2, - #[doc = "0x50c - Timer Compare N Register"] - pub timcmp3: TIMCMP3, + #[doc = "0x500 - Timer Compare N Register"] pub timcmp0: TIMCMP0, + #[doc = "0x504 - Timer Compare N Register"] pub timcmp1: TIMCMP1, + #[doc = "0x508 - Timer Compare N Register"] pub timcmp2: TIMCMP2, + #[doc = "0x50c - Timer Compare N Register"] pub timcmp3: TIMCMP3, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/flexio/param/mod.rs b/src/flexio/param/mod.rs index d4b6173..c66c27a 100644 --- a/src/flexio/param/mod.rs +++ b/src/flexio/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/flexio/pin/mod.rs b/src/flexio/pin/mod.rs index 3f1d404..d83dc3c 100644 --- a/src/flexio/pin/mod.rs +++ b/src/flexio/pin/mod.rs @@ -6,7 +6,9 @@ impl super::PIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/flexio/shiftbuf0/mod.rs b/src/flexio/shiftbuf0/mod.rs index cccab8a..3810559 100644 --- a/src/flexio/shiftbuf0/mod.rs +++ b/src/flexio/shiftbuf0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUF0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbuf1/mod.rs b/src/flexio/shiftbuf1/mod.rs index 715133c..b2812b5 100644 --- a/src/flexio/shiftbuf1/mod.rs +++ b/src/flexio/shiftbuf1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUF1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbuf2/mod.rs b/src/flexio/shiftbuf2/mod.rs index fdd4914..96adef5 100644 --- a/src/flexio/shiftbuf2/mod.rs +++ b/src/flexio/shiftbuf2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUF2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbuf3/mod.rs b/src/flexio/shiftbuf3/mod.rs index a64d54a..e832b39 100644 --- a/src/flexio/shiftbuf3/mod.rs +++ b/src/flexio/shiftbuf3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUF3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbbs0/mod.rs b/src/flexio/shiftbufbbs0/mod.rs index 4196920..6fedd5e 100644 --- a/src/flexio/shiftbufbbs0/mod.rs +++ b/src/flexio/shiftbufbbs0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbbs1/mod.rs b/src/flexio/shiftbufbbs1/mod.rs index be8574a..fff9b0e 100644 --- a/src/flexio/shiftbufbbs1/mod.rs +++ b/src/flexio/shiftbufbbs1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbbs2/mod.rs b/src/flexio/shiftbufbbs2/mod.rs index e28a6ae..d2c7b2b 100644 --- a/src/flexio/shiftbufbbs2/mod.rs +++ b/src/flexio/shiftbufbbs2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbbs3/mod.rs b/src/flexio/shiftbufbbs3/mod.rs index df7a44b..d892724 100644 --- a/src/flexio/shiftbufbbs3/mod.rs +++ b/src/flexio/shiftbufbbs3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbis0/mod.rs b/src/flexio/shiftbufbis0/mod.rs index 570c332..5a39dca 100644 --- a/src/flexio/shiftbufbis0/mod.rs +++ b/src/flexio/shiftbufbis0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbis1/mod.rs b/src/flexio/shiftbufbis1/mod.rs index fe76877..d99f481 100644 --- a/src/flexio/shiftbufbis1/mod.rs +++ b/src/flexio/shiftbufbis1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbis2/mod.rs b/src/flexio/shiftbufbis2/mod.rs index 2f6c583..a0f1970 100644 --- a/src/flexio/shiftbufbis2/mod.rs +++ b/src/flexio/shiftbufbis2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbis3/mod.rs b/src/flexio/shiftbufbis3/mod.rs index ec455a4..12f139f 100644 --- a/src/flexio/shiftbufbis3/mod.rs +++ b/src/flexio/shiftbufbis3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbys0/mod.rs b/src/flexio/shiftbufbys0/mod.rs index 78c6e86..7ae787b 100644 --- a/src/flexio/shiftbufbys0/mod.rs +++ b/src/flexio/shiftbufbys0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbys1/mod.rs b/src/flexio/shiftbufbys1/mod.rs index aa22a3e..02dadff 100644 --- a/src/flexio/shiftbufbys1/mod.rs +++ b/src/flexio/shiftbufbys1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbys2/mod.rs b/src/flexio/shiftbufbys2/mod.rs index d3d3b68..f5ff4d1 100644 --- a/src/flexio/shiftbufbys2/mod.rs +++ b/src/flexio/shiftbufbys2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftbufbys3/mod.rs b/src/flexio/shiftbufbys3/mod.rs index 9ba0b5e..3c526e0 100644 --- a/src/flexio/shiftbufbys3/mod.rs +++ b/src/flexio/shiftbufbys3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftcfg0/mod.rs b/src/flexio/shiftcfg0/mod.rs index fae8f7c..2ca4355 100644 --- a/src/flexio/shiftcfg0/mod.rs +++ b/src/flexio/shiftcfg0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCFG0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -99,10 +101,8 @@ impl SSTARTR { #[doc = "Possible values of the field `SSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSTOPR { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -155,10 +155,8 @@ impl SSTOPR { #[doc = "Possible values of the field `INSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INSRCR { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> { } #[doc = "Values that can be written to the field `SSTOP`"] pub enum SSTOPW { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> { } #[doc = "Values that can be written to the field `INSRC`"] pub enum INSRCW { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCW { #[allow(missing_docs)] diff --git a/src/flexio/shiftcfg1/mod.rs b/src/flexio/shiftcfg1/mod.rs index d3b1262..c3aa30c 100644 --- a/src/flexio/shiftcfg1/mod.rs +++ b/src/flexio/shiftcfg1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -99,10 +101,8 @@ impl SSTARTR { #[doc = "Possible values of the field `SSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSTOPR { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -155,10 +155,8 @@ impl SSTOPR { #[doc = "Possible values of the field `INSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INSRCR { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> { } #[doc = "Values that can be written to the field `SSTOP`"] pub enum SSTOPW { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> { } #[doc = "Values that can be written to the field `INSRC`"] pub enum INSRCW { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCW { #[allow(missing_docs)] diff --git a/src/flexio/shiftcfg2/mod.rs b/src/flexio/shiftcfg2/mod.rs index b5e247d..66ac161 100644 --- a/src/flexio/shiftcfg2/mod.rs +++ b/src/flexio/shiftcfg2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -99,10 +101,8 @@ impl SSTARTR { #[doc = "Possible values of the field `SSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSTOPR { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -155,10 +155,8 @@ impl SSTOPR { #[doc = "Possible values of the field `INSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INSRCR { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> { } #[doc = "Values that can be written to the field `SSTOP`"] pub enum SSTOPW { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> { } #[doc = "Values that can be written to the field `INSRC`"] pub enum INSRCW { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCW { #[allow(missing_docs)] diff --git a/src/flexio/shiftcfg3/mod.rs b/src/flexio/shiftcfg3/mod.rs index 016613e..ef37121 100644 --- a/src/flexio/shiftcfg3/mod.rs +++ b/src/flexio/shiftcfg3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCFG3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -99,10 +101,8 @@ impl SSTARTR { #[doc = "Possible values of the field `SSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSTOPR { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -155,10 +155,8 @@ impl SSTOPR { #[doc = "Possible values of the field `INSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INSRCR { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> { } #[doc = "Values that can be written to the field `SSTOP`"] pub enum SSTOPW { - #[doc = "Stop bit disabled for transmitter/receiver/match store"] - _0, - #[doc = "Reserved for transmitter/receiver/match store"] - _1, + #[doc = "Stop bit disabled for transmitter/receiver/match store"] _0, + #[doc = "Reserved for transmitter/receiver/match store"] _1, #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"] _10, #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"] @@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> { } #[doc = "Values that can be written to the field `INSRC`"] pub enum INSRCW { - #[doc = "Pin"] - _0, - #[doc = "Shifter N+1 Output"] - _1, + #[doc = "Pin"] _0, + #[doc = "Shifter N+1 Output"] _1, } impl INSRCW { #[allow(missing_docs)] diff --git a/src/flexio/shiftctl0/mod.rs b/src/flexio/shiftctl0/mod.rs index f839f9a..b86c924 100644 --- a/src/flexio/shiftctl0/mod.rs +++ b/src/flexio/shiftctl0/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCTL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::SHIFTCTL0 { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -53,8 +54,7 @@ pub enum SMODR { _100, #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."] _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -111,10 +111,8 @@ impl SMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -169,14 +167,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -225,10 +219,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TIMPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMPOLR { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,8 +274,7 @@ impl TIMSELR { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TIMPOL`"] pub enum TIMPOLW { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLW { #[allow(missing_docs)] diff --git a/src/flexio/shiftctl1/mod.rs b/src/flexio/shiftctl1/mod.rs index 8d6bff5..44d4bd0 100644 --- a/src/flexio/shiftctl1/mod.rs +++ b/src/flexio/shiftctl1/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCTL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::SHIFTCTL1 { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -53,8 +54,7 @@ pub enum SMODR { _100, #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."] _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -111,10 +111,8 @@ impl SMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -169,14 +167,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -225,10 +219,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TIMPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMPOLR { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,8 +274,7 @@ impl TIMSELR { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TIMPOL`"] pub enum TIMPOLW { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLW { #[allow(missing_docs)] diff --git a/src/flexio/shiftctl2/mod.rs b/src/flexio/shiftctl2/mod.rs index 8d07add..0d93c6a 100644 --- a/src/flexio/shiftctl2/mod.rs +++ b/src/flexio/shiftctl2/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCTL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::SHIFTCTL2 { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -53,8 +54,7 @@ pub enum SMODR { _100, #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."] _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -111,10 +111,8 @@ impl SMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -169,14 +167,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -225,10 +219,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TIMPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMPOLR { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,8 +274,7 @@ impl TIMSELR { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TIMPOL`"] pub enum TIMPOLW { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLW { #[allow(missing_docs)] diff --git a/src/flexio/shiftctl3/mod.rs b/src/flexio/shiftctl3/mod.rs index 293f9a8..7e4a781 100644 --- a/src/flexio/shiftctl3/mod.rs +++ b/src/flexio/shiftctl3/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTCTL3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::SHIFTCTL3 { #[doc = "Possible values of the field `SMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SMODR { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -53,8 +54,7 @@ pub enum SMODR { _100, #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."] _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl SMODR { #[doc = r" Value of the field as raw bits"] @@ -111,10 +111,8 @@ impl SMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -169,14 +167,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -225,10 +219,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TIMPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMPOLR { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,8 +274,7 @@ impl TIMSELR { } #[doc = "Values that can be written to the field `SMOD`"] pub enum SMODW { - #[doc = "Disabled."] - _0, + #[doc = "Disabled."] _0, #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."] _1, #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."] @@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Shifter pin output disabled"] - _0, - #[doc = "Shifter pin open drain or bidirectional output enable"] - _1, - #[doc = "Shifter pin bidirectional output data"] - _10, - #[doc = "Shifter pin output"] - _11, + #[doc = "Shifter pin output disabled"] _0, + #[doc = "Shifter pin open drain or bidirectional output enable"] _1, + #[doc = "Shifter pin bidirectional output data"] _10, + #[doc = "Shifter pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TIMPOL`"] pub enum TIMPOLW { - #[doc = "Shift on posedge of Shift clock"] - _0, - #[doc = "Shift on negedge of Shift clock"] - _1, + #[doc = "Shift on posedge of Shift clock"] _0, + #[doc = "Shift on negedge of Shift clock"] _1, } impl TIMPOLW { #[allow(missing_docs)] diff --git a/src/flexio/shifteien/mod.rs b/src/flexio/shifteien/mod.rs index fe2ac4d..d6a076a 100644 --- a/src/flexio/shifteien/mod.rs +++ b/src/flexio/shifteien/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTEIEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shifterr/mod.rs b/src/flexio/shifterr/mod.rs index 78ae315..f577eb5 100644 --- a/src/flexio/shifterr/mod.rs +++ b/src/flexio/shifterr/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTERR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftsden/mod.rs b/src/flexio/shiftsden/mod.rs index 1b9c0cf..3a684f6 100644 --- a/src/flexio/shiftsden/mod.rs +++ b/src/flexio/shiftsden/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTSDEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftsien/mod.rs b/src/flexio/shiftsien/mod.rs index 29c13a9..02e355c 100644 --- a/src/flexio/shiftsien/mod.rs +++ b/src/flexio/shiftsien/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTSIEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/shiftstat/mod.rs b/src/flexio/shiftstat/mod.rs index d004d8b..fc2dfd6 100644 --- a/src/flexio/shiftstat/mod.rs +++ b/src/flexio/shiftstat/mod.rs @@ -22,7 +22,9 @@ impl super::SHIFTSTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timcfg0/mod.rs b/src/flexio/timcfg0/mod.rs index 53b6eb4..feac226 100644 --- a/src/flexio/timcfg0/mod.rs +++ b/src/flexio/timcfg0/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCFG0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TIMCFG0 { #[doc = "Possible values of the field `TSTART`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTARTR { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,14 +90,10 @@ impl TSTARTR { #[doc = "Possible values of the field `TSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTOPR { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPR { #[doc = r" Value of the field as raw bits"] @@ -146,22 +142,14 @@ impl TSTOPR { #[doc = "Possible values of the field `TIMENA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMENAR { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAR { #[doc = r" Value of the field as raw bits"] @@ -238,22 +226,14 @@ impl TIMENAR { #[doc = "Possible values of the field `TIMDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDISR { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMDISR { #[doc = r" Value of the field as raw bits"] @@ -324,20 +304,13 @@ impl TIMDISR { #[doc = "Possible values of the field `TIMRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMRSTR { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMRSTR { #[doc = r" Value of the field as raw bits"] @@ -401,12 +374,9 @@ impl TIMRSTR { #[doc = "Possible values of the field `TIMDEC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDECR { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -457,14 +427,10 @@ impl TIMDECR { #[doc = "Possible values of the field `TIMOUT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMOUTR { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTR { #[doc = r" Value of the field as raw bits"] @@ -512,10 +478,8 @@ impl TIMOUTR { } #[doc = "Values that can be written to the field `TSTART`"] pub enum TSTARTW { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTW { #[allow(missing_docs)] @@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> { } #[doc = "Values that can be written to the field `TSTOP`"] pub enum TSTOPW { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPW { #[allow(missing_docs)] @@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> { } #[doc = "Values that can be written to the field `TIMENA`"] pub enum TIMENAW { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAW { #[allow(missing_docs)] @@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> { } #[doc = "Values that can be written to the field `TIMDIS`"] pub enum TIMDISW { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, } impl TIMDISW { #[allow(missing_docs)] @@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> { } #[doc = "Values that can be written to the field `TIMRST`"] pub enum TIMRSTW { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, } impl TIMRSTW { #[allow(missing_docs)] @@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> { } #[doc = "Values that can be written to the field `TIMDEC`"] pub enum TIMDECW { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> { } #[doc = "Values that can be written to the field `TIMOUT`"] pub enum TIMOUTW { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTW { #[allow(missing_docs)] diff --git a/src/flexio/timcfg1/mod.rs b/src/flexio/timcfg1/mod.rs index de66a8a..52ea367 100644 --- a/src/flexio/timcfg1/mod.rs +++ b/src/flexio/timcfg1/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TIMCFG1 { #[doc = "Possible values of the field `TSTART`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTARTR { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,14 +90,10 @@ impl TSTARTR { #[doc = "Possible values of the field `TSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTOPR { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPR { #[doc = r" Value of the field as raw bits"] @@ -146,22 +142,14 @@ impl TSTOPR { #[doc = "Possible values of the field `TIMENA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMENAR { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAR { #[doc = r" Value of the field as raw bits"] @@ -238,22 +226,14 @@ impl TIMENAR { #[doc = "Possible values of the field `TIMDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDISR { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMDISR { #[doc = r" Value of the field as raw bits"] @@ -324,20 +304,13 @@ impl TIMDISR { #[doc = "Possible values of the field `TIMRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMRSTR { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMRSTR { #[doc = r" Value of the field as raw bits"] @@ -401,12 +374,9 @@ impl TIMRSTR { #[doc = "Possible values of the field `TIMDEC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDECR { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -457,14 +427,10 @@ impl TIMDECR { #[doc = "Possible values of the field `TIMOUT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMOUTR { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTR { #[doc = r" Value of the field as raw bits"] @@ -512,10 +478,8 @@ impl TIMOUTR { } #[doc = "Values that can be written to the field `TSTART`"] pub enum TSTARTW { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTW { #[allow(missing_docs)] @@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> { } #[doc = "Values that can be written to the field `TSTOP`"] pub enum TSTOPW { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPW { #[allow(missing_docs)] @@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> { } #[doc = "Values that can be written to the field `TIMENA`"] pub enum TIMENAW { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAW { #[allow(missing_docs)] @@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> { } #[doc = "Values that can be written to the field `TIMDIS`"] pub enum TIMDISW { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, } impl TIMDISW { #[allow(missing_docs)] @@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> { } #[doc = "Values that can be written to the field `TIMRST`"] pub enum TIMRSTW { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, } impl TIMRSTW { #[allow(missing_docs)] @@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> { } #[doc = "Values that can be written to the field `TIMDEC`"] pub enum TIMDECW { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> { } #[doc = "Values that can be written to the field `TIMOUT`"] pub enum TIMOUTW { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTW { #[allow(missing_docs)] diff --git a/src/flexio/timcfg2/mod.rs b/src/flexio/timcfg2/mod.rs index 5bfca07..279981b 100644 --- a/src/flexio/timcfg2/mod.rs +++ b/src/flexio/timcfg2/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TIMCFG2 { #[doc = "Possible values of the field `TSTART`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTARTR { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,14 +90,10 @@ impl TSTARTR { #[doc = "Possible values of the field `TSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTOPR { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPR { #[doc = r" Value of the field as raw bits"] @@ -146,22 +142,14 @@ impl TSTOPR { #[doc = "Possible values of the field `TIMENA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMENAR { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAR { #[doc = r" Value of the field as raw bits"] @@ -238,22 +226,14 @@ impl TIMENAR { #[doc = "Possible values of the field `TIMDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDISR { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMDISR { #[doc = r" Value of the field as raw bits"] @@ -324,20 +304,13 @@ impl TIMDISR { #[doc = "Possible values of the field `TIMRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMRSTR { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMRSTR { #[doc = r" Value of the field as raw bits"] @@ -401,12 +374,9 @@ impl TIMRSTR { #[doc = "Possible values of the field `TIMDEC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDECR { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -457,14 +427,10 @@ impl TIMDECR { #[doc = "Possible values of the field `TIMOUT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMOUTR { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTR { #[doc = r" Value of the field as raw bits"] @@ -512,10 +478,8 @@ impl TIMOUTR { } #[doc = "Values that can be written to the field `TSTART`"] pub enum TSTARTW { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTW { #[allow(missing_docs)] @@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> { } #[doc = "Values that can be written to the field `TSTOP`"] pub enum TSTOPW { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPW { #[allow(missing_docs)] @@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> { } #[doc = "Values that can be written to the field `TIMENA`"] pub enum TIMENAW { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAW { #[allow(missing_docs)] @@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> { } #[doc = "Values that can be written to the field `TIMDIS`"] pub enum TIMDISW { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, } impl TIMDISW { #[allow(missing_docs)] @@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> { } #[doc = "Values that can be written to the field `TIMRST`"] pub enum TIMRSTW { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, } impl TIMRSTW { #[allow(missing_docs)] @@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> { } #[doc = "Values that can be written to the field `TIMDEC`"] pub enum TIMDECW { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> { } #[doc = "Values that can be written to the field `TIMOUT`"] pub enum TIMOUTW { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTW { #[allow(missing_docs)] diff --git a/src/flexio/timcfg3/mod.rs b/src/flexio/timcfg3/mod.rs index 439f85e..dce7aec 100644 --- a/src/flexio/timcfg3/mod.rs +++ b/src/flexio/timcfg3/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCFG3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TIMCFG3 { #[doc = "Possible values of the field `TSTART`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTARTR { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,14 +90,10 @@ impl TSTARTR { #[doc = "Possible values of the field `TSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTOPR { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPR { #[doc = r" Value of the field as raw bits"] @@ -146,22 +142,14 @@ impl TSTOPR { #[doc = "Possible values of the field `TIMENA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMENAR { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAR { #[doc = r" Value of the field as raw bits"] @@ -238,22 +226,14 @@ impl TIMENAR { #[doc = "Possible values of the field `TIMDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDISR { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMDISR { #[doc = r" Value of the field as raw bits"] @@ -324,20 +304,13 @@ impl TIMDISR { #[doc = "Possible values of the field `TIMRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMRSTR { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, + #[doc = r" Reserved"] _Reserved(u8), } impl TIMRSTR { #[doc = r" Value of the field as raw bits"] @@ -401,12 +374,9 @@ impl TIMRSTR { #[doc = "Possible values of the field `TIMDEC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMDECR { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -457,14 +427,10 @@ impl TIMDECR { #[doc = "Possible values of the field `TIMOUT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMOUTR { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTR { #[doc = r" Value of the field as raw bits"] @@ -512,10 +478,8 @@ impl TIMOUTR { } #[doc = "Values that can be written to the field `TSTART`"] pub enum TSTARTW { - #[doc = "Start bit disabled"] - _0, - #[doc = "Start bit enabled"] - _1, + #[doc = "Start bit disabled"] _0, + #[doc = "Start bit enabled"] _1, } impl TSTARTW { #[allow(missing_docs)] @@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> { } #[doc = "Values that can be written to the field `TSTOP`"] pub enum TSTOPW { - #[doc = "Stop bit disabled"] - _0, - #[doc = "Stop bit is enabled on timer compare"] - _1, - #[doc = "Stop bit is enabled on timer disable"] - _10, - #[doc = "Stop bit is enabled on timer compare and timer disable"] - _11, + #[doc = "Stop bit disabled"] _0, + #[doc = "Stop bit is enabled on timer compare"] _1, + #[doc = "Stop bit is enabled on timer disable"] _10, + #[doc = "Stop bit is enabled on timer compare and timer disable"] _11, } impl TSTOPW { #[allow(missing_docs)] @@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> { } #[doc = "Values that can be written to the field `TIMENA`"] pub enum TIMENAW { - #[doc = "Timer always enabled"] - _0, - #[doc = "Timer enabled on Timer N-1 enable"] - _1, - #[doc = "Timer enabled on Trigger high"] - _10, - #[doc = "Timer enabled on Trigger high and Pin high"] - _11, - #[doc = "Timer enabled on Pin rising edge"] - _100, - #[doc = "Timer enabled on Pin rising edge and Trigger high"] - _101, - #[doc = "Timer enabled on Trigger rising edge"] - _110, - #[doc = "Timer enabled on Trigger rising or falling edge"] - _111, + #[doc = "Timer always enabled"] _0, + #[doc = "Timer enabled on Timer N-1 enable"] _1, + #[doc = "Timer enabled on Trigger high"] _10, + #[doc = "Timer enabled on Trigger high and Pin high"] _11, + #[doc = "Timer enabled on Pin rising edge"] _100, + #[doc = "Timer enabled on Pin rising edge and Trigger high"] _101, + #[doc = "Timer enabled on Trigger rising edge"] _110, + #[doc = "Timer enabled on Trigger rising or falling edge"] _111, } impl TIMENAW { #[allow(missing_docs)] @@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> { } #[doc = "Values that can be written to the field `TIMDIS`"] pub enum TIMDISW { - #[doc = "Timer never disabled"] - _0, - #[doc = "Timer disabled on Timer N-1 disable"] - _1, - #[doc = "Timer disabled on Timer compare"] - _10, - #[doc = "Timer disabled on Timer compare and Trigger Low"] - _11, - #[doc = "Timer disabled on Pin rising or falling edge"] - _100, - #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] - _101, - #[doc = "Timer disabled on Trigger falling edge"] - _110, + #[doc = "Timer never disabled"] _0, + #[doc = "Timer disabled on Timer N-1 disable"] _1, + #[doc = "Timer disabled on Timer compare"] _10, + #[doc = "Timer disabled on Timer compare and Trigger Low"] _11, + #[doc = "Timer disabled on Pin rising or falling edge"] _100, + #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101, + #[doc = "Timer disabled on Trigger falling edge"] _110, } impl TIMDISW { #[allow(missing_docs)] @@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> { } #[doc = "Values that can be written to the field `TIMRST`"] pub enum TIMRSTW { - #[doc = "Timer never reset"] - _0, - #[doc = "Timer reset on Timer Pin equal to Timer Output"] - _10, - #[doc = "Timer reset on Timer Trigger equal to Timer Output"] - _11, - #[doc = "Timer reset on Timer Pin rising edge"] - _100, - #[doc = "Timer reset on Trigger rising edge"] - _110, - #[doc = "Timer reset on Trigger rising or falling edge"] - _111, + #[doc = "Timer never reset"] _0, + #[doc = "Timer reset on Timer Pin equal to Timer Output"] _10, + #[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11, + #[doc = "Timer reset on Timer Pin rising edge"] _100, + #[doc = "Timer reset on Trigger rising edge"] _110, + #[doc = "Timer reset on Trigger rising or falling edge"] _111, } impl TIMRSTW { #[allow(missing_docs)] @@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> { } #[doc = "Values that can be written to the field `TIMDEC`"] pub enum TIMDECW { - #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] - _0, - #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] - _1, - #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] - _10, + #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0, + #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1, + #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10, #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."] _11, } @@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> { } #[doc = "Values that can be written to the field `TIMOUT`"] pub enum TIMOUTW { - #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] - _0, - #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] - _1, - #[doc = "Timer output is logic one when enabled and on timer reset"] - _10, - #[doc = "Timer output is logic zero when enabled and on timer reset"] - _11, + #[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0, + #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1, + #[doc = "Timer output is logic one when enabled and on timer reset"] _10, + #[doc = "Timer output is logic zero when enabled and on timer reset"] _11, } impl TIMOUTW { #[allow(missing_docs)] diff --git a/src/flexio/timcmp0/mod.rs b/src/flexio/timcmp0/mod.rs index 0998a4d..d50190f 100644 --- a/src/flexio/timcmp0/mod.rs +++ b/src/flexio/timcmp0/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCMP0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timcmp1/mod.rs b/src/flexio/timcmp1/mod.rs index dc2b2eb..9bc2278 100644 --- a/src/flexio/timcmp1/mod.rs +++ b/src/flexio/timcmp1/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCMP1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timcmp2/mod.rs b/src/flexio/timcmp2/mod.rs index 1148089..8bdabb8 100644 --- a/src/flexio/timcmp2/mod.rs +++ b/src/flexio/timcmp2/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCMP2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timcmp3/mod.rs b/src/flexio/timcmp3/mod.rs index 7b2d08b..c39de6e 100644 --- a/src/flexio/timcmp3/mod.rs +++ b/src/flexio/timcmp3/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCMP3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timctl0/mod.rs b/src/flexio/timctl0/mod.rs index 0a69912..82d14db 100644 --- a/src/flexio/timctl0/mod.rs +++ b/src/flexio/timctl0/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCTL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::TIMCTL0 { #[doc = "Possible values of the field `TIMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMODR { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl TIMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -157,14 +153,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -213,10 +205,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TRGSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSRCR { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -260,10 +250,8 @@ impl TRGSRCR { #[doc = "Possible values of the field `TRGPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGPOLR { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -317,14 +305,10 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TIMOD`"] pub enum TIMODW { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODW { #[allow(missing_docs)] @@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TRGSRC`"] pub enum TRGSRCW { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCW { #[allow(missing_docs)] @@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> { } #[doc = "Values that can be written to the field `TRGPOL`"] pub enum TRGPOLW { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLW { #[allow(missing_docs)] diff --git a/src/flexio/timctl1/mod.rs b/src/flexio/timctl1/mod.rs index d016df2..a414134 100644 --- a/src/flexio/timctl1/mod.rs +++ b/src/flexio/timctl1/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCTL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::TIMCTL1 { #[doc = "Possible values of the field `TIMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMODR { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl TIMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -157,14 +153,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -213,10 +205,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TRGSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSRCR { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -260,10 +250,8 @@ impl TRGSRCR { #[doc = "Possible values of the field `TRGPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGPOLR { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -317,14 +305,10 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TIMOD`"] pub enum TIMODW { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODW { #[allow(missing_docs)] @@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TRGSRC`"] pub enum TRGSRCW { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCW { #[allow(missing_docs)] @@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> { } #[doc = "Values that can be written to the field `TRGPOL`"] pub enum TRGPOLW { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLW { #[allow(missing_docs)] diff --git a/src/flexio/timctl2/mod.rs b/src/flexio/timctl2/mod.rs index 43cae44..96d7dac 100644 --- a/src/flexio/timctl2/mod.rs +++ b/src/flexio/timctl2/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCTL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::TIMCTL2 { #[doc = "Possible values of the field `TIMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMODR { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl TIMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -157,14 +153,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -213,10 +205,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TRGSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSRCR { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -260,10 +250,8 @@ impl TRGSRCR { #[doc = "Possible values of the field `TRGPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGPOLR { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -317,14 +305,10 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TIMOD`"] pub enum TIMODW { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODW { #[allow(missing_docs)] @@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TRGSRC`"] pub enum TRGSRCW { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCW { #[allow(missing_docs)] @@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> { } #[doc = "Values that can be written to the field `TRGPOL`"] pub enum TRGPOLW { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLW { #[allow(missing_docs)] diff --git a/src/flexio/timctl3/mod.rs b/src/flexio/timctl3/mod.rs index ec0d632..364ac6c 100644 --- a/src/flexio/timctl3/mod.rs +++ b/src/flexio/timctl3/mod.rs @@ -22,7 +22,9 @@ impl super::TIMCTL3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::TIMCTL3 { #[doc = "Possible values of the field `TIMOD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMODR { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl TIMODR { #[doc = "Possible values of the field `PINPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINPOLR { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -157,14 +153,10 @@ impl PINSELR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -213,10 +205,8 @@ impl PINCFGR { #[doc = "Possible values of the field `TRGSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSRCR { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -260,10 +250,8 @@ impl TRGSRCR { #[doc = "Possible values of the field `TRGPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGPOLR { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -317,14 +305,10 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TIMOD`"] pub enum TIMODW { - #[doc = "Timer Disabled."] - _0, - #[doc = "Dual 8-bit counters baud/bit mode."] - _1, - #[doc = "Dual 8-bit counters PWM mode."] - _10, - #[doc = "Single 16-bit counter mode."] - _11, + #[doc = "Timer Disabled."] _0, + #[doc = "Dual 8-bit counters baud/bit mode."] _1, + #[doc = "Dual 8-bit counters PWM mode."] _10, + #[doc = "Single 16-bit counter mode."] _11, } impl TIMODW { #[allow(missing_docs)] @@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> { } #[doc = "Values that can be written to the field `PINPOL`"] pub enum PINPOLW { - #[doc = "Pin is active high"] - _0, - #[doc = "Pin is active low"] - _1, + #[doc = "Pin is active high"] _0, + #[doc = "Pin is active low"] _1, } impl PINPOLW { #[allow(missing_docs)] @@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "Timer pin output disabled"] - _0, - #[doc = "Timer pin open drain or bidirectional output enable"] - _1, - #[doc = "Timer pin bidirectional output data"] - _10, - #[doc = "Timer pin output"] - _11, + #[doc = "Timer pin output disabled"] _0, + #[doc = "Timer pin open drain or bidirectional output enable"] _1, + #[doc = "Timer pin bidirectional output data"] _10, + #[doc = "Timer pin output"] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `TRGSRC`"] pub enum TRGSRCW { - #[doc = "External trigger selected"] - _0, - #[doc = "Internal trigger selected"] - _1, + #[doc = "External trigger selected"] _0, + #[doc = "Internal trigger selected"] _1, } impl TRGSRCW { #[allow(missing_docs)] @@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> { } #[doc = "Values that can be written to the field `TRGPOL`"] pub enum TRGPOLW { - #[doc = "Trigger active high"] - _0, - #[doc = "Trigger active low"] - _1, + #[doc = "Trigger active high"] _0, + #[doc = "Trigger active low"] _1, } impl TRGPOLW { #[allow(missing_docs)] diff --git a/src/flexio/timien/mod.rs b/src/flexio/timien/mod.rs index 1b376d1..ae44611 100644 --- a/src/flexio/timien/mod.rs +++ b/src/flexio/timien/mod.rs @@ -22,7 +22,9 @@ impl super::TIMIEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/timstat/mod.rs b/src/flexio/timstat/mod.rs index a252234..b7ae552 100644 --- a/src/flexio/timstat/mod.rs +++ b/src/flexio/timstat/mod.rs @@ -22,7 +22,9 @@ impl super::TIMSTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/flexio/verid/mod.rs b/src/flexio/verid/mod.rs index 711092c..6358ff5 100644 --- a/src/flexio/verid/mod.rs +++ b/src/flexio/verid/mod.rs @@ -6,18 +6,17 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard features implemented."] - _0000000000000000, - #[doc = "Supports state, logic and parallel modes."] - _0000000000000001, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard features implemented."] _0000000000000000, + #[doc = "Supports state, logic and parallel modes."] _0000000000000001, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/ftfc/fccob0/mod.rs b/src/ftfc/fccob0/mod.rs index dcb5766..e71460e 100644 --- a/src/ftfc/fccob0/mod.rs +++ b/src/ftfc/fccob0/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob1/mod.rs b/src/ftfc/fccob1/mod.rs index ecbe914..96b0261 100644 --- a/src/ftfc/fccob1/mod.rs +++ b/src/ftfc/fccob1/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob2/mod.rs b/src/ftfc/fccob2/mod.rs index 8190ee7..b00629c 100644 --- a/src/ftfc/fccob2/mod.rs +++ b/src/ftfc/fccob2/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob3/mod.rs b/src/ftfc/fccob3/mod.rs index 3fa2972..08d2c25 100644 --- a/src/ftfc/fccob3/mod.rs +++ b/src/ftfc/fccob3/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob4/mod.rs b/src/ftfc/fccob4/mod.rs index 3c70c32..2a3799f 100644 --- a/src/ftfc/fccob4/mod.rs +++ b/src/ftfc/fccob4/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob5/mod.rs b/src/ftfc/fccob5/mod.rs index 80e3ef9..6a50ec3 100644 --- a/src/ftfc/fccob5/mod.rs +++ b/src/ftfc/fccob5/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob6/mod.rs b/src/ftfc/fccob6/mod.rs index 8a2f8dd..74710a4 100644 --- a/src/ftfc/fccob6/mod.rs +++ b/src/ftfc/fccob6/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob7/mod.rs b/src/ftfc/fccob7/mod.rs index 9ba80a8..7c0c9a3 100644 --- a/src/ftfc/fccob7/mod.rs +++ b/src/ftfc/fccob7/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob8/mod.rs b/src/ftfc/fccob8/mod.rs index e0ce52f..2820706 100644 --- a/src/ftfc/fccob8/mod.rs +++ b/src/ftfc/fccob8/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccob9/mod.rs b/src/ftfc/fccob9/mod.rs index 75ffa79..f49f6dc 100644 --- a/src/ftfc/fccob9/mod.rs +++ b/src/ftfc/fccob9/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOB9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccoba/mod.rs b/src/ftfc/fccoba/mod.rs index e669aa6..1cc2b61 100644 --- a/src/ftfc/fccoba/mod.rs +++ b/src/ftfc/fccoba/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOBA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fccobb/mod.rs b/src/ftfc/fccobb/mod.rs index cd7a24c..d0931c6 100644 --- a/src/ftfc/fccobb/mod.rs +++ b/src/ftfc/fccobb/mod.rs @@ -22,7 +22,9 @@ impl super::FCCOBB { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fcnfg/mod.rs b/src/ftfc/fcnfg/mod.rs index 4a2bca1..965282e 100644 --- a/src/ftfc/fcnfg/mod.rs +++ b/src/ftfc/fcnfg/mod.rs @@ -22,7 +22,9 @@ impl super::FCNFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -85,10 +87,8 @@ impl RAMRDYR { #[doc = "Possible values of the field `ERSSUSP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERSSUSPR { - #[doc = "No suspend requested"] - _0, - #[doc = "Suspend the current Erase Flash Sector command execution"] - _1, + #[doc = "No suspend requested"] _0, + #[doc = "Suspend the current Erase Flash Sector command execution"] _1, } impl ERSSUSPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl ERSSUSPR { #[doc = "Possible values of the field `ERSAREQ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERSAREQR { - #[doc = "No request or request complete"] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "No request or request complete"] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl ERSAREQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -174,8 +172,7 @@ impl ERSAREQR { #[doc = "Possible values of the field `RDCOLLIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDCOLLIER { - #[doc = "Read collision error interrupt disabled"] - _0, + #[doc = "Read collision error interrupt disabled"] _0, #[doc = "Read collision error interrupt enabled. An interrupt request is generated whenever an FTFC read collision error is detected (see the description of FSTAT[RDCOLERR])."] _1, } @@ -221,8 +218,7 @@ impl RDCOLLIER { #[doc = "Possible values of the field `CCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CCIER { - #[doc = "Command complete interrupt disabled"] - _0, + #[doc = "Command complete interrupt disabled"] _0, #[doc = "Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set."] _1, } @@ -267,10 +263,8 @@ impl CCIER { } #[doc = "Values that can be written to the field `ERSSUSP`"] pub enum ERSSUSPW { - #[doc = "No suspend requested"] - _0, - #[doc = "Suspend the current Erase Flash Sector command execution"] - _1, + #[doc = "No suspend requested"] _0, + #[doc = "Suspend the current Erase Flash Sector command execution"] _1, } impl ERSSUSPW { #[allow(missing_docs)] @@ -325,8 +319,7 @@ impl<'a> _ERSSUSPW<'a> { } #[doc = "Values that can be written to the field `RDCOLLIE`"] pub enum RDCOLLIEW { - #[doc = "Read collision error interrupt disabled"] - _0, + #[doc = "Read collision error interrupt disabled"] _0, #[doc = "Read collision error interrupt enabled. An interrupt request is generated whenever an FTFC read collision error is detected (see the description of FSTAT[RDCOLERR])."] _1, } @@ -383,8 +376,7 @@ impl<'a> _RDCOLLIEW<'a> { } #[doc = "Values that can be written to the field `CCIE`"] pub enum CCIEW { - #[doc = "Command complete interrupt disabled"] - _0, + #[doc = "Command complete interrupt disabled"] _0, #[doc = "Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set."] _1, } diff --git a/src/ftfc/fcsestat/mod.rs b/src/ftfc/fcsestat/mod.rs index b85d347..5cd6dd1 100644 --- a/src/ftfc/fcsestat/mod.rs +++ b/src/ftfc/fcsestat/mod.rs @@ -6,7 +6,9 @@ impl super::FCSESTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/ftfc/fdprot/mod.rs b/src/ftfc/fdprot/mod.rs index 4f9b341..b770088 100644 --- a/src/ftfc/fdprot/mod.rs +++ b/src/ftfc/fdprot/mod.rs @@ -22,7 +22,9 @@ impl super::FDPROT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::FDPROT { #[doc = "Possible values of the field `DPROT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPROTR { - #[doc = "Data Flash region is protected"] - _00000000, - #[doc = "Data Flash region is not protected"] - _00000001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Data Flash region is protected"] _00000000, + #[doc = "Data Flash region is not protected"] _00000001, + #[doc = r" Reserved"] _Reserved(u8), } impl DPROTR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl DPROTR { } #[doc = "Values that can be written to the field `DPROT`"] pub enum DPROTW { - #[doc = "Data Flash region is protected"] - _00000000, - #[doc = "Data Flash region is not protected"] - _00000001, + #[doc = "Data Flash region is protected"] _00000000, + #[doc = "Data Flash region is not protected"] _00000001, } impl DPROTW { #[allow(missing_docs)] diff --git a/src/ftfc/feprot/mod.rs b/src/ftfc/feprot/mod.rs index f1e8158..0e986ce 100644 --- a/src/ftfc/feprot/mod.rs +++ b/src/ftfc/feprot/mod.rs @@ -22,7 +22,9 @@ impl super::FEPROT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fercnfg/mod.rs b/src/ftfc/fercnfg/mod.rs index 7804937..7945103 100644 --- a/src/ftfc/fercnfg/mod.rs +++ b/src/ftfc/fercnfg/mod.rs @@ -22,7 +22,9 @@ impl super::FERCNFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::FERCNFG { #[doc = "Possible values of the field `DFDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DFDIER { - #[doc = "Double bit fault detect interrupt disabled"] - _0, + #[doc = "Double bit fault detect interrupt disabled"] _0, #[doc = "Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set."] _1, } @@ -136,8 +137,7 @@ impl FDFDR { } #[doc = "Values that can be written to the field `DFDIE`"] pub enum DFDIEW { - #[doc = "Double bit fault detect interrupt disabled"] - _0, + #[doc = "Double bit fault detect interrupt disabled"] _0, #[doc = "Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set."] _1, } diff --git a/src/ftfc/ferstat/mod.rs b/src/ftfc/ferstat/mod.rs index c6afe0b..a499a33 100644 --- a/src/ftfc/ferstat/mod.rs +++ b/src/ftfc/ferstat/mod.rs @@ -22,7 +22,9 @@ impl super::FERSTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fopt/mod.rs b/src/ftfc/fopt/mod.rs index 813b2ff..8dd53dd 100644 --- a/src/ftfc/fopt/mod.rs +++ b/src/ftfc/fopt/mod.rs @@ -6,7 +6,9 @@ impl super::FOPT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/ftfc/fprot0/mod.rs b/src/ftfc/fprot0/mod.rs index 85da049..06978f8 100644 --- a/src/ftfc/fprot0/mod.rs +++ b/src/ftfc/fprot0/mod.rs @@ -22,7 +22,9 @@ impl super::FPROT0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fprot1/mod.rs b/src/ftfc/fprot1/mod.rs index b882dfc..74e63e9 100644 --- a/src/ftfc/fprot1/mod.rs +++ b/src/ftfc/fprot1/mod.rs @@ -22,7 +22,9 @@ impl super::FPROT1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fprot2/mod.rs b/src/ftfc/fprot2/mod.rs index 1a6508d..903b015 100644 --- a/src/ftfc/fprot2/mod.rs +++ b/src/ftfc/fprot2/mod.rs @@ -22,7 +22,9 @@ impl super::FPROT2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fprot3/mod.rs b/src/ftfc/fprot3/mod.rs index 9fbac19..774eed4 100644 --- a/src/ftfc/fprot3/mod.rs +++ b/src/ftfc/fprot3/mod.rs @@ -22,7 +22,9 @@ impl super::FPROT3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftfc/fsec/mod.rs b/src/ftfc/fsec/mod.rs index 145b767..81a93de 100644 --- a/src/ftfc/fsec/mod.rs +++ b/src/ftfc/fsec/mod.rs @@ -6,7 +6,9 @@ impl super::FSEC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `SEC`"] @@ -14,8 +16,7 @@ impl super::FSEC { pub enum SECR { #[doc = "MCU security status is unsecure (The standard shipping condition of the FTFC is unsecure.)"] _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl SECR { #[doc = r" Value of the field as raw bits"] @@ -44,12 +45,9 @@ impl SECR { #[doc = "Possible values of the field `FSLACC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FSLACCR { - #[doc = "Factory access granted"] - _00, - #[doc = "Factory access granted"] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Factory access granted"] _00, + #[doc = "Factory access granted"] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl FSLACCR { #[doc = r" Value of the field as raw bits"] @@ -85,14 +83,10 @@ impl FSLACCR { #[doc = "Possible values of the field `MEEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MEENR { - #[doc = "Mass erase is enabled"] - _00, - #[doc = "Mass erase is enabled"] - _01, - #[doc = "Mass erase is enabled"] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Mass erase is enabled"] _00, + #[doc = "Mass erase is enabled"] _01, + #[doc = "Mass erase is enabled"] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl MEENR { #[doc = r" Value of the field as raw bits"] @@ -135,14 +129,11 @@ impl MEENR { #[doc = "Possible values of the field `KEYEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum KEYENR { - #[doc = "Backdoor key access disabled"] - _00, + #[doc = "Backdoor key access disabled"] _00, #[doc = "Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)"] _01, - #[doc = "Backdoor key access enabled"] - _10, - #[doc = "Backdoor key access disabled"] - _11, + #[doc = "Backdoor key access enabled"] _10, + #[doc = "Backdoor key access disabled"] _11, } impl KEYENR { #[doc = r" Value of the field as raw bits"] diff --git a/src/ftfc/fstat/mod.rs b/src/ftfc/fstat/mod.rs index 300bfd1..c47d0f9 100644 --- a/src/ftfc/fstat/mod.rs +++ b/src/ftfc/fstat/mod.rs @@ -22,7 +22,9 @@ impl super::FSTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl MGSTAT0R { #[doc = "Possible values of the field `FPVIOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FPVIOLR { - #[doc = "No protection violation detected"] - _0, - #[doc = "Protection violation detected"] - _1, + #[doc = "No protection violation detected"] _0, + #[doc = "Protection violation detected"] _1, } impl FPVIOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -111,10 +111,8 @@ impl FPVIOLR { #[doc = "Possible values of the field `ACCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACCERRR { - #[doc = "No access error detected"] - _0, - #[doc = "Access error detected"] - _1, + #[doc = "No access error detected"] _0, + #[doc = "Access error detected"] _1, } impl ACCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -158,10 +156,8 @@ impl ACCERRR { #[doc = "Possible values of the field `RDCOLERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDCOLERRR { - #[doc = "No collision error detected"] - _0, - #[doc = "Collision error detected"] - _1, + #[doc = "No collision error detected"] _0, + #[doc = "Collision error detected"] _1, } impl RDCOLERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -225,10 +221,8 @@ impl CCIFR { } #[doc = "Values that can be written to the field `FPVIOL`"] pub enum FPVIOLW { - #[doc = "No protection violation detected"] - _0, - #[doc = "Protection violation detected"] - _1, + #[doc = "No protection violation detected"] _0, + #[doc = "Protection violation detected"] _1, } impl FPVIOLW { #[allow(missing_docs)] @@ -283,10 +277,8 @@ impl<'a> _FPVIOLW<'a> { } #[doc = "Values that can be written to the field `ACCERR`"] pub enum ACCERRW { - #[doc = "No access error detected"] - _0, - #[doc = "Access error detected"] - _1, + #[doc = "No access error detected"] _0, + #[doc = "Access error detected"] _1, } impl ACCERRW { #[allow(missing_docs)] @@ -341,10 +333,8 @@ impl<'a> _ACCERRW<'a> { } #[doc = "Values that can be written to the field `RDCOLERR`"] pub enum RDCOLERRW { - #[doc = "No collision error detected"] - _0, - #[doc = "Collision error detected"] - _1, + #[doc = "No collision error detected"] _0, + #[doc = "Collision error detected"] _1, } impl RDCOLERRW { #[allow(missing_docs)] diff --git a/src/ftfc/mod.rs b/src/ftfc/mod.rs index 76bd5ce..692e196 100644 --- a/src/ftfc/mod.rs +++ b/src/ftfc/mod.rs @@ -2,59 +2,34 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Flash Status Register"] - pub fstat: FSTAT, - #[doc = "0x01 - Flash Configuration Register"] - pub fcnfg: FCNFG, - #[doc = "0x02 - Flash Security Register"] - pub fsec: FSEC, - #[doc = "0x03 - Flash Option Register"] - pub fopt: FOPT, - #[doc = "0x04 - Flash Common Command Object Registers"] - pub fccob3: FCCOB3, - #[doc = "0x05 - Flash Common Command Object Registers"] - pub fccob2: FCCOB2, - #[doc = "0x06 - Flash Common Command Object Registers"] - pub fccob1: FCCOB1, - #[doc = "0x07 - Flash Common Command Object Registers"] - pub fccob0: FCCOB0, - #[doc = "0x08 - Flash Common Command Object Registers"] - pub fccob7: FCCOB7, - #[doc = "0x09 - Flash Common Command Object Registers"] - pub fccob6: FCCOB6, - #[doc = "0x0a - Flash Common Command Object Registers"] - pub fccob5: FCCOB5, - #[doc = "0x0b - Flash Common Command Object Registers"] - pub fccob4: FCCOB4, - #[doc = "0x0c - Flash Common Command Object Registers"] - pub fccobb: FCCOBB, - #[doc = "0x0d - Flash Common Command Object Registers"] - pub fccoba: FCCOBA, - #[doc = "0x0e - Flash Common Command Object Registers"] - pub fccob9: FCCOB9, - #[doc = "0x0f - Flash Common Command Object Registers"] - pub fccob8: FCCOB8, - #[doc = "0x10 - Program Flash Protection Registers"] - pub fprot3: FPROT3, - #[doc = "0x11 - Program Flash Protection Registers"] - pub fprot2: FPROT2, - #[doc = "0x12 - Program Flash Protection Registers"] - pub fprot1: FPROT1, - #[doc = "0x13 - Program Flash Protection Registers"] - pub fprot0: FPROT0, + #[doc = "0x00 - Flash Status Register"] pub fstat: FSTAT, + #[doc = "0x01 - Flash Configuration Register"] pub fcnfg: FCNFG, + #[doc = "0x02 - Flash Security Register"] pub fsec: FSEC, + #[doc = "0x03 - Flash Option Register"] pub fopt: FOPT, + #[doc = "0x04 - Flash Common Command Object Registers"] pub fccob3: FCCOB3, + #[doc = "0x05 - Flash Common Command Object Registers"] pub fccob2: FCCOB2, + #[doc = "0x06 - Flash Common Command Object Registers"] pub fccob1: FCCOB1, + #[doc = "0x07 - Flash Common Command Object Registers"] pub fccob0: FCCOB0, + #[doc = "0x08 - Flash Common Command Object Registers"] pub fccob7: FCCOB7, + #[doc = "0x09 - Flash Common Command Object Registers"] pub fccob6: FCCOB6, + #[doc = "0x0a - Flash Common Command Object Registers"] pub fccob5: FCCOB5, + #[doc = "0x0b - Flash Common Command Object Registers"] pub fccob4: FCCOB4, + #[doc = "0x0c - Flash Common Command Object Registers"] pub fccobb: FCCOBB, + #[doc = "0x0d - Flash Common Command Object Registers"] pub fccoba: FCCOBA, + #[doc = "0x0e - Flash Common Command Object Registers"] pub fccob9: FCCOB9, + #[doc = "0x0f - Flash Common Command Object Registers"] pub fccob8: FCCOB8, + #[doc = "0x10 - Program Flash Protection Registers"] pub fprot3: FPROT3, + #[doc = "0x11 - Program Flash Protection Registers"] pub fprot2: FPROT2, + #[doc = "0x12 - Program Flash Protection Registers"] pub fprot1: FPROT1, + #[doc = "0x13 - Program Flash Protection Registers"] pub fprot0: FPROT0, _reserved0: [u8; 2usize], - #[doc = "0x16 - EEPROM Protection Register"] - pub feprot: FEPROT, - #[doc = "0x17 - Data Flash Protection Register"] - pub fdprot: FDPROT, + #[doc = "0x16 - EEPROM Protection Register"] pub feprot: FEPROT, + #[doc = "0x17 - Data Flash Protection Register"] pub fdprot: FDPROT, _reserved1: [u8; 20usize], - #[doc = "0x2c - Flash CSEc Status Register"] - pub fcsestat: FCSESTAT, + #[doc = "0x2c - Flash CSEc Status Register"] pub fcsestat: FCSESTAT, _reserved2: [u8; 1usize], - #[doc = "0x2e - Flash Error Status Register"] - pub ferstat: FERSTAT, - #[doc = "0x2f - Flash Error Configuration Register"] - pub fercnfg: FERCNFG, + #[doc = "0x2e - Flash Error Status Register"] pub ferstat: FERSTAT, + #[doc = "0x2f - Flash Error Configuration Register"] pub fercnfg: FERCNFG, } #[doc = "Flash Status Register"] pub struct FSTAT { diff --git a/src/ftm0/c0sc/mod.rs b/src/ftm0/c0sc/mod.rs index ceb657c..174b306 100644 --- a/src/ftm0/c0sc/mod.rs +++ b/src/ftm0/c0sc/mod.rs @@ -22,7 +22,9 @@ impl super::C0SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C0SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c0v/mod.rs b/src/ftm0/c0v/mod.rs index 9c5f35e..7138aeb 100644 --- a/src/ftm0/c0v/mod.rs +++ b/src/ftm0/c0v/mod.rs @@ -22,7 +22,9 @@ impl super::C0V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c1sc/mod.rs b/src/ftm0/c1sc/mod.rs index 75125c1..12f080d 100644 --- a/src/ftm0/c1sc/mod.rs +++ b/src/ftm0/c1sc/mod.rs @@ -22,7 +22,9 @@ impl super::C1SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C1SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c1v/mod.rs b/src/ftm0/c1v/mod.rs index 787745f..248a2b1 100644 --- a/src/ftm0/c1v/mod.rs +++ b/src/ftm0/c1v/mod.rs @@ -22,7 +22,9 @@ impl super::C1V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c2sc/mod.rs b/src/ftm0/c2sc/mod.rs index fa12b2b..e58d4c7 100644 --- a/src/ftm0/c2sc/mod.rs +++ b/src/ftm0/c2sc/mod.rs @@ -22,7 +22,9 @@ impl super::C2SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C2SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c2v/mod.rs b/src/ftm0/c2v/mod.rs index 9e3c3cd..b8ffb12 100644 --- a/src/ftm0/c2v/mod.rs +++ b/src/ftm0/c2v/mod.rs @@ -22,7 +22,9 @@ impl super::C2V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c3sc/mod.rs b/src/ftm0/c3sc/mod.rs index 2eaf887..6651e54 100644 --- a/src/ftm0/c3sc/mod.rs +++ b/src/ftm0/c3sc/mod.rs @@ -22,7 +22,9 @@ impl super::C3SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C3SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c3v/mod.rs b/src/ftm0/c3v/mod.rs index 43fb0c2..5cba611 100644 --- a/src/ftm0/c3v/mod.rs +++ b/src/ftm0/c3v/mod.rs @@ -22,7 +22,9 @@ impl super::C3V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c4sc/mod.rs b/src/ftm0/c4sc/mod.rs index bf925ca..fb92ce3 100644 --- a/src/ftm0/c4sc/mod.rs +++ b/src/ftm0/c4sc/mod.rs @@ -22,7 +22,9 @@ impl super::C4SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C4SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c4v/mod.rs b/src/ftm0/c4v/mod.rs index 234c36c..8ae59fc 100644 --- a/src/ftm0/c4v/mod.rs +++ b/src/ftm0/c4v/mod.rs @@ -22,7 +22,9 @@ impl super::C4V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c5sc/mod.rs b/src/ftm0/c5sc/mod.rs index e8cf2e7..603ff97 100644 --- a/src/ftm0/c5sc/mod.rs +++ b/src/ftm0/c5sc/mod.rs @@ -22,7 +22,9 @@ impl super::C5SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C5SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c5v/mod.rs b/src/ftm0/c5v/mod.rs index 067897f..4e32c51 100644 --- a/src/ftm0/c5v/mod.rs +++ b/src/ftm0/c5v/mod.rs @@ -22,7 +22,9 @@ impl super::C5V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c6sc/mod.rs b/src/ftm0/c6sc/mod.rs index 07b04a6..ba9dcbc 100644 --- a/src/ftm0/c6sc/mod.rs +++ b/src/ftm0/c6sc/mod.rs @@ -22,7 +22,9 @@ impl super::C6SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C6SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c6v/mod.rs b/src/ftm0/c6v/mod.rs index 51df3d8..d77fbb5 100644 --- a/src/ftm0/c6v/mod.rs +++ b/src/ftm0/c6v/mod.rs @@ -22,7 +22,9 @@ impl super::C6V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/c7sc/mod.rs b/src/ftm0/c7sc/mod.rs index c75e91b..c27a403 100644 --- a/src/ftm0/c7sc/mod.rs +++ b/src/ftm0/c7sc/mod.rs @@ -22,7 +22,9 @@ impl super::C7SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C7SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm0/c7v/mod.rs b/src/ftm0/c7v/mod.rs index 7aca3b3..a258d58 100644 --- a/src/ftm0/c7v/mod.rs +++ b/src/ftm0/c7v/mod.rs @@ -22,7 +22,9 @@ impl super::C7V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/cnt/mod.rs b/src/ftm0/cnt/mod.rs index c5ef1a1..2554297 100644 --- a/src/ftm0/cnt/mod.rs +++ b/src/ftm0/cnt/mod.rs @@ -22,7 +22,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/cntin/mod.rs b/src/ftm0/cntin/mod.rs index 8694d48..3b7f42f 100644 --- a/src/ftm0/cntin/mod.rs +++ b/src/ftm0/cntin/mod.rs @@ -22,7 +22,9 @@ impl super::CNTIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/combine/mod.rs b/src/ftm0/combine/mod.rs index 02885e8..10e7960 100644 --- a/src/ftm0/combine/mod.rs +++ b/src/ftm0/combine/mod.rs @@ -22,7 +22,9 @@ impl super::COMBINE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl COMBINE0R { #[doc = "Possible values of the field `COMP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP0R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl DECAPEN0R { #[doc = "Possible values of the field `DECAP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP0R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,10 +177,8 @@ impl DECAP0R { #[doc = "Possible values of the field `DTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN0R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl DTEN0R { #[doc = "Possible values of the field `SYNCEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN0R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl SYNCEN0R { #[doc = "Possible values of the field `FAULTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN0R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -362,10 +354,8 @@ impl COMBINE1R { #[doc = "Possible values of the field `COMP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP1R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -430,10 +420,8 @@ impl DECAPEN1R { #[doc = "Possible values of the field `DECAP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP1R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +465,8 @@ impl DECAP1R { #[doc = "Possible values of the field `DTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN1R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +510,8 @@ impl DTEN1R { #[doc = "Possible values of the field `SYNCEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN1R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -571,10 +555,8 @@ impl SYNCEN1R { #[doc = "Possible values of the field `FAULTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN1R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -660,10 +642,8 @@ impl COMBINE2R { #[doc = "Possible values of the field `COMP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP2R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -728,10 +708,8 @@ impl DECAPEN2R { #[doc = "Possible values of the field `DECAP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP2R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -775,10 +753,8 @@ impl DECAP2R { #[doc = "Possible values of the field `DTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN2R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -822,10 +798,8 @@ impl DTEN2R { #[doc = "Possible values of the field `SYNCEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN2R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -869,10 +843,8 @@ impl SYNCEN2R { #[doc = "Possible values of the field `FAULTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN2R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -958,10 +930,8 @@ impl COMBINE3R { #[doc = "Possible values of the field `COMP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP3R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1026,10 +996,8 @@ impl DECAPEN3R { #[doc = "Possible values of the field `DECAP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP3R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1073,10 +1041,8 @@ impl DECAP3R { #[doc = "Possible values of the field `DTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN3R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1120,10 +1086,8 @@ impl DTEN3R { #[doc = "Possible values of the field `SYNCEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN3R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1167,10 +1131,8 @@ impl SYNCEN3R { #[doc = "Possible values of the field `FAULTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN3R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1257,10 +1219,8 @@ impl<'a> _COMBINE0W<'a> { } #[doc = "Values that can be written to the field `COMP0`"] pub enum COMP0W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0W { #[allow(missing_docs)] @@ -1338,10 +1298,8 @@ impl<'a> _DECAPEN0W<'a> { } #[doc = "Values that can be written to the field `DECAP0`"] pub enum DECAP0W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0W { #[allow(missing_docs)] @@ -1396,10 +1354,8 @@ impl<'a> _DECAP0W<'a> { } #[doc = "Values that can be written to the field `DTEN0`"] pub enum DTEN0W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0W { #[allow(missing_docs)] @@ -1454,10 +1410,8 @@ impl<'a> _DTEN0W<'a> { } #[doc = "Values that can be written to the field `SYNCEN0`"] pub enum SYNCEN0W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0W { #[allow(missing_docs)] @@ -1512,10 +1466,8 @@ impl<'a> _SYNCEN0W<'a> { } #[doc = "Values that can be written to the field `FAULTEN0`"] pub enum FAULTEN0W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0W { #[allow(missing_docs)] @@ -1616,10 +1568,8 @@ impl<'a> _COMBINE1W<'a> { } #[doc = "Values that can be written to the field `COMP1`"] pub enum COMP1W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1W { #[allow(missing_docs)] @@ -1697,10 +1647,8 @@ impl<'a> _DECAPEN1W<'a> { } #[doc = "Values that can be written to the field `DECAP1`"] pub enum DECAP1W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1W { #[allow(missing_docs)] @@ -1755,10 +1703,8 @@ impl<'a> _DECAP1W<'a> { } #[doc = "Values that can be written to the field `DTEN1`"] pub enum DTEN1W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1W { #[allow(missing_docs)] @@ -1813,10 +1759,8 @@ impl<'a> _DTEN1W<'a> { } #[doc = "Values that can be written to the field `SYNCEN1`"] pub enum SYNCEN1W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1W { #[allow(missing_docs)] @@ -1871,10 +1815,8 @@ impl<'a> _SYNCEN1W<'a> { } #[doc = "Values that can be written to the field `FAULTEN1`"] pub enum FAULTEN1W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1W { #[allow(missing_docs)] @@ -1975,10 +1917,8 @@ impl<'a> _COMBINE2W<'a> { } #[doc = "Values that can be written to the field `COMP2`"] pub enum COMP2W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2W { #[allow(missing_docs)] @@ -2056,10 +1996,8 @@ impl<'a> _DECAPEN2W<'a> { } #[doc = "Values that can be written to the field `DECAP2`"] pub enum DECAP2W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2W { #[allow(missing_docs)] @@ -2114,10 +2052,8 @@ impl<'a> _DECAP2W<'a> { } #[doc = "Values that can be written to the field `DTEN2`"] pub enum DTEN2W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2W { #[allow(missing_docs)] @@ -2172,10 +2108,8 @@ impl<'a> _DTEN2W<'a> { } #[doc = "Values that can be written to the field `SYNCEN2`"] pub enum SYNCEN2W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2W { #[allow(missing_docs)] @@ -2230,10 +2164,8 @@ impl<'a> _SYNCEN2W<'a> { } #[doc = "Values that can be written to the field `FAULTEN2`"] pub enum FAULTEN2W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2W { #[allow(missing_docs)] @@ -2334,10 +2266,8 @@ impl<'a> _COMBINE3W<'a> { } #[doc = "Values that can be written to the field `COMP3`"] pub enum COMP3W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3W { #[allow(missing_docs)] @@ -2415,10 +2345,8 @@ impl<'a> _DECAPEN3W<'a> { } #[doc = "Values that can be written to the field `DECAP3`"] pub enum DECAP3W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3W { #[allow(missing_docs)] @@ -2473,10 +2401,8 @@ impl<'a> _DECAP3W<'a> { } #[doc = "Values that can be written to the field `DTEN3`"] pub enum DTEN3W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3W { #[allow(missing_docs)] @@ -2531,10 +2457,8 @@ impl<'a> _DTEN3W<'a> { } #[doc = "Values that can be written to the field `SYNCEN3`"] pub enum SYNCEN3W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3W { #[allow(missing_docs)] @@ -2589,10 +2513,8 @@ impl<'a> _SYNCEN3W<'a> { } #[doc = "Values that can be written to the field `FAULTEN3`"] pub enum FAULTEN3W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3W { #[allow(missing_docs)] diff --git a/src/ftm0/conf/mod.rs b/src/ftm0/conf/mod.rs index 758ddf6..fe1706a 100644 --- a/src/ftm0/conf/mod.rs +++ b/src/ftm0/conf/mod.rs @@ -22,7 +22,9 @@ impl super::CONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -107,10 +109,8 @@ impl GTBEOUTR { #[doc = "Possible values of the field `ITRIGR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ITRIGRR { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -229,10 +229,8 @@ impl<'a> _GTBEOUTW<'a> { } #[doc = "Values that can be written to the field `ITRIGR`"] pub enum ITRIGRW { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRW { #[allow(missing_docs)] diff --git a/src/ftm0/deadtime/mod.rs b/src/ftm0/deadtime/mod.rs index 3a9b0cf..f1dfdde 100644 --- a/src/ftm0/deadtime/mod.rs +++ b/src/ftm0/deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/exttrig/mod.rs b/src/ftm0/exttrig/mod.rs index cbd52f1..d85e308 100644 --- a/src/ftm0/exttrig/mod.rs +++ b/src/ftm0/exttrig/mod.rs @@ -22,7 +22,9 @@ impl super::EXTTRIG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EXTTRIG { #[doc = "Possible values of the field `CH2TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH2TRIGR { #[doc = "Possible values of the field `CH3TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH3TRIGR { #[doc = "Possible values of the field `CH4TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH4TRIGR { #[doc = "Possible values of the field `CH5TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH5TRIGR { #[doc = "Possible values of the field `CH0TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH0TRIGR { #[doc = "Possible values of the field `CH1TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH1TRIGR { #[doc = "Possible values of the field `INITTRIGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INITTRIGENR { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl INITTRIGENR { #[doc = "Possible values of the field `TRIGF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGFR { - #[doc = "No channel trigger was generated."] - _0, - #[doc = "A channel trigger was generated."] - _1, + #[doc = "No channel trigger was generated."] _0, + #[doc = "A channel trigger was generated."] _1, } impl TRIGFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl TRIGFR { #[doc = "Possible values of the field `CH6TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH6TRIGR { #[doc = "Possible values of the field `CH7TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -512,10 +494,8 @@ impl CH7TRIGR { } #[doc = "Values that can be written to the field `CH2TRIG`"] pub enum CH2TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGW { #[allow(missing_docs)] @@ -570,10 +550,8 @@ impl<'a> _CH2TRIGW<'a> { } #[doc = "Values that can be written to the field `CH3TRIG`"] pub enum CH3TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGW { #[allow(missing_docs)] @@ -628,10 +606,8 @@ impl<'a> _CH3TRIGW<'a> { } #[doc = "Values that can be written to the field `CH4TRIG`"] pub enum CH4TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGW { #[allow(missing_docs)] @@ -686,10 +662,8 @@ impl<'a> _CH4TRIGW<'a> { } #[doc = "Values that can be written to the field `CH5TRIG`"] pub enum CH5TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGW { #[allow(missing_docs)] @@ -744,10 +718,8 @@ impl<'a> _CH5TRIGW<'a> { } #[doc = "Values that can be written to the field `CH0TRIG`"] pub enum CH0TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGW { #[allow(missing_docs)] @@ -802,10 +774,8 @@ impl<'a> _CH0TRIGW<'a> { } #[doc = "Values that can be written to the field `CH1TRIG`"] pub enum CH1TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGW { #[allow(missing_docs)] @@ -860,10 +830,8 @@ impl<'a> _CH1TRIGW<'a> { } #[doc = "Values that can be written to the field `INITTRIGEN`"] pub enum INITTRIGENW { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENW { #[allow(missing_docs)] @@ -918,10 +886,8 @@ impl<'a> _INITTRIGENW<'a> { } #[doc = "Values that can be written to the field `CH6TRIG`"] pub enum CH6TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGW { #[allow(missing_docs)] @@ -976,10 +942,8 @@ impl<'a> _CH6TRIGW<'a> { } #[doc = "Values that can be written to the field `CH7TRIG`"] pub enum CH7TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGW { #[allow(missing_docs)] diff --git a/src/ftm0/filter/mod.rs b/src/ftm0/filter/mod.rs index 30911ac..19ef737 100644 --- a/src/ftm0/filter/mod.rs +++ b/src/ftm0/filter/mod.rs @@ -22,7 +22,9 @@ impl super::FILTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/fltctrl/mod.rs b/src/ftm0/fltctrl/mod.rs index d85ff3c..792a4e9 100644 --- a/src/ftm0/fltctrl/mod.rs +++ b/src/ftm0/fltctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FLTCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTCTRL { #[doc = "Possible values of the field `FAULT0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT0ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULT0ENR { #[doc = "Possible values of the field `FAULT1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT1ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULT1ENR { #[doc = "Possible values of the field `FAULT2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT2ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULT2ENR { #[doc = "Possible values of the field `FAULT3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT3ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULT3ENR { #[doc = "Possible values of the field `FFLTR0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR0ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FFLTR0ENR { #[doc = "Possible values of the field `FFLTR1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR1ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl FFLTR1ENR { #[doc = "Possible values of the field `FFLTR2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR2ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FFLTR2ENR { #[doc = "Possible values of the field `FFLTR3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR3ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +418,7 @@ impl FFVALR { pub enum FSTATER { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -476,10 +461,8 @@ impl FSTATER { } #[doc = "Values that can be written to the field `FAULT0EN`"] pub enum FAULT0ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENW { #[allow(missing_docs)] @@ -534,10 +517,8 @@ impl<'a> _FAULT0ENW<'a> { } #[doc = "Values that can be written to the field `FAULT1EN`"] pub enum FAULT1ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENW { #[allow(missing_docs)] @@ -592,10 +573,8 @@ impl<'a> _FAULT1ENW<'a> { } #[doc = "Values that can be written to the field `FAULT2EN`"] pub enum FAULT2ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENW { #[allow(missing_docs)] @@ -650,10 +629,8 @@ impl<'a> _FAULT2ENW<'a> { } #[doc = "Values that can be written to the field `FAULT3EN`"] pub enum FAULT3ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENW { #[allow(missing_docs)] @@ -708,10 +685,8 @@ impl<'a> _FAULT3ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR0EN`"] pub enum FFLTR0ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENW { #[allow(missing_docs)] @@ -766,10 +741,8 @@ impl<'a> _FFLTR0ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR1EN`"] pub enum FFLTR1ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENW { #[allow(missing_docs)] @@ -824,10 +797,8 @@ impl<'a> _FFLTR1ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR2EN`"] pub enum FFLTR2ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENW { #[allow(missing_docs)] @@ -882,10 +853,8 @@ impl<'a> _FFLTR2ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR3EN`"] pub enum FFLTR3ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENW { #[allow(missing_docs)] @@ -957,8 +926,7 @@ impl<'a> _FFVALW<'a> { pub enum FSTATEW { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATEW { #[allow(missing_docs)] diff --git a/src/ftm0/fltpol/mod.rs b/src/ftm0/fltpol/mod.rs index 5b0170d..d99042f 100644 --- a/src/ftm0/fltpol/mod.rs +++ b/src/ftm0/fltpol/mod.rs @@ -22,7 +22,9 @@ impl super::FLTPOL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTPOL { #[doc = "Possible values of the field `FLT0POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT0POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FLT0POLR { #[doc = "Possible values of the field `FLT1POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT1POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FLT1POLR { #[doc = "Possible values of the field `FLT2POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT2POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FLT2POLR { #[doc = "Possible values of the field `FLT3POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT3POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl FLT3POLR { } #[doc = "Values that can be written to the field `FLT0POL`"] pub enum FLT0POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _FLT0POLW<'a> { } #[doc = "Values that can be written to the field `FLT1POL`"] pub enum FLT1POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _FLT1POLW<'a> { } #[doc = "Values that can be written to the field `FLT2POL`"] pub enum FLT2POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _FLT2POLW<'a> { } #[doc = "Values that can be written to the field `FLT3POL`"] pub enum FLT3POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLW { #[allow(missing_docs)] diff --git a/src/ftm0/fms/mod.rs b/src/ftm0/fms/mod.rs index fb65c8b..61915be 100644 --- a/src/ftm0/fms/mod.rs +++ b/src/ftm0/fms/mod.rs @@ -22,7 +22,9 @@ impl super::FMS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FMS { #[doc = "Possible values of the field `FAULTF0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF0R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULTF0R { #[doc = "Possible values of the field `FAULTF1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF1R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULTF1R { #[doc = "Possible values of the field `FAULTF2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF2R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULTF2R { #[doc = "Possible values of the field `FAULTF3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF3R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULTF3R { #[doc = "Possible values of the field `FAULTIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTINR { - #[doc = "The logic OR of the enabled fault inputs is 0."] - _0, - #[doc = "The logic OR of the enabled fault inputs is 1."] - _1, + #[doc = "The logic OR of the enabled fault inputs is 0."] _0, + #[doc = "The logic OR of the enabled fault inputs is 1."] _1, } impl FAULTINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FAULTINR { #[doc = "Possible values of the field `WPEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPENR { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl WPENR { #[doc = "Possible values of the field `FAULTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTFR { - #[doc = "No fault condition was detected."] - _0, - #[doc = "A fault condition was detected."] - _1, + #[doc = "No fault condition was detected."] _0, + #[doc = "A fault condition was detected."] _1, } impl FAULTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -371,10 +359,8 @@ impl FAULTFR { } #[doc = "Values that can be written to the field `WPEN`"] pub enum WPENW { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENW { #[allow(missing_docs)] diff --git a/src/ftm0/hcr/mod.rs b/src/ftm0/hcr/mod.rs index 6f87eca..dfcbde9 100644 --- a/src/ftm0/hcr/mod.rs +++ b/src/ftm0/hcr/mod.rs @@ -22,7 +22,9 @@ impl super::HCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/invctrl/mod.rs b/src/ftm0/invctrl/mod.rs index 23e094b..80e4e01 100644 --- a/src/ftm0/invctrl/mod.rs +++ b/src/ftm0/invctrl/mod.rs @@ -22,7 +22,9 @@ impl super::INVCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::INVCTRL { #[doc = "Possible values of the field `INV0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV0ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl INV0ENR { #[doc = "Possible values of the field `INV1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV1ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INV1ENR { #[doc = "Possible values of the field `INV2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV2ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl INV2ENR { #[doc = "Possible values of the field `INV3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV3ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl INV3ENR { } #[doc = "Values that can be written to the field `INV0EN`"] pub enum INV0ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _INV0ENW<'a> { } #[doc = "Values that can be written to the field `INV1EN`"] pub enum INV1ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _INV1ENW<'a> { } #[doc = "Values that can be written to the field `INV2EN`"] pub enum INV2ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _INV2ENW<'a> { } #[doc = "Values that can be written to the field `INV3EN`"] pub enum INV3ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENW { #[allow(missing_docs)] diff --git a/src/ftm0/mod.rs b/src/ftm0/mod.rs index 445c1aa..294f78f 100644 --- a/src/ftm0/mod.rs +++ b/src/ftm0/mod.rs @@ -2,97 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status And Control"] - pub sc: SC, - #[doc = "0x04 - Counter"] - pub cnt: CNT, - #[doc = "0x08 - Modulo"] - pub mod_: MOD, - #[doc = "0x0c - Channel (n) Status And Control"] - pub c0sc: C0SC, - #[doc = "0x10 - Channel (n) Value"] - pub c0v: C0V, - #[doc = "0x14 - Channel (n) Status And Control"] - pub c1sc: C1SC, - #[doc = "0x18 - Channel (n) Value"] - pub c1v: C1V, - #[doc = "0x1c - Channel (n) Status And Control"] - pub c2sc: C2SC, - #[doc = "0x20 - Channel (n) Value"] - pub c2v: C2V, - #[doc = "0x24 - Channel (n) Status And Control"] - pub c3sc: C3SC, - #[doc = "0x28 - Channel (n) Value"] - pub c3v: C3V, - #[doc = "0x2c - Channel (n) Status And Control"] - pub c4sc: C4SC, - #[doc = "0x30 - Channel (n) Value"] - pub c4v: C4V, - #[doc = "0x34 - Channel (n) Status And Control"] - pub c5sc: C5SC, - #[doc = "0x38 - Channel (n) Value"] - pub c5v: C5V, - #[doc = "0x3c - Channel (n) Status And Control"] - pub c6sc: C6SC, - #[doc = "0x40 - Channel (n) Value"] - pub c6v: C6V, - #[doc = "0x44 - Channel (n) Status And Control"] - pub c7sc: C7SC, - #[doc = "0x48 - Channel (n) Value"] - pub c7v: C7V, - #[doc = "0x4c - Counter Initial Value"] - pub cntin: CNTIN, - #[doc = "0x50 - Capture And Compare Status"] - pub status: STATUS, - #[doc = "0x54 - Features Mode Selection"] - pub mode: MODE, - #[doc = "0x58 - Synchronization"] - pub sync: SYNC, - #[doc = "0x5c - Initial State For Channels Output"] - pub outinit: OUTINIT, - #[doc = "0x60 - Output Mask"] - pub outmask: OUTMASK, - #[doc = "0x64 - Function For Linked Channels"] - pub combine: COMBINE, - #[doc = "0x68 - Deadtime Configuration"] - pub deadtime: DEADTIME, - #[doc = "0x6c - FTM External Trigger"] - pub exttrig: EXTTRIG, - #[doc = "0x70 - Channels Polarity"] - pub pol: POL, - #[doc = "0x74 - Fault Mode Status"] - pub fms: FMS, - #[doc = "0x78 - Input Capture Filter Control"] - pub filter: FILTER, - #[doc = "0x7c - Fault Control"] - pub fltctrl: FLTCTRL, - #[doc = "0x80 - Quadrature Decoder Control And Status"] - pub qdctrl: QDCTRL, - #[doc = "0x84 - Configuration"] - pub conf: CONF, - #[doc = "0x88 - FTM Fault Input Polarity"] - pub fltpol: FLTPOL, - #[doc = "0x8c - Synchronization Configuration"] - pub synconf: SYNCONF, - #[doc = "0x90 - FTM Inverting Control"] - pub invctrl: INVCTRL, - #[doc = "0x94 - FTM Software Output Control"] - pub swoctrl: SWOCTRL, - #[doc = "0x98 - FTM PWM Load"] - pub pwmload: PWMLOAD, - #[doc = "0x9c - Half Cycle Register"] - pub hcr: HCR, - #[doc = "0xa0 - Pair 0 Deadtime Configuration"] - pub pair0deadtime: PAIR0DEADTIME, + #[doc = "0x00 - Status And Control"] pub sc: SC, + #[doc = "0x04 - Counter"] pub cnt: CNT, + #[doc = "0x08 - Modulo"] pub mod_: MOD, + #[doc = "0x0c - Channel (n) Status And Control"] pub c0sc: C0SC, + #[doc = "0x10 - Channel (n) Value"] pub c0v: C0V, + #[doc = "0x14 - Channel (n) Status And Control"] pub c1sc: C1SC, + #[doc = "0x18 - Channel (n) Value"] pub c1v: C1V, + #[doc = "0x1c - Channel (n) Status And Control"] pub c2sc: C2SC, + #[doc = "0x20 - Channel (n) Value"] pub c2v: C2V, + #[doc = "0x24 - Channel (n) Status And Control"] pub c3sc: C3SC, + #[doc = "0x28 - Channel (n) Value"] pub c3v: C3V, + #[doc = "0x2c - Channel (n) Status And Control"] pub c4sc: C4SC, + #[doc = "0x30 - Channel (n) Value"] pub c4v: C4V, + #[doc = "0x34 - Channel (n) Status And Control"] pub c5sc: C5SC, + #[doc = "0x38 - Channel (n) Value"] pub c5v: C5V, + #[doc = "0x3c - Channel (n) Status And Control"] pub c6sc: C6SC, + #[doc = "0x40 - Channel (n) Value"] pub c6v: C6V, + #[doc = "0x44 - Channel (n) Status And Control"] pub c7sc: C7SC, + #[doc = "0x48 - Channel (n) Value"] pub c7v: C7V, + #[doc = "0x4c - Counter Initial Value"] pub cntin: CNTIN, + #[doc = "0x50 - Capture And Compare Status"] pub status: STATUS, + #[doc = "0x54 - Features Mode Selection"] pub mode: MODE, + #[doc = "0x58 - Synchronization"] pub sync: SYNC, + #[doc = "0x5c - Initial State For Channels Output"] pub outinit: OUTINIT, + #[doc = "0x60 - Output Mask"] pub outmask: OUTMASK, + #[doc = "0x64 - Function For Linked Channels"] pub combine: COMBINE, + #[doc = "0x68 - Deadtime Configuration"] pub deadtime: DEADTIME, + #[doc = "0x6c - FTM External Trigger"] pub exttrig: EXTTRIG, + #[doc = "0x70 - Channels Polarity"] pub pol: POL, + #[doc = "0x74 - Fault Mode Status"] pub fms: FMS, + #[doc = "0x78 - Input Capture Filter Control"] pub filter: FILTER, + #[doc = "0x7c - Fault Control"] pub fltctrl: FLTCTRL, + #[doc = "0x80 - Quadrature Decoder Control And Status"] pub qdctrl: QDCTRL, + #[doc = "0x84 - Configuration"] pub conf: CONF, + #[doc = "0x88 - FTM Fault Input Polarity"] pub fltpol: FLTPOL, + #[doc = "0x8c - Synchronization Configuration"] pub synconf: SYNCONF, + #[doc = "0x90 - FTM Inverting Control"] pub invctrl: INVCTRL, + #[doc = "0x94 - FTM Software Output Control"] pub swoctrl: SWOCTRL, + #[doc = "0x98 - FTM PWM Load"] pub pwmload: PWMLOAD, + #[doc = "0x9c - Half Cycle Register"] pub hcr: HCR, + #[doc = "0xa0 - Pair 0 Deadtime Configuration"] pub pair0deadtime: PAIR0DEADTIME, _reserved0: [u8; 4usize], - #[doc = "0xa8 - Pair 1 Deadtime Configuration"] - pub pair1deadtime: PAIR1DEADTIME, + #[doc = "0xa8 - Pair 1 Deadtime Configuration"] pub pair1deadtime: PAIR1DEADTIME, _reserved1: [u8; 4usize], - #[doc = "0xb0 - Pair 2 Deadtime Configuration"] - pub pair2deadtime: PAIR2DEADTIME, + #[doc = "0xb0 - Pair 2 Deadtime Configuration"] pub pair2deadtime: PAIR2DEADTIME, _reserved2: [u8; 4usize], - #[doc = "0xb8 - Pair 3 Deadtime Configuration"] - pub pair3deadtime: PAIR3DEADTIME, + #[doc = "0xb8 - Pair 3 Deadtime Configuration"] pub pair3deadtime: PAIR3DEADTIME, } #[doc = "Status And Control"] pub struct SC { diff --git a/src/ftm0/mod_/mod.rs b/src/ftm0/mod_/mod.rs index 9ef76ef..448895c 100644 --- a/src/ftm0/mod_/mod.rs +++ b/src/ftm0/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm0/mode/mod.rs b/src/ftm0/mode/mod.rs index 6a8e2ac..c4bd468 100644 --- a/src/ftm0/mode/mod.rs +++ b/src/ftm0/mode/mod.rs @@ -22,7 +22,9 @@ impl super::MODE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MODE { #[doc = "Possible values of the field `FTMEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTMENR { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FTMENR { #[doc = "Possible values of the field `WPDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPDISR { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl PWMSYNCR { #[doc = "Possible values of the field `CAPTEST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CAPTESTR { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,8 +227,7 @@ impl CAPTESTR { #[doc = "Possible values of the field `FAULTM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTMR { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -287,10 +282,8 @@ impl FAULTMR { #[doc = "Possible values of the field `FAULTIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTIER { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -333,10 +326,8 @@ impl FAULTIER { } #[doc = "Values that can be written to the field `FTMEN`"] pub enum FTMENW { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENW { #[allow(missing_docs)] @@ -414,10 +405,8 @@ impl<'a> _INITW<'a> { } #[doc = "Values that can be written to the field `WPDIS`"] pub enum WPDISW { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISW { #[allow(missing_docs)] @@ -530,10 +519,8 @@ impl<'a> _PWMSYNCW<'a> { } #[doc = "Values that can be written to the field `CAPTEST`"] pub enum CAPTESTW { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTW { #[allow(missing_docs)] @@ -588,8 +575,7 @@ impl<'a> _CAPTESTW<'a> { } #[doc = "Values that can be written to the field `FAULTM`"] pub enum FAULTMW { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -654,10 +640,8 @@ impl<'a> _FAULTMW<'a> { } #[doc = "Values that can be written to the field `FAULTIE`"] pub enum FAULTIEW { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIEW { #[allow(missing_docs)] diff --git a/src/ftm0/outinit/mod.rs b/src/ftm0/outinit/mod.rs index 5b3b985..10e2df4 100644 --- a/src/ftm0/outinit/mod.rs +++ b/src/ftm0/outinit/mod.rs @@ -22,7 +22,9 @@ impl super::OUTINIT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTINIT { #[doc = "Possible values of the field `CH0OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OIR { #[doc = "Possible values of the field `CH1OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OIR { #[doc = "Possible values of the field `CH2OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OIR { #[doc = "Possible values of the field `CH3OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OIR { #[doc = "Possible values of the field `CH4OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OIR { #[doc = "Possible values of the field `CH5OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OIR { #[doc = "Possible values of the field `CH6OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OIR { #[doc = "Possible values of the field `CH7OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OIR { } #[doc = "Values that can be written to the field `CH0OI`"] pub enum CH0OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OIW<'a> { } #[doc = "Values that can be written to the field `CH1OI`"] pub enum CH1OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OIW<'a> { } #[doc = "Values that can be written to the field `CH2OI`"] pub enum CH2OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OIW<'a> { } #[doc = "Values that can be written to the field `CH3OI`"] pub enum CH3OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OIW<'a> { } #[doc = "Values that can be written to the field `CH4OI`"] pub enum CH4OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OIW<'a> { } #[doc = "Values that can be written to the field `CH5OI`"] pub enum CH5OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OIW<'a> { } #[doc = "Values that can be written to the field `CH6OI`"] pub enum CH6OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OIW<'a> { } #[doc = "Values that can be written to the field `CH7OI`"] pub enum CH7OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIW { #[allow(missing_docs)] diff --git a/src/ftm0/outmask/mod.rs b/src/ftm0/outmask/mod.rs index f9a4723..6d525e0 100644 --- a/src/ftm0/outmask/mod.rs +++ b/src/ftm0/outmask/mod.rs @@ -22,7 +22,9 @@ impl super::OUTMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTMASK { #[doc = "Possible values of the field `CH0OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OMR { #[doc = "Possible values of the field `CH1OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OMR { #[doc = "Possible values of the field `CH2OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OMR { #[doc = "Possible values of the field `CH3OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OMR { #[doc = "Possible values of the field `CH4OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OMR { #[doc = "Possible values of the field `CH5OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OMR { #[doc = "Possible values of the field `CH6OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OMR { #[doc = "Possible values of the field `CH7OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OMR { } #[doc = "Values that can be written to the field `CH0OM`"] pub enum CH0OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OMW<'a> { } #[doc = "Values that can be written to the field `CH1OM`"] pub enum CH1OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OMW<'a> { } #[doc = "Values that can be written to the field `CH2OM`"] pub enum CH2OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OMW<'a> { } #[doc = "Values that can be written to the field `CH3OM`"] pub enum CH3OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OMW<'a> { } #[doc = "Values that can be written to the field `CH4OM`"] pub enum CH4OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OMW<'a> { } #[doc = "Values that can be written to the field `CH5OM`"] pub enum CH5OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OMW<'a> { } #[doc = "Values that can be written to the field `CH6OM`"] pub enum CH6OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OMW<'a> { } #[doc = "Values that can be written to the field `CH7OM`"] pub enum CH7OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMW { #[allow(missing_docs)] diff --git a/src/ftm0/pair0deadtime/mod.rs b/src/ftm0/pair0deadtime/mod.rs index 57b7430..24b3a06 100644 --- a/src/ftm0/pair0deadtime/mod.rs +++ b/src/ftm0/pair0deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR0DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/pair1deadtime/mod.rs b/src/ftm0/pair1deadtime/mod.rs index 54a2334..bd244e2 100644 --- a/src/ftm0/pair1deadtime/mod.rs +++ b/src/ftm0/pair1deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR1DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/pair2deadtime/mod.rs b/src/ftm0/pair2deadtime/mod.rs index 5073dba..9e96c87 100644 --- a/src/ftm0/pair2deadtime/mod.rs +++ b/src/ftm0/pair2deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR2DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/pair3deadtime/mod.rs b/src/ftm0/pair3deadtime/mod.rs index bcb2471..d925ba8 100644 --- a/src/ftm0/pair3deadtime/mod.rs +++ b/src/ftm0/pair3deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR3DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/pol/mod.rs b/src/ftm0/pol/mod.rs index 822ce37..56d0d5a 100644 --- a/src/ftm0/pol/mod.rs +++ b/src/ftm0/pol/mod.rs @@ -22,7 +22,9 @@ impl super::POL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::POL { #[doc = "Possible values of the field `POL0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL0R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl POL0R { #[doc = "Possible values of the field `POL1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL1R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl POL1R { #[doc = "Possible values of the field `POL2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL2R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl POL2R { #[doc = "Possible values of the field `POL3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL3R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl POL3R { #[doc = "Possible values of the field `POL4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL4R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl POL4R { #[doc = "Possible values of the field `POL5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL5R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl POL5R { #[doc = "Possible values of the field `POL6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL6R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl POL6R { #[doc = "Possible values of the field `POL7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL7R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl POL7R { } #[doc = "Values that can be written to the field `POL0`"] pub enum POL0W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0W { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _POL0W<'a> { } #[doc = "Values that can be written to the field `POL1`"] pub enum POL1W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1W { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _POL1W<'a> { } #[doc = "Values that can be written to the field `POL2`"] pub enum POL2W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2W { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _POL2W<'a> { } #[doc = "Values that can be written to the field `POL3`"] pub enum POL3W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3W { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _POL3W<'a> { } #[doc = "Values that can be written to the field `POL4`"] pub enum POL4W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4W { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _POL4W<'a> { } #[doc = "Values that can be written to the field `POL5`"] pub enum POL5W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5W { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _POL5W<'a> { } #[doc = "Values that can be written to the field `POL6`"] pub enum POL6W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6W { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _POL6W<'a> { } #[doc = "Values that can be written to the field `POL7`"] pub enum POL7W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7W { #[allow(missing_docs)] diff --git a/src/ftm0/pwmload/mod.rs b/src/ftm0/pwmload/mod.rs index c95d704..e3ad1a9 100644 --- a/src/ftm0/pwmload/mod.rs +++ b/src/ftm0/pwmload/mod.rs @@ -22,7 +22,9 @@ impl super::PWMLOAD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PWMLOAD { #[doc = "Possible values of the field `CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0SELR { #[doc = "Possible values of the field `CH1SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1SELR { #[doc = "Possible values of the field `CH2SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2SELR { #[doc = "Possible values of the field `CH3SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3SELR { #[doc = "Possible values of the field `CH4SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4SELR { #[doc = "Possible values of the field `CH5SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5SELR { #[doc = "Possible values of the field `CH6SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6SELR { #[doc = "Possible values of the field `CH7SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7SELR { #[doc = "Possible values of the field `HCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HCSELR { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl HCSELR { #[doc = "Possible values of the field `LDOK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LDOKR { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,8 +495,7 @@ impl LDOKR { #[doc = "Possible values of the field `GLEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GLENR { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -559,10 +540,8 @@ impl GLENR { } #[doc = "Values that can be written to the field `CH0SEL`"] pub enum CH0SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELW { #[allow(missing_docs)] @@ -617,10 +596,8 @@ impl<'a> _CH0SELW<'a> { } #[doc = "Values that can be written to the field `CH1SEL`"] pub enum CH1SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELW { #[allow(missing_docs)] @@ -675,10 +652,8 @@ impl<'a> _CH1SELW<'a> { } #[doc = "Values that can be written to the field `CH2SEL`"] pub enum CH2SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELW { #[allow(missing_docs)] @@ -733,10 +708,8 @@ impl<'a> _CH2SELW<'a> { } #[doc = "Values that can be written to the field `CH3SEL`"] pub enum CH3SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELW { #[allow(missing_docs)] @@ -791,10 +764,8 @@ impl<'a> _CH3SELW<'a> { } #[doc = "Values that can be written to the field `CH4SEL`"] pub enum CH4SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELW { #[allow(missing_docs)] @@ -849,10 +820,8 @@ impl<'a> _CH4SELW<'a> { } #[doc = "Values that can be written to the field `CH5SEL`"] pub enum CH5SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELW { #[allow(missing_docs)] @@ -907,10 +876,8 @@ impl<'a> _CH5SELW<'a> { } #[doc = "Values that can be written to the field `CH6SEL`"] pub enum CH6SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELW { #[allow(missing_docs)] @@ -965,10 +932,8 @@ impl<'a> _CH6SELW<'a> { } #[doc = "Values that can be written to the field `CH7SEL`"] pub enum CH7SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELW { #[allow(missing_docs)] @@ -1023,10 +988,8 @@ impl<'a> _CH7SELW<'a> { } #[doc = "Values that can be written to the field `HCSEL`"] pub enum HCSELW { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELW { #[allow(missing_docs)] @@ -1081,10 +1044,8 @@ impl<'a> _HCSELW<'a> { } #[doc = "Values that can be written to the field `LDOK`"] pub enum LDOKW { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKW { #[allow(missing_docs)] @@ -1139,8 +1100,7 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `GLEN`"] pub enum GLENW { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -1197,10 +1157,8 @@ impl<'a> _GLENW<'a> { } #[doc = "Values that can be written to the field `GLDOK`"] pub enum GLDOKW { - #[doc = "No action."] - _0, - #[doc = "LDOK bit is set."] - _1, + #[doc = "No action."] _0, + #[doc = "LDOK bit is set."] _1, } impl GLDOKW { #[allow(missing_docs)] diff --git a/src/ftm0/qdctrl/mod.rs b/src/ftm0/qdctrl/mod.rs index dee224c..cccabd7 100644 --- a/src/ftm0/qdctrl/mod.rs +++ b/src/ftm0/qdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::QDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::QDCTRL { #[doc = "Possible values of the field `QUADEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADENR { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +137,8 @@ impl TOFDIRR { #[doc = "Possible values of the field `QUADIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADIRR { - #[doc = "Counting direction is decreasing (FTM counter decrement)."] - _0, - #[doc = "Counting direction is increasing (FTM counter increment)."] - _1, + #[doc = "Counting direction is decreasing (FTM counter decrement)."] _0, + #[doc = "Counting direction is increasing (FTM counter increment)."] _1, } impl QUADIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl QUADIRR { #[doc = "Possible values of the field `QUADMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADMODER { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +321,8 @@ impl PHAPOLR { #[doc = "Possible values of the field `PHBFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHBFLTRENR { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl PHBFLTRENR { #[doc = "Possible values of the field `PHAFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHAFLTRENR { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +410,8 @@ impl PHAFLTRENR { } #[doc = "Values that can be written to the field `QUADEN`"] pub enum QUADENW { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENW { #[allow(missing_docs)] @@ -476,10 +466,8 @@ impl<'a> _QUADENW<'a> { } #[doc = "Values that can be written to the field `QUADMODE`"] pub enum QUADMODEW { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODEW { #[allow(missing_docs)] @@ -650,10 +638,8 @@ impl<'a> _PHAPOLW<'a> { } #[doc = "Values that can be written to the field `PHBFLTREN`"] pub enum PHBFLTRENW { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENW { #[allow(missing_docs)] @@ -708,10 +694,8 @@ impl<'a> _PHBFLTRENW<'a> { } #[doc = "Values that can be written to the field `PHAFLTREN`"] pub enum PHAFLTRENW { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENW { #[allow(missing_docs)] diff --git a/src/ftm0/sc/mod.rs b/src/ftm0/sc/mod.rs index 24d7055..abe8d66 100644 --- a/src/ftm0/sc/mod.rs +++ b/src/ftm0/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SC { #[doc = "Possible values of the field `PS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PSR { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSR { #[doc = r" Value of the field as raw bits"] @@ -135,14 +129,10 @@ impl PSR { #[doc = "Possible values of the field `CLKS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKSR { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSR { #[doc = r" Value of the field as raw bits"] @@ -191,10 +181,8 @@ impl CLKSR { #[doc = "Possible values of the field `CPWMS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPWMSR { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -238,10 +226,8 @@ impl CPWMSR { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -285,10 +271,8 @@ impl RIER { #[doc = "Possible values of the field `RF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFR { - #[doc = "A selected reload point did not happen."] - _0, - #[doc = "A selected reload point happened."] - _1, + #[doc = "A selected reload point did not happen."] _0, + #[doc = "A selected reload point happened."] _1, } impl RFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -332,10 +316,8 @@ impl RFR { #[doc = "Possible values of the field `TOIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOIER { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -379,10 +361,8 @@ impl TOIER { #[doc = "Possible values of the field `TOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOFR { - #[doc = "FTM counter has not overflowed."] - _0, - #[doc = "FTM counter has overflowed."] - _1, + #[doc = "FTM counter has not overflowed."] _0, + #[doc = "FTM counter has overflowed."] _1, } impl TOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -426,10 +406,8 @@ impl TOFR { #[doc = "Possible values of the field `PWMEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN0R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -473,10 +451,8 @@ impl PWMEN0R { #[doc = "Possible values of the field `PWMEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN1R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -520,10 +496,8 @@ impl PWMEN1R { #[doc = "Possible values of the field `PWMEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN2R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -567,10 +541,8 @@ impl PWMEN2R { #[doc = "Possible values of the field `PWMEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN3R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -614,10 +586,8 @@ impl PWMEN3R { #[doc = "Possible values of the field `PWMEN4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN4R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -661,10 +631,8 @@ impl PWMEN4R { #[doc = "Possible values of the field `PWMEN5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN5R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -708,10 +676,8 @@ impl PWMEN5R { #[doc = "Possible values of the field `PWMEN6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN6R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -755,10 +721,8 @@ impl PWMEN6R { #[doc = "Possible values of the field `PWMEN7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN7R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -802,38 +766,22 @@ impl PWMEN7R { #[doc = "Possible values of the field `FLTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTPSR { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSR { #[doc = r" Value of the field as raw bits"] @@ -965,22 +913,14 @@ impl FLTPSR { } #[doc = "Values that can be written to the field `PS`"] pub enum PSW { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSW { #[allow(missing_docs)] @@ -1063,14 +1003,10 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `CLKS`"] pub enum CLKSW { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSW { #[allow(missing_docs)] @@ -1129,10 +1065,8 @@ impl<'a> _CLKSW<'a> { } #[doc = "Values that can be written to the field `CPWMS`"] pub enum CPWMSW { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSW { #[allow(missing_docs)] @@ -1187,10 +1121,8 @@ impl<'a> _CPWMSW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIEW { #[allow(missing_docs)] @@ -1245,10 +1177,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TOIE`"] pub enum TOIEW { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIEW { #[allow(missing_docs)] @@ -1303,10 +1233,8 @@ impl<'a> _TOIEW<'a> { } #[doc = "Values that can be written to the field `PWMEN0`"] pub enum PWMEN0W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0W { #[allow(missing_docs)] @@ -1361,10 +1289,8 @@ impl<'a> _PWMEN0W<'a> { } #[doc = "Values that can be written to the field `PWMEN1`"] pub enum PWMEN1W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1W { #[allow(missing_docs)] @@ -1419,10 +1345,8 @@ impl<'a> _PWMEN1W<'a> { } #[doc = "Values that can be written to the field `PWMEN2`"] pub enum PWMEN2W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2W { #[allow(missing_docs)] @@ -1477,10 +1401,8 @@ impl<'a> _PWMEN2W<'a> { } #[doc = "Values that can be written to the field `PWMEN3`"] pub enum PWMEN3W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3W { #[allow(missing_docs)] @@ -1535,10 +1457,8 @@ impl<'a> _PWMEN3W<'a> { } #[doc = "Values that can be written to the field `PWMEN4`"] pub enum PWMEN4W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4W { #[allow(missing_docs)] @@ -1593,10 +1513,8 @@ impl<'a> _PWMEN4W<'a> { } #[doc = "Values that can be written to the field `PWMEN5`"] pub enum PWMEN5W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5W { #[allow(missing_docs)] @@ -1651,10 +1569,8 @@ impl<'a> _PWMEN5W<'a> { } #[doc = "Values that can be written to the field `PWMEN6`"] pub enum PWMEN6W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6W { #[allow(missing_docs)] @@ -1709,10 +1625,8 @@ impl<'a> _PWMEN6W<'a> { } #[doc = "Values that can be written to the field `PWMEN7`"] pub enum PWMEN7W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7W { #[allow(missing_docs)] @@ -1767,38 +1681,22 @@ impl<'a> _PWMEN7W<'a> { } #[doc = "Values that can be written to the field `FLTPS`"] pub enum FLTPSW { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSW { #[allow(missing_docs)] diff --git a/src/ftm0/status/mod.rs b/src/ftm0/status/mod.rs index a808509..bc08657 100644 --- a/src/ftm0/status/mod.rs +++ b/src/ftm0/status/mod.rs @@ -6,16 +6,16 @@ impl super::STATUS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `CH0F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH0FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl CH0FR { #[doc = "Possible values of the field `CH1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl CH1FR { #[doc = "Possible values of the field `CH2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl CH2FR { #[doc = "Possible values of the field `CH3F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH3FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl CH3FR { #[doc = "Possible values of the field `CH4F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH4FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl CH4FR { #[doc = "Possible values of the field `CH5F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH5FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CH5FR { #[doc = "Possible values of the field `CH6F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH6FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl CH6FR { #[doc = "Possible values of the field `CH7F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH7FR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/ftm0/swoctrl/mod.rs b/src/ftm0/swoctrl/mod.rs index 247b3ec..49d6fc8 100644 --- a/src/ftm0/swoctrl/mod.rs +++ b/src/ftm0/swoctrl/mod.rs @@ -22,7 +22,9 @@ impl super::SWOCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SWOCTRL { #[doc = "Possible values of the field `CH0OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OCR { #[doc = "Possible values of the field `CH1OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OCR { #[doc = "Possible values of the field `CH2OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OCR { #[doc = "Possible values of the field `CH3OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OCR { #[doc = "Possible values of the field `CH4OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OCR { #[doc = "Possible values of the field `CH5OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OCR { #[doc = "Possible values of the field `CH6OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OCR { #[doc = "Possible values of the field `CH7OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7OCR { #[doc = "Possible values of the field `CH0OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH0OCVR { #[doc = "Possible values of the field `CH1OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl CH1OCVR { #[doc = "Possible values of the field `CH2OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl CH2OCVR { #[doc = "Possible values of the field `CH3OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl CH3OCVR { #[doc = "Possible values of the field `CH4OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl CH4OCVR { #[doc = "Possible values of the field `CH5OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl CH5OCVR { #[doc = "Possible values of the field `CH6OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl CH6OCVR { #[doc = "Possible values of the field `CH7OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl CH7OCVR { } #[doc = "Values that can be written to the field `CH0OC`"] pub enum CH0OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCW { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _CH0OCW<'a> { } #[doc = "Values that can be written to the field `CH1OC`"] pub enum CH1OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCW { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _CH1OCW<'a> { } #[doc = "Values that can be written to the field `CH2OC`"] pub enum CH2OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCW { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _CH2OCW<'a> { } #[doc = "Values that can be written to the field `CH3OC`"] pub enum CH3OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCW { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _CH3OCW<'a> { } #[doc = "Values that can be written to the field `CH4OC`"] pub enum CH4OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCW { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _CH4OCW<'a> { } #[doc = "Values that can be written to the field `CH5OC`"] pub enum CH5OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCW { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _CH5OCW<'a> { } #[doc = "Values that can be written to the field `CH6OC`"] pub enum CH6OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCW { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _CH6OCW<'a> { } #[doc = "Values that can be written to the field `CH7OC`"] pub enum CH7OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCW { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _CH7OCW<'a> { } #[doc = "Values that can be written to the field `CH0OCV`"] pub enum CH0OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVW { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _CH0OCVW<'a> { } #[doc = "Values that can be written to the field `CH1OCV`"] pub enum CH1OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVW { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _CH1OCVW<'a> { } #[doc = "Values that can be written to the field `CH2OCV`"] pub enum CH2OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVW { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _CH2OCVW<'a> { } #[doc = "Values that can be written to the field `CH3OCV`"] pub enum CH3OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVW { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _CH3OCVW<'a> { } #[doc = "Values that can be written to the field `CH4OCV`"] pub enum CH4OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVW { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _CH4OCVW<'a> { } #[doc = "Values that can be written to the field `CH5OCV`"] pub enum CH5OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVW { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _CH5OCVW<'a> { } #[doc = "Values that can be written to the field `CH6OCV`"] pub enum CH6OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVW { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _CH6OCVW<'a> { } #[doc = "Values that can be written to the field `CH7OCV`"] pub enum CH7OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVW { #[allow(missing_docs)] diff --git a/src/ftm0/sync/mod.rs b/src/ftm0/sync/mod.rs index b46f9f6..add847a 100644 --- a/src/ftm0/sync/mod.rs +++ b/src/ftm0/sync/mod.rs @@ -22,7 +22,9 @@ impl super::SYNC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SYNC { #[doc = "Possible values of the field `CNTMIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMINR { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CNTMINR { #[doc = "Possible values of the field `CNTMAX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMAXR { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,8 +135,7 @@ impl CNTMAXR { #[doc = "Possible values of the field `REINIT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REINITR { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -231,10 +228,8 @@ impl SYNCHOMR { #[doc = "Possible values of the field `TRIG0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG0R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +273,8 @@ impl TRIG0R { #[doc = "Possible values of the field `TRIG1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG1R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +318,8 @@ impl TRIG1R { #[doc = "Possible values of the field `TRIG2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG2R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +363,8 @@ impl TRIG2R { #[doc = "Possible values of the field `SWSYNC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSYNCR { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +407,8 @@ impl SWSYNCR { } #[doc = "Values that can be written to the field `CNTMIN`"] pub enum CNTMINW { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINW { #[allow(missing_docs)] @@ -476,10 +463,8 @@ impl<'a> _CNTMINW<'a> { } #[doc = "Values that can be written to the field `CNTMAX`"] pub enum CNTMAXW { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXW { #[allow(missing_docs)] @@ -534,8 +519,7 @@ impl<'a> _CNTMAXW<'a> { } #[doc = "Values that can be written to the field `REINIT`"] pub enum REINITW { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -650,10 +634,8 @@ impl<'a> _SYNCHOMW<'a> { } #[doc = "Values that can be written to the field `TRIG0`"] pub enum TRIG0W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0W { #[allow(missing_docs)] @@ -708,10 +690,8 @@ impl<'a> _TRIG0W<'a> { } #[doc = "Values that can be written to the field `TRIG1`"] pub enum TRIG1W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1W { #[allow(missing_docs)] @@ -766,10 +746,8 @@ impl<'a> _TRIG1W<'a> { } #[doc = "Values that can be written to the field `TRIG2`"] pub enum TRIG2W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2W { #[allow(missing_docs)] @@ -824,10 +802,8 @@ impl<'a> _TRIG2W<'a> { } #[doc = "Values that can be written to the field `SWSYNC`"] pub enum SWSYNCW { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCW { #[allow(missing_docs)] diff --git a/src/ftm0/synconf/mod.rs b/src/ftm0/synconf/mod.rs index 08257bc..8b29129 100644 --- a/src/ftm0/synconf/mod.rs +++ b/src/ftm0/synconf/mod.rs @@ -22,7 +22,9 @@ impl super::SYNCONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -92,8 +94,7 @@ impl HWTRIGMODER { pub enum CNTINCR { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -139,8 +140,7 @@ impl CNTINCR { pub enum INVCR { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -186,8 +186,7 @@ impl INVCR { pub enum SWOCR { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +230,8 @@ impl SWOCR { #[doc = "Possible values of the field `SYNCMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCMODER { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +275,8 @@ impl SYNCMODER { #[doc = "Possible values of the field `SWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRSTCNTR { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -327,8 +322,7 @@ impl SWRSTCNTR { pub enum SWWRBUFR { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl SWWRBUFR { #[doc = "Possible values of the field `SWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWOMR { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +411,8 @@ impl SWOMR { #[doc = "Possible values of the field `SWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWINVCR { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +456,8 @@ impl SWINVCR { #[doc = "Possible values of the field `SWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSOCR { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +501,8 @@ impl SWSOCR { #[doc = "Possible values of the field `HWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWRSTCNTR { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -562,8 +548,7 @@ impl HWRSTCNTR { pub enum HWWRBUFR { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +592,8 @@ impl HWWRBUFR { #[doc = "Possible values of the field `HWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWOMR { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +637,8 @@ impl HWOMR { #[doc = "Possible values of the field `HWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWINVCR { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +682,8 @@ impl HWINVCR { #[doc = "Possible values of the field `HWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWSOCR { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> { pub enum CNTINCW { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCW { #[allow(missing_docs)] @@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> { pub enum INVCW { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCW { #[allow(missing_docs)] @@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> { pub enum SWOCW { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCW { #[allow(missing_docs)] @@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> { } #[doc = "Values that can be written to the field `SYNCMODE`"] pub enum SYNCMODEW { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODEW { #[allow(missing_docs)] @@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> { } #[doc = "Values that can be written to the field `SWRSTCNT`"] pub enum SWRSTCNTW { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTW { #[allow(missing_docs)] @@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> { pub enum SWWRBUFW { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFW { #[allow(missing_docs)] @@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> { } #[doc = "Values that can be written to the field `SWOM`"] pub enum SWOMW { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMW { #[allow(missing_docs)] @@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> { } #[doc = "Values that can be written to the field `SWINVC`"] pub enum SWINVCW { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCW { #[allow(missing_docs)] @@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> { } #[doc = "Values that can be written to the field `SWSOC`"] pub enum SWSOCW { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCW { #[allow(missing_docs)] @@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> { } #[doc = "Values that can be written to the field `HWRSTCNT`"] pub enum HWRSTCNTW { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTW { #[allow(missing_docs)] @@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> { pub enum HWWRBUFW { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFW { #[allow(missing_docs)] @@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> { } #[doc = "Values that can be written to the field `HWOM`"] pub enum HWOMW { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMW { #[allow(missing_docs)] @@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> { } #[doc = "Values that can be written to the field `HWINVC`"] pub enum HWINVCW { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCW { #[allow(missing_docs)] @@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> { } #[doc = "Values that can be written to the field `HWSOC`"] pub enum HWSOCW { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCW { #[allow(missing_docs)] diff --git a/src/ftm1/c0sc/mod.rs b/src/ftm1/c0sc/mod.rs index ceb657c..174b306 100644 --- a/src/ftm1/c0sc/mod.rs +++ b/src/ftm1/c0sc/mod.rs @@ -22,7 +22,9 @@ impl super::C0SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C0SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c0v/mod.rs b/src/ftm1/c0v/mod.rs index 9c5f35e..7138aeb 100644 --- a/src/ftm1/c0v/mod.rs +++ b/src/ftm1/c0v/mod.rs @@ -22,7 +22,9 @@ impl super::C0V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c1sc/mod.rs b/src/ftm1/c1sc/mod.rs index 75125c1..12f080d 100644 --- a/src/ftm1/c1sc/mod.rs +++ b/src/ftm1/c1sc/mod.rs @@ -22,7 +22,9 @@ impl super::C1SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C1SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c1v/mod.rs b/src/ftm1/c1v/mod.rs index 787745f..248a2b1 100644 --- a/src/ftm1/c1v/mod.rs +++ b/src/ftm1/c1v/mod.rs @@ -22,7 +22,9 @@ impl super::C1V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c2sc/mod.rs b/src/ftm1/c2sc/mod.rs index fa12b2b..e58d4c7 100644 --- a/src/ftm1/c2sc/mod.rs +++ b/src/ftm1/c2sc/mod.rs @@ -22,7 +22,9 @@ impl super::C2SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C2SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c2v/mod.rs b/src/ftm1/c2v/mod.rs index 9e3c3cd..b8ffb12 100644 --- a/src/ftm1/c2v/mod.rs +++ b/src/ftm1/c2v/mod.rs @@ -22,7 +22,9 @@ impl super::C2V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c3sc/mod.rs b/src/ftm1/c3sc/mod.rs index 2eaf887..6651e54 100644 --- a/src/ftm1/c3sc/mod.rs +++ b/src/ftm1/c3sc/mod.rs @@ -22,7 +22,9 @@ impl super::C3SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C3SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c3v/mod.rs b/src/ftm1/c3v/mod.rs index 43fb0c2..5cba611 100644 --- a/src/ftm1/c3v/mod.rs +++ b/src/ftm1/c3v/mod.rs @@ -22,7 +22,9 @@ impl super::C3V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c4sc/mod.rs b/src/ftm1/c4sc/mod.rs index bf925ca..fb92ce3 100644 --- a/src/ftm1/c4sc/mod.rs +++ b/src/ftm1/c4sc/mod.rs @@ -22,7 +22,9 @@ impl super::C4SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C4SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c4v/mod.rs b/src/ftm1/c4v/mod.rs index 234c36c..8ae59fc 100644 --- a/src/ftm1/c4v/mod.rs +++ b/src/ftm1/c4v/mod.rs @@ -22,7 +22,9 @@ impl super::C4V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c5sc/mod.rs b/src/ftm1/c5sc/mod.rs index e8cf2e7..603ff97 100644 --- a/src/ftm1/c5sc/mod.rs +++ b/src/ftm1/c5sc/mod.rs @@ -22,7 +22,9 @@ impl super::C5SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C5SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c5v/mod.rs b/src/ftm1/c5v/mod.rs index 067897f..4e32c51 100644 --- a/src/ftm1/c5v/mod.rs +++ b/src/ftm1/c5v/mod.rs @@ -22,7 +22,9 @@ impl super::C5V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c6sc/mod.rs b/src/ftm1/c6sc/mod.rs index 07b04a6..ba9dcbc 100644 --- a/src/ftm1/c6sc/mod.rs +++ b/src/ftm1/c6sc/mod.rs @@ -22,7 +22,9 @@ impl super::C6SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C6SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c6v/mod.rs b/src/ftm1/c6v/mod.rs index 51df3d8..d77fbb5 100644 --- a/src/ftm1/c6v/mod.rs +++ b/src/ftm1/c6v/mod.rs @@ -22,7 +22,9 @@ impl super::C6V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/c7sc/mod.rs b/src/ftm1/c7sc/mod.rs index c75e91b..c27a403 100644 --- a/src/ftm1/c7sc/mod.rs +++ b/src/ftm1/c7sc/mod.rs @@ -22,7 +22,9 @@ impl super::C7SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C7SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm1/c7v/mod.rs b/src/ftm1/c7v/mod.rs index 7aca3b3..a258d58 100644 --- a/src/ftm1/c7v/mod.rs +++ b/src/ftm1/c7v/mod.rs @@ -22,7 +22,9 @@ impl super::C7V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/cnt/mod.rs b/src/ftm1/cnt/mod.rs index c5ef1a1..2554297 100644 --- a/src/ftm1/cnt/mod.rs +++ b/src/ftm1/cnt/mod.rs @@ -22,7 +22,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/cntin/mod.rs b/src/ftm1/cntin/mod.rs index 8694d48..3b7f42f 100644 --- a/src/ftm1/cntin/mod.rs +++ b/src/ftm1/cntin/mod.rs @@ -22,7 +22,9 @@ impl super::CNTIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/combine/mod.rs b/src/ftm1/combine/mod.rs index 02885e8..10e7960 100644 --- a/src/ftm1/combine/mod.rs +++ b/src/ftm1/combine/mod.rs @@ -22,7 +22,9 @@ impl super::COMBINE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl COMBINE0R { #[doc = "Possible values of the field `COMP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP0R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl DECAPEN0R { #[doc = "Possible values of the field `DECAP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP0R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,10 +177,8 @@ impl DECAP0R { #[doc = "Possible values of the field `DTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN0R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl DTEN0R { #[doc = "Possible values of the field `SYNCEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN0R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl SYNCEN0R { #[doc = "Possible values of the field `FAULTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN0R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -362,10 +354,8 @@ impl COMBINE1R { #[doc = "Possible values of the field `COMP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP1R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -430,10 +420,8 @@ impl DECAPEN1R { #[doc = "Possible values of the field `DECAP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP1R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +465,8 @@ impl DECAP1R { #[doc = "Possible values of the field `DTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN1R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +510,8 @@ impl DTEN1R { #[doc = "Possible values of the field `SYNCEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN1R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -571,10 +555,8 @@ impl SYNCEN1R { #[doc = "Possible values of the field `FAULTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN1R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -660,10 +642,8 @@ impl COMBINE2R { #[doc = "Possible values of the field `COMP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP2R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -728,10 +708,8 @@ impl DECAPEN2R { #[doc = "Possible values of the field `DECAP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP2R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -775,10 +753,8 @@ impl DECAP2R { #[doc = "Possible values of the field `DTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN2R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -822,10 +798,8 @@ impl DTEN2R { #[doc = "Possible values of the field `SYNCEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN2R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -869,10 +843,8 @@ impl SYNCEN2R { #[doc = "Possible values of the field `FAULTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN2R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -958,10 +930,8 @@ impl COMBINE3R { #[doc = "Possible values of the field `COMP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP3R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1026,10 +996,8 @@ impl DECAPEN3R { #[doc = "Possible values of the field `DECAP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP3R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1073,10 +1041,8 @@ impl DECAP3R { #[doc = "Possible values of the field `DTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN3R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1120,10 +1086,8 @@ impl DTEN3R { #[doc = "Possible values of the field `SYNCEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN3R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1167,10 +1131,8 @@ impl SYNCEN3R { #[doc = "Possible values of the field `FAULTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN3R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1257,10 +1219,8 @@ impl<'a> _COMBINE0W<'a> { } #[doc = "Values that can be written to the field `COMP0`"] pub enum COMP0W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0W { #[allow(missing_docs)] @@ -1338,10 +1298,8 @@ impl<'a> _DECAPEN0W<'a> { } #[doc = "Values that can be written to the field `DECAP0`"] pub enum DECAP0W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0W { #[allow(missing_docs)] @@ -1396,10 +1354,8 @@ impl<'a> _DECAP0W<'a> { } #[doc = "Values that can be written to the field `DTEN0`"] pub enum DTEN0W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0W { #[allow(missing_docs)] @@ -1454,10 +1410,8 @@ impl<'a> _DTEN0W<'a> { } #[doc = "Values that can be written to the field `SYNCEN0`"] pub enum SYNCEN0W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0W { #[allow(missing_docs)] @@ -1512,10 +1466,8 @@ impl<'a> _SYNCEN0W<'a> { } #[doc = "Values that can be written to the field `FAULTEN0`"] pub enum FAULTEN0W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0W { #[allow(missing_docs)] @@ -1616,10 +1568,8 @@ impl<'a> _COMBINE1W<'a> { } #[doc = "Values that can be written to the field `COMP1`"] pub enum COMP1W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1W { #[allow(missing_docs)] @@ -1697,10 +1647,8 @@ impl<'a> _DECAPEN1W<'a> { } #[doc = "Values that can be written to the field `DECAP1`"] pub enum DECAP1W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1W { #[allow(missing_docs)] @@ -1755,10 +1703,8 @@ impl<'a> _DECAP1W<'a> { } #[doc = "Values that can be written to the field `DTEN1`"] pub enum DTEN1W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1W { #[allow(missing_docs)] @@ -1813,10 +1759,8 @@ impl<'a> _DTEN1W<'a> { } #[doc = "Values that can be written to the field `SYNCEN1`"] pub enum SYNCEN1W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1W { #[allow(missing_docs)] @@ -1871,10 +1815,8 @@ impl<'a> _SYNCEN1W<'a> { } #[doc = "Values that can be written to the field `FAULTEN1`"] pub enum FAULTEN1W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1W { #[allow(missing_docs)] @@ -1975,10 +1917,8 @@ impl<'a> _COMBINE2W<'a> { } #[doc = "Values that can be written to the field `COMP2`"] pub enum COMP2W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2W { #[allow(missing_docs)] @@ -2056,10 +1996,8 @@ impl<'a> _DECAPEN2W<'a> { } #[doc = "Values that can be written to the field `DECAP2`"] pub enum DECAP2W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2W { #[allow(missing_docs)] @@ -2114,10 +2052,8 @@ impl<'a> _DECAP2W<'a> { } #[doc = "Values that can be written to the field `DTEN2`"] pub enum DTEN2W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2W { #[allow(missing_docs)] @@ -2172,10 +2108,8 @@ impl<'a> _DTEN2W<'a> { } #[doc = "Values that can be written to the field `SYNCEN2`"] pub enum SYNCEN2W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2W { #[allow(missing_docs)] @@ -2230,10 +2164,8 @@ impl<'a> _SYNCEN2W<'a> { } #[doc = "Values that can be written to the field `FAULTEN2`"] pub enum FAULTEN2W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2W { #[allow(missing_docs)] @@ -2334,10 +2266,8 @@ impl<'a> _COMBINE3W<'a> { } #[doc = "Values that can be written to the field `COMP3`"] pub enum COMP3W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3W { #[allow(missing_docs)] @@ -2415,10 +2345,8 @@ impl<'a> _DECAPEN3W<'a> { } #[doc = "Values that can be written to the field `DECAP3`"] pub enum DECAP3W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3W { #[allow(missing_docs)] @@ -2473,10 +2401,8 @@ impl<'a> _DECAP3W<'a> { } #[doc = "Values that can be written to the field `DTEN3`"] pub enum DTEN3W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3W { #[allow(missing_docs)] @@ -2531,10 +2457,8 @@ impl<'a> _DTEN3W<'a> { } #[doc = "Values that can be written to the field `SYNCEN3`"] pub enum SYNCEN3W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3W { #[allow(missing_docs)] @@ -2589,10 +2513,8 @@ impl<'a> _SYNCEN3W<'a> { } #[doc = "Values that can be written to the field `FAULTEN3`"] pub enum FAULTEN3W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3W { #[allow(missing_docs)] diff --git a/src/ftm1/conf/mod.rs b/src/ftm1/conf/mod.rs index 758ddf6..fe1706a 100644 --- a/src/ftm1/conf/mod.rs +++ b/src/ftm1/conf/mod.rs @@ -22,7 +22,9 @@ impl super::CONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -107,10 +109,8 @@ impl GTBEOUTR { #[doc = "Possible values of the field `ITRIGR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ITRIGRR { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -229,10 +229,8 @@ impl<'a> _GTBEOUTW<'a> { } #[doc = "Values that can be written to the field `ITRIGR`"] pub enum ITRIGRW { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRW { #[allow(missing_docs)] diff --git a/src/ftm1/deadtime/mod.rs b/src/ftm1/deadtime/mod.rs index 3a9b0cf..f1dfdde 100644 --- a/src/ftm1/deadtime/mod.rs +++ b/src/ftm1/deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/exttrig/mod.rs b/src/ftm1/exttrig/mod.rs index cbd52f1..d85e308 100644 --- a/src/ftm1/exttrig/mod.rs +++ b/src/ftm1/exttrig/mod.rs @@ -22,7 +22,9 @@ impl super::EXTTRIG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EXTTRIG { #[doc = "Possible values of the field `CH2TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH2TRIGR { #[doc = "Possible values of the field `CH3TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH3TRIGR { #[doc = "Possible values of the field `CH4TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH4TRIGR { #[doc = "Possible values of the field `CH5TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH5TRIGR { #[doc = "Possible values of the field `CH0TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH0TRIGR { #[doc = "Possible values of the field `CH1TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH1TRIGR { #[doc = "Possible values of the field `INITTRIGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INITTRIGENR { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl INITTRIGENR { #[doc = "Possible values of the field `TRIGF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGFR { - #[doc = "No channel trigger was generated."] - _0, - #[doc = "A channel trigger was generated."] - _1, + #[doc = "No channel trigger was generated."] _0, + #[doc = "A channel trigger was generated."] _1, } impl TRIGFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl TRIGFR { #[doc = "Possible values of the field `CH6TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH6TRIGR { #[doc = "Possible values of the field `CH7TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -512,10 +494,8 @@ impl CH7TRIGR { } #[doc = "Values that can be written to the field `CH2TRIG`"] pub enum CH2TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGW { #[allow(missing_docs)] @@ -570,10 +550,8 @@ impl<'a> _CH2TRIGW<'a> { } #[doc = "Values that can be written to the field `CH3TRIG`"] pub enum CH3TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGW { #[allow(missing_docs)] @@ -628,10 +606,8 @@ impl<'a> _CH3TRIGW<'a> { } #[doc = "Values that can be written to the field `CH4TRIG`"] pub enum CH4TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGW { #[allow(missing_docs)] @@ -686,10 +662,8 @@ impl<'a> _CH4TRIGW<'a> { } #[doc = "Values that can be written to the field `CH5TRIG`"] pub enum CH5TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGW { #[allow(missing_docs)] @@ -744,10 +718,8 @@ impl<'a> _CH5TRIGW<'a> { } #[doc = "Values that can be written to the field `CH0TRIG`"] pub enum CH0TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGW { #[allow(missing_docs)] @@ -802,10 +774,8 @@ impl<'a> _CH0TRIGW<'a> { } #[doc = "Values that can be written to the field `CH1TRIG`"] pub enum CH1TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGW { #[allow(missing_docs)] @@ -860,10 +830,8 @@ impl<'a> _CH1TRIGW<'a> { } #[doc = "Values that can be written to the field `INITTRIGEN`"] pub enum INITTRIGENW { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENW { #[allow(missing_docs)] @@ -918,10 +886,8 @@ impl<'a> _INITTRIGENW<'a> { } #[doc = "Values that can be written to the field `CH6TRIG`"] pub enum CH6TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGW { #[allow(missing_docs)] @@ -976,10 +942,8 @@ impl<'a> _CH6TRIGW<'a> { } #[doc = "Values that can be written to the field `CH7TRIG`"] pub enum CH7TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGW { #[allow(missing_docs)] diff --git a/src/ftm1/filter/mod.rs b/src/ftm1/filter/mod.rs index 30911ac..19ef737 100644 --- a/src/ftm1/filter/mod.rs +++ b/src/ftm1/filter/mod.rs @@ -22,7 +22,9 @@ impl super::FILTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/fltctrl/mod.rs b/src/ftm1/fltctrl/mod.rs index d85ff3c..792a4e9 100644 --- a/src/ftm1/fltctrl/mod.rs +++ b/src/ftm1/fltctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FLTCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTCTRL { #[doc = "Possible values of the field `FAULT0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT0ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULT0ENR { #[doc = "Possible values of the field `FAULT1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT1ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULT1ENR { #[doc = "Possible values of the field `FAULT2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT2ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULT2ENR { #[doc = "Possible values of the field `FAULT3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT3ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULT3ENR { #[doc = "Possible values of the field `FFLTR0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR0ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FFLTR0ENR { #[doc = "Possible values of the field `FFLTR1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR1ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl FFLTR1ENR { #[doc = "Possible values of the field `FFLTR2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR2ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FFLTR2ENR { #[doc = "Possible values of the field `FFLTR3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR3ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +418,7 @@ impl FFVALR { pub enum FSTATER { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -476,10 +461,8 @@ impl FSTATER { } #[doc = "Values that can be written to the field `FAULT0EN`"] pub enum FAULT0ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENW { #[allow(missing_docs)] @@ -534,10 +517,8 @@ impl<'a> _FAULT0ENW<'a> { } #[doc = "Values that can be written to the field `FAULT1EN`"] pub enum FAULT1ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENW { #[allow(missing_docs)] @@ -592,10 +573,8 @@ impl<'a> _FAULT1ENW<'a> { } #[doc = "Values that can be written to the field `FAULT2EN`"] pub enum FAULT2ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENW { #[allow(missing_docs)] @@ -650,10 +629,8 @@ impl<'a> _FAULT2ENW<'a> { } #[doc = "Values that can be written to the field `FAULT3EN`"] pub enum FAULT3ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENW { #[allow(missing_docs)] @@ -708,10 +685,8 @@ impl<'a> _FAULT3ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR0EN`"] pub enum FFLTR0ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENW { #[allow(missing_docs)] @@ -766,10 +741,8 @@ impl<'a> _FFLTR0ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR1EN`"] pub enum FFLTR1ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENW { #[allow(missing_docs)] @@ -824,10 +797,8 @@ impl<'a> _FFLTR1ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR2EN`"] pub enum FFLTR2ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENW { #[allow(missing_docs)] @@ -882,10 +853,8 @@ impl<'a> _FFLTR2ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR3EN`"] pub enum FFLTR3ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENW { #[allow(missing_docs)] @@ -957,8 +926,7 @@ impl<'a> _FFVALW<'a> { pub enum FSTATEW { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATEW { #[allow(missing_docs)] diff --git a/src/ftm1/fltpol/mod.rs b/src/ftm1/fltpol/mod.rs index 5b0170d..d99042f 100644 --- a/src/ftm1/fltpol/mod.rs +++ b/src/ftm1/fltpol/mod.rs @@ -22,7 +22,9 @@ impl super::FLTPOL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTPOL { #[doc = "Possible values of the field `FLT0POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT0POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FLT0POLR { #[doc = "Possible values of the field `FLT1POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT1POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FLT1POLR { #[doc = "Possible values of the field `FLT2POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT2POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FLT2POLR { #[doc = "Possible values of the field `FLT3POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT3POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl FLT3POLR { } #[doc = "Values that can be written to the field `FLT0POL`"] pub enum FLT0POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _FLT0POLW<'a> { } #[doc = "Values that can be written to the field `FLT1POL`"] pub enum FLT1POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _FLT1POLW<'a> { } #[doc = "Values that can be written to the field `FLT2POL`"] pub enum FLT2POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _FLT2POLW<'a> { } #[doc = "Values that can be written to the field `FLT3POL`"] pub enum FLT3POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLW { #[allow(missing_docs)] diff --git a/src/ftm1/fms/mod.rs b/src/ftm1/fms/mod.rs index fb65c8b..61915be 100644 --- a/src/ftm1/fms/mod.rs +++ b/src/ftm1/fms/mod.rs @@ -22,7 +22,9 @@ impl super::FMS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FMS { #[doc = "Possible values of the field `FAULTF0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF0R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULTF0R { #[doc = "Possible values of the field `FAULTF1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF1R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULTF1R { #[doc = "Possible values of the field `FAULTF2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF2R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULTF2R { #[doc = "Possible values of the field `FAULTF3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF3R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULTF3R { #[doc = "Possible values of the field `FAULTIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTINR { - #[doc = "The logic OR of the enabled fault inputs is 0."] - _0, - #[doc = "The logic OR of the enabled fault inputs is 1."] - _1, + #[doc = "The logic OR of the enabled fault inputs is 0."] _0, + #[doc = "The logic OR of the enabled fault inputs is 1."] _1, } impl FAULTINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FAULTINR { #[doc = "Possible values of the field `WPEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPENR { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl WPENR { #[doc = "Possible values of the field `FAULTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTFR { - #[doc = "No fault condition was detected."] - _0, - #[doc = "A fault condition was detected."] - _1, + #[doc = "No fault condition was detected."] _0, + #[doc = "A fault condition was detected."] _1, } impl FAULTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -371,10 +359,8 @@ impl FAULTFR { } #[doc = "Values that can be written to the field `WPEN`"] pub enum WPENW { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENW { #[allow(missing_docs)] diff --git a/src/ftm1/hcr/mod.rs b/src/ftm1/hcr/mod.rs index 6f87eca..dfcbde9 100644 --- a/src/ftm1/hcr/mod.rs +++ b/src/ftm1/hcr/mod.rs @@ -22,7 +22,9 @@ impl super::HCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/invctrl/mod.rs b/src/ftm1/invctrl/mod.rs index 23e094b..80e4e01 100644 --- a/src/ftm1/invctrl/mod.rs +++ b/src/ftm1/invctrl/mod.rs @@ -22,7 +22,9 @@ impl super::INVCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::INVCTRL { #[doc = "Possible values of the field `INV0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV0ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl INV0ENR { #[doc = "Possible values of the field `INV1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV1ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INV1ENR { #[doc = "Possible values of the field `INV2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV2ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl INV2ENR { #[doc = "Possible values of the field `INV3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV3ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl INV3ENR { } #[doc = "Values that can be written to the field `INV0EN`"] pub enum INV0ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _INV0ENW<'a> { } #[doc = "Values that can be written to the field `INV1EN`"] pub enum INV1ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _INV1ENW<'a> { } #[doc = "Values that can be written to the field `INV2EN`"] pub enum INV2ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _INV2ENW<'a> { } #[doc = "Values that can be written to the field `INV3EN`"] pub enum INV3ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENW { #[allow(missing_docs)] diff --git a/src/ftm1/mod.rs b/src/ftm1/mod.rs index 445c1aa..294f78f 100644 --- a/src/ftm1/mod.rs +++ b/src/ftm1/mod.rs @@ -2,97 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status And Control"] - pub sc: SC, - #[doc = "0x04 - Counter"] - pub cnt: CNT, - #[doc = "0x08 - Modulo"] - pub mod_: MOD, - #[doc = "0x0c - Channel (n) Status And Control"] - pub c0sc: C0SC, - #[doc = "0x10 - Channel (n) Value"] - pub c0v: C0V, - #[doc = "0x14 - Channel (n) Status And Control"] - pub c1sc: C1SC, - #[doc = "0x18 - Channel (n) Value"] - pub c1v: C1V, - #[doc = "0x1c - Channel (n) Status And Control"] - pub c2sc: C2SC, - #[doc = "0x20 - Channel (n) Value"] - pub c2v: C2V, - #[doc = "0x24 - Channel (n) Status And Control"] - pub c3sc: C3SC, - #[doc = "0x28 - Channel (n) Value"] - pub c3v: C3V, - #[doc = "0x2c - Channel (n) Status And Control"] - pub c4sc: C4SC, - #[doc = "0x30 - Channel (n) Value"] - pub c4v: C4V, - #[doc = "0x34 - Channel (n) Status And Control"] - pub c5sc: C5SC, - #[doc = "0x38 - Channel (n) Value"] - pub c5v: C5V, - #[doc = "0x3c - Channel (n) Status And Control"] - pub c6sc: C6SC, - #[doc = "0x40 - Channel (n) Value"] - pub c6v: C6V, - #[doc = "0x44 - Channel (n) Status And Control"] - pub c7sc: C7SC, - #[doc = "0x48 - Channel (n) Value"] - pub c7v: C7V, - #[doc = "0x4c - Counter Initial Value"] - pub cntin: CNTIN, - #[doc = "0x50 - Capture And Compare Status"] - pub status: STATUS, - #[doc = "0x54 - Features Mode Selection"] - pub mode: MODE, - #[doc = "0x58 - Synchronization"] - pub sync: SYNC, - #[doc = "0x5c - Initial State For Channels Output"] - pub outinit: OUTINIT, - #[doc = "0x60 - Output Mask"] - pub outmask: OUTMASK, - #[doc = "0x64 - Function For Linked Channels"] - pub combine: COMBINE, - #[doc = "0x68 - Deadtime Configuration"] - pub deadtime: DEADTIME, - #[doc = "0x6c - FTM External Trigger"] - pub exttrig: EXTTRIG, - #[doc = "0x70 - Channels Polarity"] - pub pol: POL, - #[doc = "0x74 - Fault Mode Status"] - pub fms: FMS, - #[doc = "0x78 - Input Capture Filter Control"] - pub filter: FILTER, - #[doc = "0x7c - Fault Control"] - pub fltctrl: FLTCTRL, - #[doc = "0x80 - Quadrature Decoder Control And Status"] - pub qdctrl: QDCTRL, - #[doc = "0x84 - Configuration"] - pub conf: CONF, - #[doc = "0x88 - FTM Fault Input Polarity"] - pub fltpol: FLTPOL, - #[doc = "0x8c - Synchronization Configuration"] - pub synconf: SYNCONF, - #[doc = "0x90 - FTM Inverting Control"] - pub invctrl: INVCTRL, - #[doc = "0x94 - FTM Software Output Control"] - pub swoctrl: SWOCTRL, - #[doc = "0x98 - FTM PWM Load"] - pub pwmload: PWMLOAD, - #[doc = "0x9c - Half Cycle Register"] - pub hcr: HCR, - #[doc = "0xa0 - Pair 0 Deadtime Configuration"] - pub pair0deadtime: PAIR0DEADTIME, + #[doc = "0x00 - Status And Control"] pub sc: SC, + #[doc = "0x04 - Counter"] pub cnt: CNT, + #[doc = "0x08 - Modulo"] pub mod_: MOD, + #[doc = "0x0c - Channel (n) Status And Control"] pub c0sc: C0SC, + #[doc = "0x10 - Channel (n) Value"] pub c0v: C0V, + #[doc = "0x14 - Channel (n) Status And Control"] pub c1sc: C1SC, + #[doc = "0x18 - Channel (n) Value"] pub c1v: C1V, + #[doc = "0x1c - Channel (n) Status And Control"] pub c2sc: C2SC, + #[doc = "0x20 - Channel (n) Value"] pub c2v: C2V, + #[doc = "0x24 - Channel (n) Status And Control"] pub c3sc: C3SC, + #[doc = "0x28 - Channel (n) Value"] pub c3v: C3V, + #[doc = "0x2c - Channel (n) Status And Control"] pub c4sc: C4SC, + #[doc = "0x30 - Channel (n) Value"] pub c4v: C4V, + #[doc = "0x34 - Channel (n) Status And Control"] pub c5sc: C5SC, + #[doc = "0x38 - Channel (n) Value"] pub c5v: C5V, + #[doc = "0x3c - Channel (n) Status And Control"] pub c6sc: C6SC, + #[doc = "0x40 - Channel (n) Value"] pub c6v: C6V, + #[doc = "0x44 - Channel (n) Status And Control"] pub c7sc: C7SC, + #[doc = "0x48 - Channel (n) Value"] pub c7v: C7V, + #[doc = "0x4c - Counter Initial Value"] pub cntin: CNTIN, + #[doc = "0x50 - Capture And Compare Status"] pub status: STATUS, + #[doc = "0x54 - Features Mode Selection"] pub mode: MODE, + #[doc = "0x58 - Synchronization"] pub sync: SYNC, + #[doc = "0x5c - Initial State For Channels Output"] pub outinit: OUTINIT, + #[doc = "0x60 - Output Mask"] pub outmask: OUTMASK, + #[doc = "0x64 - Function For Linked Channels"] pub combine: COMBINE, + #[doc = "0x68 - Deadtime Configuration"] pub deadtime: DEADTIME, + #[doc = "0x6c - FTM External Trigger"] pub exttrig: EXTTRIG, + #[doc = "0x70 - Channels Polarity"] pub pol: POL, + #[doc = "0x74 - Fault Mode Status"] pub fms: FMS, + #[doc = "0x78 - Input Capture Filter Control"] pub filter: FILTER, + #[doc = "0x7c - Fault Control"] pub fltctrl: FLTCTRL, + #[doc = "0x80 - Quadrature Decoder Control And Status"] pub qdctrl: QDCTRL, + #[doc = "0x84 - Configuration"] pub conf: CONF, + #[doc = "0x88 - FTM Fault Input Polarity"] pub fltpol: FLTPOL, + #[doc = "0x8c - Synchronization Configuration"] pub synconf: SYNCONF, + #[doc = "0x90 - FTM Inverting Control"] pub invctrl: INVCTRL, + #[doc = "0x94 - FTM Software Output Control"] pub swoctrl: SWOCTRL, + #[doc = "0x98 - FTM PWM Load"] pub pwmload: PWMLOAD, + #[doc = "0x9c - Half Cycle Register"] pub hcr: HCR, + #[doc = "0xa0 - Pair 0 Deadtime Configuration"] pub pair0deadtime: PAIR0DEADTIME, _reserved0: [u8; 4usize], - #[doc = "0xa8 - Pair 1 Deadtime Configuration"] - pub pair1deadtime: PAIR1DEADTIME, + #[doc = "0xa8 - Pair 1 Deadtime Configuration"] pub pair1deadtime: PAIR1DEADTIME, _reserved1: [u8; 4usize], - #[doc = "0xb0 - Pair 2 Deadtime Configuration"] - pub pair2deadtime: PAIR2DEADTIME, + #[doc = "0xb0 - Pair 2 Deadtime Configuration"] pub pair2deadtime: PAIR2DEADTIME, _reserved2: [u8; 4usize], - #[doc = "0xb8 - Pair 3 Deadtime Configuration"] - pub pair3deadtime: PAIR3DEADTIME, + #[doc = "0xb8 - Pair 3 Deadtime Configuration"] pub pair3deadtime: PAIR3DEADTIME, } #[doc = "Status And Control"] pub struct SC { diff --git a/src/ftm1/mod_/mod.rs b/src/ftm1/mod_/mod.rs index 9ef76ef..448895c 100644 --- a/src/ftm1/mod_/mod.rs +++ b/src/ftm1/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm1/mode/mod.rs b/src/ftm1/mode/mod.rs index 6a8e2ac..c4bd468 100644 --- a/src/ftm1/mode/mod.rs +++ b/src/ftm1/mode/mod.rs @@ -22,7 +22,9 @@ impl super::MODE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MODE { #[doc = "Possible values of the field `FTMEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTMENR { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FTMENR { #[doc = "Possible values of the field `WPDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPDISR { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl PWMSYNCR { #[doc = "Possible values of the field `CAPTEST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CAPTESTR { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,8 +227,7 @@ impl CAPTESTR { #[doc = "Possible values of the field `FAULTM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTMR { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -287,10 +282,8 @@ impl FAULTMR { #[doc = "Possible values of the field `FAULTIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTIER { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -333,10 +326,8 @@ impl FAULTIER { } #[doc = "Values that can be written to the field `FTMEN`"] pub enum FTMENW { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENW { #[allow(missing_docs)] @@ -414,10 +405,8 @@ impl<'a> _INITW<'a> { } #[doc = "Values that can be written to the field `WPDIS`"] pub enum WPDISW { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISW { #[allow(missing_docs)] @@ -530,10 +519,8 @@ impl<'a> _PWMSYNCW<'a> { } #[doc = "Values that can be written to the field `CAPTEST`"] pub enum CAPTESTW { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTW { #[allow(missing_docs)] @@ -588,8 +575,7 @@ impl<'a> _CAPTESTW<'a> { } #[doc = "Values that can be written to the field `FAULTM`"] pub enum FAULTMW { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -654,10 +640,8 @@ impl<'a> _FAULTMW<'a> { } #[doc = "Values that can be written to the field `FAULTIE`"] pub enum FAULTIEW { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIEW { #[allow(missing_docs)] diff --git a/src/ftm1/outinit/mod.rs b/src/ftm1/outinit/mod.rs index 5b3b985..10e2df4 100644 --- a/src/ftm1/outinit/mod.rs +++ b/src/ftm1/outinit/mod.rs @@ -22,7 +22,9 @@ impl super::OUTINIT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTINIT { #[doc = "Possible values of the field `CH0OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OIR { #[doc = "Possible values of the field `CH1OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OIR { #[doc = "Possible values of the field `CH2OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OIR { #[doc = "Possible values of the field `CH3OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OIR { #[doc = "Possible values of the field `CH4OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OIR { #[doc = "Possible values of the field `CH5OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OIR { #[doc = "Possible values of the field `CH6OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OIR { #[doc = "Possible values of the field `CH7OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OIR { } #[doc = "Values that can be written to the field `CH0OI`"] pub enum CH0OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OIW<'a> { } #[doc = "Values that can be written to the field `CH1OI`"] pub enum CH1OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OIW<'a> { } #[doc = "Values that can be written to the field `CH2OI`"] pub enum CH2OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OIW<'a> { } #[doc = "Values that can be written to the field `CH3OI`"] pub enum CH3OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OIW<'a> { } #[doc = "Values that can be written to the field `CH4OI`"] pub enum CH4OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OIW<'a> { } #[doc = "Values that can be written to the field `CH5OI`"] pub enum CH5OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OIW<'a> { } #[doc = "Values that can be written to the field `CH6OI`"] pub enum CH6OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OIW<'a> { } #[doc = "Values that can be written to the field `CH7OI`"] pub enum CH7OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIW { #[allow(missing_docs)] diff --git a/src/ftm1/outmask/mod.rs b/src/ftm1/outmask/mod.rs index f9a4723..6d525e0 100644 --- a/src/ftm1/outmask/mod.rs +++ b/src/ftm1/outmask/mod.rs @@ -22,7 +22,9 @@ impl super::OUTMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTMASK { #[doc = "Possible values of the field `CH0OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OMR { #[doc = "Possible values of the field `CH1OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OMR { #[doc = "Possible values of the field `CH2OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OMR { #[doc = "Possible values of the field `CH3OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OMR { #[doc = "Possible values of the field `CH4OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OMR { #[doc = "Possible values of the field `CH5OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OMR { #[doc = "Possible values of the field `CH6OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OMR { #[doc = "Possible values of the field `CH7OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OMR { } #[doc = "Values that can be written to the field `CH0OM`"] pub enum CH0OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OMW<'a> { } #[doc = "Values that can be written to the field `CH1OM`"] pub enum CH1OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OMW<'a> { } #[doc = "Values that can be written to the field `CH2OM`"] pub enum CH2OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OMW<'a> { } #[doc = "Values that can be written to the field `CH3OM`"] pub enum CH3OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OMW<'a> { } #[doc = "Values that can be written to the field `CH4OM`"] pub enum CH4OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OMW<'a> { } #[doc = "Values that can be written to the field `CH5OM`"] pub enum CH5OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OMW<'a> { } #[doc = "Values that can be written to the field `CH6OM`"] pub enum CH6OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OMW<'a> { } #[doc = "Values that can be written to the field `CH7OM`"] pub enum CH7OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMW { #[allow(missing_docs)] diff --git a/src/ftm1/pair0deadtime/mod.rs b/src/ftm1/pair0deadtime/mod.rs index 57b7430..24b3a06 100644 --- a/src/ftm1/pair0deadtime/mod.rs +++ b/src/ftm1/pair0deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR0DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/pair1deadtime/mod.rs b/src/ftm1/pair1deadtime/mod.rs index 54a2334..bd244e2 100644 --- a/src/ftm1/pair1deadtime/mod.rs +++ b/src/ftm1/pair1deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR1DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/pair2deadtime/mod.rs b/src/ftm1/pair2deadtime/mod.rs index 5073dba..9e96c87 100644 --- a/src/ftm1/pair2deadtime/mod.rs +++ b/src/ftm1/pair2deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR2DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/pair3deadtime/mod.rs b/src/ftm1/pair3deadtime/mod.rs index bcb2471..d925ba8 100644 --- a/src/ftm1/pair3deadtime/mod.rs +++ b/src/ftm1/pair3deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR3DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/pol/mod.rs b/src/ftm1/pol/mod.rs index 822ce37..56d0d5a 100644 --- a/src/ftm1/pol/mod.rs +++ b/src/ftm1/pol/mod.rs @@ -22,7 +22,9 @@ impl super::POL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::POL { #[doc = "Possible values of the field `POL0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL0R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl POL0R { #[doc = "Possible values of the field `POL1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL1R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl POL1R { #[doc = "Possible values of the field `POL2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL2R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl POL2R { #[doc = "Possible values of the field `POL3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL3R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl POL3R { #[doc = "Possible values of the field `POL4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL4R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl POL4R { #[doc = "Possible values of the field `POL5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL5R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl POL5R { #[doc = "Possible values of the field `POL6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL6R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl POL6R { #[doc = "Possible values of the field `POL7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL7R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl POL7R { } #[doc = "Values that can be written to the field `POL0`"] pub enum POL0W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0W { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _POL0W<'a> { } #[doc = "Values that can be written to the field `POL1`"] pub enum POL1W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1W { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _POL1W<'a> { } #[doc = "Values that can be written to the field `POL2`"] pub enum POL2W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2W { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _POL2W<'a> { } #[doc = "Values that can be written to the field `POL3`"] pub enum POL3W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3W { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _POL3W<'a> { } #[doc = "Values that can be written to the field `POL4`"] pub enum POL4W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4W { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _POL4W<'a> { } #[doc = "Values that can be written to the field `POL5`"] pub enum POL5W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5W { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _POL5W<'a> { } #[doc = "Values that can be written to the field `POL6`"] pub enum POL6W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6W { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _POL6W<'a> { } #[doc = "Values that can be written to the field `POL7`"] pub enum POL7W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7W { #[allow(missing_docs)] diff --git a/src/ftm1/pwmload/mod.rs b/src/ftm1/pwmload/mod.rs index c95d704..e3ad1a9 100644 --- a/src/ftm1/pwmload/mod.rs +++ b/src/ftm1/pwmload/mod.rs @@ -22,7 +22,9 @@ impl super::PWMLOAD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PWMLOAD { #[doc = "Possible values of the field `CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0SELR { #[doc = "Possible values of the field `CH1SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1SELR { #[doc = "Possible values of the field `CH2SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2SELR { #[doc = "Possible values of the field `CH3SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3SELR { #[doc = "Possible values of the field `CH4SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4SELR { #[doc = "Possible values of the field `CH5SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5SELR { #[doc = "Possible values of the field `CH6SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6SELR { #[doc = "Possible values of the field `CH7SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7SELR { #[doc = "Possible values of the field `HCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HCSELR { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl HCSELR { #[doc = "Possible values of the field `LDOK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LDOKR { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,8 +495,7 @@ impl LDOKR { #[doc = "Possible values of the field `GLEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GLENR { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -559,10 +540,8 @@ impl GLENR { } #[doc = "Values that can be written to the field `CH0SEL`"] pub enum CH0SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELW { #[allow(missing_docs)] @@ -617,10 +596,8 @@ impl<'a> _CH0SELW<'a> { } #[doc = "Values that can be written to the field `CH1SEL`"] pub enum CH1SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELW { #[allow(missing_docs)] @@ -675,10 +652,8 @@ impl<'a> _CH1SELW<'a> { } #[doc = "Values that can be written to the field `CH2SEL`"] pub enum CH2SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELW { #[allow(missing_docs)] @@ -733,10 +708,8 @@ impl<'a> _CH2SELW<'a> { } #[doc = "Values that can be written to the field `CH3SEL`"] pub enum CH3SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELW { #[allow(missing_docs)] @@ -791,10 +764,8 @@ impl<'a> _CH3SELW<'a> { } #[doc = "Values that can be written to the field `CH4SEL`"] pub enum CH4SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELW { #[allow(missing_docs)] @@ -849,10 +820,8 @@ impl<'a> _CH4SELW<'a> { } #[doc = "Values that can be written to the field `CH5SEL`"] pub enum CH5SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELW { #[allow(missing_docs)] @@ -907,10 +876,8 @@ impl<'a> _CH5SELW<'a> { } #[doc = "Values that can be written to the field `CH6SEL`"] pub enum CH6SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELW { #[allow(missing_docs)] @@ -965,10 +932,8 @@ impl<'a> _CH6SELW<'a> { } #[doc = "Values that can be written to the field `CH7SEL`"] pub enum CH7SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELW { #[allow(missing_docs)] @@ -1023,10 +988,8 @@ impl<'a> _CH7SELW<'a> { } #[doc = "Values that can be written to the field `HCSEL`"] pub enum HCSELW { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELW { #[allow(missing_docs)] @@ -1081,10 +1044,8 @@ impl<'a> _HCSELW<'a> { } #[doc = "Values that can be written to the field `LDOK`"] pub enum LDOKW { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKW { #[allow(missing_docs)] @@ -1139,8 +1100,7 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `GLEN`"] pub enum GLENW { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -1197,10 +1157,8 @@ impl<'a> _GLENW<'a> { } #[doc = "Values that can be written to the field `GLDOK`"] pub enum GLDOKW { - #[doc = "No action."] - _0, - #[doc = "LDOK bit is set."] - _1, + #[doc = "No action."] _0, + #[doc = "LDOK bit is set."] _1, } impl GLDOKW { #[allow(missing_docs)] diff --git a/src/ftm1/qdctrl/mod.rs b/src/ftm1/qdctrl/mod.rs index dee224c..cccabd7 100644 --- a/src/ftm1/qdctrl/mod.rs +++ b/src/ftm1/qdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::QDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::QDCTRL { #[doc = "Possible values of the field `QUADEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADENR { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +137,8 @@ impl TOFDIRR { #[doc = "Possible values of the field `QUADIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADIRR { - #[doc = "Counting direction is decreasing (FTM counter decrement)."] - _0, - #[doc = "Counting direction is increasing (FTM counter increment)."] - _1, + #[doc = "Counting direction is decreasing (FTM counter decrement)."] _0, + #[doc = "Counting direction is increasing (FTM counter increment)."] _1, } impl QUADIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl QUADIRR { #[doc = "Possible values of the field `QUADMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADMODER { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +321,8 @@ impl PHAPOLR { #[doc = "Possible values of the field `PHBFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHBFLTRENR { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl PHBFLTRENR { #[doc = "Possible values of the field `PHAFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHAFLTRENR { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +410,8 @@ impl PHAFLTRENR { } #[doc = "Values that can be written to the field `QUADEN`"] pub enum QUADENW { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENW { #[allow(missing_docs)] @@ -476,10 +466,8 @@ impl<'a> _QUADENW<'a> { } #[doc = "Values that can be written to the field `QUADMODE`"] pub enum QUADMODEW { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODEW { #[allow(missing_docs)] @@ -650,10 +638,8 @@ impl<'a> _PHAPOLW<'a> { } #[doc = "Values that can be written to the field `PHBFLTREN`"] pub enum PHBFLTRENW { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENW { #[allow(missing_docs)] @@ -708,10 +694,8 @@ impl<'a> _PHBFLTRENW<'a> { } #[doc = "Values that can be written to the field `PHAFLTREN`"] pub enum PHAFLTRENW { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENW { #[allow(missing_docs)] diff --git a/src/ftm1/sc/mod.rs b/src/ftm1/sc/mod.rs index 24d7055..abe8d66 100644 --- a/src/ftm1/sc/mod.rs +++ b/src/ftm1/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SC { #[doc = "Possible values of the field `PS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PSR { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSR { #[doc = r" Value of the field as raw bits"] @@ -135,14 +129,10 @@ impl PSR { #[doc = "Possible values of the field `CLKS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKSR { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSR { #[doc = r" Value of the field as raw bits"] @@ -191,10 +181,8 @@ impl CLKSR { #[doc = "Possible values of the field `CPWMS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPWMSR { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -238,10 +226,8 @@ impl CPWMSR { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -285,10 +271,8 @@ impl RIER { #[doc = "Possible values of the field `RF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFR { - #[doc = "A selected reload point did not happen."] - _0, - #[doc = "A selected reload point happened."] - _1, + #[doc = "A selected reload point did not happen."] _0, + #[doc = "A selected reload point happened."] _1, } impl RFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -332,10 +316,8 @@ impl RFR { #[doc = "Possible values of the field `TOIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOIER { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -379,10 +361,8 @@ impl TOIER { #[doc = "Possible values of the field `TOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOFR { - #[doc = "FTM counter has not overflowed."] - _0, - #[doc = "FTM counter has overflowed."] - _1, + #[doc = "FTM counter has not overflowed."] _0, + #[doc = "FTM counter has overflowed."] _1, } impl TOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -426,10 +406,8 @@ impl TOFR { #[doc = "Possible values of the field `PWMEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN0R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -473,10 +451,8 @@ impl PWMEN0R { #[doc = "Possible values of the field `PWMEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN1R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -520,10 +496,8 @@ impl PWMEN1R { #[doc = "Possible values of the field `PWMEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN2R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -567,10 +541,8 @@ impl PWMEN2R { #[doc = "Possible values of the field `PWMEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN3R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -614,10 +586,8 @@ impl PWMEN3R { #[doc = "Possible values of the field `PWMEN4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN4R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -661,10 +631,8 @@ impl PWMEN4R { #[doc = "Possible values of the field `PWMEN5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN5R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -708,10 +676,8 @@ impl PWMEN5R { #[doc = "Possible values of the field `PWMEN6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN6R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -755,10 +721,8 @@ impl PWMEN6R { #[doc = "Possible values of the field `PWMEN7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN7R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -802,38 +766,22 @@ impl PWMEN7R { #[doc = "Possible values of the field `FLTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTPSR { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSR { #[doc = r" Value of the field as raw bits"] @@ -965,22 +913,14 @@ impl FLTPSR { } #[doc = "Values that can be written to the field `PS`"] pub enum PSW { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSW { #[allow(missing_docs)] @@ -1063,14 +1003,10 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `CLKS`"] pub enum CLKSW { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSW { #[allow(missing_docs)] @@ -1129,10 +1065,8 @@ impl<'a> _CLKSW<'a> { } #[doc = "Values that can be written to the field `CPWMS`"] pub enum CPWMSW { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSW { #[allow(missing_docs)] @@ -1187,10 +1121,8 @@ impl<'a> _CPWMSW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIEW { #[allow(missing_docs)] @@ -1245,10 +1177,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TOIE`"] pub enum TOIEW { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIEW { #[allow(missing_docs)] @@ -1303,10 +1233,8 @@ impl<'a> _TOIEW<'a> { } #[doc = "Values that can be written to the field `PWMEN0`"] pub enum PWMEN0W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0W { #[allow(missing_docs)] @@ -1361,10 +1289,8 @@ impl<'a> _PWMEN0W<'a> { } #[doc = "Values that can be written to the field `PWMEN1`"] pub enum PWMEN1W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1W { #[allow(missing_docs)] @@ -1419,10 +1345,8 @@ impl<'a> _PWMEN1W<'a> { } #[doc = "Values that can be written to the field `PWMEN2`"] pub enum PWMEN2W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2W { #[allow(missing_docs)] @@ -1477,10 +1401,8 @@ impl<'a> _PWMEN2W<'a> { } #[doc = "Values that can be written to the field `PWMEN3`"] pub enum PWMEN3W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3W { #[allow(missing_docs)] @@ -1535,10 +1457,8 @@ impl<'a> _PWMEN3W<'a> { } #[doc = "Values that can be written to the field `PWMEN4`"] pub enum PWMEN4W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4W { #[allow(missing_docs)] @@ -1593,10 +1513,8 @@ impl<'a> _PWMEN4W<'a> { } #[doc = "Values that can be written to the field `PWMEN5`"] pub enum PWMEN5W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5W { #[allow(missing_docs)] @@ -1651,10 +1569,8 @@ impl<'a> _PWMEN5W<'a> { } #[doc = "Values that can be written to the field `PWMEN6`"] pub enum PWMEN6W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6W { #[allow(missing_docs)] @@ -1709,10 +1625,8 @@ impl<'a> _PWMEN6W<'a> { } #[doc = "Values that can be written to the field `PWMEN7`"] pub enum PWMEN7W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7W { #[allow(missing_docs)] @@ -1767,38 +1681,22 @@ impl<'a> _PWMEN7W<'a> { } #[doc = "Values that can be written to the field `FLTPS`"] pub enum FLTPSW { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSW { #[allow(missing_docs)] diff --git a/src/ftm1/status/mod.rs b/src/ftm1/status/mod.rs index a808509..bc08657 100644 --- a/src/ftm1/status/mod.rs +++ b/src/ftm1/status/mod.rs @@ -6,16 +6,16 @@ impl super::STATUS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `CH0F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH0FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl CH0FR { #[doc = "Possible values of the field `CH1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl CH1FR { #[doc = "Possible values of the field `CH2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl CH2FR { #[doc = "Possible values of the field `CH3F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH3FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl CH3FR { #[doc = "Possible values of the field `CH4F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH4FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl CH4FR { #[doc = "Possible values of the field `CH5F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH5FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CH5FR { #[doc = "Possible values of the field `CH6F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH6FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl CH6FR { #[doc = "Possible values of the field `CH7F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH7FR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/ftm1/swoctrl/mod.rs b/src/ftm1/swoctrl/mod.rs index 247b3ec..49d6fc8 100644 --- a/src/ftm1/swoctrl/mod.rs +++ b/src/ftm1/swoctrl/mod.rs @@ -22,7 +22,9 @@ impl super::SWOCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SWOCTRL { #[doc = "Possible values of the field `CH0OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OCR { #[doc = "Possible values of the field `CH1OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OCR { #[doc = "Possible values of the field `CH2OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OCR { #[doc = "Possible values of the field `CH3OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OCR { #[doc = "Possible values of the field `CH4OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OCR { #[doc = "Possible values of the field `CH5OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OCR { #[doc = "Possible values of the field `CH6OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OCR { #[doc = "Possible values of the field `CH7OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7OCR { #[doc = "Possible values of the field `CH0OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH0OCVR { #[doc = "Possible values of the field `CH1OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl CH1OCVR { #[doc = "Possible values of the field `CH2OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl CH2OCVR { #[doc = "Possible values of the field `CH3OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl CH3OCVR { #[doc = "Possible values of the field `CH4OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl CH4OCVR { #[doc = "Possible values of the field `CH5OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl CH5OCVR { #[doc = "Possible values of the field `CH6OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl CH6OCVR { #[doc = "Possible values of the field `CH7OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl CH7OCVR { } #[doc = "Values that can be written to the field `CH0OC`"] pub enum CH0OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCW { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _CH0OCW<'a> { } #[doc = "Values that can be written to the field `CH1OC`"] pub enum CH1OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCW { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _CH1OCW<'a> { } #[doc = "Values that can be written to the field `CH2OC`"] pub enum CH2OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCW { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _CH2OCW<'a> { } #[doc = "Values that can be written to the field `CH3OC`"] pub enum CH3OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCW { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _CH3OCW<'a> { } #[doc = "Values that can be written to the field `CH4OC`"] pub enum CH4OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCW { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _CH4OCW<'a> { } #[doc = "Values that can be written to the field `CH5OC`"] pub enum CH5OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCW { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _CH5OCW<'a> { } #[doc = "Values that can be written to the field `CH6OC`"] pub enum CH6OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCW { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _CH6OCW<'a> { } #[doc = "Values that can be written to the field `CH7OC`"] pub enum CH7OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCW { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _CH7OCW<'a> { } #[doc = "Values that can be written to the field `CH0OCV`"] pub enum CH0OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVW { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _CH0OCVW<'a> { } #[doc = "Values that can be written to the field `CH1OCV`"] pub enum CH1OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVW { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _CH1OCVW<'a> { } #[doc = "Values that can be written to the field `CH2OCV`"] pub enum CH2OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVW { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _CH2OCVW<'a> { } #[doc = "Values that can be written to the field `CH3OCV`"] pub enum CH3OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVW { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _CH3OCVW<'a> { } #[doc = "Values that can be written to the field `CH4OCV`"] pub enum CH4OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVW { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _CH4OCVW<'a> { } #[doc = "Values that can be written to the field `CH5OCV`"] pub enum CH5OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVW { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _CH5OCVW<'a> { } #[doc = "Values that can be written to the field `CH6OCV`"] pub enum CH6OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVW { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _CH6OCVW<'a> { } #[doc = "Values that can be written to the field `CH7OCV`"] pub enum CH7OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVW { #[allow(missing_docs)] diff --git a/src/ftm1/sync/mod.rs b/src/ftm1/sync/mod.rs index b46f9f6..add847a 100644 --- a/src/ftm1/sync/mod.rs +++ b/src/ftm1/sync/mod.rs @@ -22,7 +22,9 @@ impl super::SYNC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SYNC { #[doc = "Possible values of the field `CNTMIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMINR { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CNTMINR { #[doc = "Possible values of the field `CNTMAX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMAXR { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,8 +135,7 @@ impl CNTMAXR { #[doc = "Possible values of the field `REINIT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REINITR { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -231,10 +228,8 @@ impl SYNCHOMR { #[doc = "Possible values of the field `TRIG0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG0R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +273,8 @@ impl TRIG0R { #[doc = "Possible values of the field `TRIG1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG1R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +318,8 @@ impl TRIG1R { #[doc = "Possible values of the field `TRIG2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG2R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +363,8 @@ impl TRIG2R { #[doc = "Possible values of the field `SWSYNC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSYNCR { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +407,8 @@ impl SWSYNCR { } #[doc = "Values that can be written to the field `CNTMIN`"] pub enum CNTMINW { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINW { #[allow(missing_docs)] @@ -476,10 +463,8 @@ impl<'a> _CNTMINW<'a> { } #[doc = "Values that can be written to the field `CNTMAX`"] pub enum CNTMAXW { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXW { #[allow(missing_docs)] @@ -534,8 +519,7 @@ impl<'a> _CNTMAXW<'a> { } #[doc = "Values that can be written to the field `REINIT`"] pub enum REINITW { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -650,10 +634,8 @@ impl<'a> _SYNCHOMW<'a> { } #[doc = "Values that can be written to the field `TRIG0`"] pub enum TRIG0W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0W { #[allow(missing_docs)] @@ -708,10 +690,8 @@ impl<'a> _TRIG0W<'a> { } #[doc = "Values that can be written to the field `TRIG1`"] pub enum TRIG1W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1W { #[allow(missing_docs)] @@ -766,10 +746,8 @@ impl<'a> _TRIG1W<'a> { } #[doc = "Values that can be written to the field `TRIG2`"] pub enum TRIG2W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2W { #[allow(missing_docs)] @@ -824,10 +802,8 @@ impl<'a> _TRIG2W<'a> { } #[doc = "Values that can be written to the field `SWSYNC`"] pub enum SWSYNCW { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCW { #[allow(missing_docs)] diff --git a/src/ftm1/synconf/mod.rs b/src/ftm1/synconf/mod.rs index 08257bc..8b29129 100644 --- a/src/ftm1/synconf/mod.rs +++ b/src/ftm1/synconf/mod.rs @@ -22,7 +22,9 @@ impl super::SYNCONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -92,8 +94,7 @@ impl HWTRIGMODER { pub enum CNTINCR { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -139,8 +140,7 @@ impl CNTINCR { pub enum INVCR { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -186,8 +186,7 @@ impl INVCR { pub enum SWOCR { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +230,8 @@ impl SWOCR { #[doc = "Possible values of the field `SYNCMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCMODER { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +275,8 @@ impl SYNCMODER { #[doc = "Possible values of the field `SWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRSTCNTR { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -327,8 +322,7 @@ impl SWRSTCNTR { pub enum SWWRBUFR { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl SWWRBUFR { #[doc = "Possible values of the field `SWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWOMR { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +411,8 @@ impl SWOMR { #[doc = "Possible values of the field `SWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWINVCR { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +456,8 @@ impl SWINVCR { #[doc = "Possible values of the field `SWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSOCR { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +501,8 @@ impl SWSOCR { #[doc = "Possible values of the field `HWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWRSTCNTR { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -562,8 +548,7 @@ impl HWRSTCNTR { pub enum HWWRBUFR { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +592,8 @@ impl HWWRBUFR { #[doc = "Possible values of the field `HWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWOMR { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +637,8 @@ impl HWOMR { #[doc = "Possible values of the field `HWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWINVCR { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +682,8 @@ impl HWINVCR { #[doc = "Possible values of the field `HWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWSOCR { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> { pub enum CNTINCW { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCW { #[allow(missing_docs)] @@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> { pub enum INVCW { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCW { #[allow(missing_docs)] @@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> { pub enum SWOCW { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCW { #[allow(missing_docs)] @@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> { } #[doc = "Values that can be written to the field `SYNCMODE`"] pub enum SYNCMODEW { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODEW { #[allow(missing_docs)] @@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> { } #[doc = "Values that can be written to the field `SWRSTCNT`"] pub enum SWRSTCNTW { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTW { #[allow(missing_docs)] @@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> { pub enum SWWRBUFW { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFW { #[allow(missing_docs)] @@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> { } #[doc = "Values that can be written to the field `SWOM`"] pub enum SWOMW { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMW { #[allow(missing_docs)] @@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> { } #[doc = "Values that can be written to the field `SWINVC`"] pub enum SWINVCW { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCW { #[allow(missing_docs)] @@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> { } #[doc = "Values that can be written to the field `SWSOC`"] pub enum SWSOCW { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCW { #[allow(missing_docs)] @@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> { } #[doc = "Values that can be written to the field `HWRSTCNT`"] pub enum HWRSTCNTW { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTW { #[allow(missing_docs)] @@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> { pub enum HWWRBUFW { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFW { #[allow(missing_docs)] @@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> { } #[doc = "Values that can be written to the field `HWOM`"] pub enum HWOMW { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMW { #[allow(missing_docs)] @@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> { } #[doc = "Values that can be written to the field `HWINVC`"] pub enum HWINVCW { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCW { #[allow(missing_docs)] @@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> { } #[doc = "Values that can be written to the field `HWSOC`"] pub enum HWSOCW { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCW { #[allow(missing_docs)] diff --git a/src/ftm2/c0sc/mod.rs b/src/ftm2/c0sc/mod.rs index ceb657c..174b306 100644 --- a/src/ftm2/c0sc/mod.rs +++ b/src/ftm2/c0sc/mod.rs @@ -22,7 +22,9 @@ impl super::C0SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C0SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c0v/mod.rs b/src/ftm2/c0v/mod.rs index 9c5f35e..7138aeb 100644 --- a/src/ftm2/c0v/mod.rs +++ b/src/ftm2/c0v/mod.rs @@ -22,7 +22,9 @@ impl super::C0V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c1sc/mod.rs b/src/ftm2/c1sc/mod.rs index 75125c1..12f080d 100644 --- a/src/ftm2/c1sc/mod.rs +++ b/src/ftm2/c1sc/mod.rs @@ -22,7 +22,9 @@ impl super::C1SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C1SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c1v/mod.rs b/src/ftm2/c1v/mod.rs index 787745f..248a2b1 100644 --- a/src/ftm2/c1v/mod.rs +++ b/src/ftm2/c1v/mod.rs @@ -22,7 +22,9 @@ impl super::C1V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c2sc/mod.rs b/src/ftm2/c2sc/mod.rs index fa12b2b..e58d4c7 100644 --- a/src/ftm2/c2sc/mod.rs +++ b/src/ftm2/c2sc/mod.rs @@ -22,7 +22,9 @@ impl super::C2SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C2SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c2v/mod.rs b/src/ftm2/c2v/mod.rs index 9e3c3cd..b8ffb12 100644 --- a/src/ftm2/c2v/mod.rs +++ b/src/ftm2/c2v/mod.rs @@ -22,7 +22,9 @@ impl super::C2V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c3sc/mod.rs b/src/ftm2/c3sc/mod.rs index 2eaf887..6651e54 100644 --- a/src/ftm2/c3sc/mod.rs +++ b/src/ftm2/c3sc/mod.rs @@ -22,7 +22,9 @@ impl super::C3SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C3SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c3v/mod.rs b/src/ftm2/c3v/mod.rs index 43fb0c2..5cba611 100644 --- a/src/ftm2/c3v/mod.rs +++ b/src/ftm2/c3v/mod.rs @@ -22,7 +22,9 @@ impl super::C3V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c4sc/mod.rs b/src/ftm2/c4sc/mod.rs index bf925ca..fb92ce3 100644 --- a/src/ftm2/c4sc/mod.rs +++ b/src/ftm2/c4sc/mod.rs @@ -22,7 +22,9 @@ impl super::C4SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C4SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c4v/mod.rs b/src/ftm2/c4v/mod.rs index 234c36c..8ae59fc 100644 --- a/src/ftm2/c4v/mod.rs +++ b/src/ftm2/c4v/mod.rs @@ -22,7 +22,9 @@ impl super::C4V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c5sc/mod.rs b/src/ftm2/c5sc/mod.rs index e8cf2e7..603ff97 100644 --- a/src/ftm2/c5sc/mod.rs +++ b/src/ftm2/c5sc/mod.rs @@ -22,7 +22,9 @@ impl super::C5SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C5SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c5v/mod.rs b/src/ftm2/c5v/mod.rs index 067897f..4e32c51 100644 --- a/src/ftm2/c5v/mod.rs +++ b/src/ftm2/c5v/mod.rs @@ -22,7 +22,9 @@ impl super::C5V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c6sc/mod.rs b/src/ftm2/c6sc/mod.rs index 07b04a6..ba9dcbc 100644 --- a/src/ftm2/c6sc/mod.rs +++ b/src/ftm2/c6sc/mod.rs @@ -22,7 +22,9 @@ impl super::C6SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C6SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c6v/mod.rs b/src/ftm2/c6v/mod.rs index 51df3d8..d77fbb5 100644 --- a/src/ftm2/c6v/mod.rs +++ b/src/ftm2/c6v/mod.rs @@ -22,7 +22,9 @@ impl super::C6V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/c7sc/mod.rs b/src/ftm2/c7sc/mod.rs index c75e91b..c27a403 100644 --- a/src/ftm2/c7sc/mod.rs +++ b/src/ftm2/c7sc/mod.rs @@ -22,7 +22,9 @@ impl super::C7SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C7SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm2/c7v/mod.rs b/src/ftm2/c7v/mod.rs index 7aca3b3..a258d58 100644 --- a/src/ftm2/c7v/mod.rs +++ b/src/ftm2/c7v/mod.rs @@ -22,7 +22,9 @@ impl super::C7V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/cnt/mod.rs b/src/ftm2/cnt/mod.rs index c5ef1a1..2554297 100644 --- a/src/ftm2/cnt/mod.rs +++ b/src/ftm2/cnt/mod.rs @@ -22,7 +22,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/cntin/mod.rs b/src/ftm2/cntin/mod.rs index 8694d48..3b7f42f 100644 --- a/src/ftm2/cntin/mod.rs +++ b/src/ftm2/cntin/mod.rs @@ -22,7 +22,9 @@ impl super::CNTIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/combine/mod.rs b/src/ftm2/combine/mod.rs index 02885e8..10e7960 100644 --- a/src/ftm2/combine/mod.rs +++ b/src/ftm2/combine/mod.rs @@ -22,7 +22,9 @@ impl super::COMBINE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl COMBINE0R { #[doc = "Possible values of the field `COMP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP0R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl DECAPEN0R { #[doc = "Possible values of the field `DECAP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP0R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,10 +177,8 @@ impl DECAP0R { #[doc = "Possible values of the field `DTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN0R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl DTEN0R { #[doc = "Possible values of the field `SYNCEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN0R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl SYNCEN0R { #[doc = "Possible values of the field `FAULTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN0R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -362,10 +354,8 @@ impl COMBINE1R { #[doc = "Possible values of the field `COMP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP1R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -430,10 +420,8 @@ impl DECAPEN1R { #[doc = "Possible values of the field `DECAP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP1R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +465,8 @@ impl DECAP1R { #[doc = "Possible values of the field `DTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN1R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +510,8 @@ impl DTEN1R { #[doc = "Possible values of the field `SYNCEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN1R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -571,10 +555,8 @@ impl SYNCEN1R { #[doc = "Possible values of the field `FAULTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN1R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -660,10 +642,8 @@ impl COMBINE2R { #[doc = "Possible values of the field `COMP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP2R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -728,10 +708,8 @@ impl DECAPEN2R { #[doc = "Possible values of the field `DECAP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP2R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -775,10 +753,8 @@ impl DECAP2R { #[doc = "Possible values of the field `DTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN2R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -822,10 +798,8 @@ impl DTEN2R { #[doc = "Possible values of the field `SYNCEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN2R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -869,10 +843,8 @@ impl SYNCEN2R { #[doc = "Possible values of the field `FAULTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN2R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -958,10 +930,8 @@ impl COMBINE3R { #[doc = "Possible values of the field `COMP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP3R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1026,10 +996,8 @@ impl DECAPEN3R { #[doc = "Possible values of the field `DECAP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP3R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1073,10 +1041,8 @@ impl DECAP3R { #[doc = "Possible values of the field `DTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN3R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1120,10 +1086,8 @@ impl DTEN3R { #[doc = "Possible values of the field `SYNCEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN3R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1167,10 +1131,8 @@ impl SYNCEN3R { #[doc = "Possible values of the field `FAULTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN3R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1257,10 +1219,8 @@ impl<'a> _COMBINE0W<'a> { } #[doc = "Values that can be written to the field `COMP0`"] pub enum COMP0W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0W { #[allow(missing_docs)] @@ -1338,10 +1298,8 @@ impl<'a> _DECAPEN0W<'a> { } #[doc = "Values that can be written to the field `DECAP0`"] pub enum DECAP0W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0W { #[allow(missing_docs)] @@ -1396,10 +1354,8 @@ impl<'a> _DECAP0W<'a> { } #[doc = "Values that can be written to the field `DTEN0`"] pub enum DTEN0W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0W { #[allow(missing_docs)] @@ -1454,10 +1410,8 @@ impl<'a> _DTEN0W<'a> { } #[doc = "Values that can be written to the field `SYNCEN0`"] pub enum SYNCEN0W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0W { #[allow(missing_docs)] @@ -1512,10 +1466,8 @@ impl<'a> _SYNCEN0W<'a> { } #[doc = "Values that can be written to the field `FAULTEN0`"] pub enum FAULTEN0W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0W { #[allow(missing_docs)] @@ -1616,10 +1568,8 @@ impl<'a> _COMBINE1W<'a> { } #[doc = "Values that can be written to the field `COMP1`"] pub enum COMP1W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1W { #[allow(missing_docs)] @@ -1697,10 +1647,8 @@ impl<'a> _DECAPEN1W<'a> { } #[doc = "Values that can be written to the field `DECAP1`"] pub enum DECAP1W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1W { #[allow(missing_docs)] @@ -1755,10 +1703,8 @@ impl<'a> _DECAP1W<'a> { } #[doc = "Values that can be written to the field `DTEN1`"] pub enum DTEN1W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1W { #[allow(missing_docs)] @@ -1813,10 +1759,8 @@ impl<'a> _DTEN1W<'a> { } #[doc = "Values that can be written to the field `SYNCEN1`"] pub enum SYNCEN1W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1W { #[allow(missing_docs)] @@ -1871,10 +1815,8 @@ impl<'a> _SYNCEN1W<'a> { } #[doc = "Values that can be written to the field `FAULTEN1`"] pub enum FAULTEN1W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1W { #[allow(missing_docs)] @@ -1975,10 +1917,8 @@ impl<'a> _COMBINE2W<'a> { } #[doc = "Values that can be written to the field `COMP2`"] pub enum COMP2W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2W { #[allow(missing_docs)] @@ -2056,10 +1996,8 @@ impl<'a> _DECAPEN2W<'a> { } #[doc = "Values that can be written to the field `DECAP2`"] pub enum DECAP2W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2W { #[allow(missing_docs)] @@ -2114,10 +2052,8 @@ impl<'a> _DECAP2W<'a> { } #[doc = "Values that can be written to the field `DTEN2`"] pub enum DTEN2W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2W { #[allow(missing_docs)] @@ -2172,10 +2108,8 @@ impl<'a> _DTEN2W<'a> { } #[doc = "Values that can be written to the field `SYNCEN2`"] pub enum SYNCEN2W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2W { #[allow(missing_docs)] @@ -2230,10 +2164,8 @@ impl<'a> _SYNCEN2W<'a> { } #[doc = "Values that can be written to the field `FAULTEN2`"] pub enum FAULTEN2W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2W { #[allow(missing_docs)] @@ -2334,10 +2266,8 @@ impl<'a> _COMBINE3W<'a> { } #[doc = "Values that can be written to the field `COMP3`"] pub enum COMP3W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3W { #[allow(missing_docs)] @@ -2415,10 +2345,8 @@ impl<'a> _DECAPEN3W<'a> { } #[doc = "Values that can be written to the field `DECAP3`"] pub enum DECAP3W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3W { #[allow(missing_docs)] @@ -2473,10 +2401,8 @@ impl<'a> _DECAP3W<'a> { } #[doc = "Values that can be written to the field `DTEN3`"] pub enum DTEN3W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3W { #[allow(missing_docs)] @@ -2531,10 +2457,8 @@ impl<'a> _DTEN3W<'a> { } #[doc = "Values that can be written to the field `SYNCEN3`"] pub enum SYNCEN3W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3W { #[allow(missing_docs)] @@ -2589,10 +2513,8 @@ impl<'a> _SYNCEN3W<'a> { } #[doc = "Values that can be written to the field `FAULTEN3`"] pub enum FAULTEN3W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3W { #[allow(missing_docs)] diff --git a/src/ftm2/conf/mod.rs b/src/ftm2/conf/mod.rs index 758ddf6..fe1706a 100644 --- a/src/ftm2/conf/mod.rs +++ b/src/ftm2/conf/mod.rs @@ -22,7 +22,9 @@ impl super::CONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -107,10 +109,8 @@ impl GTBEOUTR { #[doc = "Possible values of the field `ITRIGR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ITRIGRR { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -229,10 +229,8 @@ impl<'a> _GTBEOUTW<'a> { } #[doc = "Values that can be written to the field `ITRIGR`"] pub enum ITRIGRW { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRW { #[allow(missing_docs)] diff --git a/src/ftm2/deadtime/mod.rs b/src/ftm2/deadtime/mod.rs index 3a9b0cf..f1dfdde 100644 --- a/src/ftm2/deadtime/mod.rs +++ b/src/ftm2/deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/exttrig/mod.rs b/src/ftm2/exttrig/mod.rs index cbd52f1..d85e308 100644 --- a/src/ftm2/exttrig/mod.rs +++ b/src/ftm2/exttrig/mod.rs @@ -22,7 +22,9 @@ impl super::EXTTRIG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EXTTRIG { #[doc = "Possible values of the field `CH2TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH2TRIGR { #[doc = "Possible values of the field `CH3TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH3TRIGR { #[doc = "Possible values of the field `CH4TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH4TRIGR { #[doc = "Possible values of the field `CH5TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH5TRIGR { #[doc = "Possible values of the field `CH0TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH0TRIGR { #[doc = "Possible values of the field `CH1TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH1TRIGR { #[doc = "Possible values of the field `INITTRIGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INITTRIGENR { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl INITTRIGENR { #[doc = "Possible values of the field `TRIGF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGFR { - #[doc = "No channel trigger was generated."] - _0, - #[doc = "A channel trigger was generated."] - _1, + #[doc = "No channel trigger was generated."] _0, + #[doc = "A channel trigger was generated."] _1, } impl TRIGFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl TRIGFR { #[doc = "Possible values of the field `CH6TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH6TRIGR { #[doc = "Possible values of the field `CH7TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -512,10 +494,8 @@ impl CH7TRIGR { } #[doc = "Values that can be written to the field `CH2TRIG`"] pub enum CH2TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGW { #[allow(missing_docs)] @@ -570,10 +550,8 @@ impl<'a> _CH2TRIGW<'a> { } #[doc = "Values that can be written to the field `CH3TRIG`"] pub enum CH3TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGW { #[allow(missing_docs)] @@ -628,10 +606,8 @@ impl<'a> _CH3TRIGW<'a> { } #[doc = "Values that can be written to the field `CH4TRIG`"] pub enum CH4TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGW { #[allow(missing_docs)] @@ -686,10 +662,8 @@ impl<'a> _CH4TRIGW<'a> { } #[doc = "Values that can be written to the field `CH5TRIG`"] pub enum CH5TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGW { #[allow(missing_docs)] @@ -744,10 +718,8 @@ impl<'a> _CH5TRIGW<'a> { } #[doc = "Values that can be written to the field `CH0TRIG`"] pub enum CH0TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGW { #[allow(missing_docs)] @@ -802,10 +774,8 @@ impl<'a> _CH0TRIGW<'a> { } #[doc = "Values that can be written to the field `CH1TRIG`"] pub enum CH1TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGW { #[allow(missing_docs)] @@ -860,10 +830,8 @@ impl<'a> _CH1TRIGW<'a> { } #[doc = "Values that can be written to the field `INITTRIGEN`"] pub enum INITTRIGENW { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENW { #[allow(missing_docs)] @@ -918,10 +886,8 @@ impl<'a> _INITTRIGENW<'a> { } #[doc = "Values that can be written to the field `CH6TRIG`"] pub enum CH6TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGW { #[allow(missing_docs)] @@ -976,10 +942,8 @@ impl<'a> _CH6TRIGW<'a> { } #[doc = "Values that can be written to the field `CH7TRIG`"] pub enum CH7TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGW { #[allow(missing_docs)] diff --git a/src/ftm2/filter/mod.rs b/src/ftm2/filter/mod.rs index 30911ac..19ef737 100644 --- a/src/ftm2/filter/mod.rs +++ b/src/ftm2/filter/mod.rs @@ -22,7 +22,9 @@ impl super::FILTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/fltctrl/mod.rs b/src/ftm2/fltctrl/mod.rs index d85ff3c..792a4e9 100644 --- a/src/ftm2/fltctrl/mod.rs +++ b/src/ftm2/fltctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FLTCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTCTRL { #[doc = "Possible values of the field `FAULT0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT0ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULT0ENR { #[doc = "Possible values of the field `FAULT1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT1ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULT1ENR { #[doc = "Possible values of the field `FAULT2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT2ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULT2ENR { #[doc = "Possible values of the field `FAULT3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT3ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULT3ENR { #[doc = "Possible values of the field `FFLTR0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR0ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FFLTR0ENR { #[doc = "Possible values of the field `FFLTR1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR1ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl FFLTR1ENR { #[doc = "Possible values of the field `FFLTR2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR2ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FFLTR2ENR { #[doc = "Possible values of the field `FFLTR3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR3ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +418,7 @@ impl FFVALR { pub enum FSTATER { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -476,10 +461,8 @@ impl FSTATER { } #[doc = "Values that can be written to the field `FAULT0EN`"] pub enum FAULT0ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENW { #[allow(missing_docs)] @@ -534,10 +517,8 @@ impl<'a> _FAULT0ENW<'a> { } #[doc = "Values that can be written to the field `FAULT1EN`"] pub enum FAULT1ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENW { #[allow(missing_docs)] @@ -592,10 +573,8 @@ impl<'a> _FAULT1ENW<'a> { } #[doc = "Values that can be written to the field `FAULT2EN`"] pub enum FAULT2ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENW { #[allow(missing_docs)] @@ -650,10 +629,8 @@ impl<'a> _FAULT2ENW<'a> { } #[doc = "Values that can be written to the field `FAULT3EN`"] pub enum FAULT3ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENW { #[allow(missing_docs)] @@ -708,10 +685,8 @@ impl<'a> _FAULT3ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR0EN`"] pub enum FFLTR0ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENW { #[allow(missing_docs)] @@ -766,10 +741,8 @@ impl<'a> _FFLTR0ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR1EN`"] pub enum FFLTR1ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENW { #[allow(missing_docs)] @@ -824,10 +797,8 @@ impl<'a> _FFLTR1ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR2EN`"] pub enum FFLTR2ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENW { #[allow(missing_docs)] @@ -882,10 +853,8 @@ impl<'a> _FFLTR2ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR3EN`"] pub enum FFLTR3ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENW { #[allow(missing_docs)] @@ -957,8 +926,7 @@ impl<'a> _FFVALW<'a> { pub enum FSTATEW { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATEW { #[allow(missing_docs)] diff --git a/src/ftm2/fltpol/mod.rs b/src/ftm2/fltpol/mod.rs index 5b0170d..d99042f 100644 --- a/src/ftm2/fltpol/mod.rs +++ b/src/ftm2/fltpol/mod.rs @@ -22,7 +22,9 @@ impl super::FLTPOL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTPOL { #[doc = "Possible values of the field `FLT0POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT0POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FLT0POLR { #[doc = "Possible values of the field `FLT1POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT1POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FLT1POLR { #[doc = "Possible values of the field `FLT2POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT2POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FLT2POLR { #[doc = "Possible values of the field `FLT3POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT3POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl FLT3POLR { } #[doc = "Values that can be written to the field `FLT0POL`"] pub enum FLT0POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _FLT0POLW<'a> { } #[doc = "Values that can be written to the field `FLT1POL`"] pub enum FLT1POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _FLT1POLW<'a> { } #[doc = "Values that can be written to the field `FLT2POL`"] pub enum FLT2POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _FLT2POLW<'a> { } #[doc = "Values that can be written to the field `FLT3POL`"] pub enum FLT3POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLW { #[allow(missing_docs)] diff --git a/src/ftm2/fms/mod.rs b/src/ftm2/fms/mod.rs index fb65c8b..61915be 100644 --- a/src/ftm2/fms/mod.rs +++ b/src/ftm2/fms/mod.rs @@ -22,7 +22,9 @@ impl super::FMS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FMS { #[doc = "Possible values of the field `FAULTF0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF0R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULTF0R { #[doc = "Possible values of the field `FAULTF1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF1R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULTF1R { #[doc = "Possible values of the field `FAULTF2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF2R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULTF2R { #[doc = "Possible values of the field `FAULTF3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF3R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULTF3R { #[doc = "Possible values of the field `FAULTIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTINR { - #[doc = "The logic OR of the enabled fault inputs is 0."] - _0, - #[doc = "The logic OR of the enabled fault inputs is 1."] - _1, + #[doc = "The logic OR of the enabled fault inputs is 0."] _0, + #[doc = "The logic OR of the enabled fault inputs is 1."] _1, } impl FAULTINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FAULTINR { #[doc = "Possible values of the field `WPEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPENR { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl WPENR { #[doc = "Possible values of the field `FAULTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTFR { - #[doc = "No fault condition was detected."] - _0, - #[doc = "A fault condition was detected."] - _1, + #[doc = "No fault condition was detected."] _0, + #[doc = "A fault condition was detected."] _1, } impl FAULTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -371,10 +359,8 @@ impl FAULTFR { } #[doc = "Values that can be written to the field `WPEN`"] pub enum WPENW { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENW { #[allow(missing_docs)] diff --git a/src/ftm2/hcr/mod.rs b/src/ftm2/hcr/mod.rs index 6f87eca..dfcbde9 100644 --- a/src/ftm2/hcr/mod.rs +++ b/src/ftm2/hcr/mod.rs @@ -22,7 +22,9 @@ impl super::HCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/invctrl/mod.rs b/src/ftm2/invctrl/mod.rs index 23e094b..80e4e01 100644 --- a/src/ftm2/invctrl/mod.rs +++ b/src/ftm2/invctrl/mod.rs @@ -22,7 +22,9 @@ impl super::INVCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::INVCTRL { #[doc = "Possible values of the field `INV0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV0ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl INV0ENR { #[doc = "Possible values of the field `INV1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV1ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INV1ENR { #[doc = "Possible values of the field `INV2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV2ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl INV2ENR { #[doc = "Possible values of the field `INV3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV3ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl INV3ENR { } #[doc = "Values that can be written to the field `INV0EN`"] pub enum INV0ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _INV0ENW<'a> { } #[doc = "Values that can be written to the field `INV1EN`"] pub enum INV1ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _INV1ENW<'a> { } #[doc = "Values that can be written to the field `INV2EN`"] pub enum INV2ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _INV2ENW<'a> { } #[doc = "Values that can be written to the field `INV3EN`"] pub enum INV3ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENW { #[allow(missing_docs)] diff --git a/src/ftm2/mod.rs b/src/ftm2/mod.rs index 445c1aa..294f78f 100644 --- a/src/ftm2/mod.rs +++ b/src/ftm2/mod.rs @@ -2,97 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status And Control"] - pub sc: SC, - #[doc = "0x04 - Counter"] - pub cnt: CNT, - #[doc = "0x08 - Modulo"] - pub mod_: MOD, - #[doc = "0x0c - Channel (n) Status And Control"] - pub c0sc: C0SC, - #[doc = "0x10 - Channel (n) Value"] - pub c0v: C0V, - #[doc = "0x14 - Channel (n) Status And Control"] - pub c1sc: C1SC, - #[doc = "0x18 - Channel (n) Value"] - pub c1v: C1V, - #[doc = "0x1c - Channel (n) Status And Control"] - pub c2sc: C2SC, - #[doc = "0x20 - Channel (n) Value"] - pub c2v: C2V, - #[doc = "0x24 - Channel (n) Status And Control"] - pub c3sc: C3SC, - #[doc = "0x28 - Channel (n) Value"] - pub c3v: C3V, - #[doc = "0x2c - Channel (n) Status And Control"] - pub c4sc: C4SC, - #[doc = "0x30 - Channel (n) Value"] - pub c4v: C4V, - #[doc = "0x34 - Channel (n) Status And Control"] - pub c5sc: C5SC, - #[doc = "0x38 - Channel (n) Value"] - pub c5v: C5V, - #[doc = "0x3c - Channel (n) Status And Control"] - pub c6sc: C6SC, - #[doc = "0x40 - Channel (n) Value"] - pub c6v: C6V, - #[doc = "0x44 - Channel (n) Status And Control"] - pub c7sc: C7SC, - #[doc = "0x48 - Channel (n) Value"] - pub c7v: C7V, - #[doc = "0x4c - Counter Initial Value"] - pub cntin: CNTIN, - #[doc = "0x50 - Capture And Compare Status"] - pub status: STATUS, - #[doc = "0x54 - Features Mode Selection"] - pub mode: MODE, - #[doc = "0x58 - Synchronization"] - pub sync: SYNC, - #[doc = "0x5c - Initial State For Channels Output"] - pub outinit: OUTINIT, - #[doc = "0x60 - Output Mask"] - pub outmask: OUTMASK, - #[doc = "0x64 - Function For Linked Channels"] - pub combine: COMBINE, - #[doc = "0x68 - Deadtime Configuration"] - pub deadtime: DEADTIME, - #[doc = "0x6c - FTM External Trigger"] - pub exttrig: EXTTRIG, - #[doc = "0x70 - Channels Polarity"] - pub pol: POL, - #[doc = "0x74 - Fault Mode Status"] - pub fms: FMS, - #[doc = "0x78 - Input Capture Filter Control"] - pub filter: FILTER, - #[doc = "0x7c - Fault Control"] - pub fltctrl: FLTCTRL, - #[doc = "0x80 - Quadrature Decoder Control And Status"] - pub qdctrl: QDCTRL, - #[doc = "0x84 - Configuration"] - pub conf: CONF, - #[doc = "0x88 - FTM Fault Input Polarity"] - pub fltpol: FLTPOL, - #[doc = "0x8c - Synchronization Configuration"] - pub synconf: SYNCONF, - #[doc = "0x90 - FTM Inverting Control"] - pub invctrl: INVCTRL, - #[doc = "0x94 - FTM Software Output Control"] - pub swoctrl: SWOCTRL, - #[doc = "0x98 - FTM PWM Load"] - pub pwmload: PWMLOAD, - #[doc = "0x9c - Half Cycle Register"] - pub hcr: HCR, - #[doc = "0xa0 - Pair 0 Deadtime Configuration"] - pub pair0deadtime: PAIR0DEADTIME, + #[doc = "0x00 - Status And Control"] pub sc: SC, + #[doc = "0x04 - Counter"] pub cnt: CNT, + #[doc = "0x08 - Modulo"] pub mod_: MOD, + #[doc = "0x0c - Channel (n) Status And Control"] pub c0sc: C0SC, + #[doc = "0x10 - Channel (n) Value"] pub c0v: C0V, + #[doc = "0x14 - Channel (n) Status And Control"] pub c1sc: C1SC, + #[doc = "0x18 - Channel (n) Value"] pub c1v: C1V, + #[doc = "0x1c - Channel (n) Status And Control"] pub c2sc: C2SC, + #[doc = "0x20 - Channel (n) Value"] pub c2v: C2V, + #[doc = "0x24 - Channel (n) Status And Control"] pub c3sc: C3SC, + #[doc = "0x28 - Channel (n) Value"] pub c3v: C3V, + #[doc = "0x2c - Channel (n) Status And Control"] pub c4sc: C4SC, + #[doc = "0x30 - Channel (n) Value"] pub c4v: C4V, + #[doc = "0x34 - Channel (n) Status And Control"] pub c5sc: C5SC, + #[doc = "0x38 - Channel (n) Value"] pub c5v: C5V, + #[doc = "0x3c - Channel (n) Status And Control"] pub c6sc: C6SC, + #[doc = "0x40 - Channel (n) Value"] pub c6v: C6V, + #[doc = "0x44 - Channel (n) Status And Control"] pub c7sc: C7SC, + #[doc = "0x48 - Channel (n) Value"] pub c7v: C7V, + #[doc = "0x4c - Counter Initial Value"] pub cntin: CNTIN, + #[doc = "0x50 - Capture And Compare Status"] pub status: STATUS, + #[doc = "0x54 - Features Mode Selection"] pub mode: MODE, + #[doc = "0x58 - Synchronization"] pub sync: SYNC, + #[doc = "0x5c - Initial State For Channels Output"] pub outinit: OUTINIT, + #[doc = "0x60 - Output Mask"] pub outmask: OUTMASK, + #[doc = "0x64 - Function For Linked Channels"] pub combine: COMBINE, + #[doc = "0x68 - Deadtime Configuration"] pub deadtime: DEADTIME, + #[doc = "0x6c - FTM External Trigger"] pub exttrig: EXTTRIG, + #[doc = "0x70 - Channels Polarity"] pub pol: POL, + #[doc = "0x74 - Fault Mode Status"] pub fms: FMS, + #[doc = "0x78 - Input Capture Filter Control"] pub filter: FILTER, + #[doc = "0x7c - Fault Control"] pub fltctrl: FLTCTRL, + #[doc = "0x80 - Quadrature Decoder Control And Status"] pub qdctrl: QDCTRL, + #[doc = "0x84 - Configuration"] pub conf: CONF, + #[doc = "0x88 - FTM Fault Input Polarity"] pub fltpol: FLTPOL, + #[doc = "0x8c - Synchronization Configuration"] pub synconf: SYNCONF, + #[doc = "0x90 - FTM Inverting Control"] pub invctrl: INVCTRL, + #[doc = "0x94 - FTM Software Output Control"] pub swoctrl: SWOCTRL, + #[doc = "0x98 - FTM PWM Load"] pub pwmload: PWMLOAD, + #[doc = "0x9c - Half Cycle Register"] pub hcr: HCR, + #[doc = "0xa0 - Pair 0 Deadtime Configuration"] pub pair0deadtime: PAIR0DEADTIME, _reserved0: [u8; 4usize], - #[doc = "0xa8 - Pair 1 Deadtime Configuration"] - pub pair1deadtime: PAIR1DEADTIME, + #[doc = "0xa8 - Pair 1 Deadtime Configuration"] pub pair1deadtime: PAIR1DEADTIME, _reserved1: [u8; 4usize], - #[doc = "0xb0 - Pair 2 Deadtime Configuration"] - pub pair2deadtime: PAIR2DEADTIME, + #[doc = "0xb0 - Pair 2 Deadtime Configuration"] pub pair2deadtime: PAIR2DEADTIME, _reserved2: [u8; 4usize], - #[doc = "0xb8 - Pair 3 Deadtime Configuration"] - pub pair3deadtime: PAIR3DEADTIME, + #[doc = "0xb8 - Pair 3 Deadtime Configuration"] pub pair3deadtime: PAIR3DEADTIME, } #[doc = "Status And Control"] pub struct SC { diff --git a/src/ftm2/mod_/mod.rs b/src/ftm2/mod_/mod.rs index 9ef76ef..448895c 100644 --- a/src/ftm2/mod_/mod.rs +++ b/src/ftm2/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm2/mode/mod.rs b/src/ftm2/mode/mod.rs index 6a8e2ac..c4bd468 100644 --- a/src/ftm2/mode/mod.rs +++ b/src/ftm2/mode/mod.rs @@ -22,7 +22,9 @@ impl super::MODE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MODE { #[doc = "Possible values of the field `FTMEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTMENR { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FTMENR { #[doc = "Possible values of the field `WPDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPDISR { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl PWMSYNCR { #[doc = "Possible values of the field `CAPTEST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CAPTESTR { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,8 +227,7 @@ impl CAPTESTR { #[doc = "Possible values of the field `FAULTM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTMR { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -287,10 +282,8 @@ impl FAULTMR { #[doc = "Possible values of the field `FAULTIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTIER { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -333,10 +326,8 @@ impl FAULTIER { } #[doc = "Values that can be written to the field `FTMEN`"] pub enum FTMENW { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENW { #[allow(missing_docs)] @@ -414,10 +405,8 @@ impl<'a> _INITW<'a> { } #[doc = "Values that can be written to the field `WPDIS`"] pub enum WPDISW { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISW { #[allow(missing_docs)] @@ -530,10 +519,8 @@ impl<'a> _PWMSYNCW<'a> { } #[doc = "Values that can be written to the field `CAPTEST`"] pub enum CAPTESTW { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTW { #[allow(missing_docs)] @@ -588,8 +575,7 @@ impl<'a> _CAPTESTW<'a> { } #[doc = "Values that can be written to the field `FAULTM`"] pub enum FAULTMW { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -654,10 +640,8 @@ impl<'a> _FAULTMW<'a> { } #[doc = "Values that can be written to the field `FAULTIE`"] pub enum FAULTIEW { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIEW { #[allow(missing_docs)] diff --git a/src/ftm2/outinit/mod.rs b/src/ftm2/outinit/mod.rs index 5b3b985..10e2df4 100644 --- a/src/ftm2/outinit/mod.rs +++ b/src/ftm2/outinit/mod.rs @@ -22,7 +22,9 @@ impl super::OUTINIT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTINIT { #[doc = "Possible values of the field `CH0OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OIR { #[doc = "Possible values of the field `CH1OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OIR { #[doc = "Possible values of the field `CH2OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OIR { #[doc = "Possible values of the field `CH3OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OIR { #[doc = "Possible values of the field `CH4OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OIR { #[doc = "Possible values of the field `CH5OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OIR { #[doc = "Possible values of the field `CH6OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OIR { #[doc = "Possible values of the field `CH7OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OIR { } #[doc = "Values that can be written to the field `CH0OI`"] pub enum CH0OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OIW<'a> { } #[doc = "Values that can be written to the field `CH1OI`"] pub enum CH1OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OIW<'a> { } #[doc = "Values that can be written to the field `CH2OI`"] pub enum CH2OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OIW<'a> { } #[doc = "Values that can be written to the field `CH3OI`"] pub enum CH3OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OIW<'a> { } #[doc = "Values that can be written to the field `CH4OI`"] pub enum CH4OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OIW<'a> { } #[doc = "Values that can be written to the field `CH5OI`"] pub enum CH5OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OIW<'a> { } #[doc = "Values that can be written to the field `CH6OI`"] pub enum CH6OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OIW<'a> { } #[doc = "Values that can be written to the field `CH7OI`"] pub enum CH7OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIW { #[allow(missing_docs)] diff --git a/src/ftm2/outmask/mod.rs b/src/ftm2/outmask/mod.rs index f9a4723..6d525e0 100644 --- a/src/ftm2/outmask/mod.rs +++ b/src/ftm2/outmask/mod.rs @@ -22,7 +22,9 @@ impl super::OUTMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTMASK { #[doc = "Possible values of the field `CH0OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OMR { #[doc = "Possible values of the field `CH1OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OMR { #[doc = "Possible values of the field `CH2OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OMR { #[doc = "Possible values of the field `CH3OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OMR { #[doc = "Possible values of the field `CH4OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OMR { #[doc = "Possible values of the field `CH5OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OMR { #[doc = "Possible values of the field `CH6OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OMR { #[doc = "Possible values of the field `CH7OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OMR { } #[doc = "Values that can be written to the field `CH0OM`"] pub enum CH0OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OMW<'a> { } #[doc = "Values that can be written to the field `CH1OM`"] pub enum CH1OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OMW<'a> { } #[doc = "Values that can be written to the field `CH2OM`"] pub enum CH2OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OMW<'a> { } #[doc = "Values that can be written to the field `CH3OM`"] pub enum CH3OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OMW<'a> { } #[doc = "Values that can be written to the field `CH4OM`"] pub enum CH4OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OMW<'a> { } #[doc = "Values that can be written to the field `CH5OM`"] pub enum CH5OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OMW<'a> { } #[doc = "Values that can be written to the field `CH6OM`"] pub enum CH6OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OMW<'a> { } #[doc = "Values that can be written to the field `CH7OM`"] pub enum CH7OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMW { #[allow(missing_docs)] diff --git a/src/ftm2/pair0deadtime/mod.rs b/src/ftm2/pair0deadtime/mod.rs index 57b7430..24b3a06 100644 --- a/src/ftm2/pair0deadtime/mod.rs +++ b/src/ftm2/pair0deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR0DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/pair1deadtime/mod.rs b/src/ftm2/pair1deadtime/mod.rs index 54a2334..bd244e2 100644 --- a/src/ftm2/pair1deadtime/mod.rs +++ b/src/ftm2/pair1deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR1DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/pair2deadtime/mod.rs b/src/ftm2/pair2deadtime/mod.rs index 5073dba..9e96c87 100644 --- a/src/ftm2/pair2deadtime/mod.rs +++ b/src/ftm2/pair2deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR2DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/pair3deadtime/mod.rs b/src/ftm2/pair3deadtime/mod.rs index bcb2471..d925ba8 100644 --- a/src/ftm2/pair3deadtime/mod.rs +++ b/src/ftm2/pair3deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR3DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/pol/mod.rs b/src/ftm2/pol/mod.rs index 822ce37..56d0d5a 100644 --- a/src/ftm2/pol/mod.rs +++ b/src/ftm2/pol/mod.rs @@ -22,7 +22,9 @@ impl super::POL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::POL { #[doc = "Possible values of the field `POL0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL0R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl POL0R { #[doc = "Possible values of the field `POL1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL1R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl POL1R { #[doc = "Possible values of the field `POL2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL2R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl POL2R { #[doc = "Possible values of the field `POL3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL3R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl POL3R { #[doc = "Possible values of the field `POL4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL4R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl POL4R { #[doc = "Possible values of the field `POL5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL5R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl POL5R { #[doc = "Possible values of the field `POL6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL6R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl POL6R { #[doc = "Possible values of the field `POL7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL7R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl POL7R { } #[doc = "Values that can be written to the field `POL0`"] pub enum POL0W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0W { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _POL0W<'a> { } #[doc = "Values that can be written to the field `POL1`"] pub enum POL1W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1W { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _POL1W<'a> { } #[doc = "Values that can be written to the field `POL2`"] pub enum POL2W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2W { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _POL2W<'a> { } #[doc = "Values that can be written to the field `POL3`"] pub enum POL3W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3W { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _POL3W<'a> { } #[doc = "Values that can be written to the field `POL4`"] pub enum POL4W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4W { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _POL4W<'a> { } #[doc = "Values that can be written to the field `POL5`"] pub enum POL5W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5W { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _POL5W<'a> { } #[doc = "Values that can be written to the field `POL6`"] pub enum POL6W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6W { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _POL6W<'a> { } #[doc = "Values that can be written to the field `POL7`"] pub enum POL7W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7W { #[allow(missing_docs)] diff --git a/src/ftm2/pwmload/mod.rs b/src/ftm2/pwmload/mod.rs index c95d704..e3ad1a9 100644 --- a/src/ftm2/pwmload/mod.rs +++ b/src/ftm2/pwmload/mod.rs @@ -22,7 +22,9 @@ impl super::PWMLOAD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PWMLOAD { #[doc = "Possible values of the field `CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0SELR { #[doc = "Possible values of the field `CH1SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1SELR { #[doc = "Possible values of the field `CH2SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2SELR { #[doc = "Possible values of the field `CH3SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3SELR { #[doc = "Possible values of the field `CH4SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4SELR { #[doc = "Possible values of the field `CH5SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5SELR { #[doc = "Possible values of the field `CH6SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6SELR { #[doc = "Possible values of the field `CH7SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7SELR { #[doc = "Possible values of the field `HCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HCSELR { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl HCSELR { #[doc = "Possible values of the field `LDOK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LDOKR { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,8 +495,7 @@ impl LDOKR { #[doc = "Possible values of the field `GLEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GLENR { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -559,10 +540,8 @@ impl GLENR { } #[doc = "Values that can be written to the field `CH0SEL`"] pub enum CH0SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELW { #[allow(missing_docs)] @@ -617,10 +596,8 @@ impl<'a> _CH0SELW<'a> { } #[doc = "Values that can be written to the field `CH1SEL`"] pub enum CH1SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELW { #[allow(missing_docs)] @@ -675,10 +652,8 @@ impl<'a> _CH1SELW<'a> { } #[doc = "Values that can be written to the field `CH2SEL`"] pub enum CH2SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELW { #[allow(missing_docs)] @@ -733,10 +708,8 @@ impl<'a> _CH2SELW<'a> { } #[doc = "Values that can be written to the field `CH3SEL`"] pub enum CH3SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELW { #[allow(missing_docs)] @@ -791,10 +764,8 @@ impl<'a> _CH3SELW<'a> { } #[doc = "Values that can be written to the field `CH4SEL`"] pub enum CH4SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELW { #[allow(missing_docs)] @@ -849,10 +820,8 @@ impl<'a> _CH4SELW<'a> { } #[doc = "Values that can be written to the field `CH5SEL`"] pub enum CH5SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELW { #[allow(missing_docs)] @@ -907,10 +876,8 @@ impl<'a> _CH5SELW<'a> { } #[doc = "Values that can be written to the field `CH6SEL`"] pub enum CH6SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELW { #[allow(missing_docs)] @@ -965,10 +932,8 @@ impl<'a> _CH6SELW<'a> { } #[doc = "Values that can be written to the field `CH7SEL`"] pub enum CH7SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELW { #[allow(missing_docs)] @@ -1023,10 +988,8 @@ impl<'a> _CH7SELW<'a> { } #[doc = "Values that can be written to the field `HCSEL`"] pub enum HCSELW { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELW { #[allow(missing_docs)] @@ -1081,10 +1044,8 @@ impl<'a> _HCSELW<'a> { } #[doc = "Values that can be written to the field `LDOK`"] pub enum LDOKW { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKW { #[allow(missing_docs)] @@ -1139,8 +1100,7 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `GLEN`"] pub enum GLENW { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -1197,10 +1157,8 @@ impl<'a> _GLENW<'a> { } #[doc = "Values that can be written to the field `GLDOK`"] pub enum GLDOKW { - #[doc = "No action."] - _0, - #[doc = "LDOK bit is set."] - _1, + #[doc = "No action."] _0, + #[doc = "LDOK bit is set."] _1, } impl GLDOKW { #[allow(missing_docs)] diff --git a/src/ftm2/qdctrl/mod.rs b/src/ftm2/qdctrl/mod.rs index dee224c..cccabd7 100644 --- a/src/ftm2/qdctrl/mod.rs +++ b/src/ftm2/qdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::QDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::QDCTRL { #[doc = "Possible values of the field `QUADEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADENR { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +137,8 @@ impl TOFDIRR { #[doc = "Possible values of the field `QUADIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADIRR { - #[doc = "Counting direction is decreasing (FTM counter decrement)."] - _0, - #[doc = "Counting direction is increasing (FTM counter increment)."] - _1, + #[doc = "Counting direction is decreasing (FTM counter decrement)."] _0, + #[doc = "Counting direction is increasing (FTM counter increment)."] _1, } impl QUADIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl QUADIRR { #[doc = "Possible values of the field `QUADMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADMODER { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +321,8 @@ impl PHAPOLR { #[doc = "Possible values of the field `PHBFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHBFLTRENR { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl PHBFLTRENR { #[doc = "Possible values of the field `PHAFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHAFLTRENR { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +410,8 @@ impl PHAFLTRENR { } #[doc = "Values that can be written to the field `QUADEN`"] pub enum QUADENW { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENW { #[allow(missing_docs)] @@ -476,10 +466,8 @@ impl<'a> _QUADENW<'a> { } #[doc = "Values that can be written to the field `QUADMODE`"] pub enum QUADMODEW { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODEW { #[allow(missing_docs)] @@ -650,10 +638,8 @@ impl<'a> _PHAPOLW<'a> { } #[doc = "Values that can be written to the field `PHBFLTREN`"] pub enum PHBFLTRENW { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENW { #[allow(missing_docs)] @@ -708,10 +694,8 @@ impl<'a> _PHBFLTRENW<'a> { } #[doc = "Values that can be written to the field `PHAFLTREN`"] pub enum PHAFLTRENW { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENW { #[allow(missing_docs)] diff --git a/src/ftm2/sc/mod.rs b/src/ftm2/sc/mod.rs index 24d7055..abe8d66 100644 --- a/src/ftm2/sc/mod.rs +++ b/src/ftm2/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SC { #[doc = "Possible values of the field `PS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PSR { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSR { #[doc = r" Value of the field as raw bits"] @@ -135,14 +129,10 @@ impl PSR { #[doc = "Possible values of the field `CLKS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKSR { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSR { #[doc = r" Value of the field as raw bits"] @@ -191,10 +181,8 @@ impl CLKSR { #[doc = "Possible values of the field `CPWMS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPWMSR { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -238,10 +226,8 @@ impl CPWMSR { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -285,10 +271,8 @@ impl RIER { #[doc = "Possible values of the field `RF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFR { - #[doc = "A selected reload point did not happen."] - _0, - #[doc = "A selected reload point happened."] - _1, + #[doc = "A selected reload point did not happen."] _0, + #[doc = "A selected reload point happened."] _1, } impl RFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -332,10 +316,8 @@ impl RFR { #[doc = "Possible values of the field `TOIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOIER { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -379,10 +361,8 @@ impl TOIER { #[doc = "Possible values of the field `TOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOFR { - #[doc = "FTM counter has not overflowed."] - _0, - #[doc = "FTM counter has overflowed."] - _1, + #[doc = "FTM counter has not overflowed."] _0, + #[doc = "FTM counter has overflowed."] _1, } impl TOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -426,10 +406,8 @@ impl TOFR { #[doc = "Possible values of the field `PWMEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN0R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -473,10 +451,8 @@ impl PWMEN0R { #[doc = "Possible values of the field `PWMEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN1R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -520,10 +496,8 @@ impl PWMEN1R { #[doc = "Possible values of the field `PWMEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN2R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -567,10 +541,8 @@ impl PWMEN2R { #[doc = "Possible values of the field `PWMEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN3R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -614,10 +586,8 @@ impl PWMEN3R { #[doc = "Possible values of the field `PWMEN4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN4R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -661,10 +631,8 @@ impl PWMEN4R { #[doc = "Possible values of the field `PWMEN5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN5R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -708,10 +676,8 @@ impl PWMEN5R { #[doc = "Possible values of the field `PWMEN6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN6R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -755,10 +721,8 @@ impl PWMEN6R { #[doc = "Possible values of the field `PWMEN7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN7R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -802,38 +766,22 @@ impl PWMEN7R { #[doc = "Possible values of the field `FLTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTPSR { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSR { #[doc = r" Value of the field as raw bits"] @@ -965,22 +913,14 @@ impl FLTPSR { } #[doc = "Values that can be written to the field `PS`"] pub enum PSW { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSW { #[allow(missing_docs)] @@ -1063,14 +1003,10 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `CLKS`"] pub enum CLKSW { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSW { #[allow(missing_docs)] @@ -1129,10 +1065,8 @@ impl<'a> _CLKSW<'a> { } #[doc = "Values that can be written to the field `CPWMS`"] pub enum CPWMSW { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSW { #[allow(missing_docs)] @@ -1187,10 +1121,8 @@ impl<'a> _CPWMSW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIEW { #[allow(missing_docs)] @@ -1245,10 +1177,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TOIE`"] pub enum TOIEW { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIEW { #[allow(missing_docs)] @@ -1303,10 +1233,8 @@ impl<'a> _TOIEW<'a> { } #[doc = "Values that can be written to the field `PWMEN0`"] pub enum PWMEN0W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0W { #[allow(missing_docs)] @@ -1361,10 +1289,8 @@ impl<'a> _PWMEN0W<'a> { } #[doc = "Values that can be written to the field `PWMEN1`"] pub enum PWMEN1W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1W { #[allow(missing_docs)] @@ -1419,10 +1345,8 @@ impl<'a> _PWMEN1W<'a> { } #[doc = "Values that can be written to the field `PWMEN2`"] pub enum PWMEN2W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2W { #[allow(missing_docs)] @@ -1477,10 +1401,8 @@ impl<'a> _PWMEN2W<'a> { } #[doc = "Values that can be written to the field `PWMEN3`"] pub enum PWMEN3W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3W { #[allow(missing_docs)] @@ -1535,10 +1457,8 @@ impl<'a> _PWMEN3W<'a> { } #[doc = "Values that can be written to the field `PWMEN4`"] pub enum PWMEN4W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4W { #[allow(missing_docs)] @@ -1593,10 +1513,8 @@ impl<'a> _PWMEN4W<'a> { } #[doc = "Values that can be written to the field `PWMEN5`"] pub enum PWMEN5W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5W { #[allow(missing_docs)] @@ -1651,10 +1569,8 @@ impl<'a> _PWMEN5W<'a> { } #[doc = "Values that can be written to the field `PWMEN6`"] pub enum PWMEN6W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6W { #[allow(missing_docs)] @@ -1709,10 +1625,8 @@ impl<'a> _PWMEN6W<'a> { } #[doc = "Values that can be written to the field `PWMEN7`"] pub enum PWMEN7W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7W { #[allow(missing_docs)] @@ -1767,38 +1681,22 @@ impl<'a> _PWMEN7W<'a> { } #[doc = "Values that can be written to the field `FLTPS`"] pub enum FLTPSW { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSW { #[allow(missing_docs)] diff --git a/src/ftm2/status/mod.rs b/src/ftm2/status/mod.rs index a808509..bc08657 100644 --- a/src/ftm2/status/mod.rs +++ b/src/ftm2/status/mod.rs @@ -6,16 +6,16 @@ impl super::STATUS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `CH0F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH0FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl CH0FR { #[doc = "Possible values of the field `CH1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl CH1FR { #[doc = "Possible values of the field `CH2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl CH2FR { #[doc = "Possible values of the field `CH3F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH3FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl CH3FR { #[doc = "Possible values of the field `CH4F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH4FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl CH4FR { #[doc = "Possible values of the field `CH5F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH5FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CH5FR { #[doc = "Possible values of the field `CH6F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH6FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl CH6FR { #[doc = "Possible values of the field `CH7F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH7FR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/ftm2/swoctrl/mod.rs b/src/ftm2/swoctrl/mod.rs index 247b3ec..49d6fc8 100644 --- a/src/ftm2/swoctrl/mod.rs +++ b/src/ftm2/swoctrl/mod.rs @@ -22,7 +22,9 @@ impl super::SWOCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SWOCTRL { #[doc = "Possible values of the field `CH0OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OCR { #[doc = "Possible values of the field `CH1OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OCR { #[doc = "Possible values of the field `CH2OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OCR { #[doc = "Possible values of the field `CH3OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OCR { #[doc = "Possible values of the field `CH4OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OCR { #[doc = "Possible values of the field `CH5OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OCR { #[doc = "Possible values of the field `CH6OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OCR { #[doc = "Possible values of the field `CH7OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7OCR { #[doc = "Possible values of the field `CH0OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH0OCVR { #[doc = "Possible values of the field `CH1OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl CH1OCVR { #[doc = "Possible values of the field `CH2OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl CH2OCVR { #[doc = "Possible values of the field `CH3OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl CH3OCVR { #[doc = "Possible values of the field `CH4OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl CH4OCVR { #[doc = "Possible values of the field `CH5OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl CH5OCVR { #[doc = "Possible values of the field `CH6OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl CH6OCVR { #[doc = "Possible values of the field `CH7OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl CH7OCVR { } #[doc = "Values that can be written to the field `CH0OC`"] pub enum CH0OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCW { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _CH0OCW<'a> { } #[doc = "Values that can be written to the field `CH1OC`"] pub enum CH1OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCW { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _CH1OCW<'a> { } #[doc = "Values that can be written to the field `CH2OC`"] pub enum CH2OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCW { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _CH2OCW<'a> { } #[doc = "Values that can be written to the field `CH3OC`"] pub enum CH3OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCW { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _CH3OCW<'a> { } #[doc = "Values that can be written to the field `CH4OC`"] pub enum CH4OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCW { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _CH4OCW<'a> { } #[doc = "Values that can be written to the field `CH5OC`"] pub enum CH5OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCW { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _CH5OCW<'a> { } #[doc = "Values that can be written to the field `CH6OC`"] pub enum CH6OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCW { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _CH6OCW<'a> { } #[doc = "Values that can be written to the field `CH7OC`"] pub enum CH7OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCW { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _CH7OCW<'a> { } #[doc = "Values that can be written to the field `CH0OCV`"] pub enum CH0OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVW { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _CH0OCVW<'a> { } #[doc = "Values that can be written to the field `CH1OCV`"] pub enum CH1OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVW { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _CH1OCVW<'a> { } #[doc = "Values that can be written to the field `CH2OCV`"] pub enum CH2OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVW { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _CH2OCVW<'a> { } #[doc = "Values that can be written to the field `CH3OCV`"] pub enum CH3OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVW { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _CH3OCVW<'a> { } #[doc = "Values that can be written to the field `CH4OCV`"] pub enum CH4OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVW { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _CH4OCVW<'a> { } #[doc = "Values that can be written to the field `CH5OCV`"] pub enum CH5OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVW { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _CH5OCVW<'a> { } #[doc = "Values that can be written to the field `CH6OCV`"] pub enum CH6OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVW { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _CH6OCVW<'a> { } #[doc = "Values that can be written to the field `CH7OCV`"] pub enum CH7OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVW { #[allow(missing_docs)] diff --git a/src/ftm2/sync/mod.rs b/src/ftm2/sync/mod.rs index b46f9f6..add847a 100644 --- a/src/ftm2/sync/mod.rs +++ b/src/ftm2/sync/mod.rs @@ -22,7 +22,9 @@ impl super::SYNC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SYNC { #[doc = "Possible values of the field `CNTMIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMINR { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CNTMINR { #[doc = "Possible values of the field `CNTMAX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMAXR { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,8 +135,7 @@ impl CNTMAXR { #[doc = "Possible values of the field `REINIT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REINITR { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -231,10 +228,8 @@ impl SYNCHOMR { #[doc = "Possible values of the field `TRIG0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG0R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +273,8 @@ impl TRIG0R { #[doc = "Possible values of the field `TRIG1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG1R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +318,8 @@ impl TRIG1R { #[doc = "Possible values of the field `TRIG2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG2R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +363,8 @@ impl TRIG2R { #[doc = "Possible values of the field `SWSYNC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSYNCR { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +407,8 @@ impl SWSYNCR { } #[doc = "Values that can be written to the field `CNTMIN`"] pub enum CNTMINW { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINW { #[allow(missing_docs)] @@ -476,10 +463,8 @@ impl<'a> _CNTMINW<'a> { } #[doc = "Values that can be written to the field `CNTMAX`"] pub enum CNTMAXW { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXW { #[allow(missing_docs)] @@ -534,8 +519,7 @@ impl<'a> _CNTMAXW<'a> { } #[doc = "Values that can be written to the field `REINIT`"] pub enum REINITW { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -650,10 +634,8 @@ impl<'a> _SYNCHOMW<'a> { } #[doc = "Values that can be written to the field `TRIG0`"] pub enum TRIG0W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0W { #[allow(missing_docs)] @@ -708,10 +690,8 @@ impl<'a> _TRIG0W<'a> { } #[doc = "Values that can be written to the field `TRIG1`"] pub enum TRIG1W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1W { #[allow(missing_docs)] @@ -766,10 +746,8 @@ impl<'a> _TRIG1W<'a> { } #[doc = "Values that can be written to the field `TRIG2`"] pub enum TRIG2W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2W { #[allow(missing_docs)] @@ -824,10 +802,8 @@ impl<'a> _TRIG2W<'a> { } #[doc = "Values that can be written to the field `SWSYNC`"] pub enum SWSYNCW { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCW { #[allow(missing_docs)] diff --git a/src/ftm2/synconf/mod.rs b/src/ftm2/synconf/mod.rs index 08257bc..8b29129 100644 --- a/src/ftm2/synconf/mod.rs +++ b/src/ftm2/synconf/mod.rs @@ -22,7 +22,9 @@ impl super::SYNCONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -92,8 +94,7 @@ impl HWTRIGMODER { pub enum CNTINCR { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -139,8 +140,7 @@ impl CNTINCR { pub enum INVCR { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -186,8 +186,7 @@ impl INVCR { pub enum SWOCR { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +230,8 @@ impl SWOCR { #[doc = "Possible values of the field `SYNCMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCMODER { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +275,8 @@ impl SYNCMODER { #[doc = "Possible values of the field `SWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRSTCNTR { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -327,8 +322,7 @@ impl SWRSTCNTR { pub enum SWWRBUFR { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl SWWRBUFR { #[doc = "Possible values of the field `SWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWOMR { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +411,8 @@ impl SWOMR { #[doc = "Possible values of the field `SWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWINVCR { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +456,8 @@ impl SWINVCR { #[doc = "Possible values of the field `SWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSOCR { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +501,8 @@ impl SWSOCR { #[doc = "Possible values of the field `HWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWRSTCNTR { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -562,8 +548,7 @@ impl HWRSTCNTR { pub enum HWWRBUFR { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +592,8 @@ impl HWWRBUFR { #[doc = "Possible values of the field `HWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWOMR { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +637,8 @@ impl HWOMR { #[doc = "Possible values of the field `HWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWINVCR { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +682,8 @@ impl HWINVCR { #[doc = "Possible values of the field `HWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWSOCR { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> { pub enum CNTINCW { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCW { #[allow(missing_docs)] @@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> { pub enum INVCW { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCW { #[allow(missing_docs)] @@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> { pub enum SWOCW { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCW { #[allow(missing_docs)] @@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> { } #[doc = "Values that can be written to the field `SYNCMODE`"] pub enum SYNCMODEW { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODEW { #[allow(missing_docs)] @@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> { } #[doc = "Values that can be written to the field `SWRSTCNT`"] pub enum SWRSTCNTW { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTW { #[allow(missing_docs)] @@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> { pub enum SWWRBUFW { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFW { #[allow(missing_docs)] @@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> { } #[doc = "Values that can be written to the field `SWOM`"] pub enum SWOMW { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMW { #[allow(missing_docs)] @@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> { } #[doc = "Values that can be written to the field `SWINVC`"] pub enum SWINVCW { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCW { #[allow(missing_docs)] @@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> { } #[doc = "Values that can be written to the field `SWSOC`"] pub enum SWSOCW { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCW { #[allow(missing_docs)] @@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> { } #[doc = "Values that can be written to the field `HWRSTCNT`"] pub enum HWRSTCNTW { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTW { #[allow(missing_docs)] @@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> { pub enum HWWRBUFW { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFW { #[allow(missing_docs)] @@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> { } #[doc = "Values that can be written to the field `HWOM`"] pub enum HWOMW { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMW { #[allow(missing_docs)] @@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> { } #[doc = "Values that can be written to the field `HWINVC`"] pub enum HWINVCW { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCW { #[allow(missing_docs)] @@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> { } #[doc = "Values that can be written to the field `HWSOC`"] pub enum HWSOCW { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCW { #[allow(missing_docs)] diff --git a/src/ftm3/c0sc/mod.rs b/src/ftm3/c0sc/mod.rs index ceb657c..174b306 100644 --- a/src/ftm3/c0sc/mod.rs +++ b/src/ftm3/c0sc/mod.rs @@ -22,7 +22,9 @@ impl super::C0SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C0SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c0v/mod.rs b/src/ftm3/c0v/mod.rs index 9c5f35e..7138aeb 100644 --- a/src/ftm3/c0v/mod.rs +++ b/src/ftm3/c0v/mod.rs @@ -22,7 +22,9 @@ impl super::C0V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c1sc/mod.rs b/src/ftm3/c1sc/mod.rs index 75125c1..12f080d 100644 --- a/src/ftm3/c1sc/mod.rs +++ b/src/ftm3/c1sc/mod.rs @@ -22,7 +22,9 @@ impl super::C1SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C1SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c1v/mod.rs b/src/ftm3/c1v/mod.rs index 787745f..248a2b1 100644 --- a/src/ftm3/c1v/mod.rs +++ b/src/ftm3/c1v/mod.rs @@ -22,7 +22,9 @@ impl super::C1V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c2sc/mod.rs b/src/ftm3/c2sc/mod.rs index fa12b2b..e58d4c7 100644 --- a/src/ftm3/c2sc/mod.rs +++ b/src/ftm3/c2sc/mod.rs @@ -22,7 +22,9 @@ impl super::C2SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C2SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c2v/mod.rs b/src/ftm3/c2v/mod.rs index 9e3c3cd..b8ffb12 100644 --- a/src/ftm3/c2v/mod.rs +++ b/src/ftm3/c2v/mod.rs @@ -22,7 +22,9 @@ impl super::C2V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c3sc/mod.rs b/src/ftm3/c3sc/mod.rs index 2eaf887..6651e54 100644 --- a/src/ftm3/c3sc/mod.rs +++ b/src/ftm3/c3sc/mod.rs @@ -22,7 +22,9 @@ impl super::C3SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C3SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c3v/mod.rs b/src/ftm3/c3v/mod.rs index 43fb0c2..5cba611 100644 --- a/src/ftm3/c3v/mod.rs +++ b/src/ftm3/c3v/mod.rs @@ -22,7 +22,9 @@ impl super::C3V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c4sc/mod.rs b/src/ftm3/c4sc/mod.rs index bf925ca..fb92ce3 100644 --- a/src/ftm3/c4sc/mod.rs +++ b/src/ftm3/c4sc/mod.rs @@ -22,7 +22,9 @@ impl super::C4SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C4SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c4v/mod.rs b/src/ftm3/c4v/mod.rs index 234c36c..8ae59fc 100644 --- a/src/ftm3/c4v/mod.rs +++ b/src/ftm3/c4v/mod.rs @@ -22,7 +22,9 @@ impl super::C4V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c5sc/mod.rs b/src/ftm3/c5sc/mod.rs index e8cf2e7..603ff97 100644 --- a/src/ftm3/c5sc/mod.rs +++ b/src/ftm3/c5sc/mod.rs @@ -22,7 +22,9 @@ impl super::C5SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C5SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c5v/mod.rs b/src/ftm3/c5v/mod.rs index 067897f..4e32c51 100644 --- a/src/ftm3/c5v/mod.rs +++ b/src/ftm3/c5v/mod.rs @@ -22,7 +22,9 @@ impl super::C5V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c6sc/mod.rs b/src/ftm3/c6sc/mod.rs index 07b04a6..ba9dcbc 100644 --- a/src/ftm3/c6sc/mod.rs +++ b/src/ftm3/c6sc/mod.rs @@ -22,7 +22,9 @@ impl super::C6SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C6SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c6v/mod.rs b/src/ftm3/c6v/mod.rs index 51df3d8..d77fbb5 100644 --- a/src/ftm3/c6v/mod.rs +++ b/src/ftm3/c6v/mod.rs @@ -22,7 +22,9 @@ impl super::C6V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/c7sc/mod.rs b/src/ftm3/c7sc/mod.rs index c75e91b..c27a403 100644 --- a/src/ftm3/c7sc/mod.rs +++ b/src/ftm3/c7sc/mod.rs @@ -22,7 +22,9 @@ impl super::C7SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::C7SC { #[doc = "Possible values of the field `DMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAR { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl DMAR { #[doc = "Possible values of the field `ICRST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ICRSTR { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,10 +219,8 @@ impl MSBR { #[doc = "Possible values of the field `CHIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHIER { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -268,10 +264,8 @@ impl CHIER { #[doc = "Possible values of the field `CHF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHFR { - #[doc = "No channel (n) event has occurred."] - _0, - #[doc = "A channel (n) event has occurred."] - _1, + #[doc = "No channel (n) event has occurred."] _0, + #[doc = "A channel (n) event has occurred."] _1, } impl CHFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -315,8 +309,7 @@ impl CHFR { #[doc = "Possible values of the field `TRIGMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGMODER { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } @@ -362,10 +355,8 @@ impl TRIGMODER { #[doc = "Possible values of the field `CHIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHISR { - #[doc = "The channel (n) input is zero."] - _0, - #[doc = "The channel (n) input is one."] - _1, + #[doc = "The channel (n) input is zero."] _0, + #[doc = "The channel (n) input is one."] _1, } impl CHISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -409,10 +400,8 @@ impl CHISR { #[doc = "Possible values of the field `CHOV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHOVR { - #[doc = "The channel (n) output is zero."] - _0, - #[doc = "The channel (n) output is one."] - _1, + #[doc = "The channel (n) output is zero."] _0, + #[doc = "The channel (n) output is one."] _1, } impl CHOVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +444,8 @@ impl CHOVR { } #[doc = "Values that can be written to the field `DMA`"] pub enum DMAW { - #[doc = "Disable DMA transfers."] - _0, - #[doc = "Enable DMA transfers."] - _1, + #[doc = "Disable DMA transfers."] _0, + #[doc = "Enable DMA transfers."] _1, } impl DMAW { #[allow(missing_docs)] @@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> { } #[doc = "Values that can be written to the field `ICRST`"] pub enum ICRSTW { - #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] - _0, - #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] - _1, + #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0, + #[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1, } impl ICRSTW { #[allow(missing_docs)] @@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> { } #[doc = "Values that can be written to the field `CHIE`"] pub enum CHIEW { - #[doc = "Disable channel (n) interrupt. Use software polling."] - _0, - #[doc = "Enable channel (n) interrupt."] - _1, + #[doc = "Disable channel (n) interrupt. Use software polling."] _0, + #[doc = "Enable channel (n) interrupt."] _1, } impl CHIEW { #[allow(missing_docs)] @@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> { } #[doc = "Values that can be written to the field `TRIGMODE`"] pub enum TRIGMODEW { - #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] - _0, + #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0, #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."] _1, } diff --git a/src/ftm3/c7v/mod.rs b/src/ftm3/c7v/mod.rs index 7aca3b3..a258d58 100644 --- a/src/ftm3/c7v/mod.rs +++ b/src/ftm3/c7v/mod.rs @@ -22,7 +22,9 @@ impl super::C7V { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/cnt/mod.rs b/src/ftm3/cnt/mod.rs index c5ef1a1..2554297 100644 --- a/src/ftm3/cnt/mod.rs +++ b/src/ftm3/cnt/mod.rs @@ -22,7 +22,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/cntin/mod.rs b/src/ftm3/cntin/mod.rs index 8694d48..3b7f42f 100644 --- a/src/ftm3/cntin/mod.rs +++ b/src/ftm3/cntin/mod.rs @@ -22,7 +22,9 @@ impl super::CNTIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/combine/mod.rs b/src/ftm3/combine/mod.rs index 02885e8..10e7960 100644 --- a/src/ftm3/combine/mod.rs +++ b/src/ftm3/combine/mod.rs @@ -22,7 +22,9 @@ impl super::COMBINE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl COMBINE0R { #[doc = "Possible values of the field `COMP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP0R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl DECAPEN0R { #[doc = "Possible values of the field `DECAP0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP0R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,10 +177,8 @@ impl DECAP0R { #[doc = "Possible values of the field `DTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN0R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl DTEN0R { #[doc = "Possible values of the field `SYNCEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN0R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl SYNCEN0R { #[doc = "Possible values of the field `FAULTEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN0R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -362,10 +354,8 @@ impl COMBINE1R { #[doc = "Possible values of the field `COMP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP1R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -430,10 +420,8 @@ impl DECAPEN1R { #[doc = "Possible values of the field `DECAP1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP1R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -477,10 +465,8 @@ impl DECAP1R { #[doc = "Possible values of the field `DTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN1R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -524,10 +510,8 @@ impl DTEN1R { #[doc = "Possible values of the field `SYNCEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN1R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -571,10 +555,8 @@ impl SYNCEN1R { #[doc = "Possible values of the field `FAULTEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN1R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -660,10 +642,8 @@ impl COMBINE2R { #[doc = "Possible values of the field `COMP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP2R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -728,10 +708,8 @@ impl DECAPEN2R { #[doc = "Possible values of the field `DECAP2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP2R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -775,10 +753,8 @@ impl DECAP2R { #[doc = "Possible values of the field `DTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN2R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -822,10 +798,8 @@ impl DTEN2R { #[doc = "Possible values of the field `SYNCEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN2R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -869,10 +843,8 @@ impl SYNCEN2R { #[doc = "Possible values of the field `FAULTEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN2R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -958,10 +930,8 @@ impl COMBINE3R { #[doc = "Possible values of the field `COMP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum COMP3R { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1026,10 +996,8 @@ impl DECAPEN3R { #[doc = "Possible values of the field `DECAP3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DECAP3R { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1073,10 +1041,8 @@ impl DECAP3R { #[doc = "Possible values of the field `DTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTEN3R { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1120,10 +1086,8 @@ impl DTEN3R { #[doc = "Possible values of the field `SYNCEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCEN3R { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1167,10 +1131,8 @@ impl SYNCEN3R { #[doc = "Possible values of the field `FAULTEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTEN3R { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1257,10 +1219,8 @@ impl<'a> _COMBINE0W<'a> { } #[doc = "Values that can be written to the field `COMP0`"] pub enum COMP0W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP0W { #[allow(missing_docs)] @@ -1338,10 +1298,8 @@ impl<'a> _DECAPEN0W<'a> { } #[doc = "Values that can be written to the field `DECAP0`"] pub enum DECAP0W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP0W { #[allow(missing_docs)] @@ -1396,10 +1354,8 @@ impl<'a> _DECAP0W<'a> { } #[doc = "Values that can be written to the field `DTEN0`"] pub enum DTEN0W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN0W { #[allow(missing_docs)] @@ -1454,10 +1410,8 @@ impl<'a> _DTEN0W<'a> { } #[doc = "Values that can be written to the field `SYNCEN0`"] pub enum SYNCEN0W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN0W { #[allow(missing_docs)] @@ -1512,10 +1466,8 @@ impl<'a> _SYNCEN0W<'a> { } #[doc = "Values that can be written to the field `FAULTEN0`"] pub enum FAULTEN0W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN0W { #[allow(missing_docs)] @@ -1616,10 +1568,8 @@ impl<'a> _COMBINE1W<'a> { } #[doc = "Values that can be written to the field `COMP1`"] pub enum COMP1W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP1W { #[allow(missing_docs)] @@ -1697,10 +1647,8 @@ impl<'a> _DECAPEN1W<'a> { } #[doc = "Values that can be written to the field `DECAP1`"] pub enum DECAP1W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP1W { #[allow(missing_docs)] @@ -1755,10 +1703,8 @@ impl<'a> _DECAP1W<'a> { } #[doc = "Values that can be written to the field `DTEN1`"] pub enum DTEN1W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN1W { #[allow(missing_docs)] @@ -1813,10 +1759,8 @@ impl<'a> _DTEN1W<'a> { } #[doc = "Values that can be written to the field `SYNCEN1`"] pub enum SYNCEN1W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN1W { #[allow(missing_docs)] @@ -1871,10 +1815,8 @@ impl<'a> _SYNCEN1W<'a> { } #[doc = "Values that can be written to the field `FAULTEN1`"] pub enum FAULTEN1W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN1W { #[allow(missing_docs)] @@ -1975,10 +1917,8 @@ impl<'a> _COMBINE2W<'a> { } #[doc = "Values that can be written to the field `COMP2`"] pub enum COMP2W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP2W { #[allow(missing_docs)] @@ -2056,10 +1996,8 @@ impl<'a> _DECAPEN2W<'a> { } #[doc = "Values that can be written to the field `DECAP2`"] pub enum DECAP2W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP2W { #[allow(missing_docs)] @@ -2114,10 +2052,8 @@ impl<'a> _DECAP2W<'a> { } #[doc = "Values that can be written to the field `DTEN2`"] pub enum DTEN2W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN2W { #[allow(missing_docs)] @@ -2172,10 +2108,8 @@ impl<'a> _DTEN2W<'a> { } #[doc = "Values that can be written to the field `SYNCEN2`"] pub enum SYNCEN2W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN2W { #[allow(missing_docs)] @@ -2230,10 +2164,8 @@ impl<'a> _SYNCEN2W<'a> { } #[doc = "Values that can be written to the field `FAULTEN2`"] pub enum FAULTEN2W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN2W { #[allow(missing_docs)] @@ -2334,10 +2266,8 @@ impl<'a> _COMBINE3W<'a> { } #[doc = "Values that can be written to the field `COMP3`"] pub enum COMP3W { - #[doc = "The channel (n+1) output is the same as the channel (n) output."] - _0, - #[doc = "The channel (n+1) output is the complement of the channel (n) output."] - _1, + #[doc = "The channel (n+1) output is the same as the channel (n) output."] _0, + #[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1, } impl COMP3W { #[allow(missing_docs)] @@ -2415,10 +2345,8 @@ impl<'a> _DECAPEN3W<'a> { } #[doc = "Values that can be written to the field `DECAP3`"] pub enum DECAP3W { - #[doc = "The dual edge captures are inactive."] - _0, - #[doc = "The dual edge captures are active."] - _1, + #[doc = "The dual edge captures are inactive."] _0, + #[doc = "The dual edge captures are active."] _1, } impl DECAP3W { #[allow(missing_docs)] @@ -2473,10 +2401,8 @@ impl<'a> _DECAP3W<'a> { } #[doc = "Values that can be written to the field `DTEN3`"] pub enum DTEN3W { - #[doc = "The deadtime insertion in this pair of channels is disabled."] - _0, - #[doc = "The deadtime insertion in this pair of channels is enabled."] - _1, + #[doc = "The deadtime insertion in this pair of channels is disabled."] _0, + #[doc = "The deadtime insertion in this pair of channels is enabled."] _1, } impl DTEN3W { #[allow(missing_docs)] @@ -2531,10 +2457,8 @@ impl<'a> _DTEN3W<'a> { } #[doc = "Values that can be written to the field `SYNCEN3`"] pub enum SYNCEN3W { - #[doc = "The PWM synchronization in this pair of channels is disabled."] - _0, - #[doc = "The PWM synchronization in this pair of channels is enabled."] - _1, + #[doc = "The PWM synchronization in this pair of channels is disabled."] _0, + #[doc = "The PWM synchronization in this pair of channels is enabled."] _1, } impl SYNCEN3W { #[allow(missing_docs)] @@ -2589,10 +2513,8 @@ impl<'a> _SYNCEN3W<'a> { } #[doc = "Values that can be written to the field `FAULTEN3`"] pub enum FAULTEN3W { - #[doc = "The fault control in this pair of channels is disabled."] - _0, - #[doc = "The fault control in this pair of channels is enabled."] - _1, + #[doc = "The fault control in this pair of channels is disabled."] _0, + #[doc = "The fault control in this pair of channels is enabled."] _1, } impl FAULTEN3W { #[allow(missing_docs)] diff --git a/src/ftm3/conf/mod.rs b/src/ftm3/conf/mod.rs index 758ddf6..fe1706a 100644 --- a/src/ftm3/conf/mod.rs +++ b/src/ftm3/conf/mod.rs @@ -22,7 +22,9 @@ impl super::CONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -107,10 +109,8 @@ impl GTBEOUTR { #[doc = "Possible values of the field `ITRIGR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ITRIGRR { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -229,10 +229,8 @@ impl<'a> _GTBEOUTW<'a> { } #[doc = "Values that can be written to the field `ITRIGR`"] pub enum ITRIGRW { - #[doc = "Initialization trigger is generated on counter wrap events."] - _0, - #[doc = "Initialization trigger is generated when a reload point is reached."] - _1, + #[doc = "Initialization trigger is generated on counter wrap events."] _0, + #[doc = "Initialization trigger is generated when a reload point is reached."] _1, } impl ITRIGRW { #[allow(missing_docs)] diff --git a/src/ftm3/deadtime/mod.rs b/src/ftm3/deadtime/mod.rs index 3a9b0cf..f1dfdde 100644 --- a/src/ftm3/deadtime/mod.rs +++ b/src/ftm3/deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/exttrig/mod.rs b/src/ftm3/exttrig/mod.rs index cbd52f1..d85e308 100644 --- a/src/ftm3/exttrig/mod.rs +++ b/src/ftm3/exttrig/mod.rs @@ -22,7 +22,9 @@ impl super::EXTTRIG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::EXTTRIG { #[doc = "Possible values of the field `CH2TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH2TRIGR { #[doc = "Possible values of the field `CH3TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH3TRIGR { #[doc = "Possible values of the field `CH4TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH4TRIGR { #[doc = "Possible values of the field `CH5TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH5TRIGR { #[doc = "Possible values of the field `CH0TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH0TRIGR { #[doc = "Possible values of the field `CH1TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH1TRIGR { #[doc = "Possible values of the field `INITTRIGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INITTRIGENR { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl INITTRIGENR { #[doc = "Possible values of the field `TRIGF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIGFR { - #[doc = "No channel trigger was generated."] - _0, - #[doc = "A channel trigger was generated."] - _1, + #[doc = "No channel trigger was generated."] _0, + #[doc = "A channel trigger was generated."] _1, } impl TRIGFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl TRIGFR { #[doc = "Possible values of the field `CH6TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH6TRIGR { #[doc = "Possible values of the field `CH7TRIG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7TRIGR { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -512,10 +494,8 @@ impl CH7TRIGR { } #[doc = "Values that can be written to the field `CH2TRIG`"] pub enum CH2TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH2TRIGW { #[allow(missing_docs)] @@ -570,10 +550,8 @@ impl<'a> _CH2TRIGW<'a> { } #[doc = "Values that can be written to the field `CH3TRIG`"] pub enum CH3TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH3TRIGW { #[allow(missing_docs)] @@ -628,10 +606,8 @@ impl<'a> _CH3TRIGW<'a> { } #[doc = "Values that can be written to the field `CH4TRIG`"] pub enum CH4TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH4TRIGW { #[allow(missing_docs)] @@ -686,10 +662,8 @@ impl<'a> _CH4TRIGW<'a> { } #[doc = "Values that can be written to the field `CH5TRIG`"] pub enum CH5TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH5TRIGW { #[allow(missing_docs)] @@ -744,10 +718,8 @@ impl<'a> _CH5TRIGW<'a> { } #[doc = "Values that can be written to the field `CH0TRIG`"] pub enum CH0TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH0TRIGW { #[allow(missing_docs)] @@ -802,10 +774,8 @@ impl<'a> _CH0TRIGW<'a> { } #[doc = "Values that can be written to the field `CH1TRIG`"] pub enum CH1TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH1TRIGW { #[allow(missing_docs)] @@ -860,10 +830,8 @@ impl<'a> _CH1TRIGW<'a> { } #[doc = "Values that can be written to the field `INITTRIGEN`"] pub enum INITTRIGENW { - #[doc = "The generation of initialization trigger is disabled."] - _0, - #[doc = "The generation of initialization trigger is enabled."] - _1, + #[doc = "The generation of initialization trigger is disabled."] _0, + #[doc = "The generation of initialization trigger is enabled."] _1, } impl INITTRIGENW { #[allow(missing_docs)] @@ -918,10 +886,8 @@ impl<'a> _INITTRIGENW<'a> { } #[doc = "Values that can be written to the field `CH6TRIG`"] pub enum CH6TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH6TRIGW { #[allow(missing_docs)] @@ -976,10 +942,8 @@ impl<'a> _CH6TRIGW<'a> { } #[doc = "Values that can be written to the field `CH7TRIG`"] pub enum CH7TRIGW { - #[doc = "The generation of this external trigger is disabled."] - _0, - #[doc = "The generation of this external trigger is enabled."] - _1, + #[doc = "The generation of this external trigger is disabled."] _0, + #[doc = "The generation of this external trigger is enabled."] _1, } impl CH7TRIGW { #[allow(missing_docs)] diff --git a/src/ftm3/filter/mod.rs b/src/ftm3/filter/mod.rs index 30911ac..19ef737 100644 --- a/src/ftm3/filter/mod.rs +++ b/src/ftm3/filter/mod.rs @@ -22,7 +22,9 @@ impl super::FILTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/fltctrl/mod.rs b/src/ftm3/fltctrl/mod.rs index d85ff3c..792a4e9 100644 --- a/src/ftm3/fltctrl/mod.rs +++ b/src/ftm3/fltctrl/mod.rs @@ -22,7 +22,9 @@ impl super::FLTCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTCTRL { #[doc = "Possible values of the field `FAULT0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT0ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULT0ENR { #[doc = "Possible values of the field `FAULT1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT1ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULT1ENR { #[doc = "Possible values of the field `FAULT2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT2ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULT2ENR { #[doc = "Possible values of the field `FAULT3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULT3ENR { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULT3ENR { #[doc = "Possible values of the field `FFLTR0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR0ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FFLTR0ENR { #[doc = "Possible values of the field `FFLTR1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR1ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl FFLTR1ENR { #[doc = "Possible values of the field `FFLTR2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR2ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FFLTR2ENR { #[doc = "Possible values of the field `FFLTR3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FFLTR3ENR { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -432,8 +418,7 @@ impl FFVALR { pub enum FSTATER { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -476,10 +461,8 @@ impl FSTATER { } #[doc = "Values that can be written to the field `FAULT0EN`"] pub enum FAULT0ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT0ENW { #[allow(missing_docs)] @@ -534,10 +517,8 @@ impl<'a> _FAULT0ENW<'a> { } #[doc = "Values that can be written to the field `FAULT1EN`"] pub enum FAULT1ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT1ENW { #[allow(missing_docs)] @@ -592,10 +573,8 @@ impl<'a> _FAULT1ENW<'a> { } #[doc = "Values that can be written to the field `FAULT2EN`"] pub enum FAULT2ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT2ENW { #[allow(missing_docs)] @@ -650,10 +629,8 @@ impl<'a> _FAULT2ENW<'a> { } #[doc = "Values that can be written to the field `FAULT3EN`"] pub enum FAULT3ENW { - #[doc = "Fault input is disabled."] - _0, - #[doc = "Fault input is enabled."] - _1, + #[doc = "Fault input is disabled."] _0, + #[doc = "Fault input is enabled."] _1, } impl FAULT3ENW { #[allow(missing_docs)] @@ -708,10 +685,8 @@ impl<'a> _FAULT3ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR0EN`"] pub enum FFLTR0ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR0ENW { #[allow(missing_docs)] @@ -766,10 +741,8 @@ impl<'a> _FFLTR0ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR1EN`"] pub enum FFLTR1ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR1ENW { #[allow(missing_docs)] @@ -824,10 +797,8 @@ impl<'a> _FFLTR1ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR2EN`"] pub enum FFLTR2ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR2ENW { #[allow(missing_docs)] @@ -882,10 +853,8 @@ impl<'a> _FFLTR2ENW<'a> { } #[doc = "Values that can be written to the field `FFLTR3EN`"] pub enum FFLTR3ENW { - #[doc = "Fault input filter is disabled."] - _0, - #[doc = "Fault input filter is enabled."] - _1, + #[doc = "Fault input filter is disabled."] _0, + #[doc = "Fault input filter is enabled."] _1, } impl FFLTR3ENW { #[allow(missing_docs)] @@ -957,8 +926,7 @@ impl<'a> _FFVALW<'a> { pub enum FSTATEW { #[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."] _0, - #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] - _1, + #[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1, } impl FSTATEW { #[allow(missing_docs)] diff --git a/src/ftm3/fltpol/mod.rs b/src/ftm3/fltpol/mod.rs index 5b0170d..d99042f 100644 --- a/src/ftm3/fltpol/mod.rs +++ b/src/ftm3/fltpol/mod.rs @@ -22,7 +22,9 @@ impl super::FLTPOL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FLTPOL { #[doc = "Possible values of the field `FLT0POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT0POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FLT0POLR { #[doc = "Possible values of the field `FLT1POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT1POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FLT1POLR { #[doc = "Possible values of the field `FLT2POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT2POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FLT2POLR { #[doc = "Possible values of the field `FLT3POL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLT3POLR { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl FLT3POLR { } #[doc = "Values that can be written to the field `FLT0POL`"] pub enum FLT0POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT0POLW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _FLT0POLW<'a> { } #[doc = "Values that can be written to the field `FLT1POL`"] pub enum FLT1POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT1POLW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _FLT1POLW<'a> { } #[doc = "Values that can be written to the field `FLT2POL`"] pub enum FLT2POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT2POLW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _FLT2POLW<'a> { } #[doc = "Values that can be written to the field `FLT3POL`"] pub enum FLT3POLW { - #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] - _0, - #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] - _1, + #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0, + #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1, } impl FLT3POLW { #[allow(missing_docs)] diff --git a/src/ftm3/fms/mod.rs b/src/ftm3/fms/mod.rs index fb65c8b..61915be 100644 --- a/src/ftm3/fms/mod.rs +++ b/src/ftm3/fms/mod.rs @@ -22,7 +22,9 @@ impl super::FMS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FMS { #[doc = "Possible values of the field `FAULTF0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF0R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FAULTF0R { #[doc = "Possible values of the field `FAULTF1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF1R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FAULTF1R { #[doc = "Possible values of the field `FAULTF2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF2R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FAULTF2R { #[doc = "Possible values of the field `FAULTF3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTF3R { - #[doc = "No fault condition was detected at the fault input."] - _0, - #[doc = "A fault condition was detected at the fault input."] - _1, + #[doc = "No fault condition was detected at the fault input."] _0, + #[doc = "A fault condition was detected at the fault input."] _1, } impl FAULTF3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FAULTF3R { #[doc = "Possible values of the field `FAULTIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTINR { - #[doc = "The logic OR of the enabled fault inputs is 0."] - _0, - #[doc = "The logic OR of the enabled fault inputs is 1."] - _1, + #[doc = "The logic OR of the enabled fault inputs is 0."] _0, + #[doc = "The logic OR of the enabled fault inputs is 1."] _1, } impl FAULTINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FAULTINR { #[doc = "Possible values of the field `WPEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPENR { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl WPENR { #[doc = "Possible values of the field `FAULTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTFR { - #[doc = "No fault condition was detected."] - _0, - #[doc = "A fault condition was detected."] - _1, + #[doc = "No fault condition was detected."] _0, + #[doc = "A fault condition was detected."] _1, } impl FAULTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -371,10 +359,8 @@ impl FAULTFR { } #[doc = "Values that can be written to the field `WPEN`"] pub enum WPENW { - #[doc = "Write protection is disabled. Write protected bits can be written."] - _0, - #[doc = "Write protection is enabled. Write protected bits cannot be written."] - _1, + #[doc = "Write protection is disabled. Write protected bits can be written."] _0, + #[doc = "Write protection is enabled. Write protected bits cannot be written."] _1, } impl WPENW { #[allow(missing_docs)] diff --git a/src/ftm3/hcr/mod.rs b/src/ftm3/hcr/mod.rs index 6f87eca..dfcbde9 100644 --- a/src/ftm3/hcr/mod.rs +++ b/src/ftm3/hcr/mod.rs @@ -22,7 +22,9 @@ impl super::HCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/invctrl/mod.rs b/src/ftm3/invctrl/mod.rs index 23e094b..80e4e01 100644 --- a/src/ftm3/invctrl/mod.rs +++ b/src/ftm3/invctrl/mod.rs @@ -22,7 +22,9 @@ impl super::INVCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::INVCTRL { #[doc = "Possible values of the field `INV0EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV0ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl INV0ENR { #[doc = "Possible values of the field `INV1EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV1ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl INV1ENR { #[doc = "Possible values of the field `INV2EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV2ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl INV2ENR { #[doc = "Possible values of the field `INV3EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INV3ENR { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl INV3ENR { } #[doc = "Values that can be written to the field `INV0EN`"] pub enum INV0ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV0ENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _INV0ENW<'a> { } #[doc = "Values that can be written to the field `INV1EN`"] pub enum INV1ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV1ENW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _INV1ENW<'a> { } #[doc = "Values that can be written to the field `INV2EN`"] pub enum INV2ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV2ENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _INV2ENW<'a> { } #[doc = "Values that can be written to the field `INV3EN`"] pub enum INV3ENW { - #[doc = "Inverting is disabled."] - _0, - #[doc = "Inverting is enabled."] - _1, + #[doc = "Inverting is disabled."] _0, + #[doc = "Inverting is enabled."] _1, } impl INV3ENW { #[allow(missing_docs)] diff --git a/src/ftm3/mod.rs b/src/ftm3/mod.rs index 445c1aa..294f78f 100644 --- a/src/ftm3/mod.rs +++ b/src/ftm3/mod.rs @@ -2,97 +2,53 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status And Control"] - pub sc: SC, - #[doc = "0x04 - Counter"] - pub cnt: CNT, - #[doc = "0x08 - Modulo"] - pub mod_: MOD, - #[doc = "0x0c - Channel (n) Status And Control"] - pub c0sc: C0SC, - #[doc = "0x10 - Channel (n) Value"] - pub c0v: C0V, - #[doc = "0x14 - Channel (n) Status And Control"] - pub c1sc: C1SC, - #[doc = "0x18 - Channel (n) Value"] - pub c1v: C1V, - #[doc = "0x1c - Channel (n) Status And Control"] - pub c2sc: C2SC, - #[doc = "0x20 - Channel (n) Value"] - pub c2v: C2V, - #[doc = "0x24 - Channel (n) Status And Control"] - pub c3sc: C3SC, - #[doc = "0x28 - Channel (n) Value"] - pub c3v: C3V, - #[doc = "0x2c - Channel (n) Status And Control"] - pub c4sc: C4SC, - #[doc = "0x30 - Channel (n) Value"] - pub c4v: C4V, - #[doc = "0x34 - Channel (n) Status And Control"] - pub c5sc: C5SC, - #[doc = "0x38 - Channel (n) Value"] - pub c5v: C5V, - #[doc = "0x3c - Channel (n) Status And Control"] - pub c6sc: C6SC, - #[doc = "0x40 - Channel (n) Value"] - pub c6v: C6V, - #[doc = "0x44 - Channel (n) Status And Control"] - pub c7sc: C7SC, - #[doc = "0x48 - Channel (n) Value"] - pub c7v: C7V, - #[doc = "0x4c - Counter Initial Value"] - pub cntin: CNTIN, - #[doc = "0x50 - Capture And Compare Status"] - pub status: STATUS, - #[doc = "0x54 - Features Mode Selection"] - pub mode: MODE, - #[doc = "0x58 - Synchronization"] - pub sync: SYNC, - #[doc = "0x5c - Initial State For Channels Output"] - pub outinit: OUTINIT, - #[doc = "0x60 - Output Mask"] - pub outmask: OUTMASK, - #[doc = "0x64 - Function For Linked Channels"] - pub combine: COMBINE, - #[doc = "0x68 - Deadtime Configuration"] - pub deadtime: DEADTIME, - #[doc = "0x6c - FTM External Trigger"] - pub exttrig: EXTTRIG, - #[doc = "0x70 - Channels Polarity"] - pub pol: POL, - #[doc = "0x74 - Fault Mode Status"] - pub fms: FMS, - #[doc = "0x78 - Input Capture Filter Control"] - pub filter: FILTER, - #[doc = "0x7c - Fault Control"] - pub fltctrl: FLTCTRL, - #[doc = "0x80 - Quadrature Decoder Control And Status"] - pub qdctrl: QDCTRL, - #[doc = "0x84 - Configuration"] - pub conf: CONF, - #[doc = "0x88 - FTM Fault Input Polarity"] - pub fltpol: FLTPOL, - #[doc = "0x8c - Synchronization Configuration"] - pub synconf: SYNCONF, - #[doc = "0x90 - FTM Inverting Control"] - pub invctrl: INVCTRL, - #[doc = "0x94 - FTM Software Output Control"] - pub swoctrl: SWOCTRL, - #[doc = "0x98 - FTM PWM Load"] - pub pwmload: PWMLOAD, - #[doc = "0x9c - Half Cycle Register"] - pub hcr: HCR, - #[doc = "0xa0 - Pair 0 Deadtime Configuration"] - pub pair0deadtime: PAIR0DEADTIME, + #[doc = "0x00 - Status And Control"] pub sc: SC, + #[doc = "0x04 - Counter"] pub cnt: CNT, + #[doc = "0x08 - Modulo"] pub mod_: MOD, + #[doc = "0x0c - Channel (n) Status And Control"] pub c0sc: C0SC, + #[doc = "0x10 - Channel (n) Value"] pub c0v: C0V, + #[doc = "0x14 - Channel (n) Status And Control"] pub c1sc: C1SC, + #[doc = "0x18 - Channel (n) Value"] pub c1v: C1V, + #[doc = "0x1c - Channel (n) Status And Control"] pub c2sc: C2SC, + #[doc = "0x20 - Channel (n) Value"] pub c2v: C2V, + #[doc = "0x24 - Channel (n) Status And Control"] pub c3sc: C3SC, + #[doc = "0x28 - Channel (n) Value"] pub c3v: C3V, + #[doc = "0x2c - Channel (n) Status And Control"] pub c4sc: C4SC, + #[doc = "0x30 - Channel (n) Value"] pub c4v: C4V, + #[doc = "0x34 - Channel (n) Status And Control"] pub c5sc: C5SC, + #[doc = "0x38 - Channel (n) Value"] pub c5v: C5V, + #[doc = "0x3c - Channel (n) Status And Control"] pub c6sc: C6SC, + #[doc = "0x40 - Channel (n) Value"] pub c6v: C6V, + #[doc = "0x44 - Channel (n) Status And Control"] pub c7sc: C7SC, + #[doc = "0x48 - Channel (n) Value"] pub c7v: C7V, + #[doc = "0x4c - Counter Initial Value"] pub cntin: CNTIN, + #[doc = "0x50 - Capture And Compare Status"] pub status: STATUS, + #[doc = "0x54 - Features Mode Selection"] pub mode: MODE, + #[doc = "0x58 - Synchronization"] pub sync: SYNC, + #[doc = "0x5c - Initial State For Channels Output"] pub outinit: OUTINIT, + #[doc = "0x60 - Output Mask"] pub outmask: OUTMASK, + #[doc = "0x64 - Function For Linked Channels"] pub combine: COMBINE, + #[doc = "0x68 - Deadtime Configuration"] pub deadtime: DEADTIME, + #[doc = "0x6c - FTM External Trigger"] pub exttrig: EXTTRIG, + #[doc = "0x70 - Channels Polarity"] pub pol: POL, + #[doc = "0x74 - Fault Mode Status"] pub fms: FMS, + #[doc = "0x78 - Input Capture Filter Control"] pub filter: FILTER, + #[doc = "0x7c - Fault Control"] pub fltctrl: FLTCTRL, + #[doc = "0x80 - Quadrature Decoder Control And Status"] pub qdctrl: QDCTRL, + #[doc = "0x84 - Configuration"] pub conf: CONF, + #[doc = "0x88 - FTM Fault Input Polarity"] pub fltpol: FLTPOL, + #[doc = "0x8c - Synchronization Configuration"] pub synconf: SYNCONF, + #[doc = "0x90 - FTM Inverting Control"] pub invctrl: INVCTRL, + #[doc = "0x94 - FTM Software Output Control"] pub swoctrl: SWOCTRL, + #[doc = "0x98 - FTM PWM Load"] pub pwmload: PWMLOAD, + #[doc = "0x9c - Half Cycle Register"] pub hcr: HCR, + #[doc = "0xa0 - Pair 0 Deadtime Configuration"] pub pair0deadtime: PAIR0DEADTIME, _reserved0: [u8; 4usize], - #[doc = "0xa8 - Pair 1 Deadtime Configuration"] - pub pair1deadtime: PAIR1DEADTIME, + #[doc = "0xa8 - Pair 1 Deadtime Configuration"] pub pair1deadtime: PAIR1DEADTIME, _reserved1: [u8; 4usize], - #[doc = "0xb0 - Pair 2 Deadtime Configuration"] - pub pair2deadtime: PAIR2DEADTIME, + #[doc = "0xb0 - Pair 2 Deadtime Configuration"] pub pair2deadtime: PAIR2DEADTIME, _reserved2: [u8; 4usize], - #[doc = "0xb8 - Pair 3 Deadtime Configuration"] - pub pair3deadtime: PAIR3DEADTIME, + #[doc = "0xb8 - Pair 3 Deadtime Configuration"] pub pair3deadtime: PAIR3DEADTIME, } #[doc = "Status And Control"] pub struct SC { diff --git a/src/ftm3/mod_/mod.rs b/src/ftm3/mod_/mod.rs index 9ef76ef..448895c 100644 --- a/src/ftm3/mod_/mod.rs +++ b/src/ftm3/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ftm3/mode/mod.rs b/src/ftm3/mode/mod.rs index 6a8e2ac..c4bd468 100644 --- a/src/ftm3/mode/mod.rs +++ b/src/ftm3/mode/mod.rs @@ -22,7 +22,9 @@ impl super::MODE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MODE { #[doc = "Possible values of the field `FTMEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTMENR { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FTMENR { #[doc = "Possible values of the field `WPDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WPDISR { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl PWMSYNCR { #[doc = "Possible values of the field `CAPTEST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CAPTESTR { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,8 +227,7 @@ impl CAPTESTR { #[doc = "Possible values of the field `FAULTM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTMR { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -287,10 +282,8 @@ impl FAULTMR { #[doc = "Possible values of the field `FAULTIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FAULTIER { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -333,10 +326,8 @@ impl FAULTIER { } #[doc = "Values that can be written to the field `FTMEN`"] pub enum FTMENW { - #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] - _0, - #[doc = "Free running counter and synchronization are different from TPM behavior."] - _1, + #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0, + #[doc = "Free running counter and synchronization are different from TPM behavior."] _1, } impl FTMENW { #[allow(missing_docs)] @@ -414,10 +405,8 @@ impl<'a> _INITW<'a> { } #[doc = "Values that can be written to the field `WPDIS`"] pub enum WPDISW { - #[doc = "Write protection is enabled."] - _0, - #[doc = "Write protection is disabled."] - _1, + #[doc = "Write protection is enabled."] _0, + #[doc = "Write protection is disabled."] _1, } impl WPDISW { #[allow(missing_docs)] @@ -530,10 +519,8 @@ impl<'a> _PWMSYNCW<'a> { } #[doc = "Values that can be written to the field `CAPTEST`"] pub enum CAPTESTW { - #[doc = "Capture test mode is disabled."] - _0, - #[doc = "Capture test mode is enabled."] - _1, + #[doc = "Capture test mode is disabled."] _0, + #[doc = "Capture test mode is enabled."] _1, } impl CAPTESTW { #[allow(missing_docs)] @@ -588,8 +575,7 @@ impl<'a> _CAPTESTW<'a> { } #[doc = "Values that can be written to the field `FAULTM`"] pub enum FAULTMW { - #[doc = "Fault control is disabled for all channels."] - _00, + #[doc = "Fault control is disabled for all channels."] _00, #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."] _01, #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."] @@ -654,10 +640,8 @@ impl<'a> _FAULTMW<'a> { } #[doc = "Values that can be written to the field `FAULTIE`"] pub enum FAULTIEW { - #[doc = "Fault control interrupt is disabled."] - _0, - #[doc = "Fault control interrupt is enabled."] - _1, + #[doc = "Fault control interrupt is disabled."] _0, + #[doc = "Fault control interrupt is enabled."] _1, } impl FAULTIEW { #[allow(missing_docs)] diff --git a/src/ftm3/outinit/mod.rs b/src/ftm3/outinit/mod.rs index 5b3b985..10e2df4 100644 --- a/src/ftm3/outinit/mod.rs +++ b/src/ftm3/outinit/mod.rs @@ -22,7 +22,9 @@ impl super::OUTINIT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTINIT { #[doc = "Possible values of the field `CH0OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OIR { #[doc = "Possible values of the field `CH1OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OIR { #[doc = "Possible values of the field `CH2OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OIR { #[doc = "Possible values of the field `CH3OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OIR { #[doc = "Possible values of the field `CH4OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OIR { #[doc = "Possible values of the field `CH5OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OIR { #[doc = "Possible values of the field `CH6OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OIR { #[doc = "Possible values of the field `CH7OI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OIR { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OIR { } #[doc = "Values that can be written to the field `CH0OI`"] pub enum CH0OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH0OIW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OIW<'a> { } #[doc = "Values that can be written to the field `CH1OI`"] pub enum CH1OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH1OIW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OIW<'a> { } #[doc = "Values that can be written to the field `CH2OI`"] pub enum CH2OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH2OIW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OIW<'a> { } #[doc = "Values that can be written to the field `CH3OI`"] pub enum CH3OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH3OIW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OIW<'a> { } #[doc = "Values that can be written to the field `CH4OI`"] pub enum CH4OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH4OIW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OIW<'a> { } #[doc = "Values that can be written to the field `CH5OI`"] pub enum CH5OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH5OIW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OIW<'a> { } #[doc = "Values that can be written to the field `CH6OI`"] pub enum CH6OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH6OIW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OIW<'a> { } #[doc = "Values that can be written to the field `CH7OI`"] pub enum CH7OIW { - #[doc = "The initialization value is 0."] - _0, - #[doc = "The initialization value is 1."] - _1, + #[doc = "The initialization value is 0."] _0, + #[doc = "The initialization value is 1."] _1, } impl CH7OIW { #[allow(missing_docs)] diff --git a/src/ftm3/outmask/mod.rs b/src/ftm3/outmask/mod.rs index f9a4723..6d525e0 100644 --- a/src/ftm3/outmask/mod.rs +++ b/src/ftm3/outmask/mod.rs @@ -22,7 +22,9 @@ impl super::OUTMASK { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::OUTMASK { #[doc = "Possible values of the field `CH0OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OMR { #[doc = "Possible values of the field `CH1OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OMR { #[doc = "Possible values of the field `CH2OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OMR { #[doc = "Possible values of the field `CH3OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OMR { #[doc = "Possible values of the field `CH4OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OMR { #[doc = "Possible values of the field `CH5OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OMR { #[doc = "Possible values of the field `CH6OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OMR { #[doc = "Possible values of the field `CH7OM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OMR { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl CH7OMR { } #[doc = "Values that can be written to the field `CH0OM`"] pub enum CH0OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH0OMW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _CH0OMW<'a> { } #[doc = "Values that can be written to the field `CH1OM`"] pub enum CH1OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH1OMW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _CH1OMW<'a> { } #[doc = "Values that can be written to the field `CH2OM`"] pub enum CH2OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH2OMW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _CH2OMW<'a> { } #[doc = "Values that can be written to the field `CH3OM`"] pub enum CH3OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH3OMW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _CH3OMW<'a> { } #[doc = "Values that can be written to the field `CH4OM`"] pub enum CH4OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH4OMW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _CH4OMW<'a> { } #[doc = "Values that can be written to the field `CH5OM`"] pub enum CH5OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH5OMW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _CH5OMW<'a> { } #[doc = "Values that can be written to the field `CH6OM`"] pub enum CH6OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH6OMW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _CH6OMW<'a> { } #[doc = "Values that can be written to the field `CH7OM`"] pub enum CH7OMW { - #[doc = "Channel output is not masked. It continues to operate normally."] - _0, - #[doc = "Channel output is masked. It is forced to its inactive state."] - _1, + #[doc = "Channel output is not masked. It continues to operate normally."] _0, + #[doc = "Channel output is masked. It is forced to its inactive state."] _1, } impl CH7OMW { #[allow(missing_docs)] diff --git a/src/ftm3/pair0deadtime/mod.rs b/src/ftm3/pair0deadtime/mod.rs index 57b7430..24b3a06 100644 --- a/src/ftm3/pair0deadtime/mod.rs +++ b/src/ftm3/pair0deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR0DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/pair1deadtime/mod.rs b/src/ftm3/pair1deadtime/mod.rs index 54a2334..bd244e2 100644 --- a/src/ftm3/pair1deadtime/mod.rs +++ b/src/ftm3/pair1deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR1DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/pair2deadtime/mod.rs b/src/ftm3/pair2deadtime/mod.rs index 5073dba..9e96c87 100644 --- a/src/ftm3/pair2deadtime/mod.rs +++ b/src/ftm3/pair2deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR2DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/pair3deadtime/mod.rs b/src/ftm3/pair3deadtime/mod.rs index bcb2471..d925ba8 100644 --- a/src/ftm3/pair3deadtime/mod.rs +++ b/src/ftm3/pair3deadtime/mod.rs @@ -22,7 +22,9 @@ impl super::PAIR3DEADTIME { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl DTVALR { #[doc = "Possible values of the field `DTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DTPSR { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl DTPSR { #[doc = r" Value of the field as raw bits"] @@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> { } #[doc = "Values that can be written to the field `DTPS`"] pub enum DTPSW { - #[doc = "Divide the FTM input clock by 1."] - _0X, - #[doc = "Divide the FTM input clock by 4."] - _10, - #[doc = "Divide the FTM input clock by 16."] - _11, + #[doc = "Divide the FTM input clock by 1."] _0X, + #[doc = "Divide the FTM input clock by 4."] _10, + #[doc = "Divide the FTM input clock by 16."] _11, } impl DTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/pol/mod.rs b/src/ftm3/pol/mod.rs index 822ce37..56d0d5a 100644 --- a/src/ftm3/pol/mod.rs +++ b/src/ftm3/pol/mod.rs @@ -22,7 +22,9 @@ impl super::POL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::POL { #[doc = "Possible values of the field `POL0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL0R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl POL0R { #[doc = "Possible values of the field `POL1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL1R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl POL1R { #[doc = "Possible values of the field `POL2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL2R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl POL2R { #[doc = "Possible values of the field `POL3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL3R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl POL3R { #[doc = "Possible values of the field `POL4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL4R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl POL4R { #[doc = "Possible values of the field `POL5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL5R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl POL5R { #[doc = "Possible values of the field `POL6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL6R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl POL6R { #[doc = "Possible values of the field `POL7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POL7R { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl POL7R { } #[doc = "Values that can be written to the field `POL0`"] pub enum POL0W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL0W { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _POL0W<'a> { } #[doc = "Values that can be written to the field `POL1`"] pub enum POL1W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL1W { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _POL1W<'a> { } #[doc = "Values that can be written to the field `POL2`"] pub enum POL2W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL2W { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _POL2W<'a> { } #[doc = "Values that can be written to the field `POL3`"] pub enum POL3W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL3W { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _POL3W<'a> { } #[doc = "Values that can be written to the field `POL4`"] pub enum POL4W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL4W { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _POL4W<'a> { } #[doc = "Values that can be written to the field `POL5`"] pub enum POL5W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL5W { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _POL5W<'a> { } #[doc = "Values that can be written to the field `POL6`"] pub enum POL6W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL6W { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _POL6W<'a> { } #[doc = "Values that can be written to the field `POL7`"] pub enum POL7W { - #[doc = "The channel polarity is active high."] - _0, - #[doc = "The channel polarity is active low."] - _1, + #[doc = "The channel polarity is active high."] _0, + #[doc = "The channel polarity is active low."] _1, } impl POL7W { #[allow(missing_docs)] diff --git a/src/ftm3/pwmload/mod.rs b/src/ftm3/pwmload/mod.rs index c95d704..e3ad1a9 100644 --- a/src/ftm3/pwmload/mod.rs +++ b/src/ftm3/pwmload/mod.rs @@ -22,7 +22,9 @@ impl super::PWMLOAD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PWMLOAD { #[doc = "Possible values of the field `CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0SELR { #[doc = "Possible values of the field `CH1SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1SELR { #[doc = "Possible values of the field `CH2SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2SELR { #[doc = "Possible values of the field `CH3SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3SELR { #[doc = "Possible values of the field `CH4SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4SELR { #[doc = "Possible values of the field `CH5SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5SELR { #[doc = "Possible values of the field `CH6SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6SELR { #[doc = "Possible values of the field `CH7SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7SELR { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7SELR { #[doc = "Possible values of the field `HCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HCSELR { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl HCSELR { #[doc = "Possible values of the field `LDOK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LDOKR { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,8 +495,7 @@ impl LDOKR { #[doc = "Possible values of the field `GLEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GLENR { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -559,10 +540,8 @@ impl GLENR { } #[doc = "Values that can be written to the field `CH0SEL`"] pub enum CH0SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH0SELW { #[allow(missing_docs)] @@ -617,10 +596,8 @@ impl<'a> _CH0SELW<'a> { } #[doc = "Values that can be written to the field `CH1SEL`"] pub enum CH1SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH1SELW { #[allow(missing_docs)] @@ -675,10 +652,8 @@ impl<'a> _CH1SELW<'a> { } #[doc = "Values that can be written to the field `CH2SEL`"] pub enum CH2SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH2SELW { #[allow(missing_docs)] @@ -733,10 +708,8 @@ impl<'a> _CH2SELW<'a> { } #[doc = "Values that can be written to the field `CH3SEL`"] pub enum CH3SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH3SELW { #[allow(missing_docs)] @@ -791,10 +764,8 @@ impl<'a> _CH3SELW<'a> { } #[doc = "Values that can be written to the field `CH4SEL`"] pub enum CH4SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH4SELW { #[allow(missing_docs)] @@ -849,10 +820,8 @@ impl<'a> _CH4SELW<'a> { } #[doc = "Values that can be written to the field `CH5SEL`"] pub enum CH5SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH5SELW { #[allow(missing_docs)] @@ -907,10 +876,8 @@ impl<'a> _CH5SELW<'a> { } #[doc = "Values that can be written to the field `CH6SEL`"] pub enum CH6SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH6SELW { #[allow(missing_docs)] @@ -965,10 +932,8 @@ impl<'a> _CH6SELW<'a> { } #[doc = "Values that can be written to the field `CH7SEL`"] pub enum CH7SELW { - #[doc = "Channel match is not included as a reload opportunity."] - _0, - #[doc = "Channel match is included as a reload opportunity."] - _1, + #[doc = "Channel match is not included as a reload opportunity."] _0, + #[doc = "Channel match is included as a reload opportunity."] _1, } impl CH7SELW { #[allow(missing_docs)] @@ -1023,10 +988,8 @@ impl<'a> _CH7SELW<'a> { } #[doc = "Values that can be written to the field `HCSEL`"] pub enum HCSELW { - #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] - _0, - #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] - _1, + #[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0, + #[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1, } impl HCSELW { #[allow(missing_docs)] @@ -1081,10 +1044,8 @@ impl<'a> _HCSELW<'a> { } #[doc = "Values that can be written to the field `LDOK`"] pub enum LDOKW { - #[doc = "Loading updated values is disabled."] - _0, - #[doc = "Loading updated values is enabled."] - _1, + #[doc = "Loading updated values is disabled."] _0, + #[doc = "Loading updated values is enabled."] _1, } impl LDOKW { #[allow(missing_docs)] @@ -1139,8 +1100,7 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `GLEN`"] pub enum GLENW { - #[doc = "Global Load Ok disabled."] - _0, + #[doc = "Global Load Ok disabled."] _0, #[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."] _1, } @@ -1197,10 +1157,8 @@ impl<'a> _GLENW<'a> { } #[doc = "Values that can be written to the field `GLDOK`"] pub enum GLDOKW { - #[doc = "No action."] - _0, - #[doc = "LDOK bit is set."] - _1, + #[doc = "No action."] _0, + #[doc = "LDOK bit is set."] _1, } impl GLDOKW { #[allow(missing_docs)] diff --git a/src/ftm3/qdctrl/mod.rs b/src/ftm3/qdctrl/mod.rs index dee224c..cccabd7 100644 --- a/src/ftm3/qdctrl/mod.rs +++ b/src/ftm3/qdctrl/mod.rs @@ -22,7 +22,9 @@ impl super::QDCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::QDCTRL { #[doc = "Possible values of the field `QUADEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADENR { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +137,8 @@ impl TOFDIRR { #[doc = "Possible values of the field `QUADIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADIRR { - #[doc = "Counting direction is decreasing (FTM counter decrement)."] - _0, - #[doc = "Counting direction is increasing (FTM counter increment)."] - _1, + #[doc = "Counting direction is decreasing (FTM counter decrement)."] _0, + #[doc = "Counting direction is increasing (FTM counter increment)."] _1, } impl QUADIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl QUADIRR { #[doc = "Possible values of the field `QUADMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum QUADMODER { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +321,8 @@ impl PHAPOLR { #[doc = "Possible values of the field `PHBFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHBFLTRENR { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl PHBFLTRENR { #[doc = "Possible values of the field `PHAFLTREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHAFLTRENR { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +410,8 @@ impl PHAFLTRENR { } #[doc = "Values that can be written to the field `QUADEN`"] pub enum QUADENW { - #[doc = "Quadrature Decoder mode is disabled."] - _0, - #[doc = "Quadrature Decoder mode is enabled."] - _1, + #[doc = "Quadrature Decoder mode is disabled."] _0, + #[doc = "Quadrature Decoder mode is enabled."] _1, } impl QUADENW { #[allow(missing_docs)] @@ -476,10 +466,8 @@ impl<'a> _QUADENW<'a> { } #[doc = "Values that can be written to the field `QUADMODE`"] pub enum QUADMODEW { - #[doc = "Phase A and phase B encoding mode."] - _0, - #[doc = "Count and direction encoding mode."] - _1, + #[doc = "Phase A and phase B encoding mode."] _0, + #[doc = "Count and direction encoding mode."] _1, } impl QUADMODEW { #[allow(missing_docs)] @@ -650,10 +638,8 @@ impl<'a> _PHAPOLW<'a> { } #[doc = "Values that can be written to the field `PHBFLTREN`"] pub enum PHBFLTRENW { - #[doc = "Phase B input filter is disabled."] - _0, - #[doc = "Phase B input filter is enabled."] - _1, + #[doc = "Phase B input filter is disabled."] _0, + #[doc = "Phase B input filter is enabled."] _1, } impl PHBFLTRENW { #[allow(missing_docs)] @@ -708,10 +694,8 @@ impl<'a> _PHBFLTRENW<'a> { } #[doc = "Values that can be written to the field `PHAFLTREN`"] pub enum PHAFLTRENW { - #[doc = "Phase A input filter is disabled."] - _0, - #[doc = "Phase A input filter is enabled."] - _1, + #[doc = "Phase A input filter is disabled."] _0, + #[doc = "Phase A input filter is enabled."] _1, } impl PHAFLTRENW { #[allow(missing_docs)] diff --git a/src/ftm3/sc/mod.rs b/src/ftm3/sc/mod.rs index 24d7055..abe8d66 100644 --- a/src/ftm3/sc/mod.rs +++ b/src/ftm3/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SC { #[doc = "Possible values of the field `PS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PSR { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSR { #[doc = r" Value of the field as raw bits"] @@ -135,14 +129,10 @@ impl PSR { #[doc = "Possible values of the field `CLKS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKSR { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSR { #[doc = r" Value of the field as raw bits"] @@ -191,10 +181,8 @@ impl CLKSR { #[doc = "Possible values of the field `CPWMS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPWMSR { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -238,10 +226,8 @@ impl CPWMSR { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -285,10 +271,8 @@ impl RIER { #[doc = "Possible values of the field `RF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RFR { - #[doc = "A selected reload point did not happen."] - _0, - #[doc = "A selected reload point happened."] - _1, + #[doc = "A selected reload point did not happen."] _0, + #[doc = "A selected reload point happened."] _1, } impl RFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -332,10 +316,8 @@ impl RFR { #[doc = "Possible values of the field `TOIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOIER { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -379,10 +361,8 @@ impl TOIER { #[doc = "Possible values of the field `TOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOFR { - #[doc = "FTM counter has not overflowed."] - _0, - #[doc = "FTM counter has overflowed."] - _1, + #[doc = "FTM counter has not overflowed."] _0, + #[doc = "FTM counter has overflowed."] _1, } impl TOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -426,10 +406,8 @@ impl TOFR { #[doc = "Possible values of the field `PWMEN0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN0R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -473,10 +451,8 @@ impl PWMEN0R { #[doc = "Possible values of the field `PWMEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN1R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -520,10 +496,8 @@ impl PWMEN1R { #[doc = "Possible values of the field `PWMEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN2R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -567,10 +541,8 @@ impl PWMEN2R { #[doc = "Possible values of the field `PWMEN3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN3R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -614,10 +586,8 @@ impl PWMEN3R { #[doc = "Possible values of the field `PWMEN4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN4R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -661,10 +631,8 @@ impl PWMEN4R { #[doc = "Possible values of the field `PWMEN5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN5R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -708,10 +676,8 @@ impl PWMEN5R { #[doc = "Possible values of the field `PWMEN6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN6R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -755,10 +721,8 @@ impl PWMEN6R { #[doc = "Possible values of the field `PWMEN7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PWMEN7R { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -802,38 +766,22 @@ impl PWMEN7R { #[doc = "Possible values of the field `FLTPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLTPSR { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSR { #[doc = r" Value of the field as raw bits"] @@ -965,22 +913,14 @@ impl FLTPSR { } #[doc = "Values that can be written to the field `PS`"] pub enum PSW { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 4"] - _010, - #[doc = "Divide by 8"] - _011, - #[doc = "Divide by 16"] - _100, - #[doc = "Divide by 32"] - _101, - #[doc = "Divide by 64"] - _110, - #[doc = "Divide by 128"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 4"] _010, + #[doc = "Divide by 8"] _011, + #[doc = "Divide by 16"] _100, + #[doc = "Divide by 32"] _101, + #[doc = "Divide by 64"] _110, + #[doc = "Divide by 128"] _111, } impl PSW { #[allow(missing_docs)] @@ -1063,14 +1003,10 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `CLKS`"] pub enum CLKSW { - #[doc = "No clock selected. This in effect disables the FTM counter."] - _00, - #[doc = "FTM input clock"] - _01, - #[doc = "Fixed frequency clock"] - _10, - #[doc = "External clock"] - _11, + #[doc = "No clock selected. This in effect disables the FTM counter."] _00, + #[doc = "FTM input clock"] _01, + #[doc = "Fixed frequency clock"] _10, + #[doc = "External clock"] _11, } impl CLKSW { #[allow(missing_docs)] @@ -1129,10 +1065,8 @@ impl<'a> _CLKSW<'a> { } #[doc = "Values that can be written to the field `CPWMS`"] pub enum CPWMSW { - #[doc = "FTM counter operates in Up Counting mode."] - _0, - #[doc = "FTM counter operates in Up-Down Counting mode."] - _1, + #[doc = "FTM counter operates in Up Counting mode."] _0, + #[doc = "FTM counter operates in Up-Down Counting mode."] _1, } impl CPWMSW { #[allow(missing_docs)] @@ -1187,10 +1121,8 @@ impl<'a> _CPWMSW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Reload point interrupt is disabled."] - _0, - #[doc = "Reload point interrupt is enabled."] - _1, + #[doc = "Reload point interrupt is disabled."] _0, + #[doc = "Reload point interrupt is enabled."] _1, } impl RIEW { #[allow(missing_docs)] @@ -1245,10 +1177,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TOIE`"] pub enum TOIEW { - #[doc = "Disable TOF interrupts. Use software polling."] - _0, - #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] - _1, + #[doc = "Disable TOF interrupts. Use software polling."] _0, + #[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1, } impl TOIEW { #[allow(missing_docs)] @@ -1303,10 +1233,8 @@ impl<'a> _TOIEW<'a> { } #[doc = "Values that can be written to the field `PWMEN0`"] pub enum PWMEN0W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN0W { #[allow(missing_docs)] @@ -1361,10 +1289,8 @@ impl<'a> _PWMEN0W<'a> { } #[doc = "Values that can be written to the field `PWMEN1`"] pub enum PWMEN1W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN1W { #[allow(missing_docs)] @@ -1419,10 +1345,8 @@ impl<'a> _PWMEN1W<'a> { } #[doc = "Values that can be written to the field `PWMEN2`"] pub enum PWMEN2W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN2W { #[allow(missing_docs)] @@ -1477,10 +1401,8 @@ impl<'a> _PWMEN2W<'a> { } #[doc = "Values that can be written to the field `PWMEN3`"] pub enum PWMEN3W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN3W { #[allow(missing_docs)] @@ -1535,10 +1457,8 @@ impl<'a> _PWMEN3W<'a> { } #[doc = "Values that can be written to the field `PWMEN4`"] pub enum PWMEN4W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN4W { #[allow(missing_docs)] @@ -1593,10 +1513,8 @@ impl<'a> _PWMEN4W<'a> { } #[doc = "Values that can be written to the field `PWMEN5`"] pub enum PWMEN5W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN5W { #[allow(missing_docs)] @@ -1651,10 +1569,8 @@ impl<'a> _PWMEN5W<'a> { } #[doc = "Values that can be written to the field `PWMEN6`"] pub enum PWMEN6W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN6W { #[allow(missing_docs)] @@ -1709,10 +1625,8 @@ impl<'a> _PWMEN6W<'a> { } #[doc = "Values that can be written to the field `PWMEN7`"] pub enum PWMEN7W { - #[doc = "Channel output port is disabled"] - _0, - #[doc = "Channel output port is enabled"] - _1, + #[doc = "Channel output port is disabled"] _0, + #[doc = "Channel output port is enabled"] _1, } impl PWMEN7W { #[allow(missing_docs)] @@ -1767,38 +1681,22 @@ impl<'a> _PWMEN7W<'a> { } #[doc = "Values that can be written to the field `FLTPS`"] pub enum FLTPSW { - #[doc = "Divide by 1"] - _0000, - #[doc = "Divide by 2"] - _0001, - #[doc = "Divide by 3"] - _0010, - #[doc = "Divide by 4"] - _0011, - #[doc = "Divide by 5"] - _0100, - #[doc = "Divide by 6"] - _0101, - #[doc = "Divide by 7"] - _0110, - #[doc = "Divide by 8"] - _0111, - #[doc = "Divide by 9"] - _1000, - #[doc = "Divide by 10"] - _1001, - #[doc = "Divide by 11"] - _1010, - #[doc = "Divide by 12"] - _1011, - #[doc = "Divide by 13"] - _1100, - #[doc = "Divide by 14"] - _1101, - #[doc = "Divide by 15"] - _1110, - #[doc = "Divide by 16"] - _1111, + #[doc = "Divide by 1"] _0000, + #[doc = "Divide by 2"] _0001, + #[doc = "Divide by 3"] _0010, + #[doc = "Divide by 4"] _0011, + #[doc = "Divide by 5"] _0100, + #[doc = "Divide by 6"] _0101, + #[doc = "Divide by 7"] _0110, + #[doc = "Divide by 8"] _0111, + #[doc = "Divide by 9"] _1000, + #[doc = "Divide by 10"] _1001, + #[doc = "Divide by 11"] _1010, + #[doc = "Divide by 12"] _1011, + #[doc = "Divide by 13"] _1100, + #[doc = "Divide by 14"] _1101, + #[doc = "Divide by 15"] _1110, + #[doc = "Divide by 16"] _1111, } impl FLTPSW { #[allow(missing_docs)] diff --git a/src/ftm3/status/mod.rs b/src/ftm3/status/mod.rs index a808509..bc08657 100644 --- a/src/ftm3/status/mod.rs +++ b/src/ftm3/status/mod.rs @@ -6,16 +6,16 @@ impl super::STATUS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `CH0F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH0FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl CH0FR { #[doc = "Possible values of the field `CH1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl CH1FR { #[doc = "Possible values of the field `CH2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl CH2FR { #[doc = "Possible values of the field `CH3F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH3FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl CH3FR { #[doc = "Possible values of the field `CH4F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH4FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl CH4FR { #[doc = "Possible values of the field `CH5F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH5FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CH5FR { #[doc = "Possible values of the field `CH6F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH6FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl CH6FR { #[doc = "Possible values of the field `CH7F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7FR { - #[doc = "No channel event has occurred."] - _0, - #[doc = "A channel event has occurred."] - _1, + #[doc = "No channel event has occurred."] _0, + #[doc = "A channel event has occurred."] _1, } impl CH7FR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/ftm3/swoctrl/mod.rs b/src/ftm3/swoctrl/mod.rs index 247b3ec..49d6fc8 100644 --- a/src/ftm3/swoctrl/mod.rs +++ b/src/ftm3/swoctrl/mod.rs @@ -22,7 +22,9 @@ impl super::SWOCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SWOCTRL { #[doc = "Possible values of the field `CH0OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CH0OCR { #[doc = "Possible values of the field `CH1OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CH1OCR { #[doc = "Possible values of the field `CH2OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CH2OCR { #[doc = "Possible values of the field `CH3OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CH3OCR { #[doc = "Possible values of the field `CH4OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl CH4OCR { #[doc = "Possible values of the field `CH5OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl CH5OCR { #[doc = "Possible values of the field `CH6OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl CH6OCR { #[doc = "Possible values of the field `CH7OC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCR { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl CH7OCR { #[doc = "Possible values of the field `CH0OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl CH0OCVR { #[doc = "Possible values of the field `CH1OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH1OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl CH1OCVR { #[doc = "Possible values of the field `CH2OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH2OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl CH2OCVR { #[doc = "Possible values of the field `CH3OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH3OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl CH3OCVR { #[doc = "Possible values of the field `CH4OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH4OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl CH4OCVR { #[doc = "Possible values of the field `CH5OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH5OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +675,8 @@ impl CH5OCVR { #[doc = "Possible values of the field `CH6OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH6OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -748,10 +720,8 @@ impl CH6OCVR { #[doc = "Possible values of the field `CH7OCV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH7OCVR { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -794,10 +764,8 @@ impl CH7OCVR { } #[doc = "Values that can be written to the field `CH0OC`"] pub enum CH0OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH0OCW { #[allow(missing_docs)] @@ -852,10 +820,8 @@ impl<'a> _CH0OCW<'a> { } #[doc = "Values that can be written to the field `CH1OC`"] pub enum CH1OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH1OCW { #[allow(missing_docs)] @@ -910,10 +876,8 @@ impl<'a> _CH1OCW<'a> { } #[doc = "Values that can be written to the field `CH2OC`"] pub enum CH2OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH2OCW { #[allow(missing_docs)] @@ -968,10 +932,8 @@ impl<'a> _CH2OCW<'a> { } #[doc = "Values that can be written to the field `CH3OC`"] pub enum CH3OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH3OCW { #[allow(missing_docs)] @@ -1026,10 +988,8 @@ impl<'a> _CH3OCW<'a> { } #[doc = "Values that can be written to the field `CH4OC`"] pub enum CH4OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH4OCW { #[allow(missing_docs)] @@ -1084,10 +1044,8 @@ impl<'a> _CH4OCW<'a> { } #[doc = "Values that can be written to the field `CH5OC`"] pub enum CH5OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH5OCW { #[allow(missing_docs)] @@ -1142,10 +1100,8 @@ impl<'a> _CH5OCW<'a> { } #[doc = "Values that can be written to the field `CH6OC`"] pub enum CH6OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH6OCW { #[allow(missing_docs)] @@ -1200,10 +1156,8 @@ impl<'a> _CH6OCW<'a> { } #[doc = "Values that can be written to the field `CH7OC`"] pub enum CH7OCW { - #[doc = "The channel output is not affected by software output control."] - _0, - #[doc = "The channel output is affected by software output control."] - _1, + #[doc = "The channel output is not affected by software output control."] _0, + #[doc = "The channel output is affected by software output control."] _1, } impl CH7OCW { #[allow(missing_docs)] @@ -1258,10 +1212,8 @@ impl<'a> _CH7OCW<'a> { } #[doc = "Values that can be written to the field `CH0OCV`"] pub enum CH0OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH0OCVW { #[allow(missing_docs)] @@ -1316,10 +1268,8 @@ impl<'a> _CH0OCVW<'a> { } #[doc = "Values that can be written to the field `CH1OCV`"] pub enum CH1OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH1OCVW { #[allow(missing_docs)] @@ -1374,10 +1324,8 @@ impl<'a> _CH1OCVW<'a> { } #[doc = "Values that can be written to the field `CH2OCV`"] pub enum CH2OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH2OCVW { #[allow(missing_docs)] @@ -1432,10 +1380,8 @@ impl<'a> _CH2OCVW<'a> { } #[doc = "Values that can be written to the field `CH3OCV`"] pub enum CH3OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH3OCVW { #[allow(missing_docs)] @@ -1490,10 +1436,8 @@ impl<'a> _CH3OCVW<'a> { } #[doc = "Values that can be written to the field `CH4OCV`"] pub enum CH4OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH4OCVW { #[allow(missing_docs)] @@ -1548,10 +1492,8 @@ impl<'a> _CH4OCVW<'a> { } #[doc = "Values that can be written to the field `CH5OCV`"] pub enum CH5OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH5OCVW { #[allow(missing_docs)] @@ -1606,10 +1548,8 @@ impl<'a> _CH5OCVW<'a> { } #[doc = "Values that can be written to the field `CH6OCV`"] pub enum CH6OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH6OCVW { #[allow(missing_docs)] @@ -1664,10 +1604,8 @@ impl<'a> _CH6OCVW<'a> { } #[doc = "Values that can be written to the field `CH7OCV`"] pub enum CH7OCVW { - #[doc = "The software output control forces 0 to the channel output."] - _0, - #[doc = "The software output control forces 1 to the channel output."] - _1, + #[doc = "The software output control forces 0 to the channel output."] _0, + #[doc = "The software output control forces 1 to the channel output."] _1, } impl CH7OCVW { #[allow(missing_docs)] diff --git a/src/ftm3/sync/mod.rs b/src/ftm3/sync/mod.rs index b46f9f6..add847a 100644 --- a/src/ftm3/sync/mod.rs +++ b/src/ftm3/sync/mod.rs @@ -22,7 +22,9 @@ impl super::SYNC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SYNC { #[doc = "Possible values of the field `CNTMIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMINR { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CNTMINR { #[doc = "Possible values of the field `CNTMAX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CNTMAXR { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,8 +135,7 @@ impl CNTMAXR { #[doc = "Possible values of the field `REINIT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REINITR { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -231,10 +228,8 @@ impl SYNCHOMR { #[doc = "Possible values of the field `TRIG0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG0R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +273,8 @@ impl TRIG0R { #[doc = "Possible values of the field `TRIG1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG1R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +318,8 @@ impl TRIG1R { #[doc = "Possible values of the field `TRIG2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRIG2R { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +363,8 @@ impl TRIG2R { #[doc = "Possible values of the field `SWSYNC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSYNCR { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +407,8 @@ impl SWSYNCR { } #[doc = "Values that can be written to the field `CNTMIN`"] pub enum CNTMINW { - #[doc = "The minimum loading point is disabled."] - _0, - #[doc = "The minimum loading point is enabled."] - _1, + #[doc = "The minimum loading point is disabled."] _0, + #[doc = "The minimum loading point is enabled."] _1, } impl CNTMINW { #[allow(missing_docs)] @@ -476,10 +463,8 @@ impl<'a> _CNTMINW<'a> { } #[doc = "Values that can be written to the field `CNTMAX`"] pub enum CNTMAXW { - #[doc = "The maximum loading point is disabled."] - _0, - #[doc = "The maximum loading point is enabled."] - _1, + #[doc = "The maximum loading point is disabled."] _0, + #[doc = "The maximum loading point is enabled."] _1, } impl CNTMAXW { #[allow(missing_docs)] @@ -534,8 +519,7 @@ impl<'a> _CNTMAXW<'a> { } #[doc = "Values that can be written to the field `REINIT`"] pub enum REINITW { - #[doc = "FTM counter continues to count normally."] - _0, + #[doc = "FTM counter continues to count normally."] _0, #[doc = "FTM counter is updated with its initial value when the selected trigger is detected."] _1, } @@ -650,10 +634,8 @@ impl<'a> _SYNCHOMW<'a> { } #[doc = "Values that can be written to the field `TRIG0`"] pub enum TRIG0W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG0W { #[allow(missing_docs)] @@ -708,10 +690,8 @@ impl<'a> _TRIG0W<'a> { } #[doc = "Values that can be written to the field `TRIG1`"] pub enum TRIG1W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG1W { #[allow(missing_docs)] @@ -766,10 +746,8 @@ impl<'a> _TRIG1W<'a> { } #[doc = "Values that can be written to the field `TRIG2`"] pub enum TRIG2W { - #[doc = "Trigger is disabled."] - _0, - #[doc = "Trigger is enabled."] - _1, + #[doc = "Trigger is disabled."] _0, + #[doc = "Trigger is enabled."] _1, } impl TRIG2W { #[allow(missing_docs)] @@ -824,10 +802,8 @@ impl<'a> _TRIG2W<'a> { } #[doc = "Values that can be written to the field `SWSYNC`"] pub enum SWSYNCW { - #[doc = "Software trigger is not selected."] - _0, - #[doc = "Software trigger is selected."] - _1, + #[doc = "Software trigger is not selected."] _0, + #[doc = "Software trigger is selected."] _1, } impl SWSYNCW { #[allow(missing_docs)] diff --git a/src/ftm3/synconf/mod.rs b/src/ftm3/synconf/mod.rs index 08257bc..8b29129 100644 --- a/src/ftm3/synconf/mod.rs +++ b/src/ftm3/synconf/mod.rs @@ -22,7 +22,9 @@ impl super::SYNCONF { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -92,8 +94,7 @@ impl HWTRIGMODER { pub enum CNTINCR { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -139,8 +140,7 @@ impl CNTINCR { pub enum INVCR { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -186,8 +186,7 @@ impl INVCR { pub enum SWOCR { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +230,8 @@ impl SWOCR { #[doc = "Possible values of the field `SYNCMODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SYNCMODER { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +275,8 @@ impl SYNCMODER { #[doc = "Possible values of the field `SWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRSTCNTR { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -327,8 +322,7 @@ impl SWRSTCNTR { pub enum SWWRBUFR { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +366,8 @@ impl SWWRBUFR { #[doc = "Possible values of the field `SWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWOMR { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +411,8 @@ impl SWOMR { #[doc = "Possible values of the field `SWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWINVCR { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +456,8 @@ impl SWINVCR { #[doc = "Possible values of the field `SWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWSOCR { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +501,8 @@ impl SWSOCR { #[doc = "Possible values of the field `HWRSTCNT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWRSTCNTR { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -562,8 +548,7 @@ impl HWRSTCNTR { pub enum HWWRBUFR { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +592,8 @@ impl HWWRBUFR { #[doc = "Possible values of the field `HWOM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWOMR { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +637,8 @@ impl HWOMR { #[doc = "Possible values of the field `HWINVC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWINVCR { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +682,8 @@ impl HWINVCR { #[doc = "Possible values of the field `HWSOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HWSOCR { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> { pub enum CNTINCW { #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1, } impl CNTINCW { #[allow(missing_docs)] @@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> { pub enum INVCW { #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl INVCW { #[allow(missing_docs)] @@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> { pub enum SWOCW { #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."] _0, - #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] - _1, + #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1, } impl SWOCW { #[allow(missing_docs)] @@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> { } #[doc = "Values that can be written to the field `SYNCMODE`"] pub enum SYNCMODEW { - #[doc = "Legacy PWM synchronization is selected."] - _0, - #[doc = "Enhanced PWM synchronization is selected."] - _1, + #[doc = "Legacy PWM synchronization is selected."] _0, + #[doc = "Enhanced PWM synchronization is selected."] _1, } impl SYNCMODEW { #[allow(missing_docs)] @@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> { } #[doc = "Values that can be written to the field `SWRSTCNT`"] pub enum SWRSTCNTW { - #[doc = "The software trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "The software trigger activates the FTM counter synchronization."] - _1, + #[doc = "The software trigger does not activate the FTM counter synchronization."] _0, + #[doc = "The software trigger activates the FTM counter synchronization."] _1, } impl SWRSTCNTW { #[allow(missing_docs)] @@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> { pub enum SWWRBUFW { #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl SWWRBUFW { #[allow(missing_docs)] @@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> { } #[doc = "Values that can be written to the field `SWOM`"] pub enum SWOMW { - #[doc = "The software trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "The software trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "The software trigger activates the OUTMASK register synchronization."] _1, } impl SWOMW { #[allow(missing_docs)] @@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> { } #[doc = "Values that can be written to the field `SWINVC`"] pub enum SWINVCW { - #[doc = "The software trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "The software trigger activates the INVCTRL register synchronization."] _1, } impl SWINVCW { #[allow(missing_docs)] @@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> { } #[doc = "Values that can be written to the field `SWSOC`"] pub enum SWSOCW { - #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "The software trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "The software trigger activates the SWOCTRL register synchronization."] _1, } impl SWSOCW { #[allow(missing_docs)] @@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> { } #[doc = "Values that can be written to the field `HWRSTCNT`"] pub enum HWRSTCNTW { - #[doc = "A hardware trigger does not activate the FTM counter synchronization."] - _0, - #[doc = "A hardware trigger activates the FTM counter synchronization."] - _1, + #[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0, + #[doc = "A hardware trigger activates the FTM counter synchronization."] _1, } impl HWRSTCNTW { #[allow(missing_docs)] @@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> { pub enum HWWRBUFW { #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."] _0, - #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] - _1, + #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1, } impl HWWRBUFW { #[allow(missing_docs)] @@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> { } #[doc = "Values that can be written to the field `HWOM`"] pub enum HWOMW { - #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] - _0, - #[doc = "A hardware trigger activates the OUTMASK register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0, + #[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1, } impl HWOMW { #[allow(missing_docs)] @@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> { } #[doc = "Values that can be written to the field `HWINVC`"] pub enum HWINVCW { - #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the INVCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1, } impl HWINVCW { #[allow(missing_docs)] @@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> { } #[doc = "Values that can be written to the field `HWSOC`"] pub enum HWSOCW { - #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] - _0, - #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] - _1, + #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0, + #[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1, } impl HWSOCW { #[allow(missing_docs)] diff --git a/src/interrupt/mod.rs b/src/interrupt/mod.rs index 6267ac9..faf0f9c 100644 --- a/src/interrupt/mod.rs +++ b/src/interrupt/mod.rs @@ -236,182 +236,94 @@ pub static INTERRUPTS: [Option; 123] = [ ]; #[doc = r" Enumeration of all the interrupts"] pub enum Interrupt { - #[doc = "0 - DMA0"] - DMA0, - #[doc = "1 - DMA1"] - DMA1, - #[doc = "2 - DMA2"] - DMA2, - #[doc = "3 - DMA3"] - DMA3, - #[doc = "4 - DMA4"] - DMA4, - #[doc = "5 - DMA5"] - DMA5, - #[doc = "6 - DMA6"] - DMA6, - #[doc = "7 - DMA7"] - DMA7, - #[doc = "8 - DMA8"] - DMA8, - #[doc = "9 - DMA9"] - DMA9, - #[doc = "10 - DMA10"] - DMA10, - #[doc = "11 - DMA11"] - DMA11, - #[doc = "12 - DMA12"] - DMA12, - #[doc = "13 - DMA13"] - DMA13, - #[doc = "14 - DMA14"] - DMA14, - #[doc = "15 - DMA15"] - DMA15, - #[doc = "16 - DMA_Error"] - DMA_ERROR, - #[doc = "17 - MCM"] - MCM, - #[doc = "18 - FTFC"] - FTFC, - #[doc = "19 - Read_Collision"] - READ_COLLISION, - #[doc = "20 - LVD_LVW"] - LVD_LVW, - #[doc = "21 - FTFC_Fault"] - FTFC_FAULT, - #[doc = "22 - WDOG_EWM"] - WDOG_EWM, - #[doc = "23 - RCM"] - RCM, - #[doc = "24 - LPI2C0_Master"] - LPI2C0_MASTER, - #[doc = "25 - LPI2C0_Slave"] - LPI2C0_SLAVE, - #[doc = "26 - LPSPI0"] - LPSPI0, - #[doc = "27 - LPSPI1"] - LPSPI1, - #[doc = "28 - LPSPI2"] - LPSPI2, - #[doc = "31 - LPUART0_RxTx"] - LPUART0_RXTX, - #[doc = "33 - LPUART1_RxTx"] - LPUART1_RXTX, - #[doc = "35 - LPUART2_RxTx"] - LPUART2_RXTX, - #[doc = "39 - ADC0"] - ADC0, - #[doc = "40 - ADC1"] - ADC1, - #[doc = "41 - CMP0"] - CMP0, - #[doc = "44 - ERM_single_fault"] - ERM_SINGLE_FAULT, - #[doc = "45 - ERM_double_fault"] - ERM_DOUBLE_FAULT, - #[doc = "46 - RTC"] - RTC, - #[doc = "47 - RTC_Seconds"] - RTC_SECONDS, - #[doc = "48 - LPIT0_Ch0"] - LPIT0_CH0, - #[doc = "49 - LPIT0_Ch1"] - LPIT0_CH1, - #[doc = "50 - LPIT0_Ch2"] - LPIT0_CH2, - #[doc = "51 - LPIT0_Ch3"] - LPIT0_CH3, - #[doc = "52 - PDB0"] - PDB0, - #[doc = "57 - SCG"] - SCG, - #[doc = "58 - LPTMR0"] - LPTMR0, - #[doc = "59 - PORTA"] - PORTA, - #[doc = "60 - PORTB"] - PORTB, - #[doc = "61 - PORTC"] - PORTC, - #[doc = "62 - PORTD"] - PORTD, - #[doc = "63 - PORTE"] - PORTE, - #[doc = "68 - PDB1"] - PDB1, - #[doc = "69 - FLEXIO"] - FLEXIO, - #[doc = "78 - CAN0_ORed"] - CAN0_ORED, - #[doc = "79 - CAN0_Error"] - CAN0_ERROR, - #[doc = "80 - CAN0_Wake_Up"] - CAN0_WAKE_UP, - #[doc = "81 - CAN0_ORed_0_15_MB"] - CAN0_ORED_0_15_MB, - #[doc = "82 - CAN0_ORed_16_31_MB"] - CAN0_ORED_16_31_MB, - #[doc = "85 - CAN1_ORed"] - CAN1_ORED, - #[doc = "86 - CAN1_Error"] - CAN1_ERROR, - #[doc = "88 - CAN1_ORed_0_15_MB"] - CAN1_ORED_0_15_MB, - #[doc = "92 - CAN2_ORed"] - CAN2_ORED, - #[doc = "93 - CAN2_Error"] - CAN2_ERROR, - #[doc = "95 - CAN2_ORed_0_15_MB"] - CAN2_ORED_0_15_MB, - #[doc = "99 - FTM0_Ch0_Ch1"] - FTM0_CH0_CH1, - #[doc = "100 - FTM0_Ch2_Ch3"] - FTM0_CH2_CH3, - #[doc = "101 - FTM0_Ch4_Ch5"] - FTM0_CH4_CH5, - #[doc = "102 - FTM0_Ch6_Ch7"] - FTM0_CH6_CH7, - #[doc = "103 - FTM0_Fault"] - FTM0_FAULT, - #[doc = "104 - FTM0_Ovf_Reload"] - FTM0_OVF_RELOAD, - #[doc = "105 - FTM1_Ch0_Ch1"] - FTM1_CH0_CH1, - #[doc = "106 - FTM1_Ch2_Ch3"] - FTM1_CH2_CH3, - #[doc = "107 - FTM1_Ch4_Ch5"] - FTM1_CH4_CH5, - #[doc = "108 - FTM1_Ch6_Ch7"] - FTM1_CH6_CH7, - #[doc = "109 - FTM1_Fault"] - FTM1_FAULT, - #[doc = "110 - FTM1_Ovf_Reload"] - FTM1_OVF_RELOAD, - #[doc = "111 - FTM2_Ch0_Ch1"] - FTM2_CH0_CH1, - #[doc = "112 - FTM2_Ch2_Ch3"] - FTM2_CH2_CH3, - #[doc = "113 - FTM2_Ch4_Ch5"] - FTM2_CH4_CH5, - #[doc = "114 - FTM2_Ch6_Ch7"] - FTM2_CH6_CH7, - #[doc = "115 - FTM2_Fault"] - FTM2_FAULT, - #[doc = "116 - FTM2_Ovf_Reload"] - FTM2_OVF_RELOAD, - #[doc = "117 - FTM3_Ch0_Ch1"] - FTM3_CH0_CH1, - #[doc = "118 - FTM3_Ch2_Ch3"] - FTM3_CH2_CH3, - #[doc = "119 - FTM3_Ch4_Ch5"] - FTM3_CH4_CH5, - #[doc = "120 - FTM3_Ch6_Ch7"] - FTM3_CH6_CH7, - #[doc = "121 - FTM3_Fault"] - FTM3_FAULT, - #[doc = "122 - FTM3_Ovf_Reload"] - FTM3_OVF_RELOAD, + #[doc = "0 - DMA0"] DMA0, + #[doc = "1 - DMA1"] DMA1, + #[doc = "2 - DMA2"] DMA2, + #[doc = "3 - DMA3"] DMA3, + #[doc = "4 - DMA4"] DMA4, + #[doc = "5 - DMA5"] DMA5, + #[doc = "6 - DMA6"] DMA6, + #[doc = "7 - DMA7"] DMA7, + #[doc = "8 - DMA8"] DMA8, + #[doc = "9 - DMA9"] DMA9, + #[doc = "10 - DMA10"] DMA10, + #[doc = "11 - DMA11"] DMA11, + #[doc = "12 - DMA12"] DMA12, + #[doc = "13 - DMA13"] DMA13, + #[doc = "14 - DMA14"] DMA14, + #[doc = "15 - DMA15"] DMA15, + #[doc = "16 - DMA_Error"] DMA_ERROR, + #[doc = "17 - MCM"] MCM, + #[doc = "18 - FTFC"] FTFC, + #[doc = "19 - Read_Collision"] READ_COLLISION, + #[doc = "20 - LVD_LVW"] LVD_LVW, + #[doc = "21 - FTFC_Fault"] FTFC_FAULT, + #[doc = "22 - WDOG_EWM"] WDOG_EWM, + #[doc = "23 - RCM"] RCM, + #[doc = "24 - LPI2C0_Master"] LPI2C0_MASTER, + #[doc = "25 - LPI2C0_Slave"] LPI2C0_SLAVE, + #[doc = "26 - LPSPI0"] LPSPI0, + #[doc = "27 - LPSPI1"] LPSPI1, + #[doc = "28 - LPSPI2"] LPSPI2, + #[doc = "31 - LPUART0_RxTx"] LPUART0_RXTX, + #[doc = "33 - LPUART1_RxTx"] LPUART1_RXTX, + #[doc = "35 - LPUART2_RxTx"] LPUART2_RXTX, + #[doc = "39 - ADC0"] ADC0, + #[doc = "40 - ADC1"] ADC1, + #[doc = "41 - CMP0"] CMP0, + #[doc = "44 - ERM_single_fault"] ERM_SINGLE_FAULT, + #[doc = "45 - ERM_double_fault"] ERM_DOUBLE_FAULT, + #[doc = "46 - RTC"] RTC, + #[doc = "47 - RTC_Seconds"] RTC_SECONDS, + #[doc = "48 - LPIT0_Ch0"] LPIT0_CH0, + #[doc = "49 - LPIT0_Ch1"] LPIT0_CH1, + #[doc = "50 - LPIT0_Ch2"] LPIT0_CH2, + #[doc = "51 - LPIT0_Ch3"] LPIT0_CH3, + #[doc = "52 - PDB0"] PDB0, + #[doc = "57 - SCG"] SCG, + #[doc = "58 - LPTMR0"] LPTMR0, + #[doc = "59 - PORTA"] PORTA, + #[doc = "60 - PORTB"] PORTB, + #[doc = "61 - PORTC"] PORTC, + #[doc = "62 - PORTD"] PORTD, + #[doc = "63 - PORTE"] PORTE, + #[doc = "68 - PDB1"] PDB1, + #[doc = "69 - FLEXIO"] FLEXIO, + #[doc = "78 - CAN0_ORed"] CAN0_ORED, + #[doc = "79 - CAN0_Error"] CAN0_ERROR, + #[doc = "80 - CAN0_Wake_Up"] CAN0_WAKE_UP, + #[doc = "81 - CAN0_ORed_0_15_MB"] CAN0_ORED_0_15_MB, + #[doc = "82 - CAN0_ORed_16_31_MB"] CAN0_ORED_16_31_MB, + #[doc = "85 - CAN1_ORed"] CAN1_ORED, + #[doc = "86 - CAN1_Error"] CAN1_ERROR, + #[doc = "88 - CAN1_ORed_0_15_MB"] CAN1_ORED_0_15_MB, + #[doc = "92 - CAN2_ORed"] CAN2_ORED, + #[doc = "93 - CAN2_Error"] CAN2_ERROR, + #[doc = "95 - CAN2_ORed_0_15_MB"] CAN2_ORED_0_15_MB, + #[doc = "99 - FTM0_Ch0_Ch1"] FTM0_CH0_CH1, + #[doc = "100 - FTM0_Ch2_Ch3"] FTM0_CH2_CH3, + #[doc = "101 - FTM0_Ch4_Ch5"] FTM0_CH4_CH5, + #[doc = "102 - FTM0_Ch6_Ch7"] FTM0_CH6_CH7, + #[doc = "103 - FTM0_Fault"] FTM0_FAULT, + #[doc = "104 - FTM0_Ovf_Reload"] FTM0_OVF_RELOAD, + #[doc = "105 - FTM1_Ch0_Ch1"] FTM1_CH0_CH1, + #[doc = "106 - FTM1_Ch2_Ch3"] FTM1_CH2_CH3, + #[doc = "107 - FTM1_Ch4_Ch5"] FTM1_CH4_CH5, + #[doc = "108 - FTM1_Ch6_Ch7"] FTM1_CH6_CH7, + #[doc = "109 - FTM1_Fault"] FTM1_FAULT, + #[doc = "110 - FTM1_Ovf_Reload"] FTM1_OVF_RELOAD, + #[doc = "111 - FTM2_Ch0_Ch1"] FTM2_CH0_CH1, + #[doc = "112 - FTM2_Ch2_Ch3"] FTM2_CH2_CH3, + #[doc = "113 - FTM2_Ch4_Ch5"] FTM2_CH4_CH5, + #[doc = "114 - FTM2_Ch6_Ch7"] FTM2_CH6_CH7, + #[doc = "115 - FTM2_Fault"] FTM2_FAULT, + #[doc = "116 - FTM2_Ovf_Reload"] FTM2_OVF_RELOAD, + #[doc = "117 - FTM3_Ch0_Ch1"] FTM3_CH0_CH1, + #[doc = "118 - FTM3_Ch2_Ch3"] FTM3_CH2_CH3, + #[doc = "119 - FTM3_Ch4_Ch5"] FTM3_CH4_CH5, + #[doc = "120 - FTM3_Ch6_Ch7"] FTM3_CH6_CH7, + #[doc = "121 - FTM3_Fault"] FTM3_FAULT, + #[doc = "122 - FTM3_Ovf_Reload"] FTM3_OVF_RELOAD, } unsafe impl Nr for Interrupt { #[inline] diff --git a/src/lib.rs b/src/lib.rs index edf4eee..ba614b6 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,9 +1,18 @@ -# ! [ cfg_attr ( feature = "rt" , feature ( global_asm ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( macro_reexport ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( used ) ) ] # ! [ doc = "Peripheral access API for S32K144 microcontrollers (generated using svd2rust v0.11.4)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.11.4/svd2rust/#peripheral-api" ] # ! [ deny ( missing_docs ) ] # ! [ deny ( warnings ) ] # ! [ allow ( non_camel_case_types ) ] # ! [ feature ( const_fn ) ] # ! [ no_std ]extern crate cortex_m ; +#![cfg_attr(feature = "rt", feature(global_asm))] +#![cfg_attr(feature = "rt", feature(macro_reexport))] +#![cfg_attr(feature = "rt", feature(used))] +#![doc = "Peripheral access API for S32K144 microcontrollers (generated using svd2rust v0.11.4)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.11.4/svd2rust/#peripheral-api"] +#![deny(missing_docs)] +#![deny(warnings)] +#![allow(non_camel_case_types)] +#![feature(const_fn)] +#![no_std] +extern crate bare_metal; +extern crate cortex_m; #[macro_reexport(default_handler, exception)] #[cfg(feature = "rt")] -extern crate cortex_m_rt ; -extern crate bare_metal ; -extern crate vcell ; +extern crate cortex_m_rt; +extern crate vcell; use core::ops::Deref; use bare_metal::Peripheral; #[doc = r" Number available in the NVIC for configuring priority"] @@ -767,134 +776,70 @@ impl Deref for LMEM { #[doc = r" All the peripherals"] #[allow(non_snake_case)] pub struct Peripherals<'a> { - #[doc = "CPUID"] - pub CPUID: &'a CPUID, - #[doc = "DCB"] - pub DCB: &'a DCB, - #[doc = "DWT"] - pub DWT: &'a DWT, - #[doc = "FPB"] - pub FPB: &'a FPB, - #[doc = "FPU"] - pub FPU: &'a FPU, - #[doc = "ITM"] - pub ITM: &'a ITM, - #[doc = "MPU"] - pub MPU: &'a MPU, - #[doc = "NVIC"] - pub NVIC: &'a NVIC, - #[doc = "SCB"] - pub SCB: &'a SCB, - #[doc = "SYST"] - pub SYST: &'a SYST, - #[doc = "TPIU"] - pub TPIU: &'a TPIU, - #[doc = "CSE_PRAM"] - pub CSE_PRAM: &'a CSE_PRAM, - #[doc = "AIPS"] - pub AIPS: &'a AIPS, - #[doc = "MSCM"] - pub MSCM: &'a MSCM, - #[doc = "DMA"] - pub DMA: &'a DMA, - #[doc = "ERM"] - pub ERM: &'a ERM, - #[doc = "EIM"] - pub EIM: &'a EIM, - #[doc = "FTFC"] - pub FTFC: &'a FTFC, - #[doc = "DMAMUX"] - pub DMAMUX: &'a DMAMUX, - #[doc = "CAN0"] - pub CAN0: &'a CAN0, - #[doc = "CAN1"] - pub CAN1: &'a CAN1, - #[doc = "CAN2"] - pub CAN2: &'a CAN2, - #[doc = "FTM0"] - pub FTM0: &'a FTM0, - #[doc = "FTM1"] - pub FTM1: &'a FTM1, - #[doc = "FTM2"] - pub FTM2: &'a FTM2, - #[doc = "FTM3"] - pub FTM3: &'a FTM3, - #[doc = "ADC0"] - pub ADC0: &'a ADC0, - #[doc = "ADC1"] - pub ADC1: &'a ADC1, - #[doc = "LPSPI0"] - pub LPSPI0: &'a LPSPI0, - #[doc = "LPSPI1"] - pub LPSPI1: &'a LPSPI1, - #[doc = "LPSPI2"] - pub LPSPI2: &'a LPSPI2, - #[doc = "PDB0"] - pub PDB0: &'a PDB0, - #[doc = "PDB1"] - pub PDB1: &'a PDB1, - #[doc = "CRC"] - pub CRC: &'a CRC, - #[doc = "LPIT0"] - pub LPIT0: &'a LPIT0, - #[doc = "RTC"] - pub RTC: &'a RTC, - #[doc = "LPTMR0"] - pub LPTMR0: &'a LPTMR0, - #[doc = "SIM"] - pub SIM: &'a SIM, - #[doc = "PORTA"] - pub PORTA: &'a PORTA, - #[doc = "PORTB"] - pub PORTB: &'a PORTB, - #[doc = "PORTC"] - pub PORTC: &'a PORTC, - #[doc = "PORTD"] - pub PORTD: &'a PORTD, - #[doc = "PORTE"] - pub PORTE: &'a PORTE, - #[doc = "WDOG"] - pub WDOG: &'a WDOG, - #[doc = "FLEXIO"] - pub FLEXIO: &'a FLEXIO, - #[doc = "EWM"] - pub EWM: &'a EWM, - #[doc = "TRGMUX"] - pub TRGMUX: &'a TRGMUX, - #[doc = "SCG"] - pub SCG: &'a SCG, - #[doc = "PCC"] - pub PCC: &'a PCC, - #[doc = "LPI2C0"] - pub LPI2C0: &'a LPI2C0, - #[doc = "LPUART0"] - pub LPUART0: &'a LPUART0, - #[doc = "LPUART1"] - pub LPUART1: &'a LPUART1, - #[doc = "LPUART2"] - pub LPUART2: &'a LPUART2, - #[doc = "CMP0"] - pub CMP0: &'a CMP0, - #[doc = "PMC"] - pub PMC: &'a PMC, - #[doc = "SMC"] - pub SMC: &'a SMC, - #[doc = "RCM"] - pub RCM: &'a RCM, - #[doc = "PTA"] - pub PTA: &'a PTA, - #[doc = "PTB"] - pub PTB: &'a PTB, - #[doc = "PTC"] - pub PTC: &'a PTC, - #[doc = "PTD"] - pub PTD: &'a PTD, - #[doc = "PTE"] - pub PTE: &'a PTE, - #[doc = "MCM"] - pub MCM: &'a MCM, - #[doc = "LMEM"] - pub LMEM: &'a LMEM, + #[doc = "CPUID"] pub CPUID: &'a CPUID, + #[doc = "DCB"] pub DCB: &'a DCB, + #[doc = "DWT"] pub DWT: &'a DWT, + #[doc = "FPB"] pub FPB: &'a FPB, + #[doc = "FPU"] pub FPU: &'a FPU, + #[doc = "ITM"] pub ITM: &'a ITM, + #[doc = "MPU"] pub MPU: &'a MPU, + #[doc = "NVIC"] pub NVIC: &'a NVIC, + #[doc = "SCB"] pub SCB: &'a SCB, + #[doc = "SYST"] pub SYST: &'a SYST, + #[doc = "TPIU"] pub TPIU: &'a TPIU, + #[doc = "CSE_PRAM"] pub CSE_PRAM: &'a CSE_PRAM, + #[doc = "AIPS"] pub AIPS: &'a AIPS, + #[doc = "MSCM"] pub MSCM: &'a MSCM, + #[doc = "DMA"] pub DMA: &'a DMA, + #[doc = "ERM"] pub ERM: &'a ERM, + #[doc = "EIM"] pub EIM: &'a EIM, + #[doc = "FTFC"] pub FTFC: &'a FTFC, + #[doc = "DMAMUX"] pub DMAMUX: &'a DMAMUX, + #[doc = "CAN0"] pub CAN0: &'a CAN0, + #[doc = "CAN1"] pub CAN1: &'a CAN1, + #[doc = "CAN2"] pub CAN2: &'a CAN2, + #[doc = "FTM0"] pub FTM0: &'a FTM0, + #[doc = "FTM1"] pub FTM1: &'a FTM1, + #[doc = "FTM2"] pub FTM2: &'a FTM2, + #[doc = "FTM3"] pub FTM3: &'a FTM3, + #[doc = "ADC0"] pub ADC0: &'a ADC0, + #[doc = "ADC1"] pub ADC1: &'a ADC1, + #[doc = "LPSPI0"] pub LPSPI0: &'a LPSPI0, + #[doc = "LPSPI1"] pub LPSPI1: &'a LPSPI1, + #[doc = "LPSPI2"] pub LPSPI2: &'a LPSPI2, + #[doc = "PDB0"] pub PDB0: &'a PDB0, + #[doc = "PDB1"] pub PDB1: &'a PDB1, + #[doc = "CRC"] pub CRC: &'a CRC, + #[doc = "LPIT0"] pub LPIT0: &'a LPIT0, + #[doc = "RTC"] pub RTC: &'a RTC, + #[doc = "LPTMR0"] pub LPTMR0: &'a LPTMR0, + #[doc = "SIM"] pub SIM: &'a SIM, + #[doc = "PORTA"] pub PORTA: &'a PORTA, + #[doc = "PORTB"] pub PORTB: &'a PORTB, + #[doc = "PORTC"] pub PORTC: &'a PORTC, + #[doc = "PORTD"] pub PORTD: &'a PORTD, + #[doc = "PORTE"] pub PORTE: &'a PORTE, + #[doc = "WDOG"] pub WDOG: &'a WDOG, + #[doc = "FLEXIO"] pub FLEXIO: &'a FLEXIO, + #[doc = "EWM"] pub EWM: &'a EWM, + #[doc = "TRGMUX"] pub TRGMUX: &'a TRGMUX, + #[doc = "SCG"] pub SCG: &'a SCG, + #[doc = "PCC"] pub PCC: &'a PCC, + #[doc = "LPI2C0"] pub LPI2C0: &'a LPI2C0, + #[doc = "LPUART0"] pub LPUART0: &'a LPUART0, + #[doc = "LPUART1"] pub LPUART1: &'a LPUART1, + #[doc = "LPUART2"] pub LPUART2: &'a LPUART2, + #[doc = "CMP0"] pub CMP0: &'a CMP0, + #[doc = "PMC"] pub PMC: &'a PMC, + #[doc = "SMC"] pub SMC: &'a SMC, + #[doc = "RCM"] pub RCM: &'a RCM, + #[doc = "PTA"] pub PTA: &'a PTA, + #[doc = "PTB"] pub PTB: &'a PTB, + #[doc = "PTC"] pub PTC: &'a PTC, + #[doc = "PTD"] pub PTD: &'a PTD, + #[doc = "PTE"] pub PTE: &'a PTE, + #[doc = "MCM"] pub MCM: &'a MCM, + #[doc = "LMEM"] pub LMEM: &'a LMEM, } impl<'a> Peripherals<'a> { #[doc = r" Grants access to all the peripherals"] diff --git a/src/lmem/lmem_pcccr/mod.rs b/src/lmem/lmem_pcccr/mod.rs index 38d0779..9c54aef 100644 --- a/src/lmem/lmem_pcccr/mod.rs +++ b/src/lmem/lmem_pcccr/mod.rs @@ -22,7 +22,9 @@ impl super::LMEM_PCCCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LMEM_PCCCR { #[doc = "Possible values of the field `ENCACHE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENCACHER { - #[doc = "Cache disabled"] - _0, - #[doc = "Cache enabled"] - _1, + #[doc = "Cache disabled"] _0, + #[doc = "Cache enabled"] _1, } impl ENCACHER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +132,8 @@ impl PCCR3R { #[doc = "Possible values of the field `INVW0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INVW0R { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, invalidate all lines in way 0."] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, invalidate all lines in way 0."] _1, } impl INVW0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,10 +177,8 @@ impl INVW0R { #[doc = "Possible values of the field `PUSHW0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PUSHW0R { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, push all modified lines in way 0"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, push all modified lines in way 0"] _1, } impl PUSHW0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl PUSHW0R { #[doc = "Possible values of the field `INVW1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INVW1R { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, invalidate all lines in way 1"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, invalidate all lines in way 1"] _1, } impl INVW1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl INVW1R { #[doc = "Possible values of the field `PUSHW1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PUSHW1R { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, push all modified lines in way 1"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, push all modified lines in way 1"] _1, } impl PUSHW1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -320,10 +312,8 @@ impl PUSHW1R { #[doc = "Possible values of the field `GO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GOR { - #[doc = "Write: no effect. Read: no cache command active."] - _0, - #[doc = "Write: initiate command indicated by bits 27-24. Read: cache command active."] - _1, + #[doc = "Write: no effect. Read: no cache command active."] _0, + #[doc = "Write: initiate command indicated by bits 27-24. Read: cache command active."] _1, } impl GOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -366,10 +356,8 @@ impl GOR { } #[doc = "Values that can be written to the field `ENCACHE`"] pub enum ENCACHEW { - #[doc = "Cache disabled"] - _0, - #[doc = "Cache enabled"] - _1, + #[doc = "Cache disabled"] _0, + #[doc = "Cache enabled"] _1, } impl ENCACHEW { #[allow(missing_docs)] @@ -470,10 +458,8 @@ impl<'a> _PCCR3W<'a> { } #[doc = "Values that can be written to the field `INVW0`"] pub enum INVW0W { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, invalidate all lines in way 0."] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, invalidate all lines in way 0."] _1, } impl INVW0W { #[allow(missing_docs)] @@ -528,10 +514,8 @@ impl<'a> _INVW0W<'a> { } #[doc = "Values that can be written to the field `PUSHW0`"] pub enum PUSHW0W { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, push all modified lines in way 0"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, push all modified lines in way 0"] _1, } impl PUSHW0W { #[allow(missing_docs)] @@ -586,10 +570,8 @@ impl<'a> _PUSHW0W<'a> { } #[doc = "Values that can be written to the field `INVW1`"] pub enum INVW1W { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, invalidate all lines in way 1"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, invalidate all lines in way 1"] _1, } impl INVW1W { #[allow(missing_docs)] @@ -644,10 +626,8 @@ impl<'a> _INVW1W<'a> { } #[doc = "Values that can be written to the field `PUSHW1`"] pub enum PUSHW1W { - #[doc = "No operation"] - _0, - #[doc = "When setting the GO bit, push all modified lines in way 1"] - _1, + #[doc = "No operation"] _0, + #[doc = "When setting the GO bit, push all modified lines in way 1"] _1, } impl PUSHW1W { #[allow(missing_docs)] @@ -702,10 +682,8 @@ impl<'a> _PUSHW1W<'a> { } #[doc = "Values that can be written to the field `GO`"] pub enum GOW { - #[doc = "Write: no effect. Read: no cache command active."] - _0, - #[doc = "Write: initiate command indicated by bits 27-24. Read: cache command active."] - _1, + #[doc = "Write: no effect. Read: no cache command active."] _0, + #[doc = "Write: initiate command indicated by bits 27-24. Read: cache command active."] _1, } impl GOW { #[allow(missing_docs)] diff --git a/src/lmem/lmem_pcccvr/mod.rs b/src/lmem/lmem_pcccvr/mod.rs index d7cbbd6..67dd252 100644 --- a/src/lmem/lmem_pcccvr/mod.rs +++ b/src/lmem/lmem_pcccvr/mod.rs @@ -22,7 +22,9 @@ impl super::LMEM_PCCCVR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lmem/lmem_pcclcr/mod.rs b/src/lmem/lmem_pcclcr/mod.rs index 4bfaaba..f51afa5 100644 --- a/src/lmem/lmem_pcclcr/mod.rs +++ b/src/lmem/lmem_pcclcr/mod.rs @@ -22,7 +22,9 @@ impl super::LMEM_PCCLCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LMEM_PCCLCR { #[doc = "Possible values of the field `LGO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LGOR { - #[doc = "Write: no effect. Read: no line command active."] - _0, - #[doc = "Write: initiate line command indicated by bits 27-24. Read: line command active."] - _1, + #[doc = "Write: no effect. Read: no line command active."] _0, + #[doc = "Write: initiate line command indicated by bits 27-24. Read: line command active."] _1, } impl LGOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl CACHEADDRR { #[doc = "Possible values of the field `WSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WSELR { - #[doc = "Way 0"] - _0, - #[doc = "Way 1"] - _1, + #[doc = "Way 0"] _0, + #[doc = "Way 1"] _1, } impl WSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl WSELR { #[doc = "Possible values of the field `TDSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDSELR { - #[doc = "Data"] - _0, - #[doc = "Tag"] - _1, + #[doc = "Data"] _0, + #[doc = "Tag"] _1, } impl TDSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -258,14 +254,10 @@ impl LCWAYR { #[doc = "Possible values of the field `LCMD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LCMDR { - #[doc = "Search and read or write"] - _00, - #[doc = "Invalidate"] - _01, - #[doc = "Push"] - _10, - #[doc = "Clear"] - _11, + #[doc = "Search and read or write"] _00, + #[doc = "Invalidate"] _01, + #[doc = "Push"] _10, + #[doc = "Clear"] _11, } impl LCMDR { #[doc = r" Value of the field as raw bits"] @@ -314,10 +306,8 @@ impl LCMDR { #[doc = "Possible values of the field `LADSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LADSELR { - #[doc = "Cache address"] - _0, - #[doc = "Physical address"] - _1, + #[doc = "Cache address"] _0, + #[doc = "Physical address"] _1, } impl LADSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -361,10 +351,8 @@ impl LADSELR { #[doc = "Possible values of the field `LACC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LACCR { - #[doc = "Read"] - _0, - #[doc = "Write"] - _1, + #[doc = "Read"] _0, + #[doc = "Write"] _1, } impl LACCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -407,10 +395,8 @@ impl LACCR { } #[doc = "Values that can be written to the field `LGO`"] pub enum LGOW { - #[doc = "Write: no effect. Read: no line command active."] - _0, - #[doc = "Write: initiate line command indicated by bits 27-24. Read: line command active."] - _1, + #[doc = "Write: no effect. Read: no line command active."] _0, + #[doc = "Write: initiate line command indicated by bits 27-24. Read: line command active."] _1, } impl LGOW { #[allow(missing_docs)] @@ -480,10 +466,8 @@ impl<'a> _CACHEADDRW<'a> { } #[doc = "Values that can be written to the field `WSEL`"] pub enum WSELW { - #[doc = "Way 0"] - _0, - #[doc = "Way 1"] - _1, + #[doc = "Way 0"] _0, + #[doc = "Way 1"] _1, } impl WSELW { #[allow(missing_docs)] @@ -538,10 +522,8 @@ impl<'a> _WSELW<'a> { } #[doc = "Values that can be written to the field `TDSEL`"] pub enum TDSELW { - #[doc = "Data"] - _0, - #[doc = "Tag"] - _1, + #[doc = "Data"] _0, + #[doc = "Tag"] _1, } impl TDSELW { #[allow(missing_docs)] @@ -665,14 +647,10 @@ impl<'a> _LCWAYW<'a> { } #[doc = "Values that can be written to the field `LCMD`"] pub enum LCMDW { - #[doc = "Search and read or write"] - _00, - #[doc = "Invalidate"] - _01, - #[doc = "Push"] - _10, - #[doc = "Clear"] - _11, + #[doc = "Search and read or write"] _00, + #[doc = "Invalidate"] _01, + #[doc = "Push"] _10, + #[doc = "Clear"] _11, } impl LCMDW { #[allow(missing_docs)] @@ -731,10 +709,8 @@ impl<'a> _LCMDW<'a> { } #[doc = "Values that can be written to the field `LADSEL`"] pub enum LADSELW { - #[doc = "Cache address"] - _0, - #[doc = "Physical address"] - _1, + #[doc = "Cache address"] _0, + #[doc = "Physical address"] _1, } impl LADSELW { #[allow(missing_docs)] @@ -789,10 +765,8 @@ impl<'a> _LADSELW<'a> { } #[doc = "Values that can be written to the field `LACC`"] pub enum LACCW { - #[doc = "Read"] - _0, - #[doc = "Write"] - _1, + #[doc = "Read"] _0, + #[doc = "Write"] _1, } impl LACCW { #[allow(missing_docs)] diff --git a/src/lmem/lmem_pccsar/mod.rs b/src/lmem/lmem_pccsar/mod.rs index 840f696..89ea652 100644 --- a/src/lmem/lmem_pccsar/mod.rs +++ b/src/lmem/lmem_pccsar/mod.rs @@ -22,7 +22,9 @@ impl super::LMEM_PCCSAR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::LMEM_PCCSAR { #[doc = "Possible values of the field `LGO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LGOR { - #[doc = "Write: no effect. Read: no line command active."] - _0, + #[doc = "Write: no effect. Read: no line command active."] _0, #[doc = "Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active."] _1, } @@ -100,8 +101,7 @@ impl PHYADDRR { } #[doc = "Values that can be written to the field `LGO`"] pub enum LGOW { - #[doc = "Write: no effect. Read: no line command active."] - _0, + #[doc = "Write: no effect. Read: no line command active."] _0, #[doc = "Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active."] _1, } diff --git a/src/lmem/mod.rs b/src/lmem/mod.rs index 61ce5c0..405b231 100644 --- a/src/lmem/mod.rs +++ b/src/lmem/mod.rs @@ -2,17 +2,12 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Cache control register"] - pub lmem_pcccr: LMEM_PCCCR, - #[doc = "0x04 - Cache line control register"] - pub lmem_pcclcr: LMEM_PCCLCR, - #[doc = "0x08 - Cache search address register"] - pub lmem_pccsar: LMEM_PCCSAR, - #[doc = "0x0c - Cache read/write value register"] - pub lmem_pcccvr: LMEM_PCCCVR, + #[doc = "0x00 - Cache control register"] pub lmem_pcccr: LMEM_PCCCR, + #[doc = "0x04 - Cache line control register"] pub lmem_pcclcr: LMEM_PCCLCR, + #[doc = "0x08 - Cache search address register"] pub lmem_pccsar: LMEM_PCCSAR, + #[doc = "0x0c - Cache read/write value register"] pub lmem_pcccvr: LMEM_PCCCVR, _reserved0: [u8; 16usize], - #[doc = "0x20 - Cache regions mode register"] - pub pccrmr: PCCRMR, + #[doc = "0x20 - Cache regions mode register"] pub pccrmr: PCCRMR, } #[doc = "Cache control register"] pub struct LMEM_PCCCR { diff --git a/src/lmem/pccrmr/mod.rs b/src/lmem/pccrmr/mod.rs index a4fcd9b..fd951e7 100644 --- a/src/lmem/pccrmr/mod.rs +++ b/src/lmem/pccrmr/mod.rs @@ -22,7 +22,9 @@ impl super::PCCRMR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::PCCRMR { #[doc = "Possible values of the field `R15`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R15R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R15R { #[doc = r" Value of the field as raw bits"] @@ -99,14 +97,10 @@ impl R15R { #[doc = "Possible values of the field `R14`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R14R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R14R { #[doc = r" Value of the field as raw bits"] @@ -155,14 +149,10 @@ impl R14R { #[doc = "Possible values of the field `R13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R13R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R13R { #[doc = r" Value of the field as raw bits"] @@ -211,14 +201,10 @@ impl R13R { #[doc = "Possible values of the field `R12`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R12R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R12R { #[doc = r" Value of the field as raw bits"] @@ -267,14 +253,10 @@ impl R12R { #[doc = "Possible values of the field `R11`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R11R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R11R { #[doc = r" Value of the field as raw bits"] @@ -323,14 +305,10 @@ impl R11R { #[doc = "Possible values of the field `R10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R10R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R10R { #[doc = r" Value of the field as raw bits"] @@ -379,14 +357,10 @@ impl R10R { #[doc = "Possible values of the field `R9`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R9R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R9R { #[doc = r" Value of the field as raw bits"] @@ -435,14 +409,10 @@ impl R9R { #[doc = "Possible values of the field `R8`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R8R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R8R { #[doc = r" Value of the field as raw bits"] @@ -491,14 +461,10 @@ impl R8R { #[doc = "Possible values of the field `R7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R7R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R7R { #[doc = r" Value of the field as raw bits"] @@ -547,14 +513,10 @@ impl R7R { #[doc = "Possible values of the field `R6`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R6R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R6R { #[doc = r" Value of the field as raw bits"] @@ -603,14 +565,10 @@ impl R6R { #[doc = "Possible values of the field `R5`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R5R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R5R { #[doc = r" Value of the field as raw bits"] @@ -659,14 +617,10 @@ impl R5R { #[doc = "Possible values of the field `R4`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R4R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R4R { #[doc = r" Value of the field as raw bits"] @@ -715,14 +669,10 @@ impl R4R { #[doc = "Possible values of the field `R3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R3R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R3R { #[doc = r" Value of the field as raw bits"] @@ -771,14 +721,10 @@ impl R3R { #[doc = "Possible values of the field `R2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R2R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R2R { #[doc = r" Value of the field as raw bits"] @@ -827,14 +773,10 @@ impl R2R { #[doc = "Possible values of the field `R1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R1R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R1R { #[doc = r" Value of the field as raw bits"] @@ -883,14 +825,10 @@ impl R1R { #[doc = "Possible values of the field `R0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum R0R { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R0R { #[doc = r" Value of the field as raw bits"] @@ -938,14 +876,10 @@ impl R0R { } #[doc = "Values that can be written to the field `R15`"] pub enum R15W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R15W { #[allow(missing_docs)] @@ -1004,14 +938,10 @@ impl<'a> _R15W<'a> { } #[doc = "Values that can be written to the field `R14`"] pub enum R14W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R14W { #[allow(missing_docs)] @@ -1070,14 +1000,10 @@ impl<'a> _R14W<'a> { } #[doc = "Values that can be written to the field `R13`"] pub enum R13W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R13W { #[allow(missing_docs)] @@ -1136,14 +1062,10 @@ impl<'a> _R13W<'a> { } #[doc = "Values that can be written to the field `R12`"] pub enum R12W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R12W { #[allow(missing_docs)] @@ -1202,14 +1124,10 @@ impl<'a> _R12W<'a> { } #[doc = "Values that can be written to the field `R11`"] pub enum R11W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R11W { #[allow(missing_docs)] @@ -1268,14 +1186,10 @@ impl<'a> _R11W<'a> { } #[doc = "Values that can be written to the field `R10`"] pub enum R10W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R10W { #[allow(missing_docs)] @@ -1334,14 +1248,10 @@ impl<'a> _R10W<'a> { } #[doc = "Values that can be written to the field `R9`"] pub enum R9W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R9W { #[allow(missing_docs)] @@ -1400,14 +1310,10 @@ impl<'a> _R9W<'a> { } #[doc = "Values that can be written to the field `R8`"] pub enum R8W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R8W { #[allow(missing_docs)] @@ -1466,14 +1372,10 @@ impl<'a> _R8W<'a> { } #[doc = "Values that can be written to the field `R7`"] pub enum R7W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R7W { #[allow(missing_docs)] @@ -1532,14 +1434,10 @@ impl<'a> _R7W<'a> { } #[doc = "Values that can be written to the field `R6`"] pub enum R6W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R6W { #[allow(missing_docs)] @@ -1598,14 +1496,10 @@ impl<'a> _R6W<'a> { } #[doc = "Values that can be written to the field `R5`"] pub enum R5W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R5W { #[allow(missing_docs)] @@ -1664,14 +1558,10 @@ impl<'a> _R5W<'a> { } #[doc = "Values that can be written to the field `R4`"] pub enum R4W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R4W { #[allow(missing_docs)] @@ -1730,14 +1620,10 @@ impl<'a> _R4W<'a> { } #[doc = "Values that can be written to the field `R3`"] pub enum R3W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R3W { #[allow(missing_docs)] @@ -1796,14 +1682,10 @@ impl<'a> _R3W<'a> { } #[doc = "Values that can be written to the field `R2`"] pub enum R2W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R2W { #[allow(missing_docs)] @@ -1862,14 +1744,10 @@ impl<'a> _R2W<'a> { } #[doc = "Values that can be written to the field `R1`"] pub enum R1W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R1W { #[allow(missing_docs)] @@ -1928,14 +1806,10 @@ impl<'a> _R1W<'a> { } #[doc = "Values that can be written to the field `R0`"] pub enum R0W { - #[doc = "Non-cacheable"] - _00, - #[doc = "Non-cacheable"] - _01, - #[doc = "Write-through"] - _10, - #[doc = "Write-back"] - _11, + #[doc = "Non-cacheable"] _00, + #[doc = "Non-cacheable"] _01, + #[doc = "Write-through"] _10, + #[doc = "Write-back"] _11, } impl R0W { #[allow(missing_docs)] diff --git a/src/lpi2c0/mccr0/mod.rs b/src/lpi2c0/mccr0/mod.rs index c33ba51..9dcd9e3 100644 --- a/src/lpi2c0/mccr0/mod.rs +++ b/src/lpi2c0/mccr0/mod.rs @@ -22,7 +22,9 @@ impl super::MCCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mccr1/mod.rs b/src/lpi2c0/mccr1/mod.rs index 34b391f..d31da34 100644 --- a/src/lpi2c0/mccr1/mod.rs +++ b/src/lpi2c0/mccr1/mod.rs @@ -22,7 +22,9 @@ impl super::MCCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mcfgr0/mod.rs b/src/lpi2c0/mcfgr0/mod.rs index 9020508..3523f6a 100644 --- a/src/lpi2c0/mcfgr0/mod.rs +++ b/src/lpi2c0/mcfgr0/mod.rs @@ -22,7 +22,9 @@ impl super::MCFGR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MCFGR0 { #[doc = "Possible values of the field `HREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRENR { - #[doc = "Host request input is disabled."] - _0, - #[doc = "Host request input is enabled."] - _1, + #[doc = "Host request input is disabled."] _0, + #[doc = "Host request input is enabled."] _1, } impl HRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl HRENR { #[doc = "Possible values of the field `HRPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRPOLR { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl HRPOLR { #[doc = "Possible values of the field `HRSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRSELR { - #[doc = "Host request input is pin HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl HRSELR { #[doc = "Possible values of the field `CIRFIFO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CIRFIFOR { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CIRFIFOR { #[doc = "Possible values of the field `RDMO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMOR { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the RMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the RMF is set."] _1, } impl RDMOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +269,8 @@ impl RDMOR { } #[doc = "Values that can be written to the field `HREN`"] pub enum HRENW { - #[doc = "Host request input is disabled."] - _0, - #[doc = "Host request input is enabled."] - _1, + #[doc = "Host request input is disabled."] _0, + #[doc = "Host request input is enabled."] _1, } impl HRENW { #[allow(missing_docs)] @@ -335,10 +325,8 @@ impl<'a> _HRENW<'a> { } #[doc = "Values that can be written to the field `HRPOL`"] pub enum HRPOLW { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLW { #[allow(missing_docs)] @@ -393,10 +381,8 @@ impl<'a> _HRPOLW<'a> { } #[doc = "Values that can be written to the field `HRSEL`"] pub enum HRSELW { - #[doc = "Host request input is pin HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELW { #[allow(missing_docs)] @@ -451,10 +437,8 @@ impl<'a> _HRSELW<'a> { } #[doc = "Values that can be written to the field `CIRFIFO`"] pub enum CIRFIFOW { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOW { #[allow(missing_docs)] @@ -509,10 +493,8 @@ impl<'a> _CIRFIFOW<'a> { } #[doc = "Values that can be written to the field `RDMO`"] pub enum RDMOW { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the RMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the RMF is set."] _1, } impl RDMOW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mcfgr1/mod.rs b/src/lpi2c0/mcfgr1/mod.rs index f4449c5..69460d1 100644 --- a/src/lpi2c0/mcfgr1/mod.rs +++ b/src/lpi2c0/mcfgr1/mod.rs @@ -22,7 +22,9 @@ impl super::MCFGR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::MCFGR1 { #[doc = "Possible values of the field `PRESCALE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALER { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALER { #[doc = r" Value of the field as raw bits"] @@ -135,8 +129,7 @@ impl PRESCALER { #[doc = "Possible values of the field `AUTOSTOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AUTOSTOPR { - #[doc = "No effect."] - _0, + #[doc = "No effect."] _0, #[doc = "STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy."] _1, } @@ -182,10 +175,8 @@ impl AUTOSTOPR { #[doc = "Possible values of the field `IGNACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IGNACKR { - #[doc = "LPI2C Master will receive ACK and NACK normally."] - _0, - #[doc = "LPI2C Master will treat a received NACK as if it was an ACK."] - _1, + #[doc = "LPI2C Master will receive ACK and NACK normally."] _0, + #[doc = "LPI2C Master will treat a received NACK as if it was an ACK."] _1, } impl IGNACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -276,22 +267,14 @@ impl TIMECFGR { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Match disabled."] - _000, - #[doc = "Match enabled (1st data word equals MATCH0 OR MATCH1)."] - _010, - #[doc = "Match enabled (any data word equals MATCH0 OR MATCH1)."] - _011, - #[doc = "Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)."] - _100, - #[doc = "Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)."] - _101, - #[doc = "Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)."] - _110, - #[doc = "Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)."] - _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Match disabled."] _000, + #[doc = "Match enabled (1st data word equals MATCH0 OR MATCH1)."] _010, + #[doc = "Match enabled (any data word equals MATCH0 OR MATCH1)."] _011, + #[doc = "Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)."] _100, + #[doc = "Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)."] _101, + #[doc = "Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)."] _110, + #[doc = "Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)."] _111, + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -362,22 +345,15 @@ impl MATCFGR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "LPI2C configured for 2-pin open drain mode."] - _000, - #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode)."] - _001, - #[doc = "LPI2C configured for 2-pin push-pull mode."] - _010, - #[doc = "LPI2C configured for 4-pin push-pull mode."] - _011, - #[doc = "LPI2C configured for 2-pin open drain mode with separate LPI2C slave."] - _100, + #[doc = "LPI2C configured for 2-pin open drain mode."] _000, + #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode)."] _001, + #[doc = "LPI2C configured for 2-pin push-pull mode."] _010, + #[doc = "LPI2C configured for 4-pin push-pull mode."] _011, + #[doc = "LPI2C configured for 2-pin open drain mode with separate LPI2C slave."] _100, #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave."] _101, - #[doc = "LPI2C configured for 2-pin push-pull mode with separate LPI2C slave."] - _110, - #[doc = "LPI2C configured for 4-pin push-pull mode (inverted outputs)."] - _111, + #[doc = "LPI2C configured for 2-pin push-pull mode with separate LPI2C slave."] _110, + #[doc = "LPI2C configured for 4-pin push-pull mode (inverted outputs)."] _111, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -453,22 +429,14 @@ impl PINCFGR { } #[doc = "Values that can be written to the field `PRESCALE`"] pub enum PRESCALEW { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALEW { #[allow(missing_docs)] @@ -551,8 +519,7 @@ impl<'a> _PRESCALEW<'a> { } #[doc = "Values that can be written to the field `AUTOSTOP`"] pub enum AUTOSTOPW { - #[doc = "No effect."] - _0, + #[doc = "No effect."] _0, #[doc = "STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy."] _1, } @@ -609,10 +576,8 @@ impl<'a> _AUTOSTOPW<'a> { } #[doc = "Values that can be written to the field `IGNACK`"] pub enum IGNACKW { - #[doc = "LPI2C Master will receive ACK and NACK normally."] - _0, - #[doc = "LPI2C Master will treat a received NACK as if it was an ACK."] - _1, + #[doc = "LPI2C Master will receive ACK and NACK normally."] _0, + #[doc = "LPI2C Master will treat a received NACK as if it was an ACK."] _1, } impl IGNACKW { #[allow(missing_docs)] @@ -725,20 +690,13 @@ impl<'a> _TIMECFGW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Match disabled."] - _000, - #[doc = "Match enabled (1st data word equals MATCH0 OR MATCH1)."] - _010, - #[doc = "Match enabled (any data word equals MATCH0 OR MATCH1)."] - _011, - #[doc = "Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)."] - _100, - #[doc = "Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)."] - _101, - #[doc = "Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)."] - _110, - #[doc = "Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)."] - _111, + #[doc = "Match disabled."] _000, + #[doc = "Match enabled (1st data word equals MATCH0 OR MATCH1)."] _010, + #[doc = "Match enabled (any data word equals MATCH0 OR MATCH1)."] _011, + #[doc = "Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)."] _100, + #[doc = "Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)."] _101, + #[doc = "Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)."] _110, + #[doc = "Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)."] _111, } impl MATCFGW { #[allow(missing_docs)] @@ -813,22 +771,15 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "LPI2C configured for 2-pin open drain mode."] - _000, - #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode)."] - _001, - #[doc = "LPI2C configured for 2-pin push-pull mode."] - _010, - #[doc = "LPI2C configured for 4-pin push-pull mode."] - _011, - #[doc = "LPI2C configured for 2-pin open drain mode with separate LPI2C slave."] - _100, + #[doc = "LPI2C configured for 2-pin open drain mode."] _000, + #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode)."] _001, + #[doc = "LPI2C configured for 2-pin push-pull mode."] _010, + #[doc = "LPI2C configured for 4-pin push-pull mode."] _011, + #[doc = "LPI2C configured for 2-pin open drain mode with separate LPI2C slave."] _100, #[doc = "LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave."] _101, - #[doc = "LPI2C configured for 2-pin push-pull mode with separate LPI2C slave."] - _110, - #[doc = "LPI2C configured for 4-pin push-pull mode (inverted outputs)."] - _111, + #[doc = "LPI2C configured for 2-pin push-pull mode with separate LPI2C slave."] _110, + #[doc = "LPI2C configured for 4-pin push-pull mode (inverted outputs)."] _111, } impl PINCFGW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mcfgr2/mod.rs b/src/lpi2c0/mcfgr2/mod.rs index 77f5509..37ac987 100644 --- a/src/lpi2c0/mcfgr2/mod.rs +++ b/src/lpi2c0/mcfgr2/mod.rs @@ -22,7 +22,9 @@ impl super::MCFGR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mcfgr3/mod.rs b/src/lpi2c0/mcfgr3/mod.rs index ba78c00..4900129 100644 --- a/src/lpi2c0/mcfgr3/mod.rs +++ b/src/lpi2c0/mcfgr3/mod.rs @@ -22,7 +22,9 @@ impl super::MCFGR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mcr/mod.rs b/src/lpi2c0/mcr/mod.rs index bb474e2..63785c4 100644 --- a/src/lpi2c0/mcr/mod.rs +++ b/src/lpi2c0/mcr/mod.rs @@ -22,7 +22,9 @@ impl super::MCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MCR { #[doc = "Possible values of the field `MEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MENR { - #[doc = "Master logic is disabled."] - _0, - #[doc = "Master logic is enabled."] - _1, + #[doc = "Master logic is disabled."] _0, + #[doc = "Master logic is enabled."] _1, } impl MENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MENR { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RSTR { #[doc = "Possible values of the field `DOZEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZENR { - #[doc = "Master is enabled in Doze mode."] - _0, - #[doc = "Master is disabled in Doze mode."] - _1, + #[doc = "Master is enabled in Doze mode."] _0, + #[doc = "Master is disabled in Doze mode."] _1, } impl DOZENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl DOZENR { #[doc = "Possible values of the field `DBGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGENR { - #[doc = "Master is disabled in debug mode."] - _0, - #[doc = "Master is enabled in debug mode."] - _1, + #[doc = "Master is disabled in debug mode."] _0, + #[doc = "Master is enabled in debug mode."] _1, } impl DBGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl DBGENR { } #[doc = "Values that can be written to the field `MEN`"] pub enum MENW { - #[doc = "Master logic is disabled."] - _0, - #[doc = "Master logic is enabled."] - _1, + #[doc = "Master logic is disabled."] _0, + #[doc = "Master logic is enabled."] _1, } impl MENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _MENW<'a> { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> { } #[doc = "Values that can be written to the field `DOZEN`"] pub enum DOZENW { - #[doc = "Master is enabled in Doze mode."] - _0, - #[doc = "Master is disabled in Doze mode."] - _1, + #[doc = "Master is enabled in Doze mode."] _0, + #[doc = "Master is disabled in Doze mode."] _1, } impl DOZENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _DOZENW<'a> { } #[doc = "Values that can be written to the field `DBGEN`"] pub enum DBGENW { - #[doc = "Master is disabled in debug mode."] - _0, - #[doc = "Master is enabled in debug mode."] - _1, + #[doc = "Master is disabled in debug mode."] _0, + #[doc = "Master is enabled in debug mode."] _1, } impl DBGENW { #[allow(missing_docs)] @@ -462,10 +448,8 @@ impl<'a> _DBGENW<'a> { } #[doc = "Values that can be written to the field `RTF`"] pub enum RTFW { - #[doc = "No effect."] - _0, - #[doc = "Transmit FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Transmit FIFO is reset."] _1, } impl RTFW { #[allow(missing_docs)] @@ -520,10 +504,8 @@ impl<'a> _RTFW<'a> { } #[doc = "Values that can be written to the field `RRF`"] pub enum RRFW { - #[doc = "No effect."] - _0, - #[doc = "Receive FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Receive FIFO is reset."] _1, } impl RRFW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mder/mod.rs b/src/lpi2c0/mder/mod.rs index 448c59b..27b30ac 100644 --- a/src/lpi2c0/mder/mod.rs +++ b/src/lpi2c0/mder/mod.rs @@ -22,7 +22,9 @@ impl super::MDER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MDER { #[doc = "Possible values of the field `TDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDDER { #[doc = "Possible values of the field `RDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl RDDER { } #[doc = "Values that can be written to the field `TDDE`"] pub enum TDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDEW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _TDDEW<'a> { } #[doc = "Values that can be written to the field `RDDE`"] pub enum RDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDEW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mdmr/mod.rs b/src/lpi2c0/mdmr/mod.rs index 23ba401..13e0faf 100644 --- a/src/lpi2c0/mdmr/mod.rs +++ b/src/lpi2c0/mdmr/mod.rs @@ -22,7 +22,9 @@ impl super::MDMR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mfcr/mod.rs b/src/lpi2c0/mfcr/mod.rs index 99259c0..3b0a4ff 100644 --- a/src/lpi2c0/mfcr/mod.rs +++ b/src/lpi2c0/mfcr/mod.rs @@ -22,7 +22,9 @@ impl super::MFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/mfsr/mod.rs b/src/lpi2c0/mfsr/mod.rs index b3e79e4..d42e7da 100644 --- a/src/lpi2c0/mfsr/mod.rs +++ b/src/lpi2c0/mfsr/mod.rs @@ -6,7 +6,9 @@ impl super::MFSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpi2c0/mier/mod.rs b/src/lpi2c0/mier/mod.rs index bf8014e..6afcc24 100644 --- a/src/lpi2c0/mier/mod.rs +++ b/src/lpi2c0/mier/mod.rs @@ -22,7 +22,9 @@ impl super::MIER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MIER { #[doc = "Possible values of the field `TDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDIER { #[doc = "Possible values of the field `RDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDIER { #[doc = "Possible values of the field `EPIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EPIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl EPIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl EPIER { #[doc = "Possible values of the field `SDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl SDIER { #[doc = "Possible values of the field `NDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl NDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl NDIER { #[doc = "Possible values of the field `ALIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ALIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl ALIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ALIER { #[doc = "Possible values of the field `FEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEIER { - #[doc = "Interrupt enabled."] - _0, - #[doc = "Interrupt disabled."] - _1, + #[doc = "Interrupt enabled."] _0, + #[doc = "Interrupt disabled."] _1, } impl FEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FEIER { #[doc = "Possible values of the field `PLTIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLTIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl PLTIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl PLTIER { #[doc = "Possible values of the field `DMIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl DMIER { } #[doc = "Values that can be written to the field `TDIE`"] pub enum TDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIEW { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _TDIEW<'a> { } #[doc = "Values that can be written to the field `RDIE`"] pub enum RDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIEW { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _RDIEW<'a> { } #[doc = "Values that can be written to the field `EPIE`"] pub enum EPIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl EPIEW { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _EPIEW<'a> { } #[doc = "Values that can be written to the field `SDIE`"] pub enum SDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SDIEW { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _SDIEW<'a> { } #[doc = "Values that can be written to the field `NDIE`"] pub enum NDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl NDIEW { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _NDIEW<'a> { } #[doc = "Values that can be written to the field `ALIE`"] pub enum ALIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl ALIEW { #[allow(missing_docs)] @@ -813,10 +785,8 @@ impl<'a> _ALIEW<'a> { } #[doc = "Values that can be written to the field `FEIE`"] pub enum FEIEW { - #[doc = "Interrupt enabled."] - _0, - #[doc = "Interrupt disabled."] - _1, + #[doc = "Interrupt enabled."] _0, + #[doc = "Interrupt disabled."] _1, } impl FEIEW { #[allow(missing_docs)] @@ -871,10 +841,8 @@ impl<'a> _FEIEW<'a> { } #[doc = "Values that can be written to the field `PLTIE`"] pub enum PLTIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl PLTIEW { #[allow(missing_docs)] @@ -929,10 +897,8 @@ impl<'a> _PLTIEW<'a> { } #[doc = "Values that can be written to the field `DMIE`"] pub enum DMIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIEW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mod.rs b/src/lpi2c0/mod.rs index f50fa1d..4211dd6 100644 --- a/src/lpi2c0/mod.rs +++ b/src/lpi2c0/mod.rs @@ -2,74 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, _reserved0: [u8; 8usize], - #[doc = "0x10 - Master Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Master Status Register"] - pub msr: MSR, - #[doc = "0x18 - Master Interrupt Enable Register"] - pub mier: MIER, - #[doc = "0x1c - Master DMA Enable Register"] - pub mder: MDER, - #[doc = "0x20 - Master Configuration Register 0"] - pub mcfgr0: MCFGR0, - #[doc = "0x24 - Master Configuration Register 1"] - pub mcfgr1: MCFGR1, - #[doc = "0x28 - Master Configuration Register 2"] - pub mcfgr2: MCFGR2, - #[doc = "0x2c - Master Configuration Register 3"] - pub mcfgr3: MCFGR3, + #[doc = "0x10 - Master Control Register"] pub mcr: MCR, + #[doc = "0x14 - Master Status Register"] pub msr: MSR, + #[doc = "0x18 - Master Interrupt Enable Register"] pub mier: MIER, + #[doc = "0x1c - Master DMA Enable Register"] pub mder: MDER, + #[doc = "0x20 - Master Configuration Register 0"] pub mcfgr0: MCFGR0, + #[doc = "0x24 - Master Configuration Register 1"] pub mcfgr1: MCFGR1, + #[doc = "0x28 - Master Configuration Register 2"] pub mcfgr2: MCFGR2, + #[doc = "0x2c - Master Configuration Register 3"] pub mcfgr3: MCFGR3, _reserved1: [u8; 16usize], - #[doc = "0x40 - Master Data Match Register"] - pub mdmr: MDMR, + #[doc = "0x40 - Master Data Match Register"] pub mdmr: MDMR, _reserved2: [u8; 4usize], - #[doc = "0x48 - Master Clock Configuration Register 0"] - pub mccr0: MCCR0, + #[doc = "0x48 - Master Clock Configuration Register 0"] pub mccr0: MCCR0, _reserved3: [u8; 4usize], - #[doc = "0x50 - Master Clock Configuration Register 1"] - pub mccr1: MCCR1, + #[doc = "0x50 - Master Clock Configuration Register 1"] pub mccr1: MCCR1, _reserved4: [u8; 4usize], - #[doc = "0x58 - Master FIFO Control Register"] - pub mfcr: MFCR, - #[doc = "0x5c - Master FIFO Status Register"] - pub mfsr: MFSR, - #[doc = "0x60 - Master Transmit Data Register"] - pub mtdr: MTDR, + #[doc = "0x58 - Master FIFO Control Register"] pub mfcr: MFCR, + #[doc = "0x5c - Master FIFO Status Register"] pub mfsr: MFSR, + #[doc = "0x60 - Master Transmit Data Register"] pub mtdr: MTDR, _reserved5: [u8; 12usize], - #[doc = "0x70 - Master Receive Data Register"] - pub mrdr: MRDR, + #[doc = "0x70 - Master Receive Data Register"] pub mrdr: MRDR, _reserved6: [u8; 156usize], - #[doc = "0x110 - Slave Control Register"] - pub scr: SCR, - #[doc = "0x114 - Slave Status Register"] - pub ssr: SSR, - #[doc = "0x118 - Slave Interrupt Enable Register"] - pub sier: SIER, - #[doc = "0x11c - Slave DMA Enable Register"] - pub sder: SDER, + #[doc = "0x110 - Slave Control Register"] pub scr: SCR, + #[doc = "0x114 - Slave Status Register"] pub ssr: SSR, + #[doc = "0x118 - Slave Interrupt Enable Register"] pub sier: SIER, + #[doc = "0x11c - Slave DMA Enable Register"] pub sder: SDER, _reserved7: [u8; 4usize], - #[doc = "0x124 - Slave Configuration Register 1"] - pub scfgr1: SCFGR1, - #[doc = "0x128 - Slave Configuration Register 2"] - pub scfgr2: SCFGR2, + #[doc = "0x124 - Slave Configuration Register 1"] pub scfgr1: SCFGR1, + #[doc = "0x128 - Slave Configuration Register 2"] pub scfgr2: SCFGR2, _reserved8: [u8; 20usize], - #[doc = "0x140 - Slave Address Match Register"] - pub samr: SAMR, + #[doc = "0x140 - Slave Address Match Register"] pub samr: SAMR, _reserved9: [u8; 12usize], - #[doc = "0x150 - Slave Address Status Register"] - pub sasr: SASR, - #[doc = "0x154 - Slave Transmit ACK Register"] - pub star: STAR, + #[doc = "0x150 - Slave Address Status Register"] pub sasr: SASR, + #[doc = "0x154 - Slave Transmit ACK Register"] pub star: STAR, _reserved10: [u8; 8usize], - #[doc = "0x160 - Slave Transmit Data Register"] - pub stdr: STDR, + #[doc = "0x160 - Slave Transmit Data Register"] pub stdr: STDR, _reserved11: [u8; 12usize], - #[doc = "0x170 - Slave Receive Data Register"] - pub srdr: SRDR, + #[doc = "0x170 - Slave Receive Data Register"] pub srdr: SRDR, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpi2c0/mrdr/mod.rs b/src/lpi2c0/mrdr/mod.rs index 8bd7066..810d86b 100644 --- a/src/lpi2c0/mrdr/mod.rs +++ b/src/lpi2c0/mrdr/mod.rs @@ -6,7 +6,9 @@ impl super::MRDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DATAR { #[doc = "Possible values of the field `RXEMPTY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTYR { - #[doc = "Receive FIFO is not empty."] - _0, - #[doc = "Receive FIFO is empty."] - _1, + #[doc = "Receive FIFO is not empty."] _0, + #[doc = "Receive FIFO is empty."] _1, } impl RXEMPTYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpi2c0/msr/mod.rs b/src/lpi2c0/msr/mod.rs index c9fbac9..6c199e8 100644 --- a/src/lpi2c0/msr/mod.rs +++ b/src/lpi2c0/msr/mod.rs @@ -22,7 +22,9 @@ impl super::MSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MSR { #[doc = "Possible values of the field `TDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDFR { - #[doc = "Transmit data not requested."] - _0, - #[doc = "Transmit data is requested."] - _1, + #[doc = "Transmit data not requested."] _0, + #[doc = "Transmit data is requested."] _1, } impl TDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDFR { #[doc = "Possible values of the field `RDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDFR { - #[doc = "Receive Data is not ready."] - _0, - #[doc = "Receive data is ready."] - _1, + #[doc = "Receive Data is not ready."] _0, + #[doc = "Receive data is ready."] _1, } impl RDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDFR { #[doc = "Possible values of the field `EPF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EPFR { - #[doc = "Master has not generated a STOP or Repeated START condition."] - _0, - #[doc = "Master has generated a STOP or Repeated START condition."] - _1, + #[doc = "Master has not generated a STOP or Repeated START condition."] _0, + #[doc = "Master has generated a STOP or Repeated START condition."] _1, } impl EPFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl EPFR { #[doc = "Possible values of the field `SDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SDFR { - #[doc = "Master has not generated a STOP condition."] - _0, - #[doc = "Master has generated a STOP condition."] - _1, + #[doc = "Master has not generated a STOP condition."] _0, + #[doc = "Master has generated a STOP condition."] _1, } impl SDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl SDFR { #[doc = "Possible values of the field `NDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NDFR { - #[doc = "Unexpected NACK not detected."] - _0, - #[doc = "Unexpected NACK was detected."] - _1, + #[doc = "Unexpected NACK not detected."] _0, + #[doc = "Unexpected NACK was detected."] _1, } impl NDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl NDFR { #[doc = "Possible values of the field `ALF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ALFR { - #[doc = "Master has not lost arbitration."] - _0, - #[doc = "Master has lost arbitration."] - _1, + #[doc = "Master has not lost arbitration."] _0, + #[doc = "Master has lost arbitration."] _1, } impl ALFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ALFR { #[doc = "Possible values of the field `FEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEFR { - #[doc = "No error."] - _0, - #[doc = "Master sending or receiving data without START condition."] - _1, + #[doc = "No error."] _0, + #[doc = "Master sending or receiving data without START condition."] _1, } impl FEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FEFR { #[doc = "Possible values of the field `PLTF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLTFR { - #[doc = "Pin low timeout has not occurred or is disabled."] - _0, - #[doc = "Pin low timeout has occurred."] - _1, + #[doc = "Pin low timeout has not occurred or is disabled."] _0, + #[doc = "Pin low timeout has occurred."] _1, } impl PLTFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl PLTFR { #[doc = "Possible values of the field `DMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMFR { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl DMFR { #[doc = "Possible values of the field `MBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBFR { - #[doc = "I2C Master is idle."] - _0, - #[doc = "I2C Master is busy."] - _1, + #[doc = "I2C Master is idle."] _0, + #[doc = "I2C Master is busy."] _1, } impl MBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl MBFR { #[doc = "Possible values of the field `BBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBFR { - #[doc = "I2C Bus is idle."] - _0, - #[doc = "I2C Bus is busy."] - _1, + #[doc = "I2C Bus is idle."] _0, + #[doc = "I2C Bus is busy."] _1, } impl BBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -559,10 +539,8 @@ impl BBFR { } #[doc = "Values that can be written to the field `EPF`"] pub enum EPFW { - #[doc = "Master has not generated a STOP or Repeated START condition."] - _0, - #[doc = "Master has generated a STOP or Repeated START condition."] - _1, + #[doc = "Master has not generated a STOP or Repeated START condition."] _0, + #[doc = "Master has generated a STOP or Repeated START condition."] _1, } impl EPFW { #[allow(missing_docs)] @@ -617,10 +595,8 @@ impl<'a> _EPFW<'a> { } #[doc = "Values that can be written to the field `SDF`"] pub enum SDFW { - #[doc = "Master has not generated a STOP condition."] - _0, - #[doc = "Master has generated a STOP condition."] - _1, + #[doc = "Master has not generated a STOP condition."] _0, + #[doc = "Master has generated a STOP condition."] _1, } impl SDFW { #[allow(missing_docs)] @@ -675,10 +651,8 @@ impl<'a> _SDFW<'a> { } #[doc = "Values that can be written to the field `NDF`"] pub enum NDFW { - #[doc = "Unexpected NACK not detected."] - _0, - #[doc = "Unexpected NACK was detected."] - _1, + #[doc = "Unexpected NACK not detected."] _0, + #[doc = "Unexpected NACK was detected."] _1, } impl NDFW { #[allow(missing_docs)] @@ -733,10 +707,8 @@ impl<'a> _NDFW<'a> { } #[doc = "Values that can be written to the field `ALF`"] pub enum ALFW { - #[doc = "Master has not lost arbitration."] - _0, - #[doc = "Master has lost arbitration."] - _1, + #[doc = "Master has not lost arbitration."] _0, + #[doc = "Master has lost arbitration."] _1, } impl ALFW { #[allow(missing_docs)] @@ -791,10 +763,8 @@ impl<'a> _ALFW<'a> { } #[doc = "Values that can be written to the field `FEF`"] pub enum FEFW { - #[doc = "No error."] - _0, - #[doc = "Master sending or receiving data without START condition."] - _1, + #[doc = "No error."] _0, + #[doc = "Master sending or receiving data without START condition."] _1, } impl FEFW { #[allow(missing_docs)] @@ -849,10 +819,8 @@ impl<'a> _FEFW<'a> { } #[doc = "Values that can be written to the field `PLTF`"] pub enum PLTFW { - #[doc = "Pin low timeout has not occurred or is disabled."] - _0, - #[doc = "Pin low timeout has occurred."] - _1, + #[doc = "Pin low timeout has not occurred or is disabled."] _0, + #[doc = "Pin low timeout has occurred."] _1, } impl PLTFW { #[allow(missing_docs)] @@ -907,10 +875,8 @@ impl<'a> _PLTFW<'a> { } #[doc = "Values that can be written to the field `DMF`"] pub enum DMFW { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFW { #[allow(missing_docs)] diff --git a/src/lpi2c0/mtdr/mod.rs b/src/lpi2c0/mtdr/mod.rs index 01a13ee..1ae456f 100644 --- a/src/lpi2c0/mtdr/mod.rs +++ b/src/lpi2c0/mtdr/mod.rs @@ -22,7 +22,9 @@ impl super::MTDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -57,16 +59,11 @@ impl<'a> _DATAW<'a> { } #[doc = "Values that can be written to the field `CMD`"] pub enum CMDW { - #[doc = "Transmit DATA[7:0]."] - _000, - #[doc = "Receive (DATA[7:0] + 1) bytes."] - _001, - #[doc = "Generate STOP condition."] - _010, - #[doc = "Receive and discard (DATA[7:0] + 1) bytes."] - _011, - #[doc = "Generate (repeated) START and transmit address in DATA[7:0]."] - _100, + #[doc = "Transmit DATA[7:0]."] _000, + #[doc = "Receive (DATA[7:0] + 1) bytes."] _001, + #[doc = "Generate STOP condition."] _010, + #[doc = "Receive and discard (DATA[7:0] + 1) bytes."] _011, + #[doc = "Generate (repeated) START and transmit address in DATA[7:0]."] _100, #[doc = "Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned."] _101, #[doc = "Generate (repeated) START and transmit address in DATA[7:0] using high speed mode."] diff --git a/src/lpi2c0/param/mod.rs b/src/lpi2c0/param/mod.rs index f3fb80b..02f852a 100644 --- a/src/lpi2c0/param/mod.rs +++ b/src/lpi2c0/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpi2c0/samr/mod.rs b/src/lpi2c0/samr/mod.rs index 2aeee48..cbc2682 100644 --- a/src/lpi2c0/samr/mod.rs +++ b/src/lpi2c0/samr/mod.rs @@ -22,7 +22,9 @@ impl super::SAMR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/sasr/mod.rs b/src/lpi2c0/sasr/mod.rs index 86f6b81..5541635 100644 --- a/src/lpi2c0/sasr/mod.rs +++ b/src/lpi2c0/sasr/mod.rs @@ -6,7 +6,9 @@ impl super::SASR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl RADDRR { #[doc = "Possible values of the field `ANV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ANVR { - #[doc = "RADDR is valid."] - _0, - #[doc = "RADDR is not valid."] - _1, + #[doc = "RADDR is valid."] _0, + #[doc = "RADDR is not valid."] _1, } impl ANVR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpi2c0/scfgr1/mod.rs b/src/lpi2c0/scfgr1/mod.rs index c65d2aa..6b4f2ed 100644 --- a/src/lpi2c0/scfgr1/mod.rs +++ b/src/lpi2c0/scfgr1/mod.rs @@ -22,7 +22,9 @@ impl super::SCFGR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SCFGR1 { #[doc = "Possible values of the field `ADRSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADRSTALLR { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl ADRSTALLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ADRSTALLR { #[doc = "Possible values of the field `RXSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXSTALLR { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl RXSTALLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RXSTALLR { #[doc = "Possible values of the field `TXDSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXDSTALLR { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl TXDSTALLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl TXDSTALLR { #[doc = "Possible values of the field `ACKSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ACKSTALLR { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl ACKSTALLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl ACKSTALLR { #[doc = "Possible values of the field `GCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GCENR { - #[doc = "General Call address is disabled."] - _0, - #[doc = "General call address is enabled."] - _1, + #[doc = "General Call address is disabled."] _0, + #[doc = "General call address is enabled."] _1, } impl GCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl GCENR { #[doc = "Possible values of the field `SAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SAENR { - #[doc = "Disables match on SMBus Alert."] - _0, - #[doc = "Enables match on SMBus Alert."] - _1, + #[doc = "Disables match on SMBus Alert."] _0, + #[doc = "Enables match on SMBus Alert."] _1, } impl SAENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -327,8 +317,7 @@ impl SAENR { pub enum TXCFGR { #[doc = "Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty."] _0, - #[doc = "Transmit Data Flag will assert whenever the transmit data register is empty."] - _1, + #[doc = "Transmit Data Flag will assert whenever the transmit data register is empty."] _1, } impl TXCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +408,8 @@ impl RXCFGR { #[doc = "Possible values of the field `IGNACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IGNACKR { - #[doc = "Slave will end transfer when NACK detected."] - _0, - #[doc = "Slave will not end transfer when NACK detected."] - _1, + #[doc = "Slave will end transfer when NACK detected."] _0, + #[doc = "Slave will not end transfer when NACK detected."] _1, } impl IGNACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +453,8 @@ impl IGNACKR { #[doc = "Possible values of the field `HSMEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HSMENR { - #[doc = "Disables detection of Hs-mode master code."] - _0, - #[doc = "Enables detection of Hs-mode master code."] - _1, + #[doc = "Disables detection of Hs-mode master code."] _0, + #[doc = "Enables detection of Hs-mode master code."] _1, } impl HSMENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,22 +498,14 @@ impl HSMENR { #[doc = "Possible values of the field `ADDRCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADDRCFGR { - #[doc = "Address match 0 (7-bit)."] - _000, - #[doc = "Address match 0 (10-bit)."] - _001, - #[doc = "Address match 0 (7-bit) or Address match 1 (7-bit)."] - _010, - #[doc = "Address match 0 (10-bit) or Address match 1 (10-bit)."] - _011, - #[doc = "Address match 0 (7-bit) or Address match 1 (10-bit)."] - _100, - #[doc = "Address match 0 (10-bit) or Address match 1 (7-bit)."] - _101, - #[doc = "From Address match 0 (7-bit) to Address match 1 (7-bit)."] - _110, - #[doc = "From Address match 0 (10-bit) to Address match 1 (10-bit)."] - _111, + #[doc = "Address match 0 (7-bit)."] _000, + #[doc = "Address match 0 (10-bit)."] _001, + #[doc = "Address match 0 (7-bit) or Address match 1 (7-bit)."] _010, + #[doc = "Address match 0 (10-bit) or Address match 1 (10-bit)."] _011, + #[doc = "Address match 0 (7-bit) or Address match 1 (10-bit)."] _100, + #[doc = "Address match 0 (10-bit) or Address match 1 (7-bit)."] _101, + #[doc = "From Address match 0 (7-bit) to Address match 1 (7-bit)."] _110, + #[doc = "From Address match 0 (10-bit) to Address match 1 (10-bit)."] _111, } impl ADDRCFGR { #[doc = r" Value of the field as raw bits"] @@ -604,10 +581,8 @@ impl ADDRCFGR { } #[doc = "Values that can be written to the field `ADRSTALL`"] pub enum ADRSTALLW { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl ADRSTALLW { #[allow(missing_docs)] @@ -662,10 +637,8 @@ impl<'a> _ADRSTALLW<'a> { } #[doc = "Values that can be written to the field `RXSTALL`"] pub enum RXSTALLW { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl RXSTALLW { #[allow(missing_docs)] @@ -720,10 +693,8 @@ impl<'a> _RXSTALLW<'a> { } #[doc = "Values that can be written to the field `TXDSTALL`"] pub enum TXDSTALLW { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl TXDSTALLW { #[allow(missing_docs)] @@ -778,10 +749,8 @@ impl<'a> _TXDSTALLW<'a> { } #[doc = "Values that can be written to the field `ACKSTALL`"] pub enum ACKSTALLW { - #[doc = "Clock stretching disabled."] - _0, - #[doc = "Clock stretching enabled."] - _1, + #[doc = "Clock stretching disabled."] _0, + #[doc = "Clock stretching enabled."] _1, } impl ACKSTALLW { #[allow(missing_docs)] @@ -836,10 +805,8 @@ impl<'a> _ACKSTALLW<'a> { } #[doc = "Values that can be written to the field `GCEN`"] pub enum GCENW { - #[doc = "General Call address is disabled."] - _0, - #[doc = "General call address is enabled."] - _1, + #[doc = "General Call address is disabled."] _0, + #[doc = "General call address is enabled."] _1, } impl GCENW { #[allow(missing_docs)] @@ -894,10 +861,8 @@ impl<'a> _GCENW<'a> { } #[doc = "Values that can be written to the field `SAEN`"] pub enum SAENW { - #[doc = "Disables match on SMBus Alert."] - _0, - #[doc = "Enables match on SMBus Alert."] - _1, + #[doc = "Disables match on SMBus Alert."] _0, + #[doc = "Enables match on SMBus Alert."] _1, } impl SAENW { #[allow(missing_docs)] @@ -954,8 +919,7 @@ impl<'a> _SAENW<'a> { pub enum TXCFGW { #[doc = "Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty."] _0, - #[doc = "Transmit Data Flag will assert whenever the transmit data register is empty."] - _1, + #[doc = "Transmit Data Flag will assert whenever the transmit data register is empty."] _1, } impl TXCFGW { #[allow(missing_docs)] @@ -1068,10 +1032,8 @@ impl<'a> _RXCFGW<'a> { } #[doc = "Values that can be written to the field `IGNACK`"] pub enum IGNACKW { - #[doc = "Slave will end transfer when NACK detected."] - _0, - #[doc = "Slave will not end transfer when NACK detected."] - _1, + #[doc = "Slave will end transfer when NACK detected."] _0, + #[doc = "Slave will not end transfer when NACK detected."] _1, } impl IGNACKW { #[allow(missing_docs)] @@ -1126,10 +1088,8 @@ impl<'a> _IGNACKW<'a> { } #[doc = "Values that can be written to the field `HSMEN`"] pub enum HSMENW { - #[doc = "Disables detection of Hs-mode master code."] - _0, - #[doc = "Enables detection of Hs-mode master code."] - _1, + #[doc = "Disables detection of Hs-mode master code."] _0, + #[doc = "Enables detection of Hs-mode master code."] _1, } impl HSMENW { #[allow(missing_docs)] @@ -1184,22 +1144,14 @@ impl<'a> _HSMENW<'a> { } #[doc = "Values that can be written to the field `ADDRCFG`"] pub enum ADDRCFGW { - #[doc = "Address match 0 (7-bit)."] - _000, - #[doc = "Address match 0 (10-bit)."] - _001, - #[doc = "Address match 0 (7-bit) or Address match 1 (7-bit)."] - _010, - #[doc = "Address match 0 (10-bit) or Address match 1 (10-bit)."] - _011, - #[doc = "Address match 0 (7-bit) or Address match 1 (10-bit)."] - _100, - #[doc = "Address match 0 (10-bit) or Address match 1 (7-bit)."] - _101, - #[doc = "From Address match 0 (7-bit) to Address match 1 (7-bit)."] - _110, - #[doc = "From Address match 0 (10-bit) to Address match 1 (10-bit)."] - _111, + #[doc = "Address match 0 (7-bit)."] _000, + #[doc = "Address match 0 (10-bit)."] _001, + #[doc = "Address match 0 (7-bit) or Address match 1 (7-bit)."] _010, + #[doc = "Address match 0 (10-bit) or Address match 1 (10-bit)."] _011, + #[doc = "Address match 0 (7-bit) or Address match 1 (10-bit)."] _100, + #[doc = "Address match 0 (10-bit) or Address match 1 (7-bit)."] _101, + #[doc = "From Address match 0 (7-bit) to Address match 1 (7-bit)."] _110, + #[doc = "From Address match 0 (10-bit) to Address match 1 (10-bit)."] _111, } impl ADDRCFGW { #[allow(missing_docs)] diff --git a/src/lpi2c0/scfgr2/mod.rs b/src/lpi2c0/scfgr2/mod.rs index 11a3618..2cf47a6 100644 --- a/src/lpi2c0/scfgr2/mod.rs +++ b/src/lpi2c0/scfgr2/mod.rs @@ -22,7 +22,9 @@ impl super::SCFGR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/scr/mod.rs b/src/lpi2c0/scr/mod.rs index 1de5554..bdea7ca 100644 --- a/src/lpi2c0/scr/mod.rs +++ b/src/lpi2c0/scr/mod.rs @@ -22,7 +22,9 @@ impl super::SCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SCR { #[doc = "Possible values of the field `SEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SENR { - #[doc = "Slave mode is disabled."] - _0, - #[doc = "Slave mode is enabled."] - _1, + #[doc = "Slave mode is disabled."] _0, + #[doc = "Slave mode is enabled."] _1, } impl SENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SENR { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Slave logic is not reset."] - _0, - #[doc = "Slave logic is reset."] - _1, + #[doc = "Slave logic is not reset."] _0, + #[doc = "Slave logic is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RSTR { #[doc = "Possible values of the field `FILTEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FILTENR { - #[doc = "Disable digital filter and output delay counter for slave mode."] - _0, - #[doc = "Enable digital filter and output delay counter for slave mode."] - _1, + #[doc = "Disable digital filter and output delay counter for slave mode."] _0, + #[doc = "Enable digital filter and output delay counter for slave mode."] _1, } impl FILTENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FILTENR { #[doc = "Possible values of the field `FILTDZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FILTDZR { - #[doc = "Filter remains enabled in Doze mode."] - _0, - #[doc = "Filter is disabled in Doze mode."] - _1, + #[doc = "Filter remains enabled in Doze mode."] _0, + #[doc = "Filter is disabled in Doze mode."] _1, } impl FILTDZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl FILTDZR { } #[doc = "Values that can be written to the field `SEN`"] pub enum SENW { - #[doc = "Slave mode is disabled."] - _0, - #[doc = "Slave mode is enabled."] - _1, + #[doc = "Slave mode is disabled."] _0, + #[doc = "Slave mode is enabled."] _1, } impl SENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _SENW<'a> { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Slave logic is not reset."] - _0, - #[doc = "Slave logic is reset."] - _1, + #[doc = "Slave logic is not reset."] _0, + #[doc = "Slave logic is reset."] _1, } impl RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> { } #[doc = "Values that can be written to the field `FILTEN`"] pub enum FILTENW { - #[doc = "Disable digital filter and output delay counter for slave mode."] - _0, - #[doc = "Enable digital filter and output delay counter for slave mode."] - _1, + #[doc = "Disable digital filter and output delay counter for slave mode."] _0, + #[doc = "Enable digital filter and output delay counter for slave mode."] _1, } impl FILTENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _FILTENW<'a> { } #[doc = "Values that can be written to the field `FILTDZ`"] pub enum FILTDZW { - #[doc = "Filter remains enabled in Doze mode."] - _0, - #[doc = "Filter is disabled in Doze mode."] - _1, + #[doc = "Filter remains enabled in Doze mode."] _0, + #[doc = "Filter is disabled in Doze mode."] _1, } impl FILTDZW { #[allow(missing_docs)] diff --git a/src/lpi2c0/sder/mod.rs b/src/lpi2c0/sder/mod.rs index 6a7e4c4..210c104 100644 --- a/src/lpi2c0/sder/mod.rs +++ b/src/lpi2c0/sder/mod.rs @@ -22,7 +22,9 @@ impl super::SDER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SDER { #[doc = "Possible values of the field `TDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDDER { #[doc = "Possible values of the field `RDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDDER { #[doc = "Possible values of the field `AVDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl AVDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl AVDER { } #[doc = "Values that can be written to the field `TDDE`"] pub enum TDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDEW { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _TDDEW<'a> { } #[doc = "Values that can be written to the field `RDDE`"] pub enum RDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDEW { #[allow(missing_docs)] @@ -299,10 +291,8 @@ impl<'a> _RDDEW<'a> { } #[doc = "Values that can be written to the field `AVDE`"] pub enum AVDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl AVDEW { #[allow(missing_docs)] diff --git a/src/lpi2c0/sier/mod.rs b/src/lpi2c0/sier/mod.rs index c28231a..4f95baf 100644 --- a/src/lpi2c0/sier/mod.rs +++ b/src/lpi2c0/sier/mod.rs @@ -22,7 +22,9 @@ impl super::SIER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SIER { #[doc = "Possible values of the field `TDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDIER { #[doc = "Possible values of the field `RDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDIER { #[doc = "Possible values of the field `AVIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl AVIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl AVIER { #[doc = "Possible values of the field `TAIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TAIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TAIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TAIER { #[doc = "Possible values of the field `RSIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RSIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl RSIER { #[doc = "Possible values of the field `SDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SDIER { #[doc = "Possible values of the field `BEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BEIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl BEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl BEIER { #[doc = "Possible values of the field `FEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl FEIER { #[doc = "Possible values of the field `AM0IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AM0IER { - #[doc = "Interrupt enabled."] - _0, - #[doc = "Interrupt disabled."] - _1, + #[doc = "Interrupt enabled."] _0, + #[doc = "Interrupt disabled."] _1, } impl AM0IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl AM0IER { #[doc = "Possible values of the field `AM1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AM1FR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl AM1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl AM1FR { #[doc = "Possible values of the field `GCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl GCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl GCIER { #[doc = "Possible values of the field `SARIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SARIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SARIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -606,10 +584,8 @@ impl SARIER { } #[doc = "Values that can be written to the field `TDIE`"] pub enum TDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIEW { #[allow(missing_docs)] @@ -664,10 +640,8 @@ impl<'a> _TDIEW<'a> { } #[doc = "Values that can be written to the field `RDIE`"] pub enum RDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIEW { #[allow(missing_docs)] @@ -722,10 +696,8 @@ impl<'a> _RDIEW<'a> { } #[doc = "Values that can be written to the field `AVIE`"] pub enum AVIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl AVIEW { #[allow(missing_docs)] @@ -780,10 +752,8 @@ impl<'a> _AVIEW<'a> { } #[doc = "Values that can be written to the field `TAIE`"] pub enum TAIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TAIEW { #[allow(missing_docs)] @@ -838,10 +808,8 @@ impl<'a> _TAIEW<'a> { } #[doc = "Values that can be written to the field `RSIE`"] pub enum RSIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RSIEW { #[allow(missing_docs)] @@ -896,10 +864,8 @@ impl<'a> _RSIEW<'a> { } #[doc = "Values that can be written to the field `SDIE`"] pub enum SDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SDIEW { #[allow(missing_docs)] @@ -954,10 +920,8 @@ impl<'a> _SDIEW<'a> { } #[doc = "Values that can be written to the field `BEIE`"] pub enum BEIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl BEIEW { #[allow(missing_docs)] @@ -1012,10 +976,8 @@ impl<'a> _BEIEW<'a> { } #[doc = "Values that can be written to the field `FEIE`"] pub enum FEIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FEIEW { #[allow(missing_docs)] @@ -1070,10 +1032,8 @@ impl<'a> _FEIEW<'a> { } #[doc = "Values that can be written to the field `AM0IE`"] pub enum AM0IEW { - #[doc = "Interrupt enabled."] - _0, - #[doc = "Interrupt disabled."] - _1, + #[doc = "Interrupt enabled."] _0, + #[doc = "Interrupt disabled."] _1, } impl AM0IEW { #[allow(missing_docs)] @@ -1128,10 +1088,8 @@ impl<'a> _AM0IEW<'a> { } #[doc = "Values that can be written to the field `AM1F`"] pub enum AM1FW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl AM1FW { #[allow(missing_docs)] @@ -1186,10 +1144,8 @@ impl<'a> _AM1FW<'a> { } #[doc = "Values that can be written to the field `GCIE`"] pub enum GCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl GCIEW { #[allow(missing_docs)] @@ -1244,10 +1200,8 @@ impl<'a> _GCIEW<'a> { } #[doc = "Values that can be written to the field `SARIE`"] pub enum SARIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SARIEW { #[allow(missing_docs)] diff --git a/src/lpi2c0/srdr/mod.rs b/src/lpi2c0/srdr/mod.rs index 40bc379..7b54728 100644 --- a/src/lpi2c0/srdr/mod.rs +++ b/src/lpi2c0/srdr/mod.rs @@ -6,7 +6,9 @@ impl super::SRDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,10 +25,8 @@ impl DATAR { #[doc = "Possible values of the field `RXEMPTY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTYR { - #[doc = "The Receive Data Register is not empty."] - _0, - #[doc = "The Receive Data Register is empty."] - _1, + #[doc = "The Receive Data Register is not empty."] _0, + #[doc = "The Receive Data Register is empty."] _1, } impl RXEMPTYR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -72,8 +72,7 @@ impl RXEMPTYR { pub enum SOFR { #[doc = "Indicates this is not the first data word since a (repeated) START or STOP condition."] _0, - #[doc = "Indicates this is the first data word since a (repeated) START or STOP condition."] - _1, + #[doc = "Indicates this is the first data word since a (repeated) START or STOP condition."] _1, } impl SOFR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpi2c0/ssr/mod.rs b/src/lpi2c0/ssr/mod.rs index 7a4ba84..46fcbed 100644 --- a/src/lpi2c0/ssr/mod.rs +++ b/src/lpi2c0/ssr/mod.rs @@ -22,7 +22,9 @@ impl super::SSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SSR { #[doc = "Possible values of the field `TDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDFR { - #[doc = "Transmit data not requested."] - _0, - #[doc = "Transmit data is requested."] - _1, + #[doc = "Transmit data not requested."] _0, + #[doc = "Transmit data is requested."] _1, } impl TDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDFR { #[doc = "Possible values of the field `RDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDFR { - #[doc = "Receive Data is not ready."] - _0, - #[doc = "Receive data is ready."] - _1, + #[doc = "Receive Data is not ready."] _0, + #[doc = "Receive data is ready."] _1, } impl RDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDFR { #[doc = "Possible values of the field `AVF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVFR { - #[doc = "Address Status Register is not valid."] - _0, - #[doc = "Address Status Register is valid."] - _1, + #[doc = "Address Status Register is not valid."] _0, + #[doc = "Address Status Register is valid."] _1, } impl AVFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl AVFR { #[doc = "Possible values of the field `TAF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TAFR { - #[doc = "Transmit ACK/NACK is not required."] - _0, - #[doc = "Transmit ACK/NACK is required."] - _1, + #[doc = "Transmit ACK/NACK is not required."] _0, + #[doc = "Transmit ACK/NACK is required."] _1, } impl TAFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl TAFR { #[doc = "Possible values of the field `RSF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSFR { - #[doc = "Slave has not detected a Repeated START condition."] - _0, - #[doc = "Slave has detected a Repeated START condition."] - _1, + #[doc = "Slave has not detected a Repeated START condition."] _0, + #[doc = "Slave has detected a Repeated START condition."] _1, } impl RSFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl RSFR { #[doc = "Possible values of the field `SDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SDFR { - #[doc = "Slave has not detected a STOP condition."] - _0, - #[doc = "Slave has detected a STOP condition."] - _1, + #[doc = "Slave has not detected a STOP condition."] _0, + #[doc = "Slave has detected a STOP condition."] _1, } impl SDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SDFR { #[doc = "Possible values of the field `BEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BEFR { - #[doc = "Slave has not detected a bit error."] - _0, - #[doc = "Slave has detected a bit error."] - _1, + #[doc = "Slave has not detected a bit error."] _0, + #[doc = "Slave has detected a bit error."] _1, } impl BEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl BEFR { #[doc = "Possible values of the field `FEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEFR { - #[doc = "FIFO underflow or overflow not detected."] - _0, - #[doc = "FIFO underflow or overflow detected."] - _1, + #[doc = "FIFO underflow or overflow not detected."] _0, + #[doc = "FIFO underflow or overflow detected."] _1, } impl FEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl FEFR { #[doc = "Possible values of the field `AM0F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AM0FR { - #[doc = "Have not received ADDR0 matching address."] - _0, - #[doc = "Have received ADDR0 matching address."] - _1, + #[doc = "Have not received ADDR0 matching address."] _0, + #[doc = "Have received ADDR0 matching address."] _1, } impl AM0FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl AM0FR { #[doc = "Possible values of the field `AM1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AM1FR { - #[doc = "Have not received ADDR1 or ADDR0/ADDR1 range matching address."] - _0, - #[doc = "Have received ADDR1 or ADDR0/ADDR1 range matching address."] - _1, + #[doc = "Have not received ADDR1 or ADDR0/ADDR1 range matching address."] _0, + #[doc = "Have received ADDR1 or ADDR0/ADDR1 range matching address."] _1, } impl AM1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl AM1FR { #[doc = "Possible values of the field `GCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GCFR { - #[doc = "Slave has not detected the General Call Address or General Call Address disabled."] - _0, - #[doc = "Slave has detected the General Call Address."] - _1, + #[doc = "Slave has not detected the General Call Address or General Call Address disabled."] _0, + #[doc = "Slave has detected the General Call Address."] _1, } impl GCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl GCFR { #[doc = "Possible values of the field `SARF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SARFR { - #[doc = "SMBus Alert Response disabled or not detected."] - _0, - #[doc = "SMBus Alert Response enabled and detected."] - _1, + #[doc = "SMBus Alert Response disabled or not detected."] _0, + #[doc = "SMBus Alert Response enabled and detected."] _1, } impl SARFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -607,10 +585,8 @@ impl SARFR { #[doc = "Possible values of the field `SBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBFR { - #[doc = "I2C Slave is idle."] - _0, - #[doc = "I2C Slave is busy."] - _1, + #[doc = "I2C Slave is idle."] _0, + #[doc = "I2C Slave is busy."] _1, } impl SBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -654,10 +630,8 @@ impl SBFR { #[doc = "Possible values of the field `BBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBFR { - #[doc = "I2C Bus is idle."] - _0, - #[doc = "I2C Bus is busy."] - _1, + #[doc = "I2C Bus is idle."] _0, + #[doc = "I2C Bus is busy."] _1, } impl BBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -700,10 +674,8 @@ impl BBFR { } #[doc = "Values that can be written to the field `RSF`"] pub enum RSFW { - #[doc = "Slave has not detected a Repeated START condition."] - _0, - #[doc = "Slave has detected a Repeated START condition."] - _1, + #[doc = "Slave has not detected a Repeated START condition."] _0, + #[doc = "Slave has detected a Repeated START condition."] _1, } impl RSFW { #[allow(missing_docs)] @@ -758,10 +730,8 @@ impl<'a> _RSFW<'a> { } #[doc = "Values that can be written to the field `SDF`"] pub enum SDFW { - #[doc = "Slave has not detected a STOP condition."] - _0, - #[doc = "Slave has detected a STOP condition."] - _1, + #[doc = "Slave has not detected a STOP condition."] _0, + #[doc = "Slave has detected a STOP condition."] _1, } impl SDFW { #[allow(missing_docs)] @@ -816,10 +786,8 @@ impl<'a> _SDFW<'a> { } #[doc = "Values that can be written to the field `BEF`"] pub enum BEFW { - #[doc = "Slave has not detected a bit error."] - _0, - #[doc = "Slave has detected a bit error."] - _1, + #[doc = "Slave has not detected a bit error."] _0, + #[doc = "Slave has detected a bit error."] _1, } impl BEFW { #[allow(missing_docs)] @@ -874,10 +842,8 @@ impl<'a> _BEFW<'a> { } #[doc = "Values that can be written to the field `FEF`"] pub enum FEFW { - #[doc = "FIFO underflow or overflow not detected."] - _0, - #[doc = "FIFO underflow or overflow detected."] - _1, + #[doc = "FIFO underflow or overflow not detected."] _0, + #[doc = "FIFO underflow or overflow detected."] _1, } impl FEFW { #[allow(missing_docs)] diff --git a/src/lpi2c0/star/mod.rs b/src/lpi2c0/star/mod.rs index 3f7b3d0..cedf395 100644 --- a/src/lpi2c0/star/mod.rs +++ b/src/lpi2c0/star/mod.rs @@ -22,7 +22,9 @@ impl super::STAR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::STAR { #[doc = "Possible values of the field `TXNACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXNACKR { - #[doc = "Transmit ACK for received word."] - _0, - #[doc = "Transmit NACK for received word."] - _1, + #[doc = "Transmit ACK for received word."] _0, + #[doc = "Transmit NACK for received word."] _1, } impl TXNACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl TXNACKR { } #[doc = "Values that can be written to the field `TXNACK`"] pub enum TXNACKW { - #[doc = "Transmit ACK for received word."] - _0, - #[doc = "Transmit NACK for received word."] - _1, + #[doc = "Transmit ACK for received word."] _0, + #[doc = "Transmit NACK for received word."] _1, } impl TXNACKW { #[allow(missing_docs)] diff --git a/src/lpi2c0/stdr/mod.rs b/src/lpi2c0/stdr/mod.rs index 115cb96..3b4e6c6 100644 --- a/src/lpi2c0/stdr/mod.rs +++ b/src/lpi2c0/stdr/mod.rs @@ -22,7 +22,9 @@ impl super::STDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpi2c0/verid/mod.rs b/src/lpi2c0/verid/mod.rs index 5d37294..035947b 100644 --- a/src/lpi2c0/verid/mod.rs +++ b/src/lpi2c0/verid/mod.rs @@ -6,18 +6,17 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Master only with standard feature set."] - _0000000000000010, - #[doc = "Master and slave with standard feature set."] - _0000000000000011, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Master only with standard feature set."] _0000000000000010, + #[doc = "Master and slave with standard feature set."] _0000000000000011, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpit0/clrten/mod.rs b/src/lpit0/clrten/mod.rs index a8131de..85a0c6d 100644 --- a/src/lpit0/clrten/mod.rs +++ b/src/lpit0/clrten/mod.rs @@ -22,7 +22,9 @@ impl super::CLRTEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -42,10 +44,8 @@ impl super::CLRTEN { } #[doc = "Values that can be written to the field `CLR_T_EN_0`"] pub enum CLR_T_EN_0W { - #[doc = "No action"] - _0, - #[doc = "Clear T_EN bit for Timer Channel 0"] - _1, + #[doc = "No action"] _0, + #[doc = "Clear T_EN bit for Timer Channel 0"] _1, } impl CLR_T_EN_0W { #[allow(missing_docs)] @@ -100,10 +100,8 @@ impl<'a> _CLR_T_EN_0W<'a> { } #[doc = "Values that can be written to the field `CLR_T_EN_1`"] pub enum CLR_T_EN_1W { - #[doc = "No Action"] - _0, - #[doc = "Clear T_EN bit for Timer Channel 1"] - _1, + #[doc = "No Action"] _0, + #[doc = "Clear T_EN bit for Timer Channel 1"] _1, } impl CLR_T_EN_1W { #[allow(missing_docs)] @@ -158,10 +156,8 @@ impl<'a> _CLR_T_EN_1W<'a> { } #[doc = "Values that can be written to the field `CLR_T_EN_2`"] pub enum CLR_T_EN_2W { - #[doc = "No Action"] - _0, - #[doc = "Clear T_EN bit for Timer Channel 2"] - _1, + #[doc = "No Action"] _0, + #[doc = "Clear T_EN bit for Timer Channel 2"] _1, } impl CLR_T_EN_2W { #[allow(missing_docs)] @@ -216,10 +212,8 @@ impl<'a> _CLR_T_EN_2W<'a> { } #[doc = "Values that can be written to the field `CLR_T_EN_3`"] pub enum CLR_T_EN_3W { - #[doc = "No Action"] - _0, - #[doc = "Clear T_EN bit for Timer Channel 3"] - _1, + #[doc = "No Action"] _0, + #[doc = "Clear T_EN bit for Timer Channel 3"] _1, } impl CLR_T_EN_3W { #[allow(missing_docs)] diff --git a/src/lpit0/cval0/mod.rs b/src/lpit0/cval0/mod.rs index b665495..9cbcd0d 100644 --- a/src/lpit0/cval0/mod.rs +++ b/src/lpit0/cval0/mod.rs @@ -6,7 +6,9 @@ impl super::CVAL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpit0/cval1/mod.rs b/src/lpit0/cval1/mod.rs index f44760f..8301d86 100644 --- a/src/lpit0/cval1/mod.rs +++ b/src/lpit0/cval1/mod.rs @@ -6,7 +6,9 @@ impl super::CVAL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpit0/cval2/mod.rs b/src/lpit0/cval2/mod.rs index 523cdb0..5925aff 100644 --- a/src/lpit0/cval2/mod.rs +++ b/src/lpit0/cval2/mod.rs @@ -6,7 +6,9 @@ impl super::CVAL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpit0/cval3/mod.rs b/src/lpit0/cval3/mod.rs index c3174d8..b91a259 100644 --- a/src/lpit0/cval3/mod.rs +++ b/src/lpit0/cval3/mod.rs @@ -6,7 +6,9 @@ impl super::CVAL3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpit0/mcr/mod.rs b/src/lpit0/mcr/mod.rs index efa56d4..b602ebe 100644 --- a/src/lpit0/mcr/mod.rs +++ b/src/lpit0/mcr/mod.rs @@ -22,7 +22,9 @@ impl super::MCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MCR { #[doc = "Possible values of the field `M_CEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M_CENR { - #[doc = "Peripheral clock to timers is disabled"] - _0, - #[doc = "Peripheral clock to timers is enabled"] - _1, + #[doc = "Peripheral clock to timers is disabled"] _0, + #[doc = "Peripheral clock to timers is enabled"] _1, } impl M_CENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl M_CENR { #[doc = "Possible values of the field `SW_RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SW_RSTR { - #[doc = "Timer channels and registers are not reset"] - _0, - #[doc = "Timer channels and registers are reset"] - _1, + #[doc = "Timer channels and registers are not reset"] _0, + #[doc = "Timer channels and registers are reset"] _1, } impl SW_RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SW_RSTR { #[doc = "Possible values of the field `DOZE_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZE_ENR { - #[doc = "Timer channels are stopped in DOZE mode"] - _0, - #[doc = "Timer channels continue to run in DOZE mode"] - _1, + #[doc = "Timer channels are stopped in DOZE mode"] _0, + #[doc = "Timer channels continue to run in DOZE mode"] _1, } impl DOZE_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl DOZE_ENR { #[doc = "Possible values of the field `DBG_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBG_ENR { - #[doc = "Timer channels are stopped in Debug mode"] - _0, - #[doc = "Timer channels continue to run in Debug mode"] - _1, + #[doc = "Timer channels are stopped in Debug mode"] _0, + #[doc = "Timer channels continue to run in Debug mode"] _1, } impl DBG_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl DBG_ENR { } #[doc = "Values that can be written to the field `M_CEN`"] pub enum M_CENW { - #[doc = "Peripheral clock to timers is disabled"] - _0, - #[doc = "Peripheral clock to timers is enabled"] - _1, + #[doc = "Peripheral clock to timers is disabled"] _0, + #[doc = "Peripheral clock to timers is enabled"] _1, } impl M_CENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _M_CENW<'a> { } #[doc = "Values that can be written to the field `SW_RST`"] pub enum SW_RSTW { - #[doc = "Timer channels and registers are not reset"] - _0, - #[doc = "Timer channels and registers are reset"] - _1, + #[doc = "Timer channels and registers are not reset"] _0, + #[doc = "Timer channels and registers are reset"] _1, } impl SW_RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _SW_RSTW<'a> { } #[doc = "Values that can be written to the field `DOZE_EN`"] pub enum DOZE_ENW { - #[doc = "Timer channels are stopped in DOZE mode"] - _0, - #[doc = "Timer channels continue to run in DOZE mode"] - _1, + #[doc = "Timer channels are stopped in DOZE mode"] _0, + #[doc = "Timer channels continue to run in DOZE mode"] _1, } impl DOZE_ENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _DOZE_ENW<'a> { } #[doc = "Values that can be written to the field `DBG_EN`"] pub enum DBG_ENW { - #[doc = "Timer channels are stopped in Debug mode"] - _0, - #[doc = "Timer channels continue to run in Debug mode"] - _1, + #[doc = "Timer channels are stopped in Debug mode"] _0, + #[doc = "Timer channels continue to run in Debug mode"] _1, } impl DBG_ENW { #[allow(missing_docs)] diff --git a/src/lpit0/mier/mod.rs b/src/lpit0/mier/mod.rs index 60cb875..5cdde4c 100644 --- a/src/lpit0/mier/mod.rs +++ b/src/lpit0/mier/mod.rs @@ -22,7 +22,9 @@ impl super::MIER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MIER { #[doc = "Possible values of the field `TIE0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIE0R { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TIE0R { #[doc = "Possible values of the field `TIE1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIE1R { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl TIE1R { #[doc = "Possible values of the field `TIE2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIE2R { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl TIE2R { #[doc = "Possible values of the field `TIE3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIE3R { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl TIE3R { } #[doc = "Values that can be written to the field `TIE0`"] pub enum TIE0W { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE0W { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _TIE0W<'a> { } #[doc = "Values that can be written to the field `TIE1`"] pub enum TIE1W { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE1W { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _TIE1W<'a> { } #[doc = "Values that can be written to the field `TIE2`"] pub enum TIE2W { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE2W { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _TIE2W<'a> { } #[doc = "Values that can be written to the field `TIE3`"] pub enum TIE3W { - #[doc = "Interrupt generation is disabled"] - _0, - #[doc = "Interrupt generation is enabled"] - _1, + #[doc = "Interrupt generation is disabled"] _0, + #[doc = "Interrupt generation is enabled"] _1, } impl TIE3W { #[allow(missing_docs)] diff --git a/src/lpit0/mod.rs b/src/lpit0/mod.rs index 1304311..9f52d1e 100644 --- a/src/lpit0/mod.rs +++ b/src/lpit0/mod.rs @@ -2,48 +2,29 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - Module Control Register"] - pub mcr: MCR, - #[doc = "0x0c - Module Status Register"] - pub msr: MSR, - #[doc = "0x10 - Module Interrupt Enable Register"] - pub mier: MIER, - #[doc = "0x14 - Set Timer Enable Register"] - pub setten: SETTEN, - #[doc = "0x18 - Clear Timer Enable Register"] - pub clrten: CLRTEN, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - Module Control Register"] pub mcr: MCR, + #[doc = "0x0c - Module Status Register"] pub msr: MSR, + #[doc = "0x10 - Module Interrupt Enable Register"] pub mier: MIER, + #[doc = "0x14 - Set Timer Enable Register"] pub setten: SETTEN, + #[doc = "0x18 - Clear Timer Enable Register"] pub clrten: CLRTEN, _reserved0: [u8; 4usize], - #[doc = "0x20 - Timer Value Register"] - pub tval0: TVAL0, - #[doc = "0x24 - Current Timer Value"] - pub cval0: CVAL0, - #[doc = "0x28 - Timer Control Register"] - pub tctrl0: TCTRL0, + #[doc = "0x20 - Timer Value Register"] pub tval0: TVAL0, + #[doc = "0x24 - Current Timer Value"] pub cval0: CVAL0, + #[doc = "0x28 - Timer Control Register"] pub tctrl0: TCTRL0, _reserved1: [u8; 4usize], - #[doc = "0x30 - Timer Value Register"] - pub tval1: TVAL1, - #[doc = "0x34 - Current Timer Value"] - pub cval1: CVAL1, - #[doc = "0x38 - Timer Control Register"] - pub tctrl1: TCTRL1, + #[doc = "0x30 - Timer Value Register"] pub tval1: TVAL1, + #[doc = "0x34 - Current Timer Value"] pub cval1: CVAL1, + #[doc = "0x38 - Timer Control Register"] pub tctrl1: TCTRL1, _reserved2: [u8; 4usize], - #[doc = "0x40 - Timer Value Register"] - pub tval2: TVAL2, - #[doc = "0x44 - Current Timer Value"] - pub cval2: CVAL2, - #[doc = "0x48 - Timer Control Register"] - pub tctrl2: TCTRL2, + #[doc = "0x40 - Timer Value Register"] pub tval2: TVAL2, + #[doc = "0x44 - Current Timer Value"] pub cval2: CVAL2, + #[doc = "0x48 - Timer Control Register"] pub tctrl2: TCTRL2, _reserved3: [u8; 4usize], - #[doc = "0x50 - Timer Value Register"] - pub tval3: TVAL3, - #[doc = "0x54 - Current Timer Value"] - pub cval3: CVAL3, - #[doc = "0x58 - Timer Control Register"] - pub tctrl3: TCTRL3, + #[doc = "0x50 - Timer Value Register"] pub tval3: TVAL3, + #[doc = "0x54 - Current Timer Value"] pub cval3: CVAL3, + #[doc = "0x58 - Timer Control Register"] pub tctrl3: TCTRL3, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpit0/msr/mod.rs b/src/lpit0/msr/mod.rs index 9eb15bd..a2844dc 100644 --- a/src/lpit0/msr/mod.rs +++ b/src/lpit0/msr/mod.rs @@ -22,7 +22,9 @@ impl super::MSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::MSR { #[doc = "Possible values of the field `TIF0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIF0R { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TIF0R { #[doc = "Possible values of the field `TIF1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIF1R { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl TIF1R { #[doc = "Possible values of the field `TIF2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIF2R { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl TIF2R { #[doc = "Possible values of the field `TIF3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIF3R { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl TIF3R { } #[doc = "Values that can be written to the field `TIF0`"] pub enum TIF0W { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF0W { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _TIF0W<'a> { } #[doc = "Values that can be written to the field `TIF1`"] pub enum TIF1W { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF1W { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _TIF1W<'a> { } #[doc = "Values that can be written to the field `TIF2`"] pub enum TIF2W { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF2W { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _TIF2W<'a> { } #[doc = "Values that can be written to the field `TIF3`"] pub enum TIF3W { - #[doc = "Timer has not timed out"] - _0, - #[doc = "Timeout has occurred"] - _1, + #[doc = "Timer has not timed out"] _0, + #[doc = "Timeout has occurred"] _1, } impl TIF3W { #[allow(missing_docs)] diff --git a/src/lpit0/param/mod.rs b/src/lpit0/param/mod.rs index 38b5859..e429d27 100644 --- a/src/lpit0/param/mod.rs +++ b/src/lpit0/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpit0/setten/mod.rs b/src/lpit0/setten/mod.rs index 2670b70..37ac867 100644 --- a/src/lpit0/setten/mod.rs +++ b/src/lpit0/setten/mod.rs @@ -22,7 +22,9 @@ impl super::SETTEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SETTEN { #[doc = "Possible values of the field `SET_T_EN_0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SET_T_EN_0R { - #[doc = "No effect"] - _0, - #[doc = "Enables the Timer Channel 0"] - _1, + #[doc = "No effect"] _0, + #[doc = "Enables the Timer Channel 0"] _1, } impl SET_T_EN_0R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SET_T_EN_0R { #[doc = "Possible values of the field `SET_T_EN_1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SET_T_EN_1R { - #[doc = "No Effect"] - _0, - #[doc = "Enables the Timer Channel 1"] - _1, + #[doc = "No Effect"] _0, + #[doc = "Enables the Timer Channel 1"] _1, } impl SET_T_EN_1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SET_T_EN_1R { #[doc = "Possible values of the field `SET_T_EN_2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SET_T_EN_2R { - #[doc = "No Effect"] - _0, - #[doc = "Enables the Timer Channel 2"] - _1, + #[doc = "No Effect"] _0, + #[doc = "Enables the Timer Channel 2"] _1, } impl SET_T_EN_2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SET_T_EN_2R { #[doc = "Possible values of the field `SET_T_EN_3`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SET_T_EN_3R { - #[doc = "No effect"] - _0, - #[doc = "Enables the Timer Channel 3"] - _1, + #[doc = "No effect"] _0, + #[doc = "Enables the Timer Channel 3"] _1, } impl SET_T_EN_3R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl SET_T_EN_3R { } #[doc = "Values that can be written to the field `SET_T_EN_0`"] pub enum SET_T_EN_0W { - #[doc = "No effect"] - _0, - #[doc = "Enables the Timer Channel 0"] - _1, + #[doc = "No effect"] _0, + #[doc = "Enables the Timer Channel 0"] _1, } impl SET_T_EN_0W { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _SET_T_EN_0W<'a> { } #[doc = "Values that can be written to the field `SET_T_EN_1`"] pub enum SET_T_EN_1W { - #[doc = "No Effect"] - _0, - #[doc = "Enables the Timer Channel 1"] - _1, + #[doc = "No Effect"] _0, + #[doc = "Enables the Timer Channel 1"] _1, } impl SET_T_EN_1W { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _SET_T_EN_1W<'a> { } #[doc = "Values that can be written to the field `SET_T_EN_2`"] pub enum SET_T_EN_2W { - #[doc = "No Effect"] - _0, - #[doc = "Enables the Timer Channel 2"] - _1, + #[doc = "No Effect"] _0, + #[doc = "Enables the Timer Channel 2"] _1, } impl SET_T_EN_2W { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _SET_T_EN_2W<'a> { } #[doc = "Values that can be written to the field `SET_T_EN_3`"] pub enum SET_T_EN_3W { - #[doc = "No effect"] - _0, - #[doc = "Enables the Timer Channel 3"] - _1, + #[doc = "No effect"] _0, + #[doc = "Enables the Timer Channel 3"] _1, } impl SET_T_EN_3W { #[allow(missing_docs)] diff --git a/src/lpit0/tctrl0/mod.rs b/src/lpit0/tctrl0/mod.rs index 3bac11a..644de26 100644 --- a/src/lpit0/tctrl0/mod.rs +++ b/src/lpit0/tctrl0/mod.rs @@ -22,7 +22,9 @@ impl super::TCTRL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCTRL0 { #[doc = "Possible values of the field `T_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum T_ENR { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl T_ENR { #[doc = "Possible values of the field `CHAIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHAINR { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl CHAINR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -195,8 +189,7 @@ impl MODER { pub enum TSOTR { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,8 +233,7 @@ impl TSOTR { #[doc = "Possible values of the field `TSOI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSOIR { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -287,10 +279,8 @@ impl TSOIR { #[doc = "Possible values of the field `TROT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TROTR { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,10 +324,8 @@ impl TROTR { #[doc = "Possible values of the field `TRG_SRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRG_SRCR { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -391,10 +379,8 @@ impl TRG_SELR { } #[doc = "Values that can be written to the field `T_EN`"] pub enum T_ENW { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENW { #[allow(missing_docs)] @@ -449,10 +435,8 @@ impl<'a> _T_ENW<'a> { } #[doc = "Values that can be written to the field `CHAIN`"] pub enum CHAINW { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINW { #[allow(missing_docs)] @@ -507,14 +491,10 @@ impl<'a> _CHAINW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODEW { #[allow(missing_docs)] @@ -575,8 +555,7 @@ impl<'a> _MODEW<'a> { pub enum TSOTW { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTW { #[allow(missing_docs)] @@ -631,8 +610,7 @@ impl<'a> _TSOTW<'a> { } #[doc = "Values that can be written to the field `TSOI`"] pub enum TSOIW { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -689,10 +667,8 @@ impl<'a> _TSOIW<'a> { } #[doc = "Values that can be written to the field `TROT`"] pub enum TROTW { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTW { #[allow(missing_docs)] @@ -747,10 +723,8 @@ impl<'a> _TROTW<'a> { } #[doc = "Values that can be written to the field `TRG_SRC`"] pub enum TRG_SRCW { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCW { #[allow(missing_docs)] diff --git a/src/lpit0/tctrl1/mod.rs b/src/lpit0/tctrl1/mod.rs index ec39f24..5dd98b9 100644 --- a/src/lpit0/tctrl1/mod.rs +++ b/src/lpit0/tctrl1/mod.rs @@ -22,7 +22,9 @@ impl super::TCTRL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCTRL1 { #[doc = "Possible values of the field `T_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum T_ENR { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl T_ENR { #[doc = "Possible values of the field `CHAIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHAINR { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl CHAINR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -195,8 +189,7 @@ impl MODER { pub enum TSOTR { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,8 +233,7 @@ impl TSOTR { #[doc = "Possible values of the field `TSOI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSOIR { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -287,10 +279,8 @@ impl TSOIR { #[doc = "Possible values of the field `TROT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TROTR { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,10 +324,8 @@ impl TROTR { #[doc = "Possible values of the field `TRG_SRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRG_SRCR { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -391,10 +379,8 @@ impl TRG_SELR { } #[doc = "Values that can be written to the field `T_EN`"] pub enum T_ENW { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENW { #[allow(missing_docs)] @@ -449,10 +435,8 @@ impl<'a> _T_ENW<'a> { } #[doc = "Values that can be written to the field `CHAIN`"] pub enum CHAINW { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINW { #[allow(missing_docs)] @@ -507,14 +491,10 @@ impl<'a> _CHAINW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODEW { #[allow(missing_docs)] @@ -575,8 +555,7 @@ impl<'a> _MODEW<'a> { pub enum TSOTW { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTW { #[allow(missing_docs)] @@ -631,8 +610,7 @@ impl<'a> _TSOTW<'a> { } #[doc = "Values that can be written to the field `TSOI`"] pub enum TSOIW { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -689,10 +667,8 @@ impl<'a> _TSOIW<'a> { } #[doc = "Values that can be written to the field `TROT`"] pub enum TROTW { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTW { #[allow(missing_docs)] @@ -747,10 +723,8 @@ impl<'a> _TROTW<'a> { } #[doc = "Values that can be written to the field `TRG_SRC`"] pub enum TRG_SRCW { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCW { #[allow(missing_docs)] diff --git a/src/lpit0/tctrl2/mod.rs b/src/lpit0/tctrl2/mod.rs index 9e247cd..8330723 100644 --- a/src/lpit0/tctrl2/mod.rs +++ b/src/lpit0/tctrl2/mod.rs @@ -22,7 +22,9 @@ impl super::TCTRL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCTRL2 { #[doc = "Possible values of the field `T_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum T_ENR { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl T_ENR { #[doc = "Possible values of the field `CHAIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHAINR { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl CHAINR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -195,8 +189,7 @@ impl MODER { pub enum TSOTR { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,8 +233,7 @@ impl TSOTR { #[doc = "Possible values of the field `TSOI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSOIR { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -287,10 +279,8 @@ impl TSOIR { #[doc = "Possible values of the field `TROT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TROTR { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,10 +324,8 @@ impl TROTR { #[doc = "Possible values of the field `TRG_SRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRG_SRCR { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -391,10 +379,8 @@ impl TRG_SELR { } #[doc = "Values that can be written to the field `T_EN`"] pub enum T_ENW { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENW { #[allow(missing_docs)] @@ -449,10 +435,8 @@ impl<'a> _T_ENW<'a> { } #[doc = "Values that can be written to the field `CHAIN`"] pub enum CHAINW { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINW { #[allow(missing_docs)] @@ -507,14 +491,10 @@ impl<'a> _CHAINW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODEW { #[allow(missing_docs)] @@ -575,8 +555,7 @@ impl<'a> _MODEW<'a> { pub enum TSOTW { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTW { #[allow(missing_docs)] @@ -631,8 +610,7 @@ impl<'a> _TSOTW<'a> { } #[doc = "Values that can be written to the field `TSOI`"] pub enum TSOIW { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -689,10 +667,8 @@ impl<'a> _TSOIW<'a> { } #[doc = "Values that can be written to the field `TROT`"] pub enum TROTW { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTW { #[allow(missing_docs)] @@ -747,10 +723,8 @@ impl<'a> _TROTW<'a> { } #[doc = "Values that can be written to the field `TRG_SRC`"] pub enum TRG_SRCW { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCW { #[allow(missing_docs)] diff --git a/src/lpit0/tctrl3/mod.rs b/src/lpit0/tctrl3/mod.rs index c5e5976..c112dec 100644 --- a/src/lpit0/tctrl3/mod.rs +++ b/src/lpit0/tctrl3/mod.rs @@ -22,7 +22,9 @@ impl super::TCTRL3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::TCTRL3 { #[doc = "Possible values of the field `T_EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum T_ENR { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl T_ENR { #[doc = "Possible values of the field `CHAIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CHAINR { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl CHAINR { #[doc = "Possible values of the field `MODE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODER { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODER { #[doc = r" Value of the field as raw bits"] @@ -195,8 +189,7 @@ impl MODER { pub enum TSOTR { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,8 +233,7 @@ impl TSOTR { #[doc = "Possible values of the field `TSOI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSOIR { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -287,10 +279,8 @@ impl TSOIR { #[doc = "Possible values of the field `TROT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TROTR { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,10 +324,8 @@ impl TROTR { #[doc = "Possible values of the field `TRG_SRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRG_SRCR { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -391,10 +379,8 @@ impl TRG_SELR { } #[doc = "Values that can be written to the field `T_EN`"] pub enum T_ENW { - #[doc = "Timer Channel is disabled"] - _0, - #[doc = "Timer Channel is enabled"] - _1, + #[doc = "Timer Channel is disabled"] _0, + #[doc = "Timer Channel is enabled"] _1, } impl T_ENW { #[allow(missing_docs)] @@ -449,10 +435,8 @@ impl<'a> _T_ENW<'a> { } #[doc = "Values that can be written to the field `CHAIN`"] pub enum CHAINW { - #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] - _0, - #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] - _1, + #[doc = "Channel Chaining is disabled. Channel Timer runs independently."] _0, + #[doc = "Channel Chaining is enabled. Timer decrements on previous channel's timeout"] _1, } impl CHAINW { #[allow(missing_docs)] @@ -507,14 +491,10 @@ impl<'a> _CHAINW<'a> { } #[doc = "Values that can be written to the field `MODE`"] pub enum MODEW { - #[doc = "32-bit Periodic Counter"] - _0, - #[doc = "Dual 16-bit Periodic Counter"] - _1, - #[doc = "32-bit Trigger Accumulator"] - _10, - #[doc = "32-bit Trigger Input Capture"] - _11, + #[doc = "32-bit Periodic Counter"] _0, + #[doc = "Dual 16-bit Periodic Counter"] _1, + #[doc = "32-bit Trigger Accumulator"] _10, + #[doc = "32-bit Trigger Input Capture"] _11, } impl MODEW { #[allow(missing_docs)] @@ -575,8 +555,7 @@ impl<'a> _MODEW<'a> { pub enum TSOTW { #[doc = "Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)"] _0, - #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] - _1, + #[doc = "Timer starts to decrement when rising edge on selected trigger is detected"] _1, } impl TSOTW { #[allow(missing_docs)] @@ -631,8 +610,7 @@ impl<'a> _TSOTW<'a> { } #[doc = "Values that can be written to the field `TSOI`"] pub enum TSOIW { - #[doc = "The channel timer does not stop after timeout."] - _0, + #[doc = "The channel timer does not stop after timeout."] _0, #[doc = "The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected."] _1, } @@ -689,10 +667,8 @@ impl<'a> _TSOIW<'a> { } #[doc = "Values that can be written to the field `TROT`"] pub enum TROTW { - #[doc = "Timer will not reload on selected trigger"] - _0, - #[doc = "Timer will reload on selected trigger"] - _1, + #[doc = "Timer will not reload on selected trigger"] _0, + #[doc = "Timer will reload on selected trigger"] _1, } impl TROTW { #[allow(missing_docs)] @@ -747,10 +723,8 @@ impl<'a> _TROTW<'a> { } #[doc = "Values that can be written to the field `TRG_SRC`"] pub enum TRG_SRCW { - #[doc = "Trigger source selected in external"] - _0, - #[doc = "Trigger source selected is the internal trigger"] - _1, + #[doc = "Trigger source selected in external"] _0, + #[doc = "Trigger source selected is the internal trigger"] _1, } impl TRG_SRCW { #[allow(missing_docs)] diff --git a/src/lpit0/tval0/mod.rs b/src/lpit0/tval0/mod.rs index 2f0eb7e..512e675 100644 --- a/src/lpit0/tval0/mod.rs +++ b/src/lpit0/tval0/mod.rs @@ -22,7 +22,9 @@ impl super::TVAL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::TVAL0 { #[doc = "Possible values of the field `TMR_VAL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMR_VALR { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, + #[doc = r" Reserved"] _Reserved(u32), } impl TMR_VALR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl TMR_VALR { } #[doc = "Values that can be written to the field `TMR_VAL`"] pub enum TMR_VALW { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, } impl TMR_VALW { #[allow(missing_docs)] diff --git a/src/lpit0/tval1/mod.rs b/src/lpit0/tval1/mod.rs index 828adfd..80e8a6a 100644 --- a/src/lpit0/tval1/mod.rs +++ b/src/lpit0/tval1/mod.rs @@ -22,7 +22,9 @@ impl super::TVAL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::TVAL1 { #[doc = "Possible values of the field `TMR_VAL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMR_VALR { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, + #[doc = r" Reserved"] _Reserved(u32), } impl TMR_VALR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl TMR_VALR { } #[doc = "Values that can be written to the field `TMR_VAL`"] pub enum TMR_VALW { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, } impl TMR_VALW { #[allow(missing_docs)] diff --git a/src/lpit0/tval2/mod.rs b/src/lpit0/tval2/mod.rs index 8b6f6f1..74074c1 100644 --- a/src/lpit0/tval2/mod.rs +++ b/src/lpit0/tval2/mod.rs @@ -22,7 +22,9 @@ impl super::TVAL2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::TVAL2 { #[doc = "Possible values of the field `TMR_VAL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMR_VALR { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, + #[doc = r" Reserved"] _Reserved(u32), } impl TMR_VALR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl TMR_VALR { } #[doc = "Values that can be written to the field `TMR_VAL`"] pub enum TMR_VALW { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, } impl TMR_VALW { #[allow(missing_docs)] diff --git a/src/lpit0/tval3/mod.rs b/src/lpit0/tval3/mod.rs index 80ee23a..6b8f678 100644 --- a/src/lpit0/tval3/mod.rs +++ b/src/lpit0/tval3/mod.rs @@ -22,7 +22,9 @@ impl super::TVAL3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::TVAL3 { #[doc = "Possible values of the field `TMR_VAL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMR_VALR { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, + #[doc = r" Reserved"] _Reserved(u32), } impl TMR_VALR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl TMR_VALR { } #[doc = "Values that can be written to the field `TMR_VAL`"] pub enum TMR_VALW { - #[doc = "Invalid load value in compare modes."] - _0, - #[doc = "Invalid load value in compare modes."] - _1, + #[doc = "Invalid load value in compare modes."] _0, + #[doc = "Invalid load value in compare modes."] _1, } impl TMR_VALW { #[allow(missing_docs)] diff --git a/src/lpit0/verid/mod.rs b/src/lpit0/verid/mod.rs index 648b16c..29eaaa8 100644 --- a/src/lpit0/verid/mod.rs +++ b/src/lpit0/verid/mod.rs @@ -6,7 +6,9 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi0/ccr/mod.rs b/src/lpspi0/ccr/mod.rs index 30c6ac2..0030b22 100644 --- a/src/lpspi0/ccr/mod.rs +++ b/src/lpspi0/ccr/mod.rs @@ -22,7 +22,9 @@ impl super::CCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi0/cfgr0/mod.rs b/src/lpspi0/cfgr0/mod.rs index 13f75e0..21988a3 100644 --- a/src/lpspi0/cfgr0/mod.rs +++ b/src/lpspi0/cfgr0/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR0 { #[doc = "Possible values of the field `HREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRENR { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl HRENR { #[doc = "Possible values of the field `HRPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRPOLR { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl HRPOLR { #[doc = "Possible values of the field `HRSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRSELR { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl HRSELR { #[doc = "Possible values of the field `CIRFIFO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CIRFIFOR { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CIRFIFOR { #[doc = "Possible values of the field `RDMO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMOR { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +269,8 @@ impl RDMOR { } #[doc = "Values that can be written to the field `HREN`"] pub enum HRENW { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENW { #[allow(missing_docs)] @@ -335,10 +325,8 @@ impl<'a> _HRENW<'a> { } #[doc = "Values that can be written to the field `HRPOL`"] pub enum HRPOLW { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLW { #[allow(missing_docs)] @@ -393,10 +381,8 @@ impl<'a> _HRPOLW<'a> { } #[doc = "Values that can be written to the field `HRSEL`"] pub enum HRSELW { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELW { #[allow(missing_docs)] @@ -451,10 +437,8 @@ impl<'a> _HRSELW<'a> { } #[doc = "Values that can be written to the field `CIRFIFO`"] pub enum CIRFIFOW { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOW { #[allow(missing_docs)] @@ -509,10 +493,8 @@ impl<'a> _CIRFIFOW<'a> { } #[doc = "Values that can be written to the field `RDMO`"] pub enum RDMOW { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOW { #[allow(missing_docs)] diff --git a/src/lpspi0/cfgr1/mod.rs b/src/lpspi0/cfgr1/mod.rs index 16779e3..f9becbf 100644 --- a/src/lpspi0/cfgr1/mod.rs +++ b/src/lpspi0/cfgr1/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR1 { #[doc = "Possible values of the field `MASTER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MASTERR { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MASTERR { #[doc = "Possible values of the field `SAMPLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SAMPLER { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SAMPLER { #[doc = "Possible values of the field `AUTOPCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AUTOPCSR { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,8 +180,7 @@ impl AUTOPCSR { #[doc = "Possible values of the field `NOSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOSTALLR { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -231,12 +226,9 @@ impl NOSTALLR { #[doc = "Possible values of the field `PCSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSPOLR { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, + #[doc = r" Reserved"] _Reserved(u8), } impl PCSPOLR { #[doc = r" Value of the field as raw bits"] @@ -272,8 +264,7 @@ impl PCSPOLR { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -286,8 +277,7 @@ pub enum MATCFGR { _110, #[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"] _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -358,14 +348,10 @@ impl MATCFGR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -414,10 +400,8 @@ impl PINCFGR { #[doc = "Possible values of the field `OUTCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OUTCFGR { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -461,10 +445,8 @@ impl OUTCFGR { #[doc = "Possible values of the field `PCSCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSCFGR { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -507,10 +489,8 @@ impl PCSCFGR { } #[doc = "Values that can be written to the field `MASTER`"] pub enum MASTERW { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERW { #[allow(missing_docs)] @@ -565,10 +545,8 @@ impl<'a> _MASTERW<'a> { } #[doc = "Values that can be written to the field `SAMPLE`"] pub enum SAMPLEW { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLEW { #[allow(missing_docs)] @@ -623,10 +601,8 @@ impl<'a> _SAMPLEW<'a> { } #[doc = "Values that can be written to the field `AUTOPCS`"] pub enum AUTOPCSW { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSW { #[allow(missing_docs)] @@ -681,8 +657,7 @@ impl<'a> _AUTOPCSW<'a> { } #[doc = "Values that can be written to the field `NOSTALL`"] pub enum NOSTALLW { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -739,10 +714,8 @@ impl<'a> _NOSTALLW<'a> { } #[doc = "Values that can be written to the field `PCSPOL`"] pub enum PCSPOLW { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, } impl PCSPOLW { #[allow(missing_docs)] @@ -787,8 +760,7 @@ impl<'a> _PCSPOLW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -875,14 +847,10 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -941,10 +909,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `OUTCFG`"] pub enum OUTCFGW { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGW { #[allow(missing_docs)] @@ -999,10 +965,8 @@ impl<'a> _OUTCFGW<'a> { } #[doc = "Values that can be written to the field `PCSCFG`"] pub enum PCSCFGW { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGW { #[allow(missing_docs)] diff --git a/src/lpspi0/cr/mod.rs b/src/lpspi0/cr/mod.rs index 8f168a0..9200050 100644 --- a/src/lpspi0/cr/mod.rs +++ b/src/lpspi0/cr/mod.rs @@ -22,7 +22,9 @@ impl super::CR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CR { #[doc = "Possible values of the field `MEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MENR { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MENR { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RSTR { #[doc = "Possible values of the field `DOZEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZENR { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl DOZENR { #[doc = "Possible values of the field `DBGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGENR { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl DBGENR { } #[doc = "Values that can be written to the field `MEN`"] pub enum MENW { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _MENW<'a> { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> { } #[doc = "Values that can be written to the field `DOZEN`"] pub enum DOZENW { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _DOZENW<'a> { } #[doc = "Values that can be written to the field `DBGEN`"] pub enum DBGENW { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENW { #[allow(missing_docs)] @@ -462,10 +448,8 @@ impl<'a> _DBGENW<'a> { } #[doc = "Values that can be written to the field `RTF`"] pub enum RTFW { - #[doc = "No effect."] - _0, - #[doc = "Transmit FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Transmit FIFO is reset."] _1, } impl RTFW { #[allow(missing_docs)] @@ -520,10 +504,8 @@ impl<'a> _RTFW<'a> { } #[doc = "Values that can be written to the field `RRF`"] pub enum RRFW { - #[doc = "No effect."] - _0, - #[doc = "Receive FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Receive FIFO is reset."] _1, } impl RRFW { #[allow(missing_docs)] diff --git a/src/lpspi0/der/mod.rs b/src/lpspi0/der/mod.rs index 0f3e2ee..de62513 100644 --- a/src/lpspi0/der/mod.rs +++ b/src/lpspi0/der/mod.rs @@ -22,7 +22,9 @@ impl super::DER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DER { #[doc = "Possible values of the field `TDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDDER { #[doc = "Possible values of the field `RDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl RDDER { } #[doc = "Values that can be written to the field `TDDE`"] pub enum TDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDEW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _TDDEW<'a> { } #[doc = "Values that can be written to the field `RDDE`"] pub enum RDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDEW { #[allow(missing_docs)] diff --git a/src/lpspi0/dmr0/mod.rs b/src/lpspi0/dmr0/mod.rs index 9507eb5..f0fcb82 100644 --- a/src/lpspi0/dmr0/mod.rs +++ b/src/lpspi0/dmr0/mod.rs @@ -22,7 +22,9 @@ impl super::DMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi0/dmr1/mod.rs b/src/lpspi0/dmr1/mod.rs index c568a1c..ff5a01b 100644 --- a/src/lpspi0/dmr1/mod.rs +++ b/src/lpspi0/dmr1/mod.rs @@ -22,7 +22,9 @@ impl super::DMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi0/fcr/mod.rs b/src/lpspi0/fcr/mod.rs index 04ca2a4..60cb2f7 100644 --- a/src/lpspi0/fcr/mod.rs +++ b/src/lpspi0/fcr/mod.rs @@ -22,7 +22,9 @@ impl super::FCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi0/fsr/mod.rs b/src/lpspi0/fsr/mod.rs index 1871a95..f37f6a7 100644 --- a/src/lpspi0/fsr/mod.rs +++ b/src/lpspi0/fsr/mod.rs @@ -6,7 +6,9 @@ impl super::FSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi0/ier/mod.rs b/src/lpspi0/ier/mod.rs index 477b75a..41259da 100644 --- a/src/lpspi0/ier/mod.rs +++ b/src/lpspi0/ier/mod.rs @@ -22,7 +22,9 @@ impl super::IER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::IER { #[doc = "Possible values of the field `TDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDIER { #[doc = "Possible values of the field `RDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDIER { #[doc = "Possible values of the field `WCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCIER { #[doc = "Possible values of the field `FCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCIER { #[doc = "Possible values of the field `TEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEIER { #[doc = "Possible values of the field `REIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REIER { #[doc = "Possible values of the field `DMIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl DMIER { } #[doc = "Values that can be written to the field `TDIE`"] pub enum TDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIEW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _TDIEW<'a> { } #[doc = "Values that can be written to the field `RDIE`"] pub enum RDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIEW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _RDIEW<'a> { } #[doc = "Values that can be written to the field `WCIE`"] pub enum WCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIEW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _WCIEW<'a> { } #[doc = "Values that can be written to the field `FCIE`"] pub enum FCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIEW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _FCIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TEIE`"] pub enum TEIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIEW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _TEIEW<'a> { } #[doc = "Values that can be written to the field `REIE`"] pub enum REIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIEW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _REIEW<'a> { } #[doc = "Values that can be written to the field `DMIE`"] pub enum DMIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIEW { #[allow(missing_docs)] diff --git a/src/lpspi0/mod.rs b/src/lpspi0/mod.rs index 65423c5..43f9181 100644 --- a/src/lpspi0/mod.rs +++ b/src/lpspi0/mod.rs @@ -2,45 +2,28 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, _reserved0: [u8; 8usize], - #[doc = "0x10 - Control Register"] - pub cr: CR, - #[doc = "0x14 - Status Register"] - pub sr: SR, - #[doc = "0x18 - Interrupt Enable Register"] - pub ier: IER, - #[doc = "0x1c - DMA Enable Register"] - pub der: DER, - #[doc = "0x20 - Configuration Register 0"] - pub cfgr0: CFGR0, - #[doc = "0x24 - Configuration Register 1"] - pub cfgr1: CFGR1, + #[doc = "0x10 - Control Register"] pub cr: CR, + #[doc = "0x14 - Status Register"] pub sr: SR, + #[doc = "0x18 - Interrupt Enable Register"] pub ier: IER, + #[doc = "0x1c - DMA Enable Register"] pub der: DER, + #[doc = "0x20 - Configuration Register 0"] pub cfgr0: CFGR0, + #[doc = "0x24 - Configuration Register 1"] pub cfgr1: CFGR1, _reserved1: [u8; 8usize], - #[doc = "0x30 - Data Match Register 0"] - pub dmr0: DMR0, - #[doc = "0x34 - Data Match Register 1"] - pub dmr1: DMR1, + #[doc = "0x30 - Data Match Register 0"] pub dmr0: DMR0, + #[doc = "0x34 - Data Match Register 1"] pub dmr1: DMR1, _reserved2: [u8; 8usize], - #[doc = "0x40 - Clock Configuration Register"] - pub ccr: CCR, + #[doc = "0x40 - Clock Configuration Register"] pub ccr: CCR, _reserved3: [u8; 20usize], - #[doc = "0x58 - FIFO Control Register"] - pub fcr: FCR, - #[doc = "0x5c - FIFO Status Register"] - pub fsr: FSR, - #[doc = "0x60 - Transmit Command Register"] - pub tcr: TCR, - #[doc = "0x64 - Transmit Data Register"] - pub tdr: TDR, + #[doc = "0x58 - FIFO Control Register"] pub fcr: FCR, + #[doc = "0x5c - FIFO Status Register"] pub fsr: FSR, + #[doc = "0x60 - Transmit Command Register"] pub tcr: TCR, + #[doc = "0x64 - Transmit Data Register"] pub tdr: TDR, _reserved4: [u8; 8usize], - #[doc = "0x70 - Receive Status Register"] - pub rsr: RSR, - #[doc = "0x74 - Receive Data Register"] - pub rdr: RDR, + #[doc = "0x70 - Receive Status Register"] pub rsr: RSR, + #[doc = "0x74 - Receive Data Register"] pub rdr: RDR, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpspi0/param/mod.rs b/src/lpspi0/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpspi0/param/mod.rs +++ b/src/lpspi0/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi0/rdr/mod.rs b/src/lpspi0/rdr/mod.rs index d6d2996..53ec30c 100644 --- a/src/lpspi0/rdr/mod.rs +++ b/src/lpspi0/rdr/mod.rs @@ -6,7 +6,9 @@ impl super::RDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi0/rsr/mod.rs b/src/lpspi0/rsr/mod.rs index dd10bf5..a6baff2 100644 --- a/src/lpspi0/rsr/mod.rs +++ b/src/lpspi0/rsr/mod.rs @@ -6,16 +6,16 @@ impl super::RSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `SOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFR { - #[doc = "Subsequent data word received after LPSPI_PCS assertion."] - _0, - #[doc = "First data word received after LPSPI_PCS assertion."] - _1, + #[doc = "Subsequent data word received after LPSPI_PCS assertion."] _0, + #[doc = "First data word received after LPSPI_PCS assertion."] _1, } impl SOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl SOFR { #[doc = "Possible values of the field `RXEMPTY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTYR { - #[doc = "RX FIFO is not empty."] - _0, - #[doc = "RX FIFO is empty."] - _1, + #[doc = "RX FIFO is not empty."] _0, + #[doc = "RX FIFO is empty."] _1, } impl RXEMPTYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpspi0/sr/mod.rs b/src/lpspi0/sr/mod.rs index e39af52..b914212 100644 --- a/src/lpspi0/sr/mod.rs +++ b/src/lpspi0/sr/mod.rs @@ -22,7 +22,9 @@ impl super::SR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SR { #[doc = "Possible values of the field `TDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDFR { - #[doc = "Transmit data not requested."] - _0, - #[doc = "Transmit data is requested."] - _1, + #[doc = "Transmit data not requested."] _0, + #[doc = "Transmit data is requested."] _1, } impl TDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDFR { #[doc = "Possible values of the field `RDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDFR { - #[doc = "Receive Data is not ready."] - _0, - #[doc = "Receive data is ready."] - _1, + #[doc = "Receive Data is not ready."] _0, + #[doc = "Receive data is ready."] _1, } impl RDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDFR { #[doc = "Possible values of the field `WCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCFR { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCFR { #[doc = "Possible values of the field `FCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCFR { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCFR { #[doc = "Possible values of the field `TCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCFR { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCFR { #[doc = "Possible values of the field `TEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEFR { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEFR { #[doc = "Possible values of the field `REF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REFR { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REFR { #[doc = "Possible values of the field `DMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMFR { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl DMFR { #[doc = "Possible values of the field `MBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBFR { - #[doc = "LPSPI is idle."] - _0, - #[doc = "LPSPI is busy."] - _1, + #[doc = "LPSPI is idle."] _0, + #[doc = "LPSPI is busy."] _1, } impl MBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl MBFR { } #[doc = "Values that can be written to the field `WCF`"] pub enum WCFW { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFW { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _WCFW<'a> { } #[doc = "Values that can be written to the field `FCF`"] pub enum FCFW { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFW { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _FCFW<'a> { } #[doc = "Values that can be written to the field `TCF`"] pub enum TCFW { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFW { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _TCFW<'a> { } #[doc = "Values that can be written to the field `TEF`"] pub enum TEFW { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFW { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TEFW<'a> { } #[doc = "Values that can be written to the field `REF`"] pub enum REFW { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFW { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _REFW<'a> { } #[doc = "Values that can be written to the field `DMF`"] pub enum DMFW { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFW { #[allow(missing_docs)] diff --git a/src/lpspi0/tcr/mod.rs b/src/lpspi0/tcr/mod.rs index f9149ea..d5fc386 100644 --- a/src/lpspi0/tcr/mod.rs +++ b/src/lpspi0/tcr/mod.rs @@ -22,7 +22,9 @@ impl super::TCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl FRAMESZR { #[doc = "Possible values of the field `WIDTH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WIDTHR { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl WIDTHR { #[doc = r" Value of the field as raw bits"] @@ -104,10 +102,8 @@ impl WIDTHR { #[doc = "Possible values of the field `TXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -151,10 +147,8 @@ impl TXMSKR { #[doc = "Possible values of the field `RXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -198,10 +192,8 @@ impl RXMSKR { #[doc = "Possible values of the field `CONTC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTCR { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -245,10 +237,8 @@ impl CONTCR { #[doc = "Possible values of the field `CONT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTR { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -292,10 +282,8 @@ impl CONTR { #[doc = "Possible values of the field `BYSW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BYSWR { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -339,10 +327,8 @@ impl BYSWR { #[doc = "Possible values of the field `LSBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LSBFR { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,14 +372,10 @@ impl LSBFR { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -442,22 +424,14 @@ impl PCSR { #[doc = "Possible values of the field `PRESCALE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALER { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALER { #[doc = r" Value of the field as raw bits"] @@ -534,10 +508,8 @@ impl PRESCALER { #[doc = "Possible values of the field `CPHA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPHAR { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -581,10 +553,8 @@ impl CPHAR { #[doc = "Possible values of the field `CPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOLR { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -642,12 +612,9 @@ impl<'a> _FRAMESZW<'a> { } #[doc = "Values that can be written to the field `WIDTH`"] pub enum WIDTHW { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, } impl WIDTHW { #[allow(missing_docs)] @@ -698,10 +665,8 @@ impl<'a> _WIDTHW<'a> { } #[doc = "Values that can be written to the field `TXMSK`"] pub enum TXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKW { #[allow(missing_docs)] @@ -756,10 +721,8 @@ impl<'a> _TXMSKW<'a> { } #[doc = "Values that can be written to the field `RXMSK`"] pub enum RXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKW { #[allow(missing_docs)] @@ -814,10 +777,8 @@ impl<'a> _RXMSKW<'a> { } #[doc = "Values that can be written to the field `CONTC`"] pub enum CONTCW { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCW { #[allow(missing_docs)] @@ -872,10 +833,8 @@ impl<'a> _CONTCW<'a> { } #[doc = "Values that can be written to the field `CONT`"] pub enum CONTW { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTW { #[allow(missing_docs)] @@ -930,10 +889,8 @@ impl<'a> _CONTW<'a> { } #[doc = "Values that can be written to the field `BYSW`"] pub enum BYSWW { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWW { #[allow(missing_docs)] @@ -988,10 +945,8 @@ impl<'a> _BYSWW<'a> { } #[doc = "Values that can be written to the field `LSBF`"] pub enum LSBFW { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFW { #[allow(missing_docs)] @@ -1046,14 +1001,10 @@ impl<'a> _LSBFW<'a> { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSW { #[allow(missing_docs)] @@ -1112,22 +1063,14 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `PRESCALE`"] pub enum PRESCALEW { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALEW { #[allow(missing_docs)] @@ -1210,10 +1153,8 @@ impl<'a> _PRESCALEW<'a> { } #[doc = "Values that can be written to the field `CPHA`"] pub enum CPHAW { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAW { #[allow(missing_docs)] @@ -1268,10 +1209,8 @@ impl<'a> _CPHAW<'a> { } #[doc = "Values that can be written to the field `CPOL`"] pub enum CPOLW { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLW { #[allow(missing_docs)] diff --git a/src/lpspi0/verid/mod.rs b/src/lpspi0/verid/mod.rs index 4f6e83c..1f0ac7a 100644 --- a/src/lpspi0/verid/mod.rs +++ b/src/lpspi0/verid/mod.rs @@ -6,16 +6,16 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set supporting 32-bit shift register."] - _0000000000000100, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set supporting 32-bit shift register."] _0000000000000100, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpspi1/ccr/mod.rs b/src/lpspi1/ccr/mod.rs index 30c6ac2..0030b22 100644 --- a/src/lpspi1/ccr/mod.rs +++ b/src/lpspi1/ccr/mod.rs @@ -22,7 +22,9 @@ impl super::CCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi1/cfgr0/mod.rs b/src/lpspi1/cfgr0/mod.rs index 13f75e0..21988a3 100644 --- a/src/lpspi1/cfgr0/mod.rs +++ b/src/lpspi1/cfgr0/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR0 { #[doc = "Possible values of the field `HREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRENR { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl HRENR { #[doc = "Possible values of the field `HRPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRPOLR { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl HRPOLR { #[doc = "Possible values of the field `HRSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRSELR { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl HRSELR { #[doc = "Possible values of the field `CIRFIFO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CIRFIFOR { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CIRFIFOR { #[doc = "Possible values of the field `RDMO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMOR { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +269,8 @@ impl RDMOR { } #[doc = "Values that can be written to the field `HREN`"] pub enum HRENW { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENW { #[allow(missing_docs)] @@ -335,10 +325,8 @@ impl<'a> _HRENW<'a> { } #[doc = "Values that can be written to the field `HRPOL`"] pub enum HRPOLW { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLW { #[allow(missing_docs)] @@ -393,10 +381,8 @@ impl<'a> _HRPOLW<'a> { } #[doc = "Values that can be written to the field `HRSEL`"] pub enum HRSELW { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELW { #[allow(missing_docs)] @@ -451,10 +437,8 @@ impl<'a> _HRSELW<'a> { } #[doc = "Values that can be written to the field `CIRFIFO`"] pub enum CIRFIFOW { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOW { #[allow(missing_docs)] @@ -509,10 +493,8 @@ impl<'a> _CIRFIFOW<'a> { } #[doc = "Values that can be written to the field `RDMO`"] pub enum RDMOW { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOW { #[allow(missing_docs)] diff --git a/src/lpspi1/cfgr1/mod.rs b/src/lpspi1/cfgr1/mod.rs index 16779e3..f9becbf 100644 --- a/src/lpspi1/cfgr1/mod.rs +++ b/src/lpspi1/cfgr1/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR1 { #[doc = "Possible values of the field `MASTER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MASTERR { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MASTERR { #[doc = "Possible values of the field `SAMPLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SAMPLER { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SAMPLER { #[doc = "Possible values of the field `AUTOPCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AUTOPCSR { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,8 +180,7 @@ impl AUTOPCSR { #[doc = "Possible values of the field `NOSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOSTALLR { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -231,12 +226,9 @@ impl NOSTALLR { #[doc = "Possible values of the field `PCSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSPOLR { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, + #[doc = r" Reserved"] _Reserved(u8), } impl PCSPOLR { #[doc = r" Value of the field as raw bits"] @@ -272,8 +264,7 @@ impl PCSPOLR { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -286,8 +277,7 @@ pub enum MATCFGR { _110, #[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"] _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -358,14 +348,10 @@ impl MATCFGR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -414,10 +400,8 @@ impl PINCFGR { #[doc = "Possible values of the field `OUTCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OUTCFGR { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -461,10 +445,8 @@ impl OUTCFGR { #[doc = "Possible values of the field `PCSCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSCFGR { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -507,10 +489,8 @@ impl PCSCFGR { } #[doc = "Values that can be written to the field `MASTER`"] pub enum MASTERW { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERW { #[allow(missing_docs)] @@ -565,10 +545,8 @@ impl<'a> _MASTERW<'a> { } #[doc = "Values that can be written to the field `SAMPLE`"] pub enum SAMPLEW { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLEW { #[allow(missing_docs)] @@ -623,10 +601,8 @@ impl<'a> _SAMPLEW<'a> { } #[doc = "Values that can be written to the field `AUTOPCS`"] pub enum AUTOPCSW { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSW { #[allow(missing_docs)] @@ -681,8 +657,7 @@ impl<'a> _AUTOPCSW<'a> { } #[doc = "Values that can be written to the field `NOSTALL`"] pub enum NOSTALLW { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -739,10 +714,8 @@ impl<'a> _NOSTALLW<'a> { } #[doc = "Values that can be written to the field `PCSPOL`"] pub enum PCSPOLW { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, } impl PCSPOLW { #[allow(missing_docs)] @@ -787,8 +760,7 @@ impl<'a> _PCSPOLW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -875,14 +847,10 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -941,10 +909,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `OUTCFG`"] pub enum OUTCFGW { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGW { #[allow(missing_docs)] @@ -999,10 +965,8 @@ impl<'a> _OUTCFGW<'a> { } #[doc = "Values that can be written to the field `PCSCFG`"] pub enum PCSCFGW { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGW { #[allow(missing_docs)] diff --git a/src/lpspi1/cr/mod.rs b/src/lpspi1/cr/mod.rs index 8f168a0..9200050 100644 --- a/src/lpspi1/cr/mod.rs +++ b/src/lpspi1/cr/mod.rs @@ -22,7 +22,9 @@ impl super::CR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CR { #[doc = "Possible values of the field `MEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MENR { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MENR { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RSTR { #[doc = "Possible values of the field `DOZEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZENR { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl DOZENR { #[doc = "Possible values of the field `DBGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGENR { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl DBGENR { } #[doc = "Values that can be written to the field `MEN`"] pub enum MENW { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _MENW<'a> { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> { } #[doc = "Values that can be written to the field `DOZEN`"] pub enum DOZENW { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _DOZENW<'a> { } #[doc = "Values that can be written to the field `DBGEN`"] pub enum DBGENW { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENW { #[allow(missing_docs)] @@ -462,10 +448,8 @@ impl<'a> _DBGENW<'a> { } #[doc = "Values that can be written to the field `RTF`"] pub enum RTFW { - #[doc = "No effect."] - _0, - #[doc = "Transmit FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Transmit FIFO is reset."] _1, } impl RTFW { #[allow(missing_docs)] @@ -520,10 +504,8 @@ impl<'a> _RTFW<'a> { } #[doc = "Values that can be written to the field `RRF`"] pub enum RRFW { - #[doc = "No effect."] - _0, - #[doc = "Receive FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Receive FIFO is reset."] _1, } impl RRFW { #[allow(missing_docs)] diff --git a/src/lpspi1/der/mod.rs b/src/lpspi1/der/mod.rs index 0f3e2ee..de62513 100644 --- a/src/lpspi1/der/mod.rs +++ b/src/lpspi1/der/mod.rs @@ -22,7 +22,9 @@ impl super::DER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DER { #[doc = "Possible values of the field `TDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDDER { #[doc = "Possible values of the field `RDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl RDDER { } #[doc = "Values that can be written to the field `TDDE`"] pub enum TDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDEW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _TDDEW<'a> { } #[doc = "Values that can be written to the field `RDDE`"] pub enum RDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDEW { #[allow(missing_docs)] diff --git a/src/lpspi1/dmr0/mod.rs b/src/lpspi1/dmr0/mod.rs index 9507eb5..f0fcb82 100644 --- a/src/lpspi1/dmr0/mod.rs +++ b/src/lpspi1/dmr0/mod.rs @@ -22,7 +22,9 @@ impl super::DMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi1/dmr1/mod.rs b/src/lpspi1/dmr1/mod.rs index c568a1c..ff5a01b 100644 --- a/src/lpspi1/dmr1/mod.rs +++ b/src/lpspi1/dmr1/mod.rs @@ -22,7 +22,9 @@ impl super::DMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi1/fcr/mod.rs b/src/lpspi1/fcr/mod.rs index 04ca2a4..60cb2f7 100644 --- a/src/lpspi1/fcr/mod.rs +++ b/src/lpspi1/fcr/mod.rs @@ -22,7 +22,9 @@ impl super::FCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi1/fsr/mod.rs b/src/lpspi1/fsr/mod.rs index 1871a95..f37f6a7 100644 --- a/src/lpspi1/fsr/mod.rs +++ b/src/lpspi1/fsr/mod.rs @@ -6,7 +6,9 @@ impl super::FSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi1/ier/mod.rs b/src/lpspi1/ier/mod.rs index 477b75a..41259da 100644 --- a/src/lpspi1/ier/mod.rs +++ b/src/lpspi1/ier/mod.rs @@ -22,7 +22,9 @@ impl super::IER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::IER { #[doc = "Possible values of the field `TDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDIER { #[doc = "Possible values of the field `RDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDIER { #[doc = "Possible values of the field `WCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCIER { #[doc = "Possible values of the field `FCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCIER { #[doc = "Possible values of the field `TEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEIER { #[doc = "Possible values of the field `REIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REIER { #[doc = "Possible values of the field `DMIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl DMIER { } #[doc = "Values that can be written to the field `TDIE`"] pub enum TDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIEW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _TDIEW<'a> { } #[doc = "Values that can be written to the field `RDIE`"] pub enum RDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIEW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _RDIEW<'a> { } #[doc = "Values that can be written to the field `WCIE`"] pub enum WCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIEW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _WCIEW<'a> { } #[doc = "Values that can be written to the field `FCIE`"] pub enum FCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIEW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _FCIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TEIE`"] pub enum TEIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIEW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _TEIEW<'a> { } #[doc = "Values that can be written to the field `REIE`"] pub enum REIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIEW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _REIEW<'a> { } #[doc = "Values that can be written to the field `DMIE`"] pub enum DMIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIEW { #[allow(missing_docs)] diff --git a/src/lpspi1/mod.rs b/src/lpspi1/mod.rs index 65423c5..43f9181 100644 --- a/src/lpspi1/mod.rs +++ b/src/lpspi1/mod.rs @@ -2,45 +2,28 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, _reserved0: [u8; 8usize], - #[doc = "0x10 - Control Register"] - pub cr: CR, - #[doc = "0x14 - Status Register"] - pub sr: SR, - #[doc = "0x18 - Interrupt Enable Register"] - pub ier: IER, - #[doc = "0x1c - DMA Enable Register"] - pub der: DER, - #[doc = "0x20 - Configuration Register 0"] - pub cfgr0: CFGR0, - #[doc = "0x24 - Configuration Register 1"] - pub cfgr1: CFGR1, + #[doc = "0x10 - Control Register"] pub cr: CR, + #[doc = "0x14 - Status Register"] pub sr: SR, + #[doc = "0x18 - Interrupt Enable Register"] pub ier: IER, + #[doc = "0x1c - DMA Enable Register"] pub der: DER, + #[doc = "0x20 - Configuration Register 0"] pub cfgr0: CFGR0, + #[doc = "0x24 - Configuration Register 1"] pub cfgr1: CFGR1, _reserved1: [u8; 8usize], - #[doc = "0x30 - Data Match Register 0"] - pub dmr0: DMR0, - #[doc = "0x34 - Data Match Register 1"] - pub dmr1: DMR1, + #[doc = "0x30 - Data Match Register 0"] pub dmr0: DMR0, + #[doc = "0x34 - Data Match Register 1"] pub dmr1: DMR1, _reserved2: [u8; 8usize], - #[doc = "0x40 - Clock Configuration Register"] - pub ccr: CCR, + #[doc = "0x40 - Clock Configuration Register"] pub ccr: CCR, _reserved3: [u8; 20usize], - #[doc = "0x58 - FIFO Control Register"] - pub fcr: FCR, - #[doc = "0x5c - FIFO Status Register"] - pub fsr: FSR, - #[doc = "0x60 - Transmit Command Register"] - pub tcr: TCR, - #[doc = "0x64 - Transmit Data Register"] - pub tdr: TDR, + #[doc = "0x58 - FIFO Control Register"] pub fcr: FCR, + #[doc = "0x5c - FIFO Status Register"] pub fsr: FSR, + #[doc = "0x60 - Transmit Command Register"] pub tcr: TCR, + #[doc = "0x64 - Transmit Data Register"] pub tdr: TDR, _reserved4: [u8; 8usize], - #[doc = "0x70 - Receive Status Register"] - pub rsr: RSR, - #[doc = "0x74 - Receive Data Register"] - pub rdr: RDR, + #[doc = "0x70 - Receive Status Register"] pub rsr: RSR, + #[doc = "0x74 - Receive Data Register"] pub rdr: RDR, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpspi1/param/mod.rs b/src/lpspi1/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpspi1/param/mod.rs +++ b/src/lpspi1/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi1/rdr/mod.rs b/src/lpspi1/rdr/mod.rs index d6d2996..53ec30c 100644 --- a/src/lpspi1/rdr/mod.rs +++ b/src/lpspi1/rdr/mod.rs @@ -6,7 +6,9 @@ impl super::RDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi1/rsr/mod.rs b/src/lpspi1/rsr/mod.rs index dd10bf5..a6baff2 100644 --- a/src/lpspi1/rsr/mod.rs +++ b/src/lpspi1/rsr/mod.rs @@ -6,16 +6,16 @@ impl super::RSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `SOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFR { - #[doc = "Subsequent data word received after LPSPI_PCS assertion."] - _0, - #[doc = "First data word received after LPSPI_PCS assertion."] - _1, + #[doc = "Subsequent data word received after LPSPI_PCS assertion."] _0, + #[doc = "First data word received after LPSPI_PCS assertion."] _1, } impl SOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl SOFR { #[doc = "Possible values of the field `RXEMPTY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTYR { - #[doc = "RX FIFO is not empty."] - _0, - #[doc = "RX FIFO is empty."] - _1, + #[doc = "RX FIFO is not empty."] _0, + #[doc = "RX FIFO is empty."] _1, } impl RXEMPTYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpspi1/sr/mod.rs b/src/lpspi1/sr/mod.rs index e39af52..b914212 100644 --- a/src/lpspi1/sr/mod.rs +++ b/src/lpspi1/sr/mod.rs @@ -22,7 +22,9 @@ impl super::SR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SR { #[doc = "Possible values of the field `TDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDFR { - #[doc = "Transmit data not requested."] - _0, - #[doc = "Transmit data is requested."] - _1, + #[doc = "Transmit data not requested."] _0, + #[doc = "Transmit data is requested."] _1, } impl TDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDFR { #[doc = "Possible values of the field `RDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDFR { - #[doc = "Receive Data is not ready."] - _0, - #[doc = "Receive data is ready."] - _1, + #[doc = "Receive Data is not ready."] _0, + #[doc = "Receive data is ready."] _1, } impl RDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDFR { #[doc = "Possible values of the field `WCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCFR { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCFR { #[doc = "Possible values of the field `FCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCFR { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCFR { #[doc = "Possible values of the field `TCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCFR { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCFR { #[doc = "Possible values of the field `TEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEFR { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEFR { #[doc = "Possible values of the field `REF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REFR { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REFR { #[doc = "Possible values of the field `DMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMFR { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl DMFR { #[doc = "Possible values of the field `MBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBFR { - #[doc = "LPSPI is idle."] - _0, - #[doc = "LPSPI is busy."] - _1, + #[doc = "LPSPI is idle."] _0, + #[doc = "LPSPI is busy."] _1, } impl MBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl MBFR { } #[doc = "Values that can be written to the field `WCF`"] pub enum WCFW { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFW { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _WCFW<'a> { } #[doc = "Values that can be written to the field `FCF`"] pub enum FCFW { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFW { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _FCFW<'a> { } #[doc = "Values that can be written to the field `TCF`"] pub enum TCFW { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFW { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _TCFW<'a> { } #[doc = "Values that can be written to the field `TEF`"] pub enum TEFW { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFW { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TEFW<'a> { } #[doc = "Values that can be written to the field `REF`"] pub enum REFW { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFW { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _REFW<'a> { } #[doc = "Values that can be written to the field `DMF`"] pub enum DMFW { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFW { #[allow(missing_docs)] diff --git a/src/lpspi1/tcr/mod.rs b/src/lpspi1/tcr/mod.rs index f9149ea..d5fc386 100644 --- a/src/lpspi1/tcr/mod.rs +++ b/src/lpspi1/tcr/mod.rs @@ -22,7 +22,9 @@ impl super::TCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl FRAMESZR { #[doc = "Possible values of the field `WIDTH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WIDTHR { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl WIDTHR { #[doc = r" Value of the field as raw bits"] @@ -104,10 +102,8 @@ impl WIDTHR { #[doc = "Possible values of the field `TXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -151,10 +147,8 @@ impl TXMSKR { #[doc = "Possible values of the field `RXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -198,10 +192,8 @@ impl RXMSKR { #[doc = "Possible values of the field `CONTC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTCR { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -245,10 +237,8 @@ impl CONTCR { #[doc = "Possible values of the field `CONT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTR { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -292,10 +282,8 @@ impl CONTR { #[doc = "Possible values of the field `BYSW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BYSWR { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -339,10 +327,8 @@ impl BYSWR { #[doc = "Possible values of the field `LSBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LSBFR { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,14 +372,10 @@ impl LSBFR { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -442,22 +424,14 @@ impl PCSR { #[doc = "Possible values of the field `PRESCALE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALER { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALER { #[doc = r" Value of the field as raw bits"] @@ -534,10 +508,8 @@ impl PRESCALER { #[doc = "Possible values of the field `CPHA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPHAR { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -581,10 +553,8 @@ impl CPHAR { #[doc = "Possible values of the field `CPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOLR { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -642,12 +612,9 @@ impl<'a> _FRAMESZW<'a> { } #[doc = "Values that can be written to the field `WIDTH`"] pub enum WIDTHW { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, } impl WIDTHW { #[allow(missing_docs)] @@ -698,10 +665,8 @@ impl<'a> _WIDTHW<'a> { } #[doc = "Values that can be written to the field `TXMSK`"] pub enum TXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKW { #[allow(missing_docs)] @@ -756,10 +721,8 @@ impl<'a> _TXMSKW<'a> { } #[doc = "Values that can be written to the field `RXMSK`"] pub enum RXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKW { #[allow(missing_docs)] @@ -814,10 +777,8 @@ impl<'a> _RXMSKW<'a> { } #[doc = "Values that can be written to the field `CONTC`"] pub enum CONTCW { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCW { #[allow(missing_docs)] @@ -872,10 +833,8 @@ impl<'a> _CONTCW<'a> { } #[doc = "Values that can be written to the field `CONT`"] pub enum CONTW { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTW { #[allow(missing_docs)] @@ -930,10 +889,8 @@ impl<'a> _CONTW<'a> { } #[doc = "Values that can be written to the field `BYSW`"] pub enum BYSWW { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWW { #[allow(missing_docs)] @@ -988,10 +945,8 @@ impl<'a> _BYSWW<'a> { } #[doc = "Values that can be written to the field `LSBF`"] pub enum LSBFW { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFW { #[allow(missing_docs)] @@ -1046,14 +1001,10 @@ impl<'a> _LSBFW<'a> { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSW { #[allow(missing_docs)] @@ -1112,22 +1063,14 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `PRESCALE`"] pub enum PRESCALEW { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALEW { #[allow(missing_docs)] @@ -1210,10 +1153,8 @@ impl<'a> _PRESCALEW<'a> { } #[doc = "Values that can be written to the field `CPHA`"] pub enum CPHAW { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAW { #[allow(missing_docs)] @@ -1268,10 +1209,8 @@ impl<'a> _CPHAW<'a> { } #[doc = "Values that can be written to the field `CPOL`"] pub enum CPOLW { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLW { #[allow(missing_docs)] diff --git a/src/lpspi1/verid/mod.rs b/src/lpspi1/verid/mod.rs index 4f6e83c..1f0ac7a 100644 --- a/src/lpspi1/verid/mod.rs +++ b/src/lpspi1/verid/mod.rs @@ -6,16 +6,16 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set supporting 32-bit shift register."] - _0000000000000100, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set supporting 32-bit shift register."] _0000000000000100, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpspi2/ccr/mod.rs b/src/lpspi2/ccr/mod.rs index 30c6ac2..0030b22 100644 --- a/src/lpspi2/ccr/mod.rs +++ b/src/lpspi2/ccr/mod.rs @@ -22,7 +22,9 @@ impl super::CCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi2/cfgr0/mod.rs b/src/lpspi2/cfgr0/mod.rs index 13f75e0..21988a3 100644 --- a/src/lpspi2/cfgr0/mod.rs +++ b/src/lpspi2/cfgr0/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR0 { #[doc = "Possible values of the field `HREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRENR { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl HRENR { #[doc = "Possible values of the field `HRPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRPOLR { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl HRPOLR { #[doc = "Possible values of the field `HRSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HRSELR { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl HRSELR { #[doc = "Possible values of the field `CIRFIFO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CIRFIFOR { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CIRFIFOR { #[doc = "Possible values of the field `RDMO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMOR { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +269,8 @@ impl RDMOR { } #[doc = "Values that can be written to the field `HREN`"] pub enum HRENW { - #[doc = "Host request is disabled."] - _0, - #[doc = "Host request is enabled."] - _1, + #[doc = "Host request is disabled."] _0, + #[doc = "Host request is enabled."] _1, } impl HRENW { #[allow(missing_docs)] @@ -335,10 +325,8 @@ impl<'a> _HRENW<'a> { } #[doc = "Values that can be written to the field `HRPOL`"] pub enum HRPOLW { - #[doc = "Active low."] - _0, - #[doc = "Active high."] - _1, + #[doc = "Active low."] _0, + #[doc = "Active high."] _1, } impl HRPOLW { #[allow(missing_docs)] @@ -393,10 +381,8 @@ impl<'a> _HRPOLW<'a> { } #[doc = "Values that can be written to the field `HRSEL`"] pub enum HRSELW { - #[doc = "Host request input is pin LPSPI_HREQ."] - _0, - #[doc = "Host request input is input trigger."] - _1, + #[doc = "Host request input is pin LPSPI_HREQ."] _0, + #[doc = "Host request input is input trigger."] _1, } impl HRSELW { #[allow(missing_docs)] @@ -451,10 +437,8 @@ impl<'a> _HRSELW<'a> { } #[doc = "Values that can be written to the field `CIRFIFO`"] pub enum CIRFIFOW { - #[doc = "Circular FIFO is disabled."] - _0, - #[doc = "Circular FIFO is enabled."] - _1, + #[doc = "Circular FIFO is disabled."] _0, + #[doc = "Circular FIFO is enabled."] _1, } impl CIRFIFOW { #[allow(missing_docs)] @@ -509,10 +493,8 @@ impl<'a> _CIRFIFOW<'a> { } #[doc = "Values that can be written to the field `RDMO`"] pub enum RDMOW { - #[doc = "Received data is stored in the receive FIFO as normal."] - _0, - #[doc = "Received data is discarded unless the DMF is set."] - _1, + #[doc = "Received data is stored in the receive FIFO as normal."] _0, + #[doc = "Received data is discarded unless the DMF is set."] _1, } impl RDMOW { #[allow(missing_docs)] diff --git a/src/lpspi2/cfgr1/mod.rs b/src/lpspi2/cfgr1/mod.rs index 16779e3..f9becbf 100644 --- a/src/lpspi2/cfgr1/mod.rs +++ b/src/lpspi2/cfgr1/mod.rs @@ -22,7 +22,9 @@ impl super::CFGR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CFGR1 { #[doc = "Possible values of the field `MASTER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MASTERR { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MASTERR { #[doc = "Possible values of the field `SAMPLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SAMPLER { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SAMPLER { #[doc = "Possible values of the field `AUTOPCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AUTOPCSR { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,8 +180,7 @@ impl AUTOPCSR { #[doc = "Possible values of the field `NOSTALL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOSTALLR { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -231,12 +226,9 @@ impl NOSTALLR { #[doc = "Possible values of the field `PCSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSPOLR { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, + #[doc = r" Reserved"] _Reserved(u8), } impl PCSPOLR { #[doc = r" Value of the field as raw bits"] @@ -272,8 +264,7 @@ impl PCSPOLR { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -286,8 +277,7 @@ pub enum MATCFGR { _110, #[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"] _111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -358,14 +348,10 @@ impl MATCFGR { #[doc = "Possible values of the field `PINCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINCFGR { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGR { #[doc = r" Value of the field as raw bits"] @@ -414,10 +400,8 @@ impl PINCFGR { #[doc = "Possible values of the field `OUTCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OUTCFGR { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -461,10 +445,8 @@ impl OUTCFGR { #[doc = "Possible values of the field `PCSCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSCFGR { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -507,10 +489,8 @@ impl PCSCFGR { } #[doc = "Values that can be written to the field `MASTER`"] pub enum MASTERW { - #[doc = "Slave mode."] - _0, - #[doc = "Master mode."] - _1, + #[doc = "Slave mode."] _0, + #[doc = "Master mode."] _1, } impl MASTERW { #[allow(missing_docs)] @@ -565,10 +545,8 @@ impl<'a> _MASTERW<'a> { } #[doc = "Values that can be written to the field `SAMPLE`"] pub enum SAMPLEW { - #[doc = "Input data sampled on SCK edge."] - _0, - #[doc = "Input data sampled on delayed SCK edge."] - _1, + #[doc = "Input data sampled on SCK edge."] _0, + #[doc = "Input data sampled on delayed SCK edge."] _1, } impl SAMPLEW { #[allow(missing_docs)] @@ -623,10 +601,8 @@ impl<'a> _SAMPLEW<'a> { } #[doc = "Values that can be written to the field `AUTOPCS`"] pub enum AUTOPCSW { - #[doc = "Automatic PCS generation disabled."] - _0, - #[doc = "Automatic PCS generation enabled."] - _1, + #[doc = "Automatic PCS generation disabled."] _0, + #[doc = "Automatic PCS generation enabled."] _1, } impl AUTOPCSW { #[allow(missing_docs)] @@ -681,8 +657,7 @@ impl<'a> _AUTOPCSW<'a> { } #[doc = "Values that can be written to the field `NOSTALL`"] pub enum NOSTALLW { - #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] - _0, + #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0, #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."] _1, } @@ -739,10 +714,8 @@ impl<'a> _NOSTALLW<'a> { } #[doc = "Values that can be written to the field `PCSPOL`"] pub enum PCSPOLW { - #[doc = "The PCSx is active low."] - _0000, - #[doc = "The PCSx is active high."] - _0001, + #[doc = "The PCSx is active low."] _0000, + #[doc = "The PCSx is active high."] _0001, } impl PCSPOLW { #[allow(missing_docs)] @@ -787,8 +760,7 @@ impl<'a> _PCSPOLW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Match is disabled."] - _000, + #[doc = "Match is disabled."] _000, #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"] _010, #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"] @@ -875,14 +847,10 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `PINCFG`"] pub enum PINCFGW { - #[doc = "SIN is used for input data and SOUT for output data."] - _00, - #[doc = "SIN is used for both input and output data."] - _01, - #[doc = "SOUT is used for both input and output data."] - _10, - #[doc = "SOUT is used for input data and SIN for output data."] - _11, + #[doc = "SIN is used for input data and SOUT for output data."] _00, + #[doc = "SIN is used for both input and output data."] _01, + #[doc = "SOUT is used for both input and output data."] _10, + #[doc = "SOUT is used for input data and SIN for output data."] _11, } impl PINCFGW { #[allow(missing_docs)] @@ -941,10 +909,8 @@ impl<'a> _PINCFGW<'a> { } #[doc = "Values that can be written to the field `OUTCFG`"] pub enum OUTCFGW { - #[doc = "Output data retains last value when chip select is negated."] - _0, - #[doc = "Output data is tristated when chip select is negated."] - _1, + #[doc = "Output data retains last value when chip select is negated."] _0, + #[doc = "Output data is tristated when chip select is negated."] _1, } impl OUTCFGW { #[allow(missing_docs)] @@ -999,10 +965,8 @@ impl<'a> _OUTCFGW<'a> { } #[doc = "Values that can be written to the field `PCSCFG`"] pub enum PCSCFGW { - #[doc = "PCS[3:2] are enabled."] - _0, - #[doc = "PCS[3:2] are disabled."] - _1, + #[doc = "PCS[3:2] are enabled."] _0, + #[doc = "PCS[3:2] are disabled."] _1, } impl PCSCFGW { #[allow(missing_docs)] diff --git a/src/lpspi2/cr/mod.rs b/src/lpspi2/cr/mod.rs index 8f168a0..9200050 100644 --- a/src/lpspi2/cr/mod.rs +++ b/src/lpspi2/cr/mod.rs @@ -22,7 +22,9 @@ impl super::CR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CR { #[doc = "Possible values of the field `MEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MENR { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MENR { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RSTR { #[doc = "Possible values of the field `DOZEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZENR { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl DOZENR { #[doc = "Possible values of the field `DBGEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGENR { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl DBGENR { } #[doc = "Values that can be written to the field `MEN`"] pub enum MENW { - #[doc = "Module is disabled."] - _0, - #[doc = "Module is enabled."] - _1, + #[doc = "Module is disabled."] _0, + #[doc = "Module is enabled."] _1, } impl MENW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _MENW<'a> { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Master logic is not reset."] - _0, - #[doc = "Master logic is reset."] - _1, + #[doc = "Master logic is not reset."] _0, + #[doc = "Master logic is reset."] _1, } impl RSTW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> { } #[doc = "Values that can be written to the field `DOZEN`"] pub enum DOZENW { - #[doc = "Module is enabled in Doze mode."] - _0, - #[doc = "Module is disabled in Doze mode."] - _1, + #[doc = "Module is enabled in Doze mode."] _0, + #[doc = "Module is disabled in Doze mode."] _1, } impl DOZENW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _DOZENW<'a> { } #[doc = "Values that can be written to the field `DBGEN`"] pub enum DBGENW { - #[doc = "Module is disabled in debug mode."] - _0, - #[doc = "Module is enabled in debug mode."] - _1, + #[doc = "Module is disabled in debug mode."] _0, + #[doc = "Module is enabled in debug mode."] _1, } impl DBGENW { #[allow(missing_docs)] @@ -462,10 +448,8 @@ impl<'a> _DBGENW<'a> { } #[doc = "Values that can be written to the field `RTF`"] pub enum RTFW { - #[doc = "No effect."] - _0, - #[doc = "Transmit FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Transmit FIFO is reset."] _1, } impl RTFW { #[allow(missing_docs)] @@ -520,10 +504,8 @@ impl<'a> _RTFW<'a> { } #[doc = "Values that can be written to the field `RRF`"] pub enum RRFW { - #[doc = "No effect."] - _0, - #[doc = "Receive FIFO is reset."] - _1, + #[doc = "No effect."] _0, + #[doc = "Receive FIFO is reset."] _1, } impl RRFW { #[allow(missing_docs)] diff --git a/src/lpspi2/der/mod.rs b/src/lpspi2/der/mod.rs index 0f3e2ee..de62513 100644 --- a/src/lpspi2/der/mod.rs +++ b/src/lpspi2/der/mod.rs @@ -22,7 +22,9 @@ impl super::DER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DER { #[doc = "Possible values of the field `TDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDDER { #[doc = "Possible values of the field `RDDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDDER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl RDDER { } #[doc = "Values that can be written to the field `TDDE`"] pub enum TDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled"] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled"] _1, } impl TDDEW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _TDDEW<'a> { } #[doc = "Values that can be written to the field `RDDE`"] pub enum RDDEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDDEW { #[allow(missing_docs)] diff --git a/src/lpspi2/dmr0/mod.rs b/src/lpspi2/dmr0/mod.rs index 9507eb5..f0fcb82 100644 --- a/src/lpspi2/dmr0/mod.rs +++ b/src/lpspi2/dmr0/mod.rs @@ -22,7 +22,9 @@ impl super::DMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi2/dmr1/mod.rs b/src/lpspi2/dmr1/mod.rs index c568a1c..ff5a01b 100644 --- a/src/lpspi2/dmr1/mod.rs +++ b/src/lpspi2/dmr1/mod.rs @@ -22,7 +22,9 @@ impl super::DMR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi2/fcr/mod.rs b/src/lpspi2/fcr/mod.rs index 04ca2a4..60cb2f7 100644 --- a/src/lpspi2/fcr/mod.rs +++ b/src/lpspi2/fcr/mod.rs @@ -22,7 +22,9 @@ impl super::FCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpspi2/fsr/mod.rs b/src/lpspi2/fsr/mod.rs index 1871a95..f37f6a7 100644 --- a/src/lpspi2/fsr/mod.rs +++ b/src/lpspi2/fsr/mod.rs @@ -6,7 +6,9 @@ impl super::FSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi2/ier/mod.rs b/src/lpspi2/ier/mod.rs index 477b75a..41259da 100644 --- a/src/lpspi2/ier/mod.rs +++ b/src/lpspi2/ier/mod.rs @@ -22,7 +22,9 @@ impl super::IER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::IER { #[doc = "Possible values of the field `TDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDIER { #[doc = "Possible values of the field `RDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDIER { #[doc = "Possible values of the field `WCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCIER { #[doc = "Possible values of the field `FCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCIER { #[doc = "Possible values of the field `TEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEIER { #[doc = "Possible values of the field `REIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REIER { #[doc = "Possible values of the field `DMIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMIER { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -418,10 +404,8 @@ impl DMIER { } #[doc = "Values that can be written to the field `TDIE`"] pub enum TDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled"] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled"] _1, } impl TDIEW { #[allow(missing_docs)] @@ -476,10 +460,8 @@ impl<'a> _TDIEW<'a> { } #[doc = "Values that can be written to the field `RDIE`"] pub enum RDIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl RDIEW { #[allow(missing_docs)] @@ -534,10 +516,8 @@ impl<'a> _RDIEW<'a> { } #[doc = "Values that can be written to the field `WCIE`"] pub enum WCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WCIEW { #[allow(missing_docs)] @@ -592,10 +572,8 @@ impl<'a> _WCIEW<'a> { } #[doc = "Values that can be written to the field `FCIE`"] pub enum FCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl FCIEW { #[allow(missing_docs)] @@ -650,10 +628,8 @@ impl<'a> _FCIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -708,10 +684,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TEIE`"] pub enum TEIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl TEIEW { #[allow(missing_docs)] @@ -766,10 +740,8 @@ impl<'a> _TEIEW<'a> { } #[doc = "Values that can be written to the field `REIE`"] pub enum REIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl REIEW { #[allow(missing_docs)] @@ -824,10 +796,8 @@ impl<'a> _REIEW<'a> { } #[doc = "Values that can be written to the field `DMIE`"] pub enum DMIEW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl DMIEW { #[allow(missing_docs)] diff --git a/src/lpspi2/mod.rs b/src/lpspi2/mod.rs index 65423c5..43f9181 100644 --- a/src/lpspi2/mod.rs +++ b/src/lpspi2/mod.rs @@ -2,45 +2,28 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, _reserved0: [u8; 8usize], - #[doc = "0x10 - Control Register"] - pub cr: CR, - #[doc = "0x14 - Status Register"] - pub sr: SR, - #[doc = "0x18 - Interrupt Enable Register"] - pub ier: IER, - #[doc = "0x1c - DMA Enable Register"] - pub der: DER, - #[doc = "0x20 - Configuration Register 0"] - pub cfgr0: CFGR0, - #[doc = "0x24 - Configuration Register 1"] - pub cfgr1: CFGR1, + #[doc = "0x10 - Control Register"] pub cr: CR, + #[doc = "0x14 - Status Register"] pub sr: SR, + #[doc = "0x18 - Interrupt Enable Register"] pub ier: IER, + #[doc = "0x1c - DMA Enable Register"] pub der: DER, + #[doc = "0x20 - Configuration Register 0"] pub cfgr0: CFGR0, + #[doc = "0x24 - Configuration Register 1"] pub cfgr1: CFGR1, _reserved1: [u8; 8usize], - #[doc = "0x30 - Data Match Register 0"] - pub dmr0: DMR0, - #[doc = "0x34 - Data Match Register 1"] - pub dmr1: DMR1, + #[doc = "0x30 - Data Match Register 0"] pub dmr0: DMR0, + #[doc = "0x34 - Data Match Register 1"] pub dmr1: DMR1, _reserved2: [u8; 8usize], - #[doc = "0x40 - Clock Configuration Register"] - pub ccr: CCR, + #[doc = "0x40 - Clock Configuration Register"] pub ccr: CCR, _reserved3: [u8; 20usize], - #[doc = "0x58 - FIFO Control Register"] - pub fcr: FCR, - #[doc = "0x5c - FIFO Status Register"] - pub fsr: FSR, - #[doc = "0x60 - Transmit Command Register"] - pub tcr: TCR, - #[doc = "0x64 - Transmit Data Register"] - pub tdr: TDR, + #[doc = "0x58 - FIFO Control Register"] pub fcr: FCR, + #[doc = "0x5c - FIFO Status Register"] pub fsr: FSR, + #[doc = "0x60 - Transmit Command Register"] pub tcr: TCR, + #[doc = "0x64 - Transmit Data Register"] pub tdr: TDR, _reserved4: [u8; 8usize], - #[doc = "0x70 - Receive Status Register"] - pub rsr: RSR, - #[doc = "0x74 - Receive Data Register"] - pub rdr: RDR, + #[doc = "0x70 - Receive Status Register"] pub rsr: RSR, + #[doc = "0x74 - Receive Data Register"] pub rdr: RDR, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpspi2/param/mod.rs b/src/lpspi2/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpspi2/param/mod.rs +++ b/src/lpspi2/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi2/rdr/mod.rs b/src/lpspi2/rdr/mod.rs index d6d2996..53ec30c 100644 --- a/src/lpspi2/rdr/mod.rs +++ b/src/lpspi2/rdr/mod.rs @@ -6,7 +6,9 @@ impl super::RDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpspi2/rsr/mod.rs b/src/lpspi2/rsr/mod.rs index dd10bf5..a6baff2 100644 --- a/src/lpspi2/rsr/mod.rs +++ b/src/lpspi2/rsr/mod.rs @@ -6,16 +6,16 @@ impl super::RSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `SOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOFR { - #[doc = "Subsequent data word received after LPSPI_PCS assertion."] - _0, - #[doc = "First data word received after LPSPI_PCS assertion."] - _1, + #[doc = "Subsequent data word received after LPSPI_PCS assertion."] _0, + #[doc = "First data word received after LPSPI_PCS assertion."] _1, } impl SOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl SOFR { #[doc = "Possible values of the field `RXEMPTY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTYR { - #[doc = "RX FIFO is not empty."] - _0, - #[doc = "RX FIFO is empty."] - _1, + #[doc = "RX FIFO is not empty."] _0, + #[doc = "RX FIFO is empty."] _1, } impl RXEMPTYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpspi2/sr/mod.rs b/src/lpspi2/sr/mod.rs index e39af52..b914212 100644 --- a/src/lpspi2/sr/mod.rs +++ b/src/lpspi2/sr/mod.rs @@ -22,7 +22,9 @@ impl super::SR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SR { #[doc = "Possible values of the field `TDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDFR { - #[doc = "Transmit data not requested."] - _0, - #[doc = "Transmit data is requested."] - _1, + #[doc = "Transmit data not requested."] _0, + #[doc = "Transmit data is requested."] _1, } impl TDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TDFR { #[doc = "Possible values of the field `RDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDFR { - #[doc = "Receive Data is not ready."] - _0, - #[doc = "Receive data is ready."] - _1, + #[doc = "Receive Data is not ready."] _0, + #[doc = "Receive data is ready."] _1, } impl RDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl RDFR { #[doc = "Possible values of the field `WCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WCFR { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl WCFR { #[doc = "Possible values of the field `FCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FCFR { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FCFR { #[doc = "Possible values of the field `TCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCFR { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl TCFR { #[doc = "Possible values of the field `TEF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TEFR { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl TEFR { #[doc = "Possible values of the field `REF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REFR { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl REFR { #[doc = "Possible values of the field `DMF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMFR { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl DMFR { #[doc = "Possible values of the field `MBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MBFR { - #[doc = "LPSPI is idle."] - _0, - #[doc = "LPSPI is busy."] - _1, + #[doc = "LPSPI is idle."] _0, + #[doc = "LPSPI is busy."] _1, } impl MBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -465,10 +449,8 @@ impl MBFR { } #[doc = "Values that can be written to the field `WCF`"] pub enum WCFW { - #[doc = "Transfer word not completed."] - _0, - #[doc = "Transfer word completed."] - _1, + #[doc = "Transfer word not completed."] _0, + #[doc = "Transfer word completed."] _1, } impl WCFW { #[allow(missing_docs)] @@ -523,10 +505,8 @@ impl<'a> _WCFW<'a> { } #[doc = "Values that can be written to the field `FCF`"] pub enum FCFW { - #[doc = "Frame transfer has not completed."] - _0, - #[doc = "Frame transfer has completed."] - _1, + #[doc = "Frame transfer has not completed."] _0, + #[doc = "Frame transfer has completed."] _1, } impl FCFW { #[allow(missing_docs)] @@ -581,10 +561,8 @@ impl<'a> _FCFW<'a> { } #[doc = "Values that can be written to the field `TCF`"] pub enum TCFW { - #[doc = "All transfers have not completed."] - _0, - #[doc = "All transfers have completed."] - _1, + #[doc = "All transfers have not completed."] _0, + #[doc = "All transfers have completed."] _1, } impl TCFW { #[allow(missing_docs)] @@ -639,10 +617,8 @@ impl<'a> _TCFW<'a> { } #[doc = "Values that can be written to the field `TEF`"] pub enum TEFW { - #[doc = "Transmit FIFO underrun has not occurred."] - _0, - #[doc = "Transmit FIFO underrun has occurred"] - _1, + #[doc = "Transmit FIFO underrun has not occurred."] _0, + #[doc = "Transmit FIFO underrun has occurred"] _1, } impl TEFW { #[allow(missing_docs)] @@ -697,10 +673,8 @@ impl<'a> _TEFW<'a> { } #[doc = "Values that can be written to the field `REF`"] pub enum REFW { - #[doc = "Receive FIFO has not overflowed."] - _0, - #[doc = "Receive FIFO has overflowed."] - _1, + #[doc = "Receive FIFO has not overflowed."] _0, + #[doc = "Receive FIFO has overflowed."] _1, } impl REFW { #[allow(missing_docs)] @@ -755,10 +729,8 @@ impl<'a> _REFW<'a> { } #[doc = "Values that can be written to the field `DMF`"] pub enum DMFW { - #[doc = "Have not received matching data."] - _0, - #[doc = "Have received matching data."] - _1, + #[doc = "Have not received matching data."] _0, + #[doc = "Have received matching data."] _1, } impl DMFW { #[allow(missing_docs)] diff --git a/src/lpspi2/tcr/mod.rs b/src/lpspi2/tcr/mod.rs index f9149ea..d5fc386 100644 --- a/src/lpspi2/tcr/mod.rs +++ b/src/lpspi2/tcr/mod.rs @@ -22,7 +22,9 @@ impl super::TCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,14 +56,10 @@ impl FRAMESZR { #[doc = "Possible values of the field `WIDTH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WIDTHR { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl WIDTHR { #[doc = r" Value of the field as raw bits"] @@ -104,10 +102,8 @@ impl WIDTHR { #[doc = "Possible values of the field `TXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -151,10 +147,8 @@ impl TXMSKR { #[doc = "Possible values of the field `RXMSK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXMSKR { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -198,10 +192,8 @@ impl RXMSKR { #[doc = "Possible values of the field `CONTC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTCR { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -245,10 +237,8 @@ impl CONTCR { #[doc = "Possible values of the field `CONT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTR { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -292,10 +282,8 @@ impl CONTR { #[doc = "Possible values of the field `BYSW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BYSWR { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -339,10 +327,8 @@ impl BYSWR { #[doc = "Possible values of the field `LSBF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LSBFR { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,14 +372,10 @@ impl LSBFR { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -442,22 +424,14 @@ impl PCSR { #[doc = "Possible values of the field `PRESCALE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALER { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALER { #[doc = r" Value of the field as raw bits"] @@ -534,10 +508,8 @@ impl PRESCALER { #[doc = "Possible values of the field `CPHA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPHAR { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -581,10 +553,8 @@ impl CPHAR { #[doc = "Possible values of the field `CPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOLR { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -642,12 +612,9 @@ impl<'a> _FRAMESZW<'a> { } #[doc = "Values that can be written to the field `WIDTH`"] pub enum WIDTHW { - #[doc = "Single bit transfer."] - _00, - #[doc = "Two bit transfer."] - _01, - #[doc = "Four bit transfer."] - _10, + #[doc = "Single bit transfer."] _00, + #[doc = "Two bit transfer."] _01, + #[doc = "Four bit transfer."] _10, } impl WIDTHW { #[allow(missing_docs)] @@ -698,10 +665,8 @@ impl<'a> _WIDTHW<'a> { } #[doc = "Values that can be written to the field `TXMSK`"] pub enum TXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Mask transmit data."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Mask transmit data."] _1, } impl TXMSKW { #[allow(missing_docs)] @@ -756,10 +721,8 @@ impl<'a> _TXMSKW<'a> { } #[doc = "Values that can be written to the field `RXMSK`"] pub enum RXMSKW { - #[doc = "Normal transfer."] - _0, - #[doc = "Receive data is masked."] - _1, + #[doc = "Normal transfer."] _0, + #[doc = "Receive data is masked."] _1, } impl RXMSKW { #[allow(missing_docs)] @@ -814,10 +777,8 @@ impl<'a> _RXMSKW<'a> { } #[doc = "Values that can be written to the field `CONTC`"] pub enum CONTCW { - #[doc = "Command word for start of new transfer."] - _0, - #[doc = "Command word for continuing transfer."] - _1, + #[doc = "Command word for start of new transfer."] _0, + #[doc = "Command word for continuing transfer."] _1, } impl CONTCW { #[allow(missing_docs)] @@ -872,10 +833,8 @@ impl<'a> _CONTCW<'a> { } #[doc = "Values that can be written to the field `CONT`"] pub enum CONTW { - #[doc = "Continuous transfer disabled."] - _0, - #[doc = "Continuous transfer enabled."] - _1, + #[doc = "Continuous transfer disabled."] _0, + #[doc = "Continuous transfer enabled."] _1, } impl CONTW { #[allow(missing_docs)] @@ -930,10 +889,8 @@ impl<'a> _CONTW<'a> { } #[doc = "Values that can be written to the field `BYSW`"] pub enum BYSWW { - #[doc = "Byte swap disabled."] - _0, - #[doc = "Byte swap enabled."] - _1, + #[doc = "Byte swap disabled."] _0, + #[doc = "Byte swap enabled."] _1, } impl BYSWW { #[allow(missing_docs)] @@ -988,10 +945,8 @@ impl<'a> _BYSWW<'a> { } #[doc = "Values that can be written to the field `LSBF`"] pub enum LSBFW { - #[doc = "Data is transferred MSB first."] - _0, - #[doc = "Data is transferred LSB first."] - _1, + #[doc = "Data is transferred MSB first."] _0, + #[doc = "Data is transferred LSB first."] _1, } impl LSBFW { #[allow(missing_docs)] @@ -1046,14 +1001,10 @@ impl<'a> _LSBFW<'a> { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Transfer using LPSPI_PCS[0]"] - _00, - #[doc = "Transfer using LPSPI_PCS[1]"] - _01, - #[doc = "Transfer using LPSPI_PCS[2]"] - _10, - #[doc = "Transfer using LPSPI_PCS[3]"] - _11, + #[doc = "Transfer using LPSPI_PCS[0]"] _00, + #[doc = "Transfer using LPSPI_PCS[1]"] _01, + #[doc = "Transfer using LPSPI_PCS[2]"] _10, + #[doc = "Transfer using LPSPI_PCS[3]"] _11, } impl PCSW { #[allow(missing_docs)] @@ -1112,22 +1063,14 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `PRESCALE`"] pub enum PRESCALEW { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 4."] - _010, - #[doc = "Divide by 8."] - _011, - #[doc = "Divide by 16."] - _100, - #[doc = "Divide by 32."] - _101, - #[doc = "Divide by 64."] - _110, - #[doc = "Divide by 128."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 4."] _010, + #[doc = "Divide by 8."] _011, + #[doc = "Divide by 16."] _100, + #[doc = "Divide by 32."] _101, + #[doc = "Divide by 64."] _110, + #[doc = "Divide by 128."] _111, } impl PRESCALEW { #[allow(missing_docs)] @@ -1210,10 +1153,8 @@ impl<'a> _PRESCALEW<'a> { } #[doc = "Values that can be written to the field `CPHA`"] pub enum CPHAW { - #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] - _0, - #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] - _1, + #[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0, + #[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1, } impl CPHAW { #[allow(missing_docs)] @@ -1268,10 +1209,8 @@ impl<'a> _CPHAW<'a> { } #[doc = "Values that can be written to the field `CPOL`"] pub enum CPOLW { - #[doc = "The inactive state value of SCK is low."] - _0, - #[doc = "The inactive state value of SCK is high."] - _1, + #[doc = "The inactive state value of SCK is low."] _0, + #[doc = "The inactive state value of SCK is high."] _1, } impl CPOLW { #[allow(missing_docs)] diff --git a/src/lpspi2/verid/mod.rs b/src/lpspi2/verid/mod.rs index 4f6e83c..1f0ac7a 100644 --- a/src/lpspi2/verid/mod.rs +++ b/src/lpspi2/verid/mod.rs @@ -6,16 +6,16 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set supporting 32-bit shift register."] - _0000000000000100, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set supporting 32-bit shift register."] _0000000000000100, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lptmr0/cmr/mod.rs b/src/lptmr0/cmr/mod.rs index 0220b20..8c00971 100644 --- a/src/lptmr0/cmr/mod.rs +++ b/src/lptmr0/cmr/mod.rs @@ -22,7 +22,9 @@ impl super::CMR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lptmr0/cnr/mod.rs b/src/lptmr0/cnr/mod.rs index fef23da..7e45516 100644 --- a/src/lptmr0/cnr/mod.rs +++ b/src/lptmr0/cnr/mod.rs @@ -22,7 +22,9 @@ impl super::CNR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lptmr0/csr/mod.rs b/src/lptmr0/csr/mod.rs index 575c88e..621c0d2 100644 --- a/src/lptmr0/csr/mod.rs +++ b/src/lptmr0/csr/mod.rs @@ -22,7 +22,9 @@ impl super::CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CSR { #[doc = "Possible values of the field `TEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TENR { - #[doc = "LPTMR is disabled and internal logic is reset."] - _0, - #[doc = "LPTMR is enabled."] - _1, + #[doc = "LPTMR is disabled and internal logic is reset."] _0, + #[doc = "LPTMR is enabled."] _1, } impl TENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TENR { #[doc = "Possible values of the field `TMS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMSR { - #[doc = "Time Counter mode."] - _0, - #[doc = "Pulse Counter mode."] - _1, + #[doc = "Time Counter mode."] _0, + #[doc = "Pulse Counter mode."] _1, } impl TMSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl TMSR { #[doc = "Possible values of the field `TFC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TFCR { - #[doc = "CNR is reset whenever TCF is set."] - _0, - #[doc = "CNR is reset on overflow."] - _1, + #[doc = "CNR is reset whenever TCF is set."] _0, + #[doc = "CNR is reset on overflow."] _1, } impl TFCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,14 +227,10 @@ impl TPPR { #[doc = "Possible values of the field `TPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TPSR { - #[doc = "Pulse counter input 0 is selected."] - _00, - #[doc = "Pulse counter input 1 is selected."] - _01, - #[doc = "Pulse counter input 2 is selected."] - _10, - #[doc = "Pulse counter input 3 is selected."] - _11, + #[doc = "Pulse counter input 0 is selected."] _00, + #[doc = "Pulse counter input 1 is selected."] _01, + #[doc = "Pulse counter input 2 is selected."] _10, + #[doc = "Pulse counter input 3 is selected."] _11, } impl TPSR { #[doc = r" Value of the field as raw bits"] @@ -287,10 +279,8 @@ impl TPSR { #[doc = "Possible values of the field `TIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIER { - #[doc = "Timer interrupt disabled."] - _0, - #[doc = "Timer interrupt enabled."] - _1, + #[doc = "Timer interrupt disabled."] _0, + #[doc = "Timer interrupt enabled."] _1, } impl TIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,10 +324,8 @@ impl TIER { #[doc = "Possible values of the field `TCF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCFR { - #[doc = "The value of CNR is not equal to CMR and increments."] - _0, - #[doc = "The value of CNR is equal to CMR and increments."] - _1, + #[doc = "The value of CNR is not equal to CMR and increments."] _0, + #[doc = "The value of CNR is equal to CMR and increments."] _1, } impl TCFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -381,10 +369,8 @@ impl TCFR { #[doc = "Possible values of the field `TDRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDRER { - #[doc = "Timer DMA Request disabled."] - _0, - #[doc = "Timer DMA Request enabled."] - _1, + #[doc = "Timer DMA Request disabled."] _0, + #[doc = "Timer DMA Request enabled."] _1, } impl TDRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -427,10 +413,8 @@ impl TDRER { } #[doc = "Values that can be written to the field `TEN`"] pub enum TENW { - #[doc = "LPTMR is disabled and internal logic is reset."] - _0, - #[doc = "LPTMR is enabled."] - _1, + #[doc = "LPTMR is disabled and internal logic is reset."] _0, + #[doc = "LPTMR is enabled."] _1, } impl TENW { #[allow(missing_docs)] @@ -485,10 +469,8 @@ impl<'a> _TENW<'a> { } #[doc = "Values that can be written to the field `TMS`"] pub enum TMSW { - #[doc = "Time Counter mode."] - _0, - #[doc = "Pulse Counter mode."] - _1, + #[doc = "Time Counter mode."] _0, + #[doc = "Pulse Counter mode."] _1, } impl TMSW { #[allow(missing_docs)] @@ -543,10 +525,8 @@ impl<'a> _TMSW<'a> { } #[doc = "Values that can be written to the field `TFC`"] pub enum TFCW { - #[doc = "CNR is reset whenever TCF is set."] - _0, - #[doc = "CNR is reset on overflow."] - _1, + #[doc = "CNR is reset whenever TCF is set."] _0, + #[doc = "CNR is reset on overflow."] _1, } impl TFCW { #[allow(missing_docs)] @@ -659,14 +639,10 @@ impl<'a> _TPPW<'a> { } #[doc = "Values that can be written to the field `TPS`"] pub enum TPSW { - #[doc = "Pulse counter input 0 is selected."] - _00, - #[doc = "Pulse counter input 1 is selected."] - _01, - #[doc = "Pulse counter input 2 is selected."] - _10, - #[doc = "Pulse counter input 3 is selected."] - _11, + #[doc = "Pulse counter input 0 is selected."] _00, + #[doc = "Pulse counter input 1 is selected."] _01, + #[doc = "Pulse counter input 2 is selected."] _10, + #[doc = "Pulse counter input 3 is selected."] _11, } impl TPSW { #[allow(missing_docs)] @@ -725,10 +701,8 @@ impl<'a> _TPSW<'a> { } #[doc = "Values that can be written to the field `TIE`"] pub enum TIEW { - #[doc = "Timer interrupt disabled."] - _0, - #[doc = "Timer interrupt enabled."] - _1, + #[doc = "Timer interrupt disabled."] _0, + #[doc = "Timer interrupt enabled."] _1, } impl TIEW { #[allow(missing_docs)] @@ -783,10 +757,8 @@ impl<'a> _TIEW<'a> { } #[doc = "Values that can be written to the field `TCF`"] pub enum TCFW { - #[doc = "The value of CNR is not equal to CMR and increments."] - _0, - #[doc = "The value of CNR is equal to CMR and increments."] - _1, + #[doc = "The value of CNR is not equal to CMR and increments."] _0, + #[doc = "The value of CNR is equal to CMR and increments."] _1, } impl TCFW { #[allow(missing_docs)] @@ -841,10 +813,8 @@ impl<'a> _TCFW<'a> { } #[doc = "Values that can be written to the field `TDRE`"] pub enum TDREW { - #[doc = "Timer DMA Request disabled."] - _0, - #[doc = "Timer DMA Request enabled."] - _1, + #[doc = "Timer DMA Request disabled."] _0, + #[doc = "Timer DMA Request enabled."] _1, } impl TDREW { #[allow(missing_docs)] diff --git a/src/lptmr0/mod.rs b/src/lptmr0/mod.rs index 34c9e8a..3886d7b 100644 --- a/src/lptmr0/mod.rs +++ b/src/lptmr0/mod.rs @@ -2,14 +2,10 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Low Power Timer Control Status Register"] - pub csr: CSR, - #[doc = "0x04 - Low Power Timer Prescale Register"] - pub psr: PSR, - #[doc = "0x08 - Low Power Timer Compare Register"] - pub cmr: CMR, - #[doc = "0x0c - Low Power Timer Counter Register"] - pub cnr: CNR, + #[doc = "0x00 - Low Power Timer Control Status Register"] pub csr: CSR, + #[doc = "0x04 - Low Power Timer Prescale Register"] pub psr: PSR, + #[doc = "0x08 - Low Power Timer Compare Register"] pub cmr: CMR, + #[doc = "0x0c - Low Power Timer Counter Register"] pub cnr: CNR, } #[doc = "Low Power Timer Control Status Register"] pub struct CSR { diff --git a/src/lptmr0/psr/mod.rs b/src/lptmr0/psr/mod.rs index e8f67da..36b7065 100644 --- a/src/lptmr0/psr/mod.rs +++ b/src/lptmr0/psr/mod.rs @@ -22,7 +22,9 @@ impl super::PSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::PSR { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Prescaler/glitch filter clock 0 selected."] - _00, - #[doc = "Prescaler/glitch filter clock 1 selected."] - _01, - #[doc = "Prescaler/glitch filter clock 2 selected."] - _10, - #[doc = "Prescaler/glitch filter clock 3 selected."] - _11, + #[doc = "Prescaler/glitch filter clock 0 selected."] _00, + #[doc = "Prescaler/glitch filter clock 1 selected."] _01, + #[doc = "Prescaler/glitch filter clock 2 selected."] _10, + #[doc = "Prescaler/glitch filter clock 3 selected."] _11, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl PCSR { #[doc = "Possible values of the field `PBYP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PBYPR { - #[doc = "Prescaler/glitch filter is enabled."] - _0, - #[doc = "Prescaler/glitch filter is bypassed."] - _1, + #[doc = "Prescaler/glitch filter is enabled."] _0, + #[doc = "Prescaler/glitch filter is bypassed."] _1, } impl PBYPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -309,14 +305,10 @@ impl PRESCALER { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Prescaler/glitch filter clock 0 selected."] - _00, - #[doc = "Prescaler/glitch filter clock 1 selected."] - _01, - #[doc = "Prescaler/glitch filter clock 2 selected."] - _10, - #[doc = "Prescaler/glitch filter clock 3 selected."] - _11, + #[doc = "Prescaler/glitch filter clock 0 selected."] _00, + #[doc = "Prescaler/glitch filter clock 1 selected."] _01, + #[doc = "Prescaler/glitch filter clock 2 selected."] _10, + #[doc = "Prescaler/glitch filter clock 3 selected."] _11, } impl PCSW { #[allow(missing_docs)] @@ -375,10 +367,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `PBYP`"] pub enum PBYPW { - #[doc = "Prescaler/glitch filter is enabled."] - _0, - #[doc = "Prescaler/glitch filter is bypassed."] - _1, + #[doc = "Prescaler/glitch filter is enabled."] _0, + #[doc = "Prescaler/glitch filter is bypassed."] _1, } impl PBYPW { #[allow(missing_docs)] diff --git a/src/lpuart0/baud/mod.rs b/src/lpuart0/baud/mod.rs index fb82caa..fae2b24 100644 --- a/src/lpuart0/baud/mod.rs +++ b/src/lpuart0/baud/mod.rs @@ -22,7 +22,9 @@ impl super::BAUD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SBRR { #[doc = "Possible values of the field `SBNS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBNSR { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl SBNSR { #[doc = "Possible values of the field `RXEDGIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIER { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl RXEDGIER { #[doc = "Possible values of the field `LBKDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIER { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl LBKDIER { #[doc = "Possible values of the field `RESYNCDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RESYNCDISR { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl RESYNCDISR { #[doc = "Possible values of the field `BOTHEDGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOTHEDGER { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -289,14 +282,10 @@ impl BOTHEDGER { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -339,10 +328,8 @@ impl MATCFGR { #[doc = "Possible values of the field `RIDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,10 +373,8 @@ impl RIDMAER { #[doc = "Possible values of the field `RDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,10 +418,8 @@ impl RDMAER { #[doc = "Possible values of the field `TDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -480,68 +463,37 @@ impl TDMAER { #[doc = "Possible values of the field `OSR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OSRR { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, + #[doc = r" Reserved"] _Reserved(u8), } impl OSRR { #[doc = r" Value of the field as raw bits"] @@ -773,10 +725,8 @@ impl OSRR { #[doc = "Possible values of the field `M10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M10R { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -820,10 +770,8 @@ impl M10R { #[doc = "Possible values of the field `MAEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN2R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -867,10 +815,8 @@ impl MAEN2R { #[doc = "Possible values of the field `MAEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN1R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -928,10 +874,8 @@ impl<'a> _SBRW<'a> { } #[doc = "Values that can be written to the field `SBNS`"] pub enum SBNSW { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSW { #[allow(missing_docs)] @@ -986,10 +930,8 @@ impl<'a> _SBNSW<'a> { } #[doc = "Values that can be written to the field `RXEDGIE`"] pub enum RXEDGIEW { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIEW { #[allow(missing_docs)] @@ -1044,10 +986,8 @@ impl<'a> _RXEDGIEW<'a> { } #[doc = "Values that can be written to the field `LBKDIE`"] pub enum LBKDIEW { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIEW { #[allow(missing_docs)] @@ -1102,10 +1042,8 @@ impl<'a> _LBKDIEW<'a> { } #[doc = "Values that can be written to the field `RESYNCDIS`"] pub enum RESYNCDISW { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISW { #[allow(missing_docs)] @@ -1160,8 +1098,7 @@ impl<'a> _RESYNCDISW<'a> { } #[doc = "Values that can be written to the field `BOTHEDGE`"] pub enum BOTHEDGEW { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -1218,12 +1155,9 @@ impl<'a> _BOTHEDGEW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, } impl MATCFGW { #[allow(missing_docs)] @@ -1274,10 +1208,8 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `RIDMAE`"] pub enum RIDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAEW { #[allow(missing_docs)] @@ -1332,10 +1264,8 @@ impl<'a> _RIDMAEW<'a> { } #[doc = "Values that can be written to the field `RDMAE`"] pub enum RDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAEW { #[allow(missing_docs)] @@ -1390,10 +1320,8 @@ impl<'a> _RDMAEW<'a> { } #[doc = "Values that can be written to the field `TDMAE`"] pub enum TDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAEW { #[allow(missing_docs)] @@ -1448,66 +1376,36 @@ impl<'a> _TDMAEW<'a> { } #[doc = "Values that can be written to the field `OSR`"] pub enum OSRW { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, } impl OSRW { #[allow(missing_docs)] @@ -1720,10 +1618,8 @@ impl<'a> _OSRW<'a> { } #[doc = "Values that can be written to the field `M10`"] pub enum M10W { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10W { #[allow(missing_docs)] @@ -1778,10 +1674,8 @@ impl<'a> _M10W<'a> { } #[doc = "Values that can be written to the field `MAEN2`"] pub enum MAEN2W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2W { #[allow(missing_docs)] @@ -1836,10 +1730,8 @@ impl<'a> _MAEN2W<'a> { } #[doc = "Values that can be written to the field `MAEN1`"] pub enum MAEN1W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1W { #[allow(missing_docs)] diff --git a/src/lpuart0/ctrl/mod.rs b/src/lpuart0/ctrl/mod.rs index 98de98c..30a6612 100644 --- a/src/lpuart0/ctrl/mod.rs +++ b/src/lpuart0/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL { #[doc = "Possible values of the field `PT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PTR { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl PTR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl PER { #[doc = "Possible values of the field `ILT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILTR { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ILTR { #[doc = "Possible values of the field `WAKE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WAKER { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl WAKER { #[doc = "Possible values of the field `M`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MR { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +317,8 @@ impl RSRCR { #[doc = "Possible values of the field `DOZEEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZEENR { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,8 +362,7 @@ impl DOZEENR { #[doc = "Possible values of the field `LOOPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOOPSR { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -419,22 +408,14 @@ impl LOOPSR { #[doc = "Possible values of the field `IDLECFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLECFGR { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGR { #[doc = r" Value of the field as raw bits"] @@ -511,10 +492,8 @@ impl IDLECFGR { #[doc = "Possible values of the field `M7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M7R { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -558,10 +537,8 @@ impl M7R { #[doc = "Possible values of the field `MA2IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2IER { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -605,10 +582,8 @@ impl MA2IER { #[doc = "Possible values of the field `MA1IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1IER { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -652,10 +627,8 @@ impl MA1IER { #[doc = "Possible values of the field `SBK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBKR { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -699,10 +672,8 @@ impl SBKR { #[doc = "Possible values of the field `RWU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWUR { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -746,10 +717,8 @@ impl RWUR { #[doc = "Possible values of the field `RE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RER { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl RER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -793,10 +762,8 @@ impl RER { #[doc = "Possible values of the field `TE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TER { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -840,10 +807,8 @@ impl TER { #[doc = "Possible values of the field `ILIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILIER { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -887,10 +852,8 @@ impl ILIER { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -934,10 +897,8 @@ impl RIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -981,10 +942,8 @@ impl TCIER { #[doc = "Possible values of the field `TIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIER { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1028,10 +987,8 @@ impl TIER { #[doc = "Possible values of the field `PEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PEIER { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1075,10 +1032,8 @@ impl PEIER { #[doc = "Possible values of the field `FEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEIER { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1122,10 +1077,8 @@ impl FEIER { #[doc = "Possible values of the field `NEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NEIER { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1169,10 +1122,8 @@ impl NEIER { #[doc = "Possible values of the field `ORIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORIER { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1216,10 +1167,8 @@ impl ORIER { #[doc = "Possible values of the field `TXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXINVR { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1263,10 +1212,8 @@ impl TXINVR { #[doc = "Possible values of the field `TXDIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXDIRR { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1351,10 +1298,8 @@ impl R8T9R { } #[doc = "Values that can be written to the field `PT`"] pub enum PTW { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTW { #[allow(missing_docs)] @@ -1409,10 +1354,8 @@ impl<'a> _PTW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PEW { #[allow(missing_docs)] @@ -1467,10 +1410,8 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `ILT`"] pub enum ILTW { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTW { #[allow(missing_docs)] @@ -1525,10 +1466,8 @@ impl<'a> _ILTW<'a> { } #[doc = "Values that can be written to the field `WAKE`"] pub enum WAKEW { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKEW { #[allow(missing_docs)] @@ -1583,10 +1522,8 @@ impl<'a> _WAKEW<'a> { } #[doc = "Values that can be written to the field `M`"] pub enum MW { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MW { #[allow(missing_docs)] @@ -1699,10 +1636,8 @@ impl<'a> _RSRCW<'a> { } #[doc = "Values that can be written to the field `DOZEEN`"] pub enum DOZEENW { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENW { #[allow(missing_docs)] @@ -1757,8 +1692,7 @@ impl<'a> _DOZEENW<'a> { } #[doc = "Values that can be written to the field `LOOPS`"] pub enum LOOPSW { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -1815,22 +1749,14 @@ impl<'a> _LOOPSW<'a> { } #[doc = "Values that can be written to the field `IDLECFG`"] pub enum IDLECFGW { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGW { #[allow(missing_docs)] @@ -1913,10 +1839,8 @@ impl<'a> _IDLECFGW<'a> { } #[doc = "Values that can be written to the field `M7`"] pub enum M7W { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7W { #[allow(missing_docs)] @@ -1971,10 +1895,8 @@ impl<'a> _M7W<'a> { } #[doc = "Values that can be written to the field `MA2IE`"] pub enum MA2IEW { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IEW { #[allow(missing_docs)] @@ -2029,10 +1951,8 @@ impl<'a> _MA2IEW<'a> { } #[doc = "Values that can be written to the field `MA1IE`"] pub enum MA1IEW { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IEW { #[allow(missing_docs)] @@ -2087,10 +2007,8 @@ impl<'a> _MA1IEW<'a> { } #[doc = "Values that can be written to the field `SBK`"] pub enum SBKW { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKW { #[allow(missing_docs)] @@ -2145,10 +2063,8 @@ impl<'a> _SBKW<'a> { } #[doc = "Values that can be written to the field `RWU`"] pub enum RWUW { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUW { #[allow(missing_docs)] @@ -2203,10 +2119,8 @@ impl<'a> _RWUW<'a> { } #[doc = "Values that can be written to the field `RE`"] pub enum REW { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl REW { #[allow(missing_docs)] @@ -2261,10 +2175,8 @@ impl<'a> _REW<'a> { } #[doc = "Values that can be written to the field `TE`"] pub enum TEW { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TEW { #[allow(missing_docs)] @@ -2319,10 +2231,8 @@ impl<'a> _TEW<'a> { } #[doc = "Values that can be written to the field `ILIE`"] pub enum ILIEW { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIEW { #[allow(missing_docs)] @@ -2377,10 +2287,8 @@ impl<'a> _ILIEW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIEW { #[allow(missing_docs)] @@ -2435,10 +2343,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -2493,10 +2399,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TIE`"] pub enum TIEW { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIEW { #[allow(missing_docs)] @@ -2551,10 +2455,8 @@ impl<'a> _TIEW<'a> { } #[doc = "Values that can be written to the field `PEIE`"] pub enum PEIEW { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIEW { #[allow(missing_docs)] @@ -2609,10 +2511,8 @@ impl<'a> _PEIEW<'a> { } #[doc = "Values that can be written to the field `FEIE`"] pub enum FEIEW { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIEW { #[allow(missing_docs)] @@ -2667,10 +2567,8 @@ impl<'a> _FEIEW<'a> { } #[doc = "Values that can be written to the field `NEIE`"] pub enum NEIEW { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIEW { #[allow(missing_docs)] @@ -2725,10 +2623,8 @@ impl<'a> _NEIEW<'a> { } #[doc = "Values that can be written to the field `ORIE`"] pub enum ORIEW { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIEW { #[allow(missing_docs)] @@ -2783,10 +2679,8 @@ impl<'a> _ORIEW<'a> { } #[doc = "Values that can be written to the field `TXINV`"] pub enum TXINVW { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVW { #[allow(missing_docs)] @@ -2841,10 +2735,8 @@ impl<'a> _TXINVW<'a> { } #[doc = "Values that can be written to the field `TXDIR`"] pub enum TXDIRW { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRW { #[allow(missing_docs)] diff --git a/src/lpuart0/data/mod.rs b/src/lpuart0/data/mod.rs index 3e2e726..bf5d575 100644 --- a/src/lpuart0/data/mod.rs +++ b/src/lpuart0/data/mod.rs @@ -22,7 +22,9 @@ impl super::DATA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -253,10 +255,8 @@ impl R9T9R { #[doc = "Possible values of the field `IDLINE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLINER { - #[doc = "Receiver was not idle before receiving this character."] - _0, - #[doc = "Receiver was idle before receiving this character."] - _1, + #[doc = "Receiver was not idle before receiving this character."] _0, + #[doc = "Receiver was idle before receiving this character."] _1, } impl IDLINER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -300,10 +300,8 @@ impl IDLINER { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer contains valid data."] - _0, - #[doc = "Receive buffer is empty, data returned on read is not valid."] - _1, + #[doc = "Receive buffer contains valid data."] _0, + #[doc = "Receive buffer is empty, data returned on read is not valid."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +392,8 @@ impl FRETSCR { #[doc = "Possible values of the field `PARITYE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PARITYER { - #[doc = "The dataword was received without a parity error."] - _0, - #[doc = "The dataword was received with a parity error."] - _1, + #[doc = "The dataword was received without a parity error."] _0, + #[doc = "The dataword was received with a parity error."] _1, } impl PARITYER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +437,8 @@ impl PARITYER { #[doc = "Possible values of the field `NOISY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOISYR { - #[doc = "The dataword was received without noise."] - _0, - #[doc = "The data was received with noise."] - _1, + #[doc = "The dataword was received without noise."] _0, + #[doc = "The data was received with noise."] _1, } impl NOISYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpuart0/fifo/mod.rs b/src/lpuart0/fifo/mod.rs index 7ce5dd2..1ca8b00 100644 --- a/src/lpuart0/fifo/mod.rs +++ b/src/lpuart0/fifo/mod.rs @@ -22,7 +22,9 @@ impl super::FIFO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::FIFO { #[doc = "Possible values of the field `RXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFIFOSIZER { - #[doc = "Receive FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Receive FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Receive FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Receive FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Receive FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Receive FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Receive FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Receive FIFO/Buffer depth = 256 datawords."] - _111, + #[doc = "Receive FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Receive FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Receive FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Receive FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Receive FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Receive FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Receive FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Receive FIFO/Buffer depth = 256 datawords."] _111, } impl RXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl RXFIFOSIZER { #[doc = "Possible values of the field `RXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFER { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,22 +174,14 @@ impl RXFER { #[doc = "Possible values of the field `TXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFIFOSIZER { - #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] - _111, + #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] _111, } impl TXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -274,10 +258,8 @@ impl TXFIFOSIZER { #[doc = "Possible values of the field `TXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFER { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -321,10 +303,8 @@ impl TXFER { #[doc = "Possible values of the field `RXUFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFER { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -368,10 +348,8 @@ impl RXUFER { #[doc = "Possible values of the field `TXOFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFER { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -415,8 +393,7 @@ impl TXOFER { #[doc = "Possible values of the field `RXIDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXIDENR { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -507,8 +484,7 @@ impl RXIDENR { #[doc = "Possible values of the field `RXUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFR { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -554,8 +530,7 @@ impl RXUFR { #[doc = "Possible values of the field `TXOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFR { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } @@ -601,10 +576,8 @@ impl TXOFR { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer is not empty."] - _0, - #[doc = "Receive buffer is empty."] - _1, + #[doc = "Receive buffer is not empty."] _0, + #[doc = "Receive buffer is empty."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +621,8 @@ impl RXEMPTR { #[doc = "Possible values of the field `TXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXEMPTR { - #[doc = "Transmit buffer is not empty."] - _0, - #[doc = "Transmit buffer is empty."] - _1, + #[doc = "Transmit buffer is not empty."] _0, + #[doc = "Transmit buffer is empty."] _1, } impl TXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -694,10 +665,8 @@ impl TXEMPTR { } #[doc = "Values that can be written to the field `RXFE`"] pub enum RXFEW { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFEW { #[allow(missing_docs)] @@ -752,10 +721,8 @@ impl<'a> _RXFEW<'a> { } #[doc = "Values that can be written to the field `TXFE`"] pub enum TXFEW { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFEW { #[allow(missing_docs)] @@ -810,10 +777,8 @@ impl<'a> _TXFEW<'a> { } #[doc = "Values that can be written to the field `RXUFE`"] pub enum RXUFEW { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFEW { #[allow(missing_docs)] @@ -868,10 +833,8 @@ impl<'a> _RXUFEW<'a> { } #[doc = "Values that can be written to the field `TXOFE`"] pub enum TXOFEW { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFEW { #[allow(missing_docs)] @@ -926,8 +889,7 @@ impl<'a> _TXOFEW<'a> { } #[doc = "Values that can be written to the field `RXIDEN`"] pub enum RXIDENW { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -1024,10 +986,8 @@ impl<'a> _RXIDENW<'a> { } #[doc = "Values that can be written to the field `RXFLUSH`"] pub enum RXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the receive FIFO/buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the receive FIFO/buffer is cleared out."] _1, } impl RXFLUSHW { #[allow(missing_docs)] @@ -1082,10 +1042,8 @@ impl<'a> _RXFLUSHW<'a> { } #[doc = "Values that can be written to the field `TXFLUSH`"] pub enum TXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the transmit FIFO/Buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the transmit FIFO/Buffer is cleared out."] _1, } impl TXFLUSHW { #[allow(missing_docs)] @@ -1140,8 +1098,7 @@ impl<'a> _TXFLUSHW<'a> { } #[doc = "Values that can be written to the field `RXUF`"] pub enum RXUFW { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -1198,8 +1155,7 @@ impl<'a> _RXUFW<'a> { } #[doc = "Values that can be written to the field `TXOF`"] pub enum TXOFW { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } diff --git a/src/lpuart0/global/mod.rs b/src/lpuart0/global/mod.rs index d481688..ab15f12 100644 --- a/src/lpuart0/global/mod.rs +++ b/src/lpuart0/global/mod.rs @@ -22,7 +22,9 @@ impl super::GLOBAL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::GLOBAL { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl RSTR { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTW { #[allow(missing_docs)] diff --git a/src/lpuart0/match_/mod.rs b/src/lpuart0/match_/mod.rs index 3bbca15..ccaf148 100644 --- a/src/lpuart0/match_/mod.rs +++ b/src/lpuart0/match_/mod.rs @@ -22,7 +22,9 @@ impl super::MATCH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpuart0/mod.rs b/src/lpuart0/mod.rs index fdbf7c0..d0eca48 100644 --- a/src/lpuart0/mod.rs +++ b/src/lpuart0/mod.rs @@ -2,30 +2,18 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - LPUART Global Register"] - pub global: GLOBAL, - #[doc = "0x0c - LPUART Pin Configuration Register"] - pub pincfg: PINCFG, - #[doc = "0x10 - LPUART Baud Rate Register"] - pub baud: BAUD, - #[doc = "0x14 - LPUART Status Register"] - pub stat: STAT, - #[doc = "0x18 - LPUART Control Register"] - pub ctrl: CTRL, - #[doc = "0x1c - LPUART Data Register"] - pub data: DATA, - #[doc = "0x20 - LPUART Match Address Register"] - pub match_: MATCH, - #[doc = "0x24 - LPUART Modem IrDA Register"] - pub modir: MODIR, - #[doc = "0x28 - LPUART FIFO Register"] - pub fifo: FIFO, - #[doc = "0x2c - LPUART Watermark Register"] - pub water: WATER, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - LPUART Global Register"] pub global: GLOBAL, + #[doc = "0x0c - LPUART Pin Configuration Register"] pub pincfg: PINCFG, + #[doc = "0x10 - LPUART Baud Rate Register"] pub baud: BAUD, + #[doc = "0x14 - LPUART Status Register"] pub stat: STAT, + #[doc = "0x18 - LPUART Control Register"] pub ctrl: CTRL, + #[doc = "0x1c - LPUART Data Register"] pub data: DATA, + #[doc = "0x20 - LPUART Match Address Register"] pub match_: MATCH, + #[doc = "0x24 - LPUART Modem IrDA Register"] pub modir: MODIR, + #[doc = "0x28 - LPUART FIFO Register"] pub fifo: FIFO, + #[doc = "0x2c - LPUART Watermark Register"] pub water: WATER, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpuart0/modir/mod.rs b/src/lpuart0/modir/mod.rs index 7432076..badea62 100644 --- a/src/lpuart0/modir/mod.rs +++ b/src/lpuart0/modir/mod.rs @@ -22,7 +22,9 @@ impl super::MODIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::MODIR { #[doc = "Possible values of the field `TXCTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSER { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -90,8 +91,7 @@ impl TXCTSER { #[doc = "Possible values of the field `TXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSER { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -137,10 +137,8 @@ impl TXRTSER { #[doc = "Possible values of the field `TXRTSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSPOLR { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl TXRTSPOLR { #[doc = "Possible values of the field `RXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXRTSER { - #[doc = "The receiver has no effect on RTS."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "The receiver has no effect on RTS."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl RXRTSER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl RXRTSER { #[doc = "Possible values of the field `TXCTSC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSCR { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl TXCTSCR { #[doc = "Possible values of the field `TXCTSSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSSRCR { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -331,14 +323,10 @@ impl RTSWATERR { #[doc = "Possible values of the field `TNP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TNPR { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPR { #[doc = r" Value of the field as raw bits"] @@ -387,10 +375,8 @@ impl TNPR { #[doc = "Possible values of the field `IREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRENR { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,8 +419,7 @@ impl IRENR { } #[doc = "Values that can be written to the field `TXCTSE`"] pub enum TXCTSEW { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -491,8 +476,7 @@ impl<'a> _TXCTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSE`"] pub enum TXRTSEW { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -549,10 +533,8 @@ impl<'a> _TXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSPOL`"] pub enum TXRTSPOLW { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLW { #[allow(missing_docs)] @@ -607,8 +589,7 @@ impl<'a> _TXRTSPOLW<'a> { } #[doc = "Values that can be written to the field `RXRTSE`"] pub enum RXRTSEW { - #[doc = "The receiver has no effect on RTS."] - _0, + #[doc = "The receiver has no effect on RTS."] _0, } impl RXRTSEW { #[allow(missing_docs)] @@ -657,10 +638,8 @@ impl<'a> _RXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXCTSC`"] pub enum TXCTSCW { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCW { #[allow(missing_docs)] @@ -715,10 +694,8 @@ impl<'a> _TXCTSCW<'a> { } #[doc = "Values that can be written to the field `TXCTSSRC`"] pub enum TXCTSSRCW { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCW { #[allow(missing_docs)] @@ -788,14 +765,10 @@ impl<'a> _RTSWATERW<'a> { } #[doc = "Values that can be written to the field `TNP`"] pub enum TNPW { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPW { #[allow(missing_docs)] @@ -854,10 +827,8 @@ impl<'a> _TNPW<'a> { } #[doc = "Values that can be written to the field `IREN`"] pub enum IRENW { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENW { #[allow(missing_docs)] diff --git a/src/lpuart0/param/mod.rs b/src/lpuart0/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpuart0/param/mod.rs +++ b/src/lpuart0/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpuart0/pincfg/mod.rs b/src/lpuart0/pincfg/mod.rs index c76fae5..799cd21 100644 --- a/src/lpuart0/pincfg/mod.rs +++ b/src/lpuart0/pincfg/mod.rs @@ -22,7 +22,9 @@ impl super::PINCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::PINCFG { #[doc = "Possible values of the field `TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSELR { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } @@ -98,12 +97,9 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TRGSEL`"] pub enum TRGSELW { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } diff --git a/src/lpuart0/stat/mod.rs b/src/lpuart0/stat/mod.rs index 4b96449..6a322b6 100644 --- a/src/lpuart0/stat/mod.rs +++ b/src/lpuart0/stat/mod.rs @@ -22,7 +22,9 @@ impl super::STAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::STAT { #[doc = "Possible values of the field `MA2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2FR { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MA2FR { #[doc = "Possible values of the field `MA1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1FR { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl MA1FR { #[doc = "Possible values of the field `PF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PFR { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl PFR { #[doc = "Possible values of the field `FE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FER { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FER { #[doc = "Possible values of the field `NF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NFR { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl NFR { #[doc = "Possible values of the field `OR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORR { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ORR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl IDLER { #[doc = "Possible values of the field `RDRF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDRFR { - #[doc = "Receive data buffer empty."] - _0, - #[doc = "Receive data buffer full."] - _1, + #[doc = "Receive data buffer empty."] _0, + #[doc = "Receive data buffer full."] _1, } impl RDRFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl RDRFR { #[doc = "Possible values of the field `TC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCR { - #[doc = "Transmitter active (sending data, a preamble, or a break)."] - _0, - #[doc = "Transmitter idle (transmission activity complete)."] - _1, + #[doc = "Transmitter active (sending data, a preamble, or a break)."] _0, + #[doc = "Transmitter idle (transmission activity complete)."] _1, } impl TCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl TCR { #[doc = "Possible values of the field `TDRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDRER { - #[doc = "Transmit data buffer full."] - _0, - #[doc = "Transmit data buffer empty."] - _1, + #[doc = "Transmit data buffer full."] _0, + #[doc = "Transmit data buffer empty."] _1, } impl TDRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TDRER { #[doc = "Possible values of the field `RAF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RAFR { - #[doc = "LPUART receiver idle waiting for a start bit."] - _0, - #[doc = "LPUART receiver active (RXD input not idle)."] - _1, + #[doc = "LPUART receiver idle waiting for a start bit."] _0, + #[doc = "LPUART receiver active (RXD input not idle)."] _1, } impl RAFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,8 +540,7 @@ impl RAFR { #[doc = "Possible values of the field `LBKDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDER { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -607,10 +586,8 @@ impl LBKDER { #[doc = "Possible values of the field `BRK13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BRK13R { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +678,8 @@ impl RWUIDR { #[doc = "Possible values of the field `RXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXINVR { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -795,10 +770,8 @@ impl MSBFR { #[doc = "Possible values of the field `RXEDGIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIFR { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -842,10 +815,8 @@ impl RXEDGIFR { #[doc = "Possible values of the field `LBKDIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIFR { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -888,10 +859,8 @@ impl LBKDIFR { } #[doc = "Values that can be written to the field `MA2F`"] pub enum MA2FW { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FW { #[allow(missing_docs)] @@ -946,10 +915,8 @@ impl<'a> _MA2FW<'a> { } #[doc = "Values that can be written to the field `MA1F`"] pub enum MA1FW { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FW { #[allow(missing_docs)] @@ -1004,10 +971,8 @@ impl<'a> _MA1FW<'a> { } #[doc = "Values that can be written to the field `PF`"] pub enum PFW { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFW { #[allow(missing_docs)] @@ -1062,10 +1027,8 @@ impl<'a> _PFW<'a> { } #[doc = "Values that can be written to the field `FE`"] pub enum FEW { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FEW { #[allow(missing_docs)] @@ -1120,10 +1083,8 @@ impl<'a> _FEW<'a> { } #[doc = "Values that can be written to the field `NF`"] pub enum NFW { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFW { #[allow(missing_docs)] @@ -1178,10 +1139,8 @@ impl<'a> _NFW<'a> { } #[doc = "Values that can be written to the field `OR`"] pub enum ORW { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORW { #[allow(missing_docs)] @@ -1236,10 +1195,8 @@ impl<'a> _ORW<'a> { } #[doc = "Values that can be written to the field `IDLE`"] pub enum IDLEW { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLEW { #[allow(missing_docs)] @@ -1294,8 +1251,7 @@ impl<'a> _IDLEW<'a> { } #[doc = "Values that can be written to the field `LBKDE`"] pub enum LBKDEW { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -1352,10 +1308,8 @@ impl<'a> _LBKDEW<'a> { } #[doc = "Values that can be written to the field `BRK13`"] pub enum BRK13W { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13W { #[allow(missing_docs)] @@ -1468,10 +1422,8 @@ impl<'a> _RWUIDW<'a> { } #[doc = "Values that can be written to the field `RXINV`"] pub enum RXINVW { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVW { #[allow(missing_docs)] @@ -1584,10 +1536,8 @@ impl<'a> _MSBFW<'a> { } #[doc = "Values that can be written to the field `RXEDGIF`"] pub enum RXEDGIFW { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFW { #[allow(missing_docs)] @@ -1642,10 +1592,8 @@ impl<'a> _RXEDGIFW<'a> { } #[doc = "Values that can be written to the field `LBKDIF`"] pub enum LBKDIFW { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFW { #[allow(missing_docs)] diff --git a/src/lpuart0/verid/mod.rs b/src/lpuart0/verid/mod.rs index e3f9566..647ac7a 100644 --- a/src/lpuart0/verid/mod.rs +++ b/src/lpuart0/verid/mod.rs @@ -6,18 +6,17 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set."] - _0000000000000001, - #[doc = "Standard feature set with MODEM/IrDA support."] - _0000000000000011, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set."] _0000000000000001, + #[doc = "Standard feature set with MODEM/IrDA support."] _0000000000000011, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpuart0/water/mod.rs b/src/lpuart0/water/mod.rs index 4ad84b2..b3b5898 100644 --- a/src/lpuart0/water/mod.rs +++ b/src/lpuart0/water/mod.rs @@ -22,7 +22,9 @@ impl super::WATER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpuart1/baud/mod.rs b/src/lpuart1/baud/mod.rs index fb82caa..fae2b24 100644 --- a/src/lpuart1/baud/mod.rs +++ b/src/lpuart1/baud/mod.rs @@ -22,7 +22,9 @@ impl super::BAUD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SBRR { #[doc = "Possible values of the field `SBNS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBNSR { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl SBNSR { #[doc = "Possible values of the field `RXEDGIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIER { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl RXEDGIER { #[doc = "Possible values of the field `LBKDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIER { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl LBKDIER { #[doc = "Possible values of the field `RESYNCDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RESYNCDISR { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl RESYNCDISR { #[doc = "Possible values of the field `BOTHEDGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOTHEDGER { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -289,14 +282,10 @@ impl BOTHEDGER { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -339,10 +328,8 @@ impl MATCFGR { #[doc = "Possible values of the field `RIDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,10 +373,8 @@ impl RIDMAER { #[doc = "Possible values of the field `RDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,10 +418,8 @@ impl RDMAER { #[doc = "Possible values of the field `TDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -480,68 +463,37 @@ impl TDMAER { #[doc = "Possible values of the field `OSR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OSRR { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, + #[doc = r" Reserved"] _Reserved(u8), } impl OSRR { #[doc = r" Value of the field as raw bits"] @@ -773,10 +725,8 @@ impl OSRR { #[doc = "Possible values of the field `M10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M10R { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -820,10 +770,8 @@ impl M10R { #[doc = "Possible values of the field `MAEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN2R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -867,10 +815,8 @@ impl MAEN2R { #[doc = "Possible values of the field `MAEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN1R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -928,10 +874,8 @@ impl<'a> _SBRW<'a> { } #[doc = "Values that can be written to the field `SBNS`"] pub enum SBNSW { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSW { #[allow(missing_docs)] @@ -986,10 +930,8 @@ impl<'a> _SBNSW<'a> { } #[doc = "Values that can be written to the field `RXEDGIE`"] pub enum RXEDGIEW { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIEW { #[allow(missing_docs)] @@ -1044,10 +986,8 @@ impl<'a> _RXEDGIEW<'a> { } #[doc = "Values that can be written to the field `LBKDIE`"] pub enum LBKDIEW { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIEW { #[allow(missing_docs)] @@ -1102,10 +1042,8 @@ impl<'a> _LBKDIEW<'a> { } #[doc = "Values that can be written to the field `RESYNCDIS`"] pub enum RESYNCDISW { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISW { #[allow(missing_docs)] @@ -1160,8 +1098,7 @@ impl<'a> _RESYNCDISW<'a> { } #[doc = "Values that can be written to the field `BOTHEDGE`"] pub enum BOTHEDGEW { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -1218,12 +1155,9 @@ impl<'a> _BOTHEDGEW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, } impl MATCFGW { #[allow(missing_docs)] @@ -1274,10 +1208,8 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `RIDMAE`"] pub enum RIDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAEW { #[allow(missing_docs)] @@ -1332,10 +1264,8 @@ impl<'a> _RIDMAEW<'a> { } #[doc = "Values that can be written to the field `RDMAE`"] pub enum RDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAEW { #[allow(missing_docs)] @@ -1390,10 +1320,8 @@ impl<'a> _RDMAEW<'a> { } #[doc = "Values that can be written to the field `TDMAE`"] pub enum TDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAEW { #[allow(missing_docs)] @@ -1448,66 +1376,36 @@ impl<'a> _TDMAEW<'a> { } #[doc = "Values that can be written to the field `OSR`"] pub enum OSRW { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, } impl OSRW { #[allow(missing_docs)] @@ -1720,10 +1618,8 @@ impl<'a> _OSRW<'a> { } #[doc = "Values that can be written to the field `M10`"] pub enum M10W { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10W { #[allow(missing_docs)] @@ -1778,10 +1674,8 @@ impl<'a> _M10W<'a> { } #[doc = "Values that can be written to the field `MAEN2`"] pub enum MAEN2W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2W { #[allow(missing_docs)] @@ -1836,10 +1730,8 @@ impl<'a> _MAEN2W<'a> { } #[doc = "Values that can be written to the field `MAEN1`"] pub enum MAEN1W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1W { #[allow(missing_docs)] diff --git a/src/lpuart1/ctrl/mod.rs b/src/lpuart1/ctrl/mod.rs index 98de98c..30a6612 100644 --- a/src/lpuart1/ctrl/mod.rs +++ b/src/lpuart1/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL { #[doc = "Possible values of the field `PT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PTR { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl PTR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl PER { #[doc = "Possible values of the field `ILT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILTR { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ILTR { #[doc = "Possible values of the field `WAKE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WAKER { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl WAKER { #[doc = "Possible values of the field `M`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MR { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +317,8 @@ impl RSRCR { #[doc = "Possible values of the field `DOZEEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZEENR { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,8 +362,7 @@ impl DOZEENR { #[doc = "Possible values of the field `LOOPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOOPSR { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -419,22 +408,14 @@ impl LOOPSR { #[doc = "Possible values of the field `IDLECFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLECFGR { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGR { #[doc = r" Value of the field as raw bits"] @@ -511,10 +492,8 @@ impl IDLECFGR { #[doc = "Possible values of the field `M7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M7R { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -558,10 +537,8 @@ impl M7R { #[doc = "Possible values of the field `MA2IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2IER { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -605,10 +582,8 @@ impl MA2IER { #[doc = "Possible values of the field `MA1IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1IER { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -652,10 +627,8 @@ impl MA1IER { #[doc = "Possible values of the field `SBK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBKR { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -699,10 +672,8 @@ impl SBKR { #[doc = "Possible values of the field `RWU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWUR { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -746,10 +717,8 @@ impl RWUR { #[doc = "Possible values of the field `RE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RER { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl RER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -793,10 +762,8 @@ impl RER { #[doc = "Possible values of the field `TE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TER { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -840,10 +807,8 @@ impl TER { #[doc = "Possible values of the field `ILIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILIER { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -887,10 +852,8 @@ impl ILIER { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -934,10 +897,8 @@ impl RIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -981,10 +942,8 @@ impl TCIER { #[doc = "Possible values of the field `TIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIER { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1028,10 +987,8 @@ impl TIER { #[doc = "Possible values of the field `PEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PEIER { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1075,10 +1032,8 @@ impl PEIER { #[doc = "Possible values of the field `FEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEIER { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1122,10 +1077,8 @@ impl FEIER { #[doc = "Possible values of the field `NEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NEIER { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1169,10 +1122,8 @@ impl NEIER { #[doc = "Possible values of the field `ORIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORIER { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1216,10 +1167,8 @@ impl ORIER { #[doc = "Possible values of the field `TXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXINVR { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1263,10 +1212,8 @@ impl TXINVR { #[doc = "Possible values of the field `TXDIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXDIRR { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1351,10 +1298,8 @@ impl R8T9R { } #[doc = "Values that can be written to the field `PT`"] pub enum PTW { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTW { #[allow(missing_docs)] @@ -1409,10 +1354,8 @@ impl<'a> _PTW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PEW { #[allow(missing_docs)] @@ -1467,10 +1410,8 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `ILT`"] pub enum ILTW { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTW { #[allow(missing_docs)] @@ -1525,10 +1466,8 @@ impl<'a> _ILTW<'a> { } #[doc = "Values that can be written to the field `WAKE`"] pub enum WAKEW { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKEW { #[allow(missing_docs)] @@ -1583,10 +1522,8 @@ impl<'a> _WAKEW<'a> { } #[doc = "Values that can be written to the field `M`"] pub enum MW { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MW { #[allow(missing_docs)] @@ -1699,10 +1636,8 @@ impl<'a> _RSRCW<'a> { } #[doc = "Values that can be written to the field `DOZEEN`"] pub enum DOZEENW { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENW { #[allow(missing_docs)] @@ -1757,8 +1692,7 @@ impl<'a> _DOZEENW<'a> { } #[doc = "Values that can be written to the field `LOOPS`"] pub enum LOOPSW { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -1815,22 +1749,14 @@ impl<'a> _LOOPSW<'a> { } #[doc = "Values that can be written to the field `IDLECFG`"] pub enum IDLECFGW { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGW { #[allow(missing_docs)] @@ -1913,10 +1839,8 @@ impl<'a> _IDLECFGW<'a> { } #[doc = "Values that can be written to the field `M7`"] pub enum M7W { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7W { #[allow(missing_docs)] @@ -1971,10 +1895,8 @@ impl<'a> _M7W<'a> { } #[doc = "Values that can be written to the field `MA2IE`"] pub enum MA2IEW { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IEW { #[allow(missing_docs)] @@ -2029,10 +1951,8 @@ impl<'a> _MA2IEW<'a> { } #[doc = "Values that can be written to the field `MA1IE`"] pub enum MA1IEW { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IEW { #[allow(missing_docs)] @@ -2087,10 +2007,8 @@ impl<'a> _MA1IEW<'a> { } #[doc = "Values that can be written to the field `SBK`"] pub enum SBKW { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKW { #[allow(missing_docs)] @@ -2145,10 +2063,8 @@ impl<'a> _SBKW<'a> { } #[doc = "Values that can be written to the field `RWU`"] pub enum RWUW { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUW { #[allow(missing_docs)] @@ -2203,10 +2119,8 @@ impl<'a> _RWUW<'a> { } #[doc = "Values that can be written to the field `RE`"] pub enum REW { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl REW { #[allow(missing_docs)] @@ -2261,10 +2175,8 @@ impl<'a> _REW<'a> { } #[doc = "Values that can be written to the field `TE`"] pub enum TEW { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TEW { #[allow(missing_docs)] @@ -2319,10 +2231,8 @@ impl<'a> _TEW<'a> { } #[doc = "Values that can be written to the field `ILIE`"] pub enum ILIEW { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIEW { #[allow(missing_docs)] @@ -2377,10 +2287,8 @@ impl<'a> _ILIEW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIEW { #[allow(missing_docs)] @@ -2435,10 +2343,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -2493,10 +2399,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TIE`"] pub enum TIEW { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIEW { #[allow(missing_docs)] @@ -2551,10 +2455,8 @@ impl<'a> _TIEW<'a> { } #[doc = "Values that can be written to the field `PEIE`"] pub enum PEIEW { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIEW { #[allow(missing_docs)] @@ -2609,10 +2511,8 @@ impl<'a> _PEIEW<'a> { } #[doc = "Values that can be written to the field `FEIE`"] pub enum FEIEW { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIEW { #[allow(missing_docs)] @@ -2667,10 +2567,8 @@ impl<'a> _FEIEW<'a> { } #[doc = "Values that can be written to the field `NEIE`"] pub enum NEIEW { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIEW { #[allow(missing_docs)] @@ -2725,10 +2623,8 @@ impl<'a> _NEIEW<'a> { } #[doc = "Values that can be written to the field `ORIE`"] pub enum ORIEW { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIEW { #[allow(missing_docs)] @@ -2783,10 +2679,8 @@ impl<'a> _ORIEW<'a> { } #[doc = "Values that can be written to the field `TXINV`"] pub enum TXINVW { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVW { #[allow(missing_docs)] @@ -2841,10 +2735,8 @@ impl<'a> _TXINVW<'a> { } #[doc = "Values that can be written to the field `TXDIR`"] pub enum TXDIRW { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRW { #[allow(missing_docs)] diff --git a/src/lpuart1/data/mod.rs b/src/lpuart1/data/mod.rs index 3e2e726..bf5d575 100644 --- a/src/lpuart1/data/mod.rs +++ b/src/lpuart1/data/mod.rs @@ -22,7 +22,9 @@ impl super::DATA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -253,10 +255,8 @@ impl R9T9R { #[doc = "Possible values of the field `IDLINE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLINER { - #[doc = "Receiver was not idle before receiving this character."] - _0, - #[doc = "Receiver was idle before receiving this character."] - _1, + #[doc = "Receiver was not idle before receiving this character."] _0, + #[doc = "Receiver was idle before receiving this character."] _1, } impl IDLINER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -300,10 +300,8 @@ impl IDLINER { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer contains valid data."] - _0, - #[doc = "Receive buffer is empty, data returned on read is not valid."] - _1, + #[doc = "Receive buffer contains valid data."] _0, + #[doc = "Receive buffer is empty, data returned on read is not valid."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +392,8 @@ impl FRETSCR { #[doc = "Possible values of the field `PARITYE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PARITYER { - #[doc = "The dataword was received without a parity error."] - _0, - #[doc = "The dataword was received with a parity error."] - _1, + #[doc = "The dataword was received without a parity error."] _0, + #[doc = "The dataword was received with a parity error."] _1, } impl PARITYER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +437,8 @@ impl PARITYER { #[doc = "Possible values of the field `NOISY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOISYR { - #[doc = "The dataword was received without noise."] - _0, - #[doc = "The data was received with noise."] - _1, + #[doc = "The dataword was received without noise."] _0, + #[doc = "The data was received with noise."] _1, } impl NOISYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpuart1/fifo/mod.rs b/src/lpuart1/fifo/mod.rs index 7ce5dd2..1ca8b00 100644 --- a/src/lpuart1/fifo/mod.rs +++ b/src/lpuart1/fifo/mod.rs @@ -22,7 +22,9 @@ impl super::FIFO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::FIFO { #[doc = "Possible values of the field `RXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFIFOSIZER { - #[doc = "Receive FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Receive FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Receive FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Receive FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Receive FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Receive FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Receive FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Receive FIFO/Buffer depth = 256 datawords."] - _111, + #[doc = "Receive FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Receive FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Receive FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Receive FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Receive FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Receive FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Receive FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Receive FIFO/Buffer depth = 256 datawords."] _111, } impl RXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl RXFIFOSIZER { #[doc = "Possible values of the field `RXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFER { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,22 +174,14 @@ impl RXFER { #[doc = "Possible values of the field `TXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFIFOSIZER { - #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] - _111, + #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] _111, } impl TXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -274,10 +258,8 @@ impl TXFIFOSIZER { #[doc = "Possible values of the field `TXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFER { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -321,10 +303,8 @@ impl TXFER { #[doc = "Possible values of the field `RXUFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFER { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -368,10 +348,8 @@ impl RXUFER { #[doc = "Possible values of the field `TXOFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFER { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -415,8 +393,7 @@ impl TXOFER { #[doc = "Possible values of the field `RXIDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXIDENR { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -507,8 +484,7 @@ impl RXIDENR { #[doc = "Possible values of the field `RXUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFR { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -554,8 +530,7 @@ impl RXUFR { #[doc = "Possible values of the field `TXOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFR { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } @@ -601,10 +576,8 @@ impl TXOFR { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer is not empty."] - _0, - #[doc = "Receive buffer is empty."] - _1, + #[doc = "Receive buffer is not empty."] _0, + #[doc = "Receive buffer is empty."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +621,8 @@ impl RXEMPTR { #[doc = "Possible values of the field `TXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXEMPTR { - #[doc = "Transmit buffer is not empty."] - _0, - #[doc = "Transmit buffer is empty."] - _1, + #[doc = "Transmit buffer is not empty."] _0, + #[doc = "Transmit buffer is empty."] _1, } impl TXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -694,10 +665,8 @@ impl TXEMPTR { } #[doc = "Values that can be written to the field `RXFE`"] pub enum RXFEW { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFEW { #[allow(missing_docs)] @@ -752,10 +721,8 @@ impl<'a> _RXFEW<'a> { } #[doc = "Values that can be written to the field `TXFE`"] pub enum TXFEW { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFEW { #[allow(missing_docs)] @@ -810,10 +777,8 @@ impl<'a> _TXFEW<'a> { } #[doc = "Values that can be written to the field `RXUFE`"] pub enum RXUFEW { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFEW { #[allow(missing_docs)] @@ -868,10 +833,8 @@ impl<'a> _RXUFEW<'a> { } #[doc = "Values that can be written to the field `TXOFE`"] pub enum TXOFEW { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFEW { #[allow(missing_docs)] @@ -926,8 +889,7 @@ impl<'a> _TXOFEW<'a> { } #[doc = "Values that can be written to the field `RXIDEN`"] pub enum RXIDENW { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -1024,10 +986,8 @@ impl<'a> _RXIDENW<'a> { } #[doc = "Values that can be written to the field `RXFLUSH`"] pub enum RXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the receive FIFO/buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the receive FIFO/buffer is cleared out."] _1, } impl RXFLUSHW { #[allow(missing_docs)] @@ -1082,10 +1042,8 @@ impl<'a> _RXFLUSHW<'a> { } #[doc = "Values that can be written to the field `TXFLUSH`"] pub enum TXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the transmit FIFO/Buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the transmit FIFO/Buffer is cleared out."] _1, } impl TXFLUSHW { #[allow(missing_docs)] @@ -1140,8 +1098,7 @@ impl<'a> _TXFLUSHW<'a> { } #[doc = "Values that can be written to the field `RXUF`"] pub enum RXUFW { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -1198,8 +1155,7 @@ impl<'a> _RXUFW<'a> { } #[doc = "Values that can be written to the field `TXOF`"] pub enum TXOFW { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } diff --git a/src/lpuart1/global/mod.rs b/src/lpuart1/global/mod.rs index d481688..ab15f12 100644 --- a/src/lpuart1/global/mod.rs +++ b/src/lpuart1/global/mod.rs @@ -22,7 +22,9 @@ impl super::GLOBAL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::GLOBAL { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl RSTR { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTW { #[allow(missing_docs)] diff --git a/src/lpuart1/match_/mod.rs b/src/lpuart1/match_/mod.rs index 3bbca15..ccaf148 100644 --- a/src/lpuart1/match_/mod.rs +++ b/src/lpuart1/match_/mod.rs @@ -22,7 +22,9 @@ impl super::MATCH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpuart1/mod.rs b/src/lpuart1/mod.rs index fdbf7c0..d0eca48 100644 --- a/src/lpuart1/mod.rs +++ b/src/lpuart1/mod.rs @@ -2,30 +2,18 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - LPUART Global Register"] - pub global: GLOBAL, - #[doc = "0x0c - LPUART Pin Configuration Register"] - pub pincfg: PINCFG, - #[doc = "0x10 - LPUART Baud Rate Register"] - pub baud: BAUD, - #[doc = "0x14 - LPUART Status Register"] - pub stat: STAT, - #[doc = "0x18 - LPUART Control Register"] - pub ctrl: CTRL, - #[doc = "0x1c - LPUART Data Register"] - pub data: DATA, - #[doc = "0x20 - LPUART Match Address Register"] - pub match_: MATCH, - #[doc = "0x24 - LPUART Modem IrDA Register"] - pub modir: MODIR, - #[doc = "0x28 - LPUART FIFO Register"] - pub fifo: FIFO, - #[doc = "0x2c - LPUART Watermark Register"] - pub water: WATER, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - LPUART Global Register"] pub global: GLOBAL, + #[doc = "0x0c - LPUART Pin Configuration Register"] pub pincfg: PINCFG, + #[doc = "0x10 - LPUART Baud Rate Register"] pub baud: BAUD, + #[doc = "0x14 - LPUART Status Register"] pub stat: STAT, + #[doc = "0x18 - LPUART Control Register"] pub ctrl: CTRL, + #[doc = "0x1c - LPUART Data Register"] pub data: DATA, + #[doc = "0x20 - LPUART Match Address Register"] pub match_: MATCH, + #[doc = "0x24 - LPUART Modem IrDA Register"] pub modir: MODIR, + #[doc = "0x28 - LPUART FIFO Register"] pub fifo: FIFO, + #[doc = "0x2c - LPUART Watermark Register"] pub water: WATER, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpuart1/modir/mod.rs b/src/lpuart1/modir/mod.rs index 7432076..badea62 100644 --- a/src/lpuart1/modir/mod.rs +++ b/src/lpuart1/modir/mod.rs @@ -22,7 +22,9 @@ impl super::MODIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::MODIR { #[doc = "Possible values of the field `TXCTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSER { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -90,8 +91,7 @@ impl TXCTSER { #[doc = "Possible values of the field `TXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSER { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -137,10 +137,8 @@ impl TXRTSER { #[doc = "Possible values of the field `TXRTSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSPOLR { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl TXRTSPOLR { #[doc = "Possible values of the field `RXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXRTSER { - #[doc = "The receiver has no effect on RTS."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "The receiver has no effect on RTS."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl RXRTSER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl RXRTSER { #[doc = "Possible values of the field `TXCTSC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSCR { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl TXCTSCR { #[doc = "Possible values of the field `TXCTSSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSSRCR { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -331,14 +323,10 @@ impl RTSWATERR { #[doc = "Possible values of the field `TNP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TNPR { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPR { #[doc = r" Value of the field as raw bits"] @@ -387,10 +375,8 @@ impl TNPR { #[doc = "Possible values of the field `IREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRENR { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,8 +419,7 @@ impl IRENR { } #[doc = "Values that can be written to the field `TXCTSE`"] pub enum TXCTSEW { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -491,8 +476,7 @@ impl<'a> _TXCTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSE`"] pub enum TXRTSEW { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -549,10 +533,8 @@ impl<'a> _TXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSPOL`"] pub enum TXRTSPOLW { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLW { #[allow(missing_docs)] @@ -607,8 +589,7 @@ impl<'a> _TXRTSPOLW<'a> { } #[doc = "Values that can be written to the field `RXRTSE`"] pub enum RXRTSEW { - #[doc = "The receiver has no effect on RTS."] - _0, + #[doc = "The receiver has no effect on RTS."] _0, } impl RXRTSEW { #[allow(missing_docs)] @@ -657,10 +638,8 @@ impl<'a> _RXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXCTSC`"] pub enum TXCTSCW { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCW { #[allow(missing_docs)] @@ -715,10 +694,8 @@ impl<'a> _TXCTSCW<'a> { } #[doc = "Values that can be written to the field `TXCTSSRC`"] pub enum TXCTSSRCW { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCW { #[allow(missing_docs)] @@ -788,14 +765,10 @@ impl<'a> _RTSWATERW<'a> { } #[doc = "Values that can be written to the field `TNP`"] pub enum TNPW { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPW { #[allow(missing_docs)] @@ -854,10 +827,8 @@ impl<'a> _TNPW<'a> { } #[doc = "Values that can be written to the field `IREN`"] pub enum IRENW { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENW { #[allow(missing_docs)] diff --git a/src/lpuart1/param/mod.rs b/src/lpuart1/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpuart1/param/mod.rs +++ b/src/lpuart1/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpuart1/pincfg/mod.rs b/src/lpuart1/pincfg/mod.rs index c76fae5..799cd21 100644 --- a/src/lpuart1/pincfg/mod.rs +++ b/src/lpuart1/pincfg/mod.rs @@ -22,7 +22,9 @@ impl super::PINCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::PINCFG { #[doc = "Possible values of the field `TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSELR { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } @@ -98,12 +97,9 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TRGSEL`"] pub enum TRGSELW { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } diff --git a/src/lpuart1/stat/mod.rs b/src/lpuart1/stat/mod.rs index 4b96449..6a322b6 100644 --- a/src/lpuart1/stat/mod.rs +++ b/src/lpuart1/stat/mod.rs @@ -22,7 +22,9 @@ impl super::STAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::STAT { #[doc = "Possible values of the field `MA2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2FR { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MA2FR { #[doc = "Possible values of the field `MA1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1FR { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl MA1FR { #[doc = "Possible values of the field `PF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PFR { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl PFR { #[doc = "Possible values of the field `FE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FER { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FER { #[doc = "Possible values of the field `NF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NFR { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl NFR { #[doc = "Possible values of the field `OR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORR { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ORR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl IDLER { #[doc = "Possible values of the field `RDRF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDRFR { - #[doc = "Receive data buffer empty."] - _0, - #[doc = "Receive data buffer full."] - _1, + #[doc = "Receive data buffer empty."] _0, + #[doc = "Receive data buffer full."] _1, } impl RDRFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl RDRFR { #[doc = "Possible values of the field `TC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCR { - #[doc = "Transmitter active (sending data, a preamble, or a break)."] - _0, - #[doc = "Transmitter idle (transmission activity complete)."] - _1, + #[doc = "Transmitter active (sending data, a preamble, or a break)."] _0, + #[doc = "Transmitter idle (transmission activity complete)."] _1, } impl TCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl TCR { #[doc = "Possible values of the field `TDRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDRER { - #[doc = "Transmit data buffer full."] - _0, - #[doc = "Transmit data buffer empty."] - _1, + #[doc = "Transmit data buffer full."] _0, + #[doc = "Transmit data buffer empty."] _1, } impl TDRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TDRER { #[doc = "Possible values of the field `RAF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RAFR { - #[doc = "LPUART receiver idle waiting for a start bit."] - _0, - #[doc = "LPUART receiver active (RXD input not idle)."] - _1, + #[doc = "LPUART receiver idle waiting for a start bit."] _0, + #[doc = "LPUART receiver active (RXD input not idle)."] _1, } impl RAFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,8 +540,7 @@ impl RAFR { #[doc = "Possible values of the field `LBKDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDER { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -607,10 +586,8 @@ impl LBKDER { #[doc = "Possible values of the field `BRK13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BRK13R { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +678,8 @@ impl RWUIDR { #[doc = "Possible values of the field `RXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXINVR { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -795,10 +770,8 @@ impl MSBFR { #[doc = "Possible values of the field `RXEDGIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIFR { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -842,10 +815,8 @@ impl RXEDGIFR { #[doc = "Possible values of the field `LBKDIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIFR { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -888,10 +859,8 @@ impl LBKDIFR { } #[doc = "Values that can be written to the field `MA2F`"] pub enum MA2FW { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FW { #[allow(missing_docs)] @@ -946,10 +915,8 @@ impl<'a> _MA2FW<'a> { } #[doc = "Values that can be written to the field `MA1F`"] pub enum MA1FW { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FW { #[allow(missing_docs)] @@ -1004,10 +971,8 @@ impl<'a> _MA1FW<'a> { } #[doc = "Values that can be written to the field `PF`"] pub enum PFW { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFW { #[allow(missing_docs)] @@ -1062,10 +1027,8 @@ impl<'a> _PFW<'a> { } #[doc = "Values that can be written to the field `FE`"] pub enum FEW { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FEW { #[allow(missing_docs)] @@ -1120,10 +1083,8 @@ impl<'a> _FEW<'a> { } #[doc = "Values that can be written to the field `NF`"] pub enum NFW { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFW { #[allow(missing_docs)] @@ -1178,10 +1139,8 @@ impl<'a> _NFW<'a> { } #[doc = "Values that can be written to the field `OR`"] pub enum ORW { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORW { #[allow(missing_docs)] @@ -1236,10 +1195,8 @@ impl<'a> _ORW<'a> { } #[doc = "Values that can be written to the field `IDLE`"] pub enum IDLEW { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLEW { #[allow(missing_docs)] @@ -1294,8 +1251,7 @@ impl<'a> _IDLEW<'a> { } #[doc = "Values that can be written to the field `LBKDE`"] pub enum LBKDEW { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -1352,10 +1308,8 @@ impl<'a> _LBKDEW<'a> { } #[doc = "Values that can be written to the field `BRK13`"] pub enum BRK13W { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13W { #[allow(missing_docs)] @@ -1468,10 +1422,8 @@ impl<'a> _RWUIDW<'a> { } #[doc = "Values that can be written to the field `RXINV`"] pub enum RXINVW { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVW { #[allow(missing_docs)] @@ -1584,10 +1536,8 @@ impl<'a> _MSBFW<'a> { } #[doc = "Values that can be written to the field `RXEDGIF`"] pub enum RXEDGIFW { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFW { #[allow(missing_docs)] @@ -1642,10 +1592,8 @@ impl<'a> _RXEDGIFW<'a> { } #[doc = "Values that can be written to the field `LBKDIF`"] pub enum LBKDIFW { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFW { #[allow(missing_docs)] diff --git a/src/lpuart1/verid/mod.rs b/src/lpuart1/verid/mod.rs index e3f9566..647ac7a 100644 --- a/src/lpuart1/verid/mod.rs +++ b/src/lpuart1/verid/mod.rs @@ -6,18 +6,17 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set."] - _0000000000000001, - #[doc = "Standard feature set with MODEM/IrDA support."] - _0000000000000011, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set."] _0000000000000001, + #[doc = "Standard feature set with MODEM/IrDA support."] _0000000000000011, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpuart1/water/mod.rs b/src/lpuart1/water/mod.rs index 4ad84b2..b3b5898 100644 --- a/src/lpuart1/water/mod.rs +++ b/src/lpuart1/water/mod.rs @@ -22,7 +22,9 @@ impl super::WATER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpuart2/baud/mod.rs b/src/lpuart2/baud/mod.rs index fb82caa..fae2b24 100644 --- a/src/lpuart2/baud/mod.rs +++ b/src/lpuart2/baud/mod.rs @@ -22,7 +22,9 @@ impl super::BAUD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SBRR { #[doc = "Possible values of the field `SBNS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBNSR { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -101,10 +101,8 @@ impl SBNSR { #[doc = "Possible values of the field `RXEDGIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIER { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -148,10 +146,8 @@ impl RXEDGIER { #[doc = "Possible values of the field `LBKDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIER { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -195,10 +191,8 @@ impl LBKDIER { #[doc = "Possible values of the field `RESYNCDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RESYNCDISR { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -242,8 +236,7 @@ impl RESYNCDISR { #[doc = "Possible values of the field `BOTHEDGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BOTHEDGER { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -289,14 +282,10 @@ impl BOTHEDGER { #[doc = "Possible values of the field `MATCFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MATCFGR { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl MATCFGR { #[doc = r" Value of the field as raw bits"] @@ -339,10 +328,8 @@ impl MATCFGR { #[doc = "Possible values of the field `RIDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -386,10 +373,8 @@ impl RIDMAER { #[doc = "Possible values of the field `RDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,10 +418,8 @@ impl RDMAER { #[doc = "Possible values of the field `TDMAE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDMAER { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -480,68 +463,37 @@ impl TDMAER { #[doc = "Possible values of the field `OSR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OSRR { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, + #[doc = r" Reserved"] _Reserved(u8), } impl OSRR { #[doc = r" Value of the field as raw bits"] @@ -773,10 +725,8 @@ impl OSRR { #[doc = "Possible values of the field `M10`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M10R { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -820,10 +770,8 @@ impl M10R { #[doc = "Possible values of the field `MAEN2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN2R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -867,10 +815,8 @@ impl MAEN2R { #[doc = "Possible values of the field `MAEN1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MAEN1R { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -928,10 +874,8 @@ impl<'a> _SBRW<'a> { } #[doc = "Values that can be written to the field `SBNS`"] pub enum SBNSW { - #[doc = "One stop bit."] - _0, - #[doc = "Two stop bits."] - _1, + #[doc = "One stop bit."] _0, + #[doc = "Two stop bits."] _1, } impl SBNSW { #[allow(missing_docs)] @@ -986,10 +930,8 @@ impl<'a> _SBNSW<'a> { } #[doc = "Values that can be written to the field `RXEDGIE`"] pub enum RXEDGIEW { - #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[RXEDGIF] disabled."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1."] _1, } impl RXEDGIEW { #[allow(missing_docs)] @@ -1044,10 +986,8 @@ impl<'a> _RXEDGIEW<'a> { } #[doc = "Values that can be written to the field `LBKDIE`"] pub enum LBKDIEW { - #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] - _0, - #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] - _1, + #[doc = "Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling)."] _0, + #[doc = "Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1."] _1, } impl LBKDIEW { #[allow(missing_docs)] @@ -1102,10 +1042,8 @@ impl<'a> _LBKDIEW<'a> { } #[doc = "Values that can be written to the field `RESYNCDIS`"] pub enum RESYNCDISW { - #[doc = "Resynchronization during received data word is supported"] - _0, - #[doc = "Resynchronization during received data word is disabled"] - _1, + #[doc = "Resynchronization during received data word is supported"] _0, + #[doc = "Resynchronization during received data word is disabled"] _1, } impl RESYNCDISW { #[allow(missing_docs)] @@ -1160,8 +1098,7 @@ impl<'a> _RESYNCDISW<'a> { } #[doc = "Values that can be written to the field `BOTHEDGE`"] pub enum BOTHEDGEW { - #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] - _0, + #[doc = "Receiver samples input data using the rising edge of the baud rate clock."] _0, #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."] _1, } @@ -1218,12 +1155,9 @@ impl<'a> _BOTHEDGEW<'a> { } #[doc = "Values that can be written to the field `MATCFG`"] pub enum MATCFGW { - #[doc = "Address Match Wakeup"] - _00, - #[doc = "Idle Match Wakeup"] - _01, - #[doc = "Match On and Match Off"] - _10, + #[doc = "Address Match Wakeup"] _00, + #[doc = "Idle Match Wakeup"] _01, + #[doc = "Match On and Match Off"] _10, } impl MATCFGW { #[allow(missing_docs)] @@ -1274,10 +1208,8 @@ impl<'a> _MATCFGW<'a> { } #[doc = "Values that can be written to the field `RIDMAE`"] pub enum RIDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RIDMAEW { #[allow(missing_docs)] @@ -1332,10 +1264,8 @@ impl<'a> _RIDMAEW<'a> { } #[doc = "Values that can be written to the field `RDMAE`"] pub enum RDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl RDMAEW { #[allow(missing_docs)] @@ -1390,10 +1320,8 @@ impl<'a> _RDMAEW<'a> { } #[doc = "Values that can be written to the field `TDMAE`"] pub enum TDMAEW { - #[doc = "DMA request disabled."] - _0, - #[doc = "DMA request enabled."] - _1, + #[doc = "DMA request disabled."] _0, + #[doc = "DMA request enabled."] _1, } impl TDMAEW { #[allow(missing_docs)] @@ -1448,66 +1376,36 @@ impl<'a> _TDMAEW<'a> { } #[doc = "Values that can be written to the field `OSR`"] pub enum OSRW { - #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] - _00000, - #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] - _00011, - #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] - _00100, - #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] - _00101, - #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] - _00110, - #[doc = "Oversampling ratio of 8."] - _00111, - #[doc = "Oversampling ratio of 9."] - _01000, - #[doc = "Oversampling ratio of 10."] - _01001, - #[doc = "Oversampling ratio of 11."] - _01010, - #[doc = "Oversampling ratio of 12."] - _01011, - #[doc = "Oversampling ratio of 13."] - _01100, - #[doc = "Oversampling ratio of 14."] - _01101, - #[doc = "Oversampling ratio of 15."] - _01110, - #[doc = "Oversampling ratio of 16."] - _01111, - #[doc = "Oversampling ratio of 17."] - _10000, - #[doc = "Oversampling ratio of 18."] - _10001, - #[doc = "Oversampling ratio of 19."] - _10010, - #[doc = "Oversampling ratio of 20."] - _10011, - #[doc = "Oversampling ratio of 21."] - _10100, - #[doc = "Oversampling ratio of 22."] - _10101, - #[doc = "Oversampling ratio of 23."] - _10110, - #[doc = "Oversampling ratio of 24."] - _10111, - #[doc = "Oversampling ratio of 25."] - _11000, - #[doc = "Oversampling ratio of 26."] - _11001, - #[doc = "Oversampling ratio of 27."] - _11010, - #[doc = "Oversampling ratio of 28."] - _11011, - #[doc = "Oversampling ratio of 29."] - _11100, - #[doc = "Oversampling ratio of 30."] - _11101, - #[doc = "Oversampling ratio of 31."] - _11110, - #[doc = "Oversampling ratio of 32."] - _11111, + #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"] _00000, + #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."] _00011, + #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."] _00100, + #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."] _00101, + #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."] _00110, + #[doc = "Oversampling ratio of 8."] _00111, + #[doc = "Oversampling ratio of 9."] _01000, + #[doc = "Oversampling ratio of 10."] _01001, + #[doc = "Oversampling ratio of 11."] _01010, + #[doc = "Oversampling ratio of 12."] _01011, + #[doc = "Oversampling ratio of 13."] _01100, + #[doc = "Oversampling ratio of 14."] _01101, + #[doc = "Oversampling ratio of 15."] _01110, + #[doc = "Oversampling ratio of 16."] _01111, + #[doc = "Oversampling ratio of 17."] _10000, + #[doc = "Oversampling ratio of 18."] _10001, + #[doc = "Oversampling ratio of 19."] _10010, + #[doc = "Oversampling ratio of 20."] _10011, + #[doc = "Oversampling ratio of 21."] _10100, + #[doc = "Oversampling ratio of 22."] _10101, + #[doc = "Oversampling ratio of 23."] _10110, + #[doc = "Oversampling ratio of 24."] _10111, + #[doc = "Oversampling ratio of 25."] _11000, + #[doc = "Oversampling ratio of 26."] _11001, + #[doc = "Oversampling ratio of 27."] _11010, + #[doc = "Oversampling ratio of 28."] _11011, + #[doc = "Oversampling ratio of 29."] _11100, + #[doc = "Oversampling ratio of 30."] _11101, + #[doc = "Oversampling ratio of 31."] _11110, + #[doc = "Oversampling ratio of 32."] _11111, } impl OSRW { #[allow(missing_docs)] @@ -1720,10 +1618,8 @@ impl<'a> _OSRW<'a> { } #[doc = "Values that can be written to the field `M10`"] pub enum M10W { - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 10-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."] _0, + #[doc = "Receiver and transmitter use 10-bit data characters."] _1, } impl M10W { #[allow(missing_docs)] @@ -1778,10 +1674,8 @@ impl<'a> _M10W<'a> { } #[doc = "Values that can be written to the field `MAEN2`"] pub enum MAEN2W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA2]."] _1, } impl MAEN2W { #[allow(missing_docs)] @@ -1836,10 +1730,8 @@ impl<'a> _MAEN2W<'a> { } #[doc = "Values that can be written to the field `MAEN1`"] pub enum MAEN1W { - #[doc = "Normal operation."] - _0, - #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] - _1, + #[doc = "Normal operation."] _0, + #[doc = "Enables automatic address matching or data matching mode for MATCH[MA1]."] _1, } impl MAEN1W { #[allow(missing_docs)] diff --git a/src/lpuart2/ctrl/mod.rs b/src/lpuart2/ctrl/mod.rs index 98de98c..30a6612 100644 --- a/src/lpuart2/ctrl/mod.rs +++ b/src/lpuart2/ctrl/mod.rs @@ -22,7 +22,9 @@ impl super::CTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CTRL { #[doc = "Possible values of the field `PT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PTR { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl PTR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl PER { #[doc = "Possible values of the field `ILT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILTR { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl ILTR { #[doc = "Possible values of the field `WAKE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WAKER { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl WAKER { #[doc = "Possible values of the field `M`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MR { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +317,8 @@ impl RSRCR { #[doc = "Possible values of the field `DOZEEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DOZEENR { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,8 +362,7 @@ impl DOZEENR { #[doc = "Possible values of the field `LOOPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOOPSR { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -419,22 +408,14 @@ impl LOOPSR { #[doc = "Possible values of the field `IDLECFG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLECFGR { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGR { #[doc = r" Value of the field as raw bits"] @@ -511,10 +492,8 @@ impl IDLECFGR { #[doc = "Possible values of the field `M7`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum M7R { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -558,10 +537,8 @@ impl M7R { #[doc = "Possible values of the field `MA2IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2IER { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -605,10 +582,8 @@ impl MA2IER { #[doc = "Possible values of the field `MA1IE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1IER { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -652,10 +627,8 @@ impl MA1IER { #[doc = "Possible values of the field `SBK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SBKR { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -699,10 +672,8 @@ impl SBKR { #[doc = "Possible values of the field `RWU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RWUR { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -746,10 +717,8 @@ impl RWUR { #[doc = "Possible values of the field `RE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RER { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl RER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -793,10 +762,8 @@ impl RER { #[doc = "Possible values of the field `TE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TER { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -840,10 +807,8 @@ impl TER { #[doc = "Possible values of the field `ILIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ILIER { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -887,10 +852,8 @@ impl ILIER { #[doc = "Possible values of the field `RIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RIER { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -934,10 +897,8 @@ impl RIER { #[doc = "Possible values of the field `TCIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCIER { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -981,10 +942,8 @@ impl TCIER { #[doc = "Possible values of the field `TIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIER { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1028,10 +987,8 @@ impl TIER { #[doc = "Possible values of the field `PEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PEIER { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1075,10 +1032,8 @@ impl PEIER { #[doc = "Possible values of the field `FEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEIER { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1122,10 +1077,8 @@ impl FEIER { #[doc = "Possible values of the field `NEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NEIER { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1169,10 +1122,8 @@ impl NEIER { #[doc = "Possible values of the field `ORIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORIER { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1216,10 +1167,8 @@ impl ORIER { #[doc = "Possible values of the field `TXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXINVR { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1263,10 +1212,8 @@ impl TXINVR { #[doc = "Possible values of the field `TXDIR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXDIRR { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -1351,10 +1298,8 @@ impl R8T9R { } #[doc = "Values that can be written to the field `PT`"] pub enum PTW { - #[doc = "Even parity."] - _0, - #[doc = "Odd parity."] - _1, + #[doc = "Even parity."] _0, + #[doc = "Odd parity."] _1, } impl PTW { #[allow(missing_docs)] @@ -1409,10 +1354,8 @@ impl<'a> _PTW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "No hardware parity generation or checking."] - _0, - #[doc = "Parity enabled."] - _1, + #[doc = "No hardware parity generation or checking."] _0, + #[doc = "Parity enabled."] _1, } impl PEW { #[allow(missing_docs)] @@ -1467,10 +1410,8 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `ILT`"] pub enum ILTW { - #[doc = "Idle character bit count starts after start bit."] - _0, - #[doc = "Idle character bit count starts after stop bit."] - _1, + #[doc = "Idle character bit count starts after start bit."] _0, + #[doc = "Idle character bit count starts after stop bit."] _1, } impl ILTW { #[allow(missing_docs)] @@ -1525,10 +1466,8 @@ impl<'a> _ILTW<'a> { } #[doc = "Values that can be written to the field `WAKE`"] pub enum WAKEW { - #[doc = "Configures RWU for idle-line wakeup."] - _0, - #[doc = "Configures RWU with address-mark wakeup."] - _1, + #[doc = "Configures RWU for idle-line wakeup."] _0, + #[doc = "Configures RWU with address-mark wakeup."] _1, } impl WAKEW { #[allow(missing_docs)] @@ -1583,10 +1522,8 @@ impl<'a> _WAKEW<'a> { } #[doc = "Values that can be written to the field `M`"] pub enum MW { - #[doc = "Receiver and transmitter use 8-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 9-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit data characters."] _0, + #[doc = "Receiver and transmitter use 9-bit data characters."] _1, } impl MW { #[allow(missing_docs)] @@ -1699,10 +1636,8 @@ impl<'a> _RSRCW<'a> { } #[doc = "Values that can be written to the field `DOZEEN`"] pub enum DOZEENW { - #[doc = "LPUART is enabled in Doze mode."] - _0, - #[doc = "LPUART is disabled in Doze mode."] - _1, + #[doc = "LPUART is enabled in Doze mode."] _0, + #[doc = "LPUART is disabled in Doze mode."] _1, } impl DOZEENW { #[allow(missing_docs)] @@ -1757,8 +1692,7 @@ impl<'a> _DOZEENW<'a> { } #[doc = "Values that can be written to the field `LOOPS`"] pub enum LOOPSW { - #[doc = "Normal operation - RXD and TXD use separate pins."] - _0, + #[doc = "Normal operation - RXD and TXD use separate pins."] _0, #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."] _1, } @@ -1815,22 +1749,14 @@ impl<'a> _LOOPSW<'a> { } #[doc = "Values that can be written to the field `IDLECFG`"] pub enum IDLECFGW { - #[doc = "1 idle character"] - _000, - #[doc = "2 idle characters"] - _001, - #[doc = "4 idle characters"] - _010, - #[doc = "8 idle characters"] - _011, - #[doc = "16 idle characters"] - _100, - #[doc = "32 idle characters"] - _101, - #[doc = "64 idle characters"] - _110, - #[doc = "128 idle characters"] - _111, + #[doc = "1 idle character"] _000, + #[doc = "2 idle characters"] _001, + #[doc = "4 idle characters"] _010, + #[doc = "8 idle characters"] _011, + #[doc = "16 idle characters"] _100, + #[doc = "32 idle characters"] _101, + #[doc = "64 idle characters"] _110, + #[doc = "128 idle characters"] _111, } impl IDLECFGW { #[allow(missing_docs)] @@ -1913,10 +1839,8 @@ impl<'a> _IDLECFGW<'a> { } #[doc = "Values that can be written to the field `M7`"] pub enum M7W { - #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] - _0, - #[doc = "Receiver and transmitter use 7-bit data characters."] - _1, + #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."] _0, + #[doc = "Receiver and transmitter use 7-bit data characters."] _1, } impl M7W { #[allow(missing_docs)] @@ -1971,10 +1895,8 @@ impl<'a> _M7W<'a> { } #[doc = "Values that can be written to the field `MA2IE`"] pub enum MA2IEW { - #[doc = "MA2F interrupt disabled"] - _0, - #[doc = "MA2F interrupt enabled"] - _1, + #[doc = "MA2F interrupt disabled"] _0, + #[doc = "MA2F interrupt enabled"] _1, } impl MA2IEW { #[allow(missing_docs)] @@ -2029,10 +1951,8 @@ impl<'a> _MA2IEW<'a> { } #[doc = "Values that can be written to the field `MA1IE`"] pub enum MA1IEW { - #[doc = "MA1F interrupt disabled"] - _0, - #[doc = "MA1F interrupt enabled"] - _1, + #[doc = "MA1F interrupt disabled"] _0, + #[doc = "MA1F interrupt enabled"] _1, } impl MA1IEW { #[allow(missing_docs)] @@ -2087,10 +2007,8 @@ impl<'a> _MA1IEW<'a> { } #[doc = "Values that can be written to the field `SBK`"] pub enum SBKW { - #[doc = "Normal transmitter operation."] - _0, - #[doc = "Queue break character(s) to be sent."] - _1, + #[doc = "Normal transmitter operation."] _0, + #[doc = "Queue break character(s) to be sent."] _1, } impl SBKW { #[allow(missing_docs)] @@ -2145,10 +2063,8 @@ impl<'a> _SBKW<'a> { } #[doc = "Values that can be written to the field `RWU`"] pub enum RWUW { - #[doc = "Normal receiver operation."] - _0, - #[doc = "LPUART receiver in standby waiting for wakeup condition."] - _1, + #[doc = "Normal receiver operation."] _0, + #[doc = "LPUART receiver in standby waiting for wakeup condition."] _1, } impl RWUW { #[allow(missing_docs)] @@ -2203,10 +2119,8 @@ impl<'a> _RWUW<'a> { } #[doc = "Values that can be written to the field `RE`"] pub enum REW { - #[doc = "Receiver disabled."] - _0, - #[doc = "Receiver enabled."] - _1, + #[doc = "Receiver disabled."] _0, + #[doc = "Receiver enabled."] _1, } impl REW { #[allow(missing_docs)] @@ -2261,10 +2175,8 @@ impl<'a> _REW<'a> { } #[doc = "Values that can be written to the field `TE`"] pub enum TEW { - #[doc = "Transmitter disabled."] - _0, - #[doc = "Transmitter enabled."] - _1, + #[doc = "Transmitter disabled."] _0, + #[doc = "Transmitter enabled."] _1, } impl TEW { #[allow(missing_docs)] @@ -2319,10 +2231,8 @@ impl<'a> _TEW<'a> { } #[doc = "Values that can be written to the field `ILIE`"] pub enum ILIEW { - #[doc = "Hardware interrupts from IDLE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when IDLE flag is 1."] - _1, + #[doc = "Hardware interrupts from IDLE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when IDLE flag is 1."] _1, } impl ILIEW { #[allow(missing_docs)] @@ -2377,10 +2287,8 @@ impl<'a> _ILIEW<'a> { } #[doc = "Values that can be written to the field `RIE`"] pub enum RIEW { - #[doc = "Hardware interrupts from RDRF disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when RDRF flag is 1."] - _1, + #[doc = "Hardware interrupts from RDRF disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when RDRF flag is 1."] _1, } impl RIEW { #[allow(missing_docs)] @@ -2435,10 +2343,8 @@ impl<'a> _RIEW<'a> { } #[doc = "Values that can be written to the field `TCIE`"] pub enum TCIEW { - #[doc = "Hardware interrupts from TC disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TC flag is 1."] - _1, + #[doc = "Hardware interrupts from TC disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TC flag is 1."] _1, } impl TCIEW { #[allow(missing_docs)] @@ -2493,10 +2399,8 @@ impl<'a> _TCIEW<'a> { } #[doc = "Values that can be written to the field `TIE`"] pub enum TIEW { - #[doc = "Hardware interrupts from TDRE disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when TDRE flag is 1."] - _1, + #[doc = "Hardware interrupts from TDRE disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when TDRE flag is 1."] _1, } impl TIEW { #[allow(missing_docs)] @@ -2551,10 +2455,8 @@ impl<'a> _TIEW<'a> { } #[doc = "Values that can be written to the field `PEIE`"] pub enum PEIEW { - #[doc = "PF interrupts disabled; use polling)."] - _0, - #[doc = "Hardware interrupt requested when PF is set."] - _1, + #[doc = "PF interrupts disabled; use polling)."] _0, + #[doc = "Hardware interrupt requested when PF is set."] _1, } impl PEIEW { #[allow(missing_docs)] @@ -2609,10 +2511,8 @@ impl<'a> _PEIEW<'a> { } #[doc = "Values that can be written to the field `FEIE`"] pub enum FEIEW { - #[doc = "FE interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when FE is set."] - _1, + #[doc = "FE interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when FE is set."] _1, } impl FEIEW { #[allow(missing_docs)] @@ -2667,10 +2567,8 @@ impl<'a> _FEIEW<'a> { } #[doc = "Values that can be written to the field `NEIE`"] pub enum NEIEW { - #[doc = "NF interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when NF is set."] - _1, + #[doc = "NF interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when NF is set."] _1, } impl NEIEW { #[allow(missing_docs)] @@ -2725,10 +2623,8 @@ impl<'a> _NEIEW<'a> { } #[doc = "Values that can be written to the field `ORIE`"] pub enum ORIEW { - #[doc = "OR interrupts disabled; use polling."] - _0, - #[doc = "Hardware interrupt requested when OR is set."] - _1, + #[doc = "OR interrupts disabled; use polling."] _0, + #[doc = "Hardware interrupt requested when OR is set."] _1, } impl ORIEW { #[allow(missing_docs)] @@ -2783,10 +2679,8 @@ impl<'a> _ORIEW<'a> { } #[doc = "Values that can be written to the field `TXINV`"] pub enum TXINVW { - #[doc = "Transmit data not inverted."] - _0, - #[doc = "Transmit data inverted."] - _1, + #[doc = "Transmit data not inverted."] _0, + #[doc = "Transmit data inverted."] _1, } impl TXINVW { #[allow(missing_docs)] @@ -2841,10 +2735,8 @@ impl<'a> _TXINVW<'a> { } #[doc = "Values that can be written to the field `TXDIR`"] pub enum TXDIRW { - #[doc = "TXD pin is an input in single-wire mode."] - _0, - #[doc = "TXD pin is an output in single-wire mode."] - _1, + #[doc = "TXD pin is an input in single-wire mode."] _0, + #[doc = "TXD pin is an output in single-wire mode."] _1, } impl TXDIRW { #[allow(missing_docs)] diff --git a/src/lpuart2/data/mod.rs b/src/lpuart2/data/mod.rs index 3e2e726..bf5d575 100644 --- a/src/lpuart2/data/mod.rs +++ b/src/lpuart2/data/mod.rs @@ -22,7 +22,9 @@ impl super::DATA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -253,10 +255,8 @@ impl R9T9R { #[doc = "Possible values of the field `IDLINE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLINER { - #[doc = "Receiver was not idle before receiving this character."] - _0, - #[doc = "Receiver was idle before receiving this character."] - _1, + #[doc = "Receiver was not idle before receiving this character."] _0, + #[doc = "Receiver was idle before receiving this character."] _1, } impl IDLINER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -300,10 +300,8 @@ impl IDLINER { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer contains valid data."] - _0, - #[doc = "Receive buffer is empty, data returned on read is not valid."] - _1, + #[doc = "Receive buffer contains valid data."] _0, + #[doc = "Receive buffer is empty, data returned on read is not valid."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -394,10 +392,8 @@ impl FRETSCR { #[doc = "Possible values of the field `PARITYE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PARITYER { - #[doc = "The dataword was received without a parity error."] - _0, - #[doc = "The dataword was received with a parity error."] - _1, + #[doc = "The dataword was received without a parity error."] _0, + #[doc = "The dataword was received with a parity error."] _1, } impl PARITYER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -441,10 +437,8 @@ impl PARITYER { #[doc = "Possible values of the field `NOISY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NOISYR { - #[doc = "The dataword was received without noise."] - _0, - #[doc = "The data was received with noise."] - _1, + #[doc = "The dataword was received without noise."] _0, + #[doc = "The data was received with noise."] _1, } impl NOISYR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/lpuart2/fifo/mod.rs b/src/lpuart2/fifo/mod.rs index 7ce5dd2..1ca8b00 100644 --- a/src/lpuart2/fifo/mod.rs +++ b/src/lpuart2/fifo/mod.rs @@ -22,7 +22,9 @@ impl super::FIFO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::FIFO { #[doc = "Possible values of the field `RXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFIFOSIZER { - #[doc = "Receive FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Receive FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Receive FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Receive FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Receive FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Receive FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Receive FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Receive FIFO/Buffer depth = 256 datawords."] - _111, + #[doc = "Receive FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Receive FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Receive FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Receive FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Receive FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Receive FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Receive FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Receive FIFO/Buffer depth = 256 datawords."] _111, } impl RXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl RXFIFOSIZER { #[doc = "Possible values of the field `RXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXFER { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,22 +174,14 @@ impl RXFER { #[doc = "Possible values of the field `TXFIFOSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFIFOSIZER { - #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] - _000, - #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] - _001, - #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] - _010, - #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] - _011, - #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] - _100, - #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] - _101, - #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] - _110, - #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] - _111, + #[doc = "Transmit FIFO/Buffer depth = 1 dataword."] _000, + #[doc = "Transmit FIFO/Buffer depth = 4 datawords."] _001, + #[doc = "Transmit FIFO/Buffer depth = 8 datawords."] _010, + #[doc = "Transmit FIFO/Buffer depth = 16 datawords."] _011, + #[doc = "Transmit FIFO/Buffer depth = 32 datawords."] _100, + #[doc = "Transmit FIFO/Buffer depth = 64 datawords."] _101, + #[doc = "Transmit FIFO/Buffer depth = 128 datawords."] _110, + #[doc = "Transmit FIFO/Buffer depth = 256 datawords"] _111, } impl TXFIFOSIZER { #[doc = r" Value of the field as raw bits"] @@ -274,10 +258,8 @@ impl TXFIFOSIZER { #[doc = "Possible values of the field `TXFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXFER { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -321,10 +303,8 @@ impl TXFER { #[doc = "Possible values of the field `RXUFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFER { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -368,10 +348,8 @@ impl RXUFER { #[doc = "Possible values of the field `TXOFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFER { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -415,8 +393,7 @@ impl TXOFER { #[doc = "Possible values of the field `RXIDEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXIDENR { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -507,8 +484,7 @@ impl RXIDENR { #[doc = "Possible values of the field `RXUF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXUFR { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -554,8 +530,7 @@ impl RXUFR { #[doc = "Possible values of the field `TXOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXOFR { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } @@ -601,10 +576,8 @@ impl TXOFR { #[doc = "Possible values of the field `RXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEMPTR { - #[doc = "Receive buffer is not empty."] - _0, - #[doc = "Receive buffer is empty."] - _1, + #[doc = "Receive buffer is not empty."] _0, + #[doc = "Receive buffer is empty."] _1, } impl RXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -648,10 +621,8 @@ impl RXEMPTR { #[doc = "Possible values of the field `TXEMPT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXEMPTR { - #[doc = "Transmit buffer is not empty."] - _0, - #[doc = "Transmit buffer is empty."] - _1, + #[doc = "Transmit buffer is not empty."] _0, + #[doc = "Transmit buffer is empty."] _1, } impl TXEMPTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -694,10 +665,8 @@ impl TXEMPTR { } #[doc = "Values that can be written to the field `RXFE`"] pub enum RXFEW { - #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] - _0, - #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] - _1, + #[doc = "Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)"] _0, + #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."] _1, } impl RXFEW { #[allow(missing_docs)] @@ -752,10 +721,8 @@ impl<'a> _RXFEW<'a> { } #[doc = "Values that can be written to the field `TXFE`"] pub enum TXFEW { - #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] - _0, - #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] - _1, + #[doc = "Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support)."] _0, + #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."] _1, } impl TXFEW { #[allow(missing_docs)] @@ -810,10 +777,8 @@ impl<'a> _TXFEW<'a> { } #[doc = "Values that can be written to the field `RXUFE`"] pub enum RXUFEW { - #[doc = "RXUF flag does not generate an interrupt to the host."] - _0, - #[doc = "RXUF flag generates an interrupt to the host."] - _1, + #[doc = "RXUF flag does not generate an interrupt to the host."] _0, + #[doc = "RXUF flag generates an interrupt to the host."] _1, } impl RXUFEW { #[allow(missing_docs)] @@ -868,10 +833,8 @@ impl<'a> _RXUFEW<'a> { } #[doc = "Values that can be written to the field `TXOFE`"] pub enum TXOFEW { - #[doc = "TXOF flag does not generate an interrupt to the host."] - _0, - #[doc = "TXOF flag generates an interrupt to the host."] - _1, + #[doc = "TXOF flag does not generate an interrupt to the host."] _0, + #[doc = "TXOF flag generates an interrupt to the host."] _1, } impl TXOFEW { #[allow(missing_docs)] @@ -926,8 +889,7 @@ impl<'a> _TXOFEW<'a> { } #[doc = "Values that can be written to the field `RXIDEN`"] pub enum RXIDENW { - #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] - _000, + #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."] _000, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."] _001, #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."] @@ -1024,10 +986,8 @@ impl<'a> _RXIDENW<'a> { } #[doc = "Values that can be written to the field `RXFLUSH`"] pub enum RXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the receive FIFO/buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the receive FIFO/buffer is cleared out."] _1, } impl RXFLUSHW { #[allow(missing_docs)] @@ -1082,10 +1042,8 @@ impl<'a> _RXFLUSHW<'a> { } #[doc = "Values that can be written to the field `TXFLUSH`"] pub enum TXFLUSHW { - #[doc = "No flush operation occurs."] - _0, - #[doc = "All data in the transmit FIFO/Buffer is cleared out."] - _1, + #[doc = "No flush operation occurs."] _0, + #[doc = "All data in the transmit FIFO/Buffer is cleared out."] _1, } impl TXFLUSHW { #[allow(missing_docs)] @@ -1140,8 +1098,7 @@ impl<'a> _TXFLUSHW<'a> { } #[doc = "Values that can be written to the field `RXUF`"] pub enum RXUFW { - #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."] _1, } @@ -1198,8 +1155,7 @@ impl<'a> _RXUFW<'a> { } #[doc = "Values that can be written to the field `TXOF`"] pub enum TXOFW { - #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] - _0, + #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."] _0, #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."] _1, } diff --git a/src/lpuart2/global/mod.rs b/src/lpuart2/global/mod.rs index d481688..ab15f12 100644 --- a/src/lpuart2/global/mod.rs +++ b/src/lpuart2/global/mod.rs @@ -22,7 +22,9 @@ impl super::GLOBAL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::GLOBAL { #[doc = "Possible values of the field `RST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTR { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl RSTR { } #[doc = "Values that can be written to the field `RST`"] pub enum RSTW { - #[doc = "Module is not reset."] - _0, - #[doc = "Module is reset."] - _1, + #[doc = "Module is not reset."] _0, + #[doc = "Module is reset."] _1, } impl RSTW { #[allow(missing_docs)] diff --git a/src/lpuart2/match_/mod.rs b/src/lpuart2/match_/mod.rs index 3bbca15..ccaf148 100644 --- a/src/lpuart2/match_/mod.rs +++ b/src/lpuart2/match_/mod.rs @@ -22,7 +22,9 @@ impl super::MATCH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/lpuart2/mod.rs b/src/lpuart2/mod.rs index fdbf7c0..d0eca48 100644 --- a/src/lpuart2/mod.rs +++ b/src/lpuart2/mod.rs @@ -2,30 +2,18 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - LPUART Global Register"] - pub global: GLOBAL, - #[doc = "0x0c - LPUART Pin Configuration Register"] - pub pincfg: PINCFG, - #[doc = "0x10 - LPUART Baud Rate Register"] - pub baud: BAUD, - #[doc = "0x14 - LPUART Status Register"] - pub stat: STAT, - #[doc = "0x18 - LPUART Control Register"] - pub ctrl: CTRL, - #[doc = "0x1c - LPUART Data Register"] - pub data: DATA, - #[doc = "0x20 - LPUART Match Address Register"] - pub match_: MATCH, - #[doc = "0x24 - LPUART Modem IrDA Register"] - pub modir: MODIR, - #[doc = "0x28 - LPUART FIFO Register"] - pub fifo: FIFO, - #[doc = "0x2c - LPUART Watermark Register"] - pub water: WATER, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - LPUART Global Register"] pub global: GLOBAL, + #[doc = "0x0c - LPUART Pin Configuration Register"] pub pincfg: PINCFG, + #[doc = "0x10 - LPUART Baud Rate Register"] pub baud: BAUD, + #[doc = "0x14 - LPUART Status Register"] pub stat: STAT, + #[doc = "0x18 - LPUART Control Register"] pub ctrl: CTRL, + #[doc = "0x1c - LPUART Data Register"] pub data: DATA, + #[doc = "0x20 - LPUART Match Address Register"] pub match_: MATCH, + #[doc = "0x24 - LPUART Modem IrDA Register"] pub modir: MODIR, + #[doc = "0x28 - LPUART FIFO Register"] pub fifo: FIFO, + #[doc = "0x2c - LPUART Watermark Register"] pub water: WATER, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/lpuart2/modir/mod.rs b/src/lpuart2/modir/mod.rs index 7432076..badea62 100644 --- a/src/lpuart2/modir/mod.rs +++ b/src/lpuart2/modir/mod.rs @@ -22,7 +22,9 @@ impl super::MODIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::MODIR { #[doc = "Possible values of the field `TXCTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSER { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -90,8 +91,7 @@ impl TXCTSER { #[doc = "Possible values of the field `TXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSER { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -137,10 +137,8 @@ impl TXRTSER { #[doc = "Possible values of the field `TXRTSPOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXRTSPOLR { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl TXRTSPOLR { #[doc = "Possible values of the field `RXRTSE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXRTSER { - #[doc = "The receiver has no effect on RTS."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "The receiver has no effect on RTS."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl RXRTSER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -226,10 +222,8 @@ impl RXRTSER { #[doc = "Possible values of the field `TXCTSC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSCR { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +267,8 @@ impl TXCTSCR { #[doc = "Possible values of the field `TXCTSSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXCTSSRCR { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -331,14 +323,10 @@ impl RTSWATERR { #[doc = "Possible values of the field `TNP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TNPR { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPR { #[doc = r" Value of the field as raw bits"] @@ -387,10 +375,8 @@ impl TNPR { #[doc = "Possible values of the field `IREN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRENR { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -433,8 +419,7 @@ impl IRENR { } #[doc = "Values that can be written to the field `TXCTSE`"] pub enum TXCTSEW { - #[doc = "CTS has no effect on the transmitter."] - _0, + #[doc = "CTS has no effect on the transmitter."] _0, #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."] _1, } @@ -491,8 +476,7 @@ impl<'a> _TXCTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSE`"] pub enum TXRTSEW { - #[doc = "The transmitter has no effect on RTS."] - _0, + #[doc = "The transmitter has no effect on RTS."] _0, #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."] _1, } @@ -549,10 +533,8 @@ impl<'a> _TXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXRTSPOL`"] pub enum TXRTSPOLW { - #[doc = "Transmitter RTS is active low."] - _0, - #[doc = "Transmitter RTS is active high."] - _1, + #[doc = "Transmitter RTS is active low."] _0, + #[doc = "Transmitter RTS is active high."] _1, } impl TXRTSPOLW { #[allow(missing_docs)] @@ -607,8 +589,7 @@ impl<'a> _TXRTSPOLW<'a> { } #[doc = "Values that can be written to the field `RXRTSE`"] pub enum RXRTSEW { - #[doc = "The receiver has no effect on RTS."] - _0, + #[doc = "The receiver has no effect on RTS."] _0, } impl RXRTSEW { #[allow(missing_docs)] @@ -657,10 +638,8 @@ impl<'a> _RXRTSEW<'a> { } #[doc = "Values that can be written to the field `TXCTSC`"] pub enum TXCTSCW { - #[doc = "CTS input is sampled at the start of each character."] - _0, - #[doc = "CTS input is sampled when the transmitter is idle."] - _1, + #[doc = "CTS input is sampled at the start of each character."] _0, + #[doc = "CTS input is sampled when the transmitter is idle."] _1, } impl TXCTSCW { #[allow(missing_docs)] @@ -715,10 +694,8 @@ impl<'a> _TXCTSCW<'a> { } #[doc = "Values that can be written to the field `TXCTSSRC`"] pub enum TXCTSSRCW { - #[doc = "CTS input is the CTS_B pin."] - _0, - #[doc = "CTS input is the inverted Receiver Match result."] - _1, + #[doc = "CTS input is the CTS_B pin."] _0, + #[doc = "CTS input is the inverted Receiver Match result."] _1, } impl TXCTSSRCW { #[allow(missing_docs)] @@ -788,14 +765,10 @@ impl<'a> _RTSWATERW<'a> { } #[doc = "Values that can be written to the field `TNP`"] pub enum TNPW { - #[doc = "1/OSR."] - _00, - #[doc = "2/OSR."] - _01, - #[doc = "3/OSR."] - _10, - #[doc = "4/OSR."] - _11, + #[doc = "1/OSR."] _00, + #[doc = "2/OSR."] _01, + #[doc = "3/OSR."] _10, + #[doc = "4/OSR."] _11, } impl TNPW { #[allow(missing_docs)] @@ -854,10 +827,8 @@ impl<'a> _TNPW<'a> { } #[doc = "Values that can be written to the field `IREN`"] pub enum IRENW { - #[doc = "IR disabled."] - _0, - #[doc = "IR enabled."] - _1, + #[doc = "IR disabled."] _0, + #[doc = "IR enabled."] _1, } impl IRENW { #[allow(missing_docs)] diff --git a/src/lpuart2/param/mod.rs b/src/lpuart2/param/mod.rs index 1fcd795..de98cf0 100644 --- a/src/lpuart2/param/mod.rs +++ b/src/lpuart2/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/lpuart2/pincfg/mod.rs b/src/lpuart2/pincfg/mod.rs index c76fae5..799cd21 100644 --- a/src/lpuart2/pincfg/mod.rs +++ b/src/lpuart2/pincfg/mod.rs @@ -22,7 +22,9 @@ impl super::PINCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::PINCFG { #[doc = "Possible values of the field `TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSELR { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } @@ -98,12 +97,9 @@ impl TRGSELR { } #[doc = "Values that can be written to the field `TRGSEL`"] pub enum TRGSELW { - #[doc = "Input trigger is disabled."] - _00, - #[doc = "Input trigger is used instead of RXD pin input."] - _01, - #[doc = "Input trigger is used instead of CTS_B pin input."] - _10, + #[doc = "Input trigger is disabled."] _00, + #[doc = "Input trigger is used instead of RXD pin input."] _01, + #[doc = "Input trigger is used instead of CTS_B pin input."] _10, #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."] _11, } diff --git a/src/lpuart2/stat/mod.rs b/src/lpuart2/stat/mod.rs index 4b96449..6a322b6 100644 --- a/src/lpuart2/stat/mod.rs +++ b/src/lpuart2/stat/mod.rs @@ -22,7 +22,9 @@ impl super::STAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::STAT { #[doc = "Possible values of the field `MA2F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA2FR { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl MA2FR { #[doc = "Possible values of the field `MA1F`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MA1FR { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl MA1FR { #[doc = "Possible values of the field `PF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PFR { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl PFR { #[doc = "Possible values of the field `FE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FER { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FER { #[doc = "Possible values of the field `NF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum NFR { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl NFR { #[doc = "Possible values of the field `OR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ORR { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl ORR { #[doc = "Possible values of the field `IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IDLER { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl IDLER { #[doc = "Possible values of the field `RDRF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RDRFR { - #[doc = "Receive data buffer empty."] - _0, - #[doc = "Receive data buffer full."] - _1, + #[doc = "Receive data buffer empty."] _0, + #[doc = "Receive data buffer full."] _1, } impl RDRFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl RDRFR { #[doc = "Possible values of the field `TC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCR { - #[doc = "Transmitter active (sending data, a preamble, or a break)."] - _0, - #[doc = "Transmitter idle (transmission activity complete)."] - _1, + #[doc = "Transmitter active (sending data, a preamble, or a break)."] _0, + #[doc = "Transmitter idle (transmission activity complete)."] _1, } impl TCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl TCR { #[doc = "Possible values of the field `TDRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TDRER { - #[doc = "Transmit data buffer full."] - _0, - #[doc = "Transmit data buffer empty."] - _1, + #[doc = "Transmit data buffer full."] _0, + #[doc = "Transmit data buffer empty."] _1, } impl TDRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl TDRER { #[doc = "Possible values of the field `RAF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RAFR { - #[doc = "LPUART receiver idle waiting for a start bit."] - _0, - #[doc = "LPUART receiver active (RXD input not idle)."] - _1, + #[doc = "LPUART receiver idle waiting for a start bit."] _0, + #[doc = "LPUART receiver active (RXD input not idle)."] _1, } impl RAFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,8 +540,7 @@ impl RAFR { #[doc = "Possible values of the field `LBKDE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDER { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -607,10 +586,8 @@ impl LBKDER { #[doc = "Possible values of the field `BRK13`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BRK13R { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -701,10 +678,8 @@ impl RWUIDR { #[doc = "Possible values of the field `RXINV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXINVR { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -795,10 +770,8 @@ impl MSBFR { #[doc = "Possible values of the field `RXEDGIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RXEDGIFR { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -842,10 +815,8 @@ impl RXEDGIFR { #[doc = "Possible values of the field `LBKDIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LBKDIFR { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -888,10 +859,8 @@ impl LBKDIFR { } #[doc = "Values that can be written to the field `MA2F`"] pub enum MA2FW { - #[doc = "Received data is not equal to MA2"] - _0, - #[doc = "Received data is equal to MA2"] - _1, + #[doc = "Received data is not equal to MA2"] _0, + #[doc = "Received data is equal to MA2"] _1, } impl MA2FW { #[allow(missing_docs)] @@ -946,10 +915,8 @@ impl<'a> _MA2FW<'a> { } #[doc = "Values that can be written to the field `MA1F`"] pub enum MA1FW { - #[doc = "Received data is not equal to MA1"] - _0, - #[doc = "Received data is equal to MA1"] - _1, + #[doc = "Received data is not equal to MA1"] _0, + #[doc = "Received data is equal to MA1"] _1, } impl MA1FW { #[allow(missing_docs)] @@ -1004,10 +971,8 @@ impl<'a> _MA1FW<'a> { } #[doc = "Values that can be written to the field `PF`"] pub enum PFW { - #[doc = "No parity error."] - _0, - #[doc = "Parity error."] - _1, + #[doc = "No parity error."] _0, + #[doc = "Parity error."] _1, } impl PFW { #[allow(missing_docs)] @@ -1062,10 +1027,8 @@ impl<'a> _PFW<'a> { } #[doc = "Values that can be written to the field `FE`"] pub enum FEW { - #[doc = "No framing error detected. This does not guarantee the framing is correct."] - _0, - #[doc = "Framing error."] - _1, + #[doc = "No framing error detected. This does not guarantee the framing is correct."] _0, + #[doc = "Framing error."] _1, } impl FEW { #[allow(missing_docs)] @@ -1120,10 +1083,8 @@ impl<'a> _FEW<'a> { } #[doc = "Values that can be written to the field `NF`"] pub enum NFW { - #[doc = "No noise detected."] - _0, - #[doc = "Noise detected in the received character in LPUART_DATA."] - _1, + #[doc = "No noise detected."] _0, + #[doc = "Noise detected in the received character in LPUART_DATA."] _1, } impl NFW { #[allow(missing_docs)] @@ -1178,10 +1139,8 @@ impl<'a> _NFW<'a> { } #[doc = "Values that can be written to the field `OR`"] pub enum ORW { - #[doc = "No overrun."] - _0, - #[doc = "Receive overrun (new LPUART data lost)."] - _1, + #[doc = "No overrun."] _0, + #[doc = "Receive overrun (new LPUART data lost)."] _1, } impl ORW { #[allow(missing_docs)] @@ -1236,10 +1195,8 @@ impl<'a> _ORW<'a> { } #[doc = "Values that can be written to the field `IDLE`"] pub enum IDLEW { - #[doc = "No idle line detected."] - _0, - #[doc = "Idle line was detected."] - _1, + #[doc = "No idle line detected."] _0, + #[doc = "Idle line was detected."] _1, } impl IDLEW { #[allow(missing_docs)] @@ -1294,8 +1251,7 @@ impl<'a> _IDLEW<'a> { } #[doc = "Values that can be written to the field `LBKDE`"] pub enum LBKDEW { - #[doc = "LIN break detect is disabled, normal break character can be detected."] - _0, + #[doc = "LIN break detect is disabled, normal break character can be detected."] _0, #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."] _1, } @@ -1352,10 +1308,8 @@ impl<'a> _LBKDEW<'a> { } #[doc = "Values that can be written to the field `BRK13`"] pub enum BRK13W { - #[doc = "Break character is transmitted with length of 9 to 13 bit times."] - _0, - #[doc = "Break character is transmitted with length of 12 to 15 bit times."] - _1, + #[doc = "Break character is transmitted with length of 9 to 13 bit times."] _0, + #[doc = "Break character is transmitted with length of 12 to 15 bit times."] _1, } impl BRK13W { #[allow(missing_docs)] @@ -1468,10 +1422,8 @@ impl<'a> _RWUIDW<'a> { } #[doc = "Values that can be written to the field `RXINV`"] pub enum RXINVW { - #[doc = "Receive data not inverted."] - _0, - #[doc = "Receive data inverted."] - _1, + #[doc = "Receive data not inverted."] _0, + #[doc = "Receive data inverted."] _1, } impl RXINVW { #[allow(missing_docs)] @@ -1584,10 +1536,8 @@ impl<'a> _MSBFW<'a> { } #[doc = "Values that can be written to the field `RXEDGIF`"] pub enum RXEDGIFW { - #[doc = "No active edge on the receive pin has occurred."] - _0, - #[doc = "An active edge on the receive pin has occurred."] - _1, + #[doc = "No active edge on the receive pin has occurred."] _0, + #[doc = "An active edge on the receive pin has occurred."] _1, } impl RXEDGIFW { #[allow(missing_docs)] @@ -1642,10 +1592,8 @@ impl<'a> _RXEDGIFW<'a> { } #[doc = "Values that can be written to the field `LBKDIF`"] pub enum LBKDIFW { - #[doc = "No LIN break character has been detected."] - _0, - #[doc = "LIN break character has been detected."] - _1, + #[doc = "No LIN break character has been detected."] _0, + #[doc = "LIN break character has been detected."] _1, } impl LBKDIFW { #[allow(missing_docs)] diff --git a/src/lpuart2/verid/mod.rs b/src/lpuart2/verid/mod.rs index e3f9566..647ac7a 100644 --- a/src/lpuart2/verid/mod.rs +++ b/src/lpuart2/verid/mod.rs @@ -6,18 +6,17 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set."] - _0000000000000001, - #[doc = "Standard feature set with MODEM/IrDA support."] - _0000000000000011, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set."] _0000000000000001, + #[doc = "Standard feature set with MODEM/IrDA support."] _0000000000000011, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/lpuart2/water/mod.rs b/src/lpuart2/water/mod.rs index 4ad84b2..b3b5898 100644 --- a/src/lpuart2/water/mod.rs +++ b/src/lpuart2/water/mod.rs @@ -22,7 +22,9 @@ impl super::WATER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/mcm/cpcr/mod.rs b/src/mcm/cpcr/mod.rs index 95e1ccd..a7d95f9 100644 --- a/src/mcm/cpcr/mod.rs +++ b/src/mcm/cpcr/mod.rs @@ -22,7 +22,9 @@ impl super::CPCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::CPCR { #[doc = "Possible values of the field `HLT_FSM_ST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HLT_FSM_STR { - #[doc = "Waiting for request"] - _00, - #[doc = "Waiting for platform idle"] - _01, - #[doc = "Platform stalled"] - _11, - #[doc = "Unused state"] - _10, + #[doc = "Waiting for request"] _00, + #[doc = "Waiting for platform idle"] _01, + #[doc = "Platform stalled"] _11, + #[doc = "Unused state"] _10, } impl HLT_FSM_STR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl HLT_FSM_STR { #[doc = "Possible values of the field `AXBS_HLT_REQ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AXBS_HLT_REQR { - #[doc = "AXBS is not receiving halt request"] - _0, - #[doc = "AXBS is receiving halt request"] - _1, + #[doc = "AXBS is not receiving halt request"] _0, + #[doc = "AXBS is receiving halt request"] _1, } impl AXBS_HLT_REQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -146,10 +142,8 @@ impl AXBS_HLT_REQR { #[doc = "Possible values of the field `AXBS_HLTD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AXBS_HLTDR { - #[doc = "AXBS is not currently halted"] - _0, - #[doc = "AXBS is currently halted"] - _1, + #[doc = "AXBS is not currently halted"] _0, + #[doc = "AXBS is currently halted"] _1, } impl AXBS_HLTDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +187,8 @@ impl AXBS_HLTDR { #[doc = "Possible values of the field `FMC_PF_IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FMC_PF_IDLER { - #[doc = "FMC program flash is not idle"] - _0, - #[doc = "FMC program flash is currently idle"] - _1, + #[doc = "FMC program flash is not idle"] _0, + #[doc = "FMC program flash is currently idle"] _1, } impl FMC_PF_IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,10 +232,8 @@ impl FMC_PF_IDLER { #[doc = "Possible values of the field `PBRIDGE_IDLE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PBRIDGE_IDLER { - #[doc = "PBRIDGE is not idle"] - _0, - #[doc = "PBRIDGE is currently idle"] - _1, + #[doc = "PBRIDGE is not idle"] _0, + #[doc = "PBRIDGE is currently idle"] _1, } impl PBRIDGE_IDLER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -287,10 +277,8 @@ impl PBRIDGE_IDLER { #[doc = "Possible values of the field `CBRR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CBRRR { - #[doc = "Fixed-priority arbitration"] - _0, - #[doc = "Round-robin arbitration"] - _1, + #[doc = "Fixed-priority arbitration"] _0, + #[doc = "Round-robin arbitration"] _1, } impl CBRRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -334,14 +322,10 @@ impl CBRRR { #[doc = "Possible values of the field `SRAMUAP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRAMUAPR { - #[doc = "Round robin"] - _00, - #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] - _01, - #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] - _10, - #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] - _11, + #[doc = "Round robin"] _00, + #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] _01, + #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] _10, + #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] _11, } impl SRAMUAPR { #[doc = r" Value of the field as raw bits"] @@ -411,14 +395,10 @@ impl SRAMUWPR { #[doc = "Possible values of the field `SRAMLAP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRAMLAPR { - #[doc = "Round robin"] - _00, - #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] - _01, - #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] - _10, - #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] - _11, + #[doc = "Round robin"] _00, + #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] _01, + #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] _10, + #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] _11, } impl SRAMLAPR { #[doc = r" Value of the field as raw bits"] @@ -487,10 +467,8 @@ impl SRAMLWPR { } #[doc = "Values that can be written to the field `CBRR`"] pub enum CBRRW { - #[doc = "Fixed-priority arbitration"] - _0, - #[doc = "Round-robin arbitration"] - _1, + #[doc = "Fixed-priority arbitration"] _0, + #[doc = "Round-robin arbitration"] _1, } impl CBRRW { #[allow(missing_docs)] @@ -545,14 +523,10 @@ impl<'a> _CBRRW<'a> { } #[doc = "Values that can be written to the field `SRAMUAP`"] pub enum SRAMUAPW { - #[doc = "Round robin"] - _00, - #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] - _01, - #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] - _10, - #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] - _11, + #[doc = "Round robin"] _00, + #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] _01, + #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] _10, + #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] _11, } impl SRAMUAPW { #[allow(missing_docs)] @@ -634,14 +608,10 @@ impl<'a> _SRAMUWPW<'a> { } #[doc = "Values that can be written to the field `SRAMLAP`"] pub enum SRAMLAPW { - #[doc = "Round robin"] - _00, - #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] - _01, - #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] - _10, - #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] - _11, + #[doc = "Round robin"] _00, + #[doc = "Special round robin (favors SRAM backdoor accesses over the processor)"] _01, + #[doc = "Fixed priority. Processor has highest, backdoor has lowest"] _10, + #[doc = "Fixed priority. Backdoor has highest, processor has lowest"] _11, } impl SRAMLAPW { #[allow(missing_docs)] diff --git a/src/mcm/cpo/mod.rs b/src/mcm/cpo/mod.rs index 119baf7..b2475fe 100644 --- a/src/mcm/cpo/mod.rs +++ b/src/mcm/cpo/mod.rs @@ -22,7 +22,9 @@ impl super::CPO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CPO { #[doc = "Possible values of the field `CPOREQ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOREQR { - #[doc = "Request is cleared."] - _0, - #[doc = "Request Compute Operation."] - _1, + #[doc = "Request is cleared."] _0, + #[doc = "Request Compute Operation."] _1, } impl CPOREQR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CPOREQR { #[doc = "Possible values of the field `CPOACK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOACKR { - #[doc = "Compute operation entry has not completed or compute operation exit has completed."] - _0, - #[doc = "Compute operation entry has completed or compute operation exit has not completed."] - _1, + #[doc = "Compute operation entry has not completed or compute operation exit has completed."] _0, + #[doc = "Compute operation entry has completed or compute operation exit has not completed."] _1, } impl CPOACKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CPOACKR { #[doc = "Possible values of the field `CPOWOI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPOWOIR { - #[doc = "No effect."] - _0, - #[doc = "When set, the CPOREQ is cleared on any interrupt or exception vector fetch."] - _1, + #[doc = "No effect."] _0, + #[doc = "When set, the CPOREQ is cleared on any interrupt or exception vector fetch."] _1, } impl CPOWOIR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl CPOWOIR { } #[doc = "Values that can be written to the field `CPOREQ`"] pub enum CPOREQW { - #[doc = "Request is cleared."] - _0, - #[doc = "Request Compute Operation."] - _1, + #[doc = "Request is cleared."] _0, + #[doc = "Request Compute Operation."] _1, } impl CPOREQW { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _CPOREQW<'a> { } #[doc = "Values that can be written to the field `CPOWOI`"] pub enum CPOWOIW { - #[doc = "No effect."] - _0, - #[doc = "When set, the CPOREQ is cleared on any interrupt or exception vector fetch."] - _1, + #[doc = "No effect."] _0, + #[doc = "When set, the CPOREQ is cleared on any interrupt or exception vector fetch."] _1, } impl CPOWOIW { #[allow(missing_docs)] diff --git a/src/mcm/iscr/mod.rs b/src/mcm/iscr/mod.rs index 889dbdc..2408e29 100644 --- a/src/mcm/iscr/mod.rs +++ b/src/mcm/iscr/mod.rs @@ -22,7 +22,9 @@ impl super::ISCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ISCR { #[doc = "Possible values of the field `FIOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIOCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FIOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FIOCR { #[doc = "Possible values of the field `FDZC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FDZCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FDZCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FDZCR { #[doc = "Possible values of the field `FOFC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FOFCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FOFCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl FOFCR { #[doc = "Possible values of the field `FUFC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FUFCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FUFCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl FUFCR { #[doc = "Possible values of the field `FIXC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIXCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FIXCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl FIXCR { #[doc = "Possible values of the field `FIDC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIDCR { - #[doc = "No interrupt"] - _0, - #[doc = "Interrupt occurred"] - _1, + #[doc = "No interrupt"] _0, + #[doc = "Interrupt occurred"] _1, } impl FIDCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl FIDCR { #[doc = "Possible values of the field `FIOCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIOCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIOCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl FIOCER { #[doc = "Possible values of the field `FDZCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FDZCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FDZCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl FDZCER { #[doc = "Possible values of the field `FOFCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FOFCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FOFCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -466,10 +450,8 @@ impl FOFCER { #[doc = "Possible values of the field `FUFCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FUFCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FUFCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +495,8 @@ impl FUFCER { #[doc = "Possible values of the field `FIXCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIXCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIXCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -560,10 +540,8 @@ impl FIXCER { #[doc = "Possible values of the field `FIDCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIDCER { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIDCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -606,10 +584,8 @@ impl FIDCER { } #[doc = "Values that can be written to the field `FIOCE`"] pub enum FIOCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIOCEW { #[allow(missing_docs)] @@ -664,10 +640,8 @@ impl<'a> _FIOCEW<'a> { } #[doc = "Values that can be written to the field `FDZCE`"] pub enum FDZCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FDZCEW { #[allow(missing_docs)] @@ -722,10 +696,8 @@ impl<'a> _FDZCEW<'a> { } #[doc = "Values that can be written to the field `FOFCE`"] pub enum FOFCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FOFCEW { #[allow(missing_docs)] @@ -780,10 +752,8 @@ impl<'a> _FOFCEW<'a> { } #[doc = "Values that can be written to the field `FUFCE`"] pub enum FUFCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FUFCEW { #[allow(missing_docs)] @@ -838,10 +808,8 @@ impl<'a> _FUFCEW<'a> { } #[doc = "Values that can be written to the field `FIXCE`"] pub enum FIXCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIXCEW { #[allow(missing_docs)] @@ -896,10 +864,8 @@ impl<'a> _FIXCEW<'a> { } #[doc = "Values that can be written to the field `FIDCE`"] pub enum FIDCEW { - #[doc = "Disable interrupt"] - _0, - #[doc = "Enable interrupt"] - _1, + #[doc = "Disable interrupt"] _0, + #[doc = "Enable interrupt"] _1, } impl FIDCEW { #[allow(missing_docs)] diff --git a/src/mcm/lmdr0/mod.rs b/src/mcm/lmdr0/mod.rs index 03657d4..f9bef8a 100644 --- a/src/mcm/lmdr0/mod.rs +++ b/src/mcm/lmdr0/mod.rs @@ -22,7 +22,9 @@ impl super::LMDR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,12 +67,9 @@ impl CF1R { #[doc = "Possible values of the field `MT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR { - #[doc = "SRAM_L"] - _000, - #[doc = "SRAM_U"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "SRAM_L"] _000, + #[doc = "SRAM_U"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl MTR { #[doc = r" Value of the field as raw bits"] @@ -106,10 +105,8 @@ impl MTR { #[doc = "Possible values of the field `LOCK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCKR { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,12 +150,9 @@ impl LOCKR { #[doc = "Possible values of the field `DPW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPWR { - #[doc = "LMEMn 32-bits wide"] - _010, - #[doc = "LMEMn 64-bits wide"] - _011, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "LMEMn 32-bits wide"] _010, + #[doc = "LMEMn 64-bits wide"] _011, + #[doc = r" Reserved"] _Reserved(u8), } impl DPWR { #[doc = r" Value of the field as raw bits"] @@ -194,14 +188,10 @@ impl DPWR { #[doc = "Possible values of the field `WY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WYR { - #[doc = "No Cache"] - _0000, - #[doc = "2-Way Set Associative"] - _0010, - #[doc = "4-Way Set Associative"] - _0100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No Cache"] _0000, + #[doc = "2-Way Set Associative"] _0010, + #[doc = "4-Way Set Associative"] _0100, + #[doc = r" Reserved"] _Reserved(u8), } impl WYR { #[doc = r" Value of the field as raw bits"] @@ -244,38 +234,22 @@ impl WYR { #[doc = "Possible values of the field `LMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZR { - #[doc = "no LMEMn (0 KB)"] - _0000, - #[doc = "1 KB LMEMn"] - _0001, - #[doc = "2 KB LMEMn"] - _0010, - #[doc = "4 KB LMEMn"] - _0011, - #[doc = "8 KB LMEMn"] - _0100, - #[doc = "16 KB LMEMn"] - _0101, - #[doc = "32 KB LMEMn"] - _0110, - #[doc = "64 KB LMEMn"] - _0111, - #[doc = "128 KB LMEMn"] - _1000, - #[doc = "256 KB LMEMn"] - _1001, - #[doc = "512 KB LMEMn"] - _1010, - #[doc = "1024 KB LMEMn"] - _1011, - #[doc = "2048 KB LMEMn"] - _1100, - #[doc = "4096 KB LMEMn"] - _1101, - #[doc = "8192 KB LMEMn"] - _1110, - #[doc = "16384 KB LMEMn"] - _1111, + #[doc = "no LMEMn (0 KB)"] _0000, + #[doc = "1 KB LMEMn"] _0001, + #[doc = "2 KB LMEMn"] _0010, + #[doc = "4 KB LMEMn"] _0011, + #[doc = "8 KB LMEMn"] _0100, + #[doc = "16 KB LMEMn"] _0101, + #[doc = "32 KB LMEMn"] _0110, + #[doc = "64 KB LMEMn"] _0111, + #[doc = "128 KB LMEMn"] _1000, + #[doc = "256 KB LMEMn"] _1001, + #[doc = "512 KB LMEMn"] _1010, + #[doc = "1024 KB LMEMn"] _1011, + #[doc = "2048 KB LMEMn"] _1100, + #[doc = "4096 KB LMEMn"] _1101, + #[doc = "8192 KB LMEMn"] _1110, + #[doc = "16384 KB LMEMn"] _1111, } impl LMSZR { #[doc = r" Value of the field as raw bits"] @@ -408,10 +382,8 @@ impl LMSZR { #[doc = "Possible values of the field `LMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZHR { - #[doc = "LMEMn is a power-of-2 capacity."] - _0, - #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] - _1, + #[doc = "LMEMn is a power-of-2 capacity."] _0, + #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] _1, } impl LMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +427,8 @@ impl LMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "LMEMn is not present."] - _0, - #[doc = "LMEMn is present."] - _1, + #[doc = "LMEMn is not present."] _0, + #[doc = "LMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -531,10 +501,8 @@ impl<'a> _CF1W<'a> { } #[doc = "Values that can be written to the field `LOCK`"] pub enum LOCKW { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKW { #[allow(missing_docs)] diff --git a/src/mcm/lmdr1/mod.rs b/src/mcm/lmdr1/mod.rs index 281470c..bca038f 100644 --- a/src/mcm/lmdr1/mod.rs +++ b/src/mcm/lmdr1/mod.rs @@ -22,7 +22,9 @@ impl super::LMDR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -65,12 +67,9 @@ impl CF1R { #[doc = "Possible values of the field `MT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR { - #[doc = "SRAM_L"] - _000, - #[doc = "SRAM_U"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "SRAM_L"] _000, + #[doc = "SRAM_U"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl MTR { #[doc = r" Value of the field as raw bits"] @@ -106,10 +105,8 @@ impl MTR { #[doc = "Possible values of the field `LOCK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCKR { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,12 +150,9 @@ impl LOCKR { #[doc = "Possible values of the field `DPW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPWR { - #[doc = "LMEMn 32-bits wide"] - _010, - #[doc = "LMEMn 64-bits wide"] - _011, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "LMEMn 32-bits wide"] _010, + #[doc = "LMEMn 64-bits wide"] _011, + #[doc = r" Reserved"] _Reserved(u8), } impl DPWR { #[doc = r" Value of the field as raw bits"] @@ -194,14 +188,10 @@ impl DPWR { #[doc = "Possible values of the field `WY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WYR { - #[doc = "No Cache"] - _0000, - #[doc = "2-Way Set Associative"] - _0010, - #[doc = "4-Way Set Associative"] - _0100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No Cache"] _0000, + #[doc = "2-Way Set Associative"] _0010, + #[doc = "4-Way Set Associative"] _0100, + #[doc = r" Reserved"] _Reserved(u8), } impl WYR { #[doc = r" Value of the field as raw bits"] @@ -244,38 +234,22 @@ impl WYR { #[doc = "Possible values of the field `LMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZR { - #[doc = "no LMEMn (0 KB)"] - _0000, - #[doc = "1 KB LMEMn"] - _0001, - #[doc = "2 KB LMEMn"] - _0010, - #[doc = "4 KB LMEMn"] - _0011, - #[doc = "8 KB LMEMn"] - _0100, - #[doc = "16 KB LMEMn"] - _0101, - #[doc = "32 KB LMEMn"] - _0110, - #[doc = "64 KB LMEMn"] - _0111, - #[doc = "128 KB LMEMn"] - _1000, - #[doc = "256 KB LMEMn"] - _1001, - #[doc = "512 KB LMEMn"] - _1010, - #[doc = "1024 KB LMEMn"] - _1011, - #[doc = "2048 KB LMEMn"] - _1100, - #[doc = "4096 KB LMEMn"] - _1101, - #[doc = "8192 KB LMEMn"] - _1110, - #[doc = "16384 KB LMEMn"] - _1111, + #[doc = "no LMEMn (0 KB)"] _0000, + #[doc = "1 KB LMEMn"] _0001, + #[doc = "2 KB LMEMn"] _0010, + #[doc = "4 KB LMEMn"] _0011, + #[doc = "8 KB LMEMn"] _0100, + #[doc = "16 KB LMEMn"] _0101, + #[doc = "32 KB LMEMn"] _0110, + #[doc = "64 KB LMEMn"] _0111, + #[doc = "128 KB LMEMn"] _1000, + #[doc = "256 KB LMEMn"] _1001, + #[doc = "512 KB LMEMn"] _1010, + #[doc = "1024 KB LMEMn"] _1011, + #[doc = "2048 KB LMEMn"] _1100, + #[doc = "4096 KB LMEMn"] _1101, + #[doc = "8192 KB LMEMn"] _1110, + #[doc = "16384 KB LMEMn"] _1111, } impl LMSZR { #[doc = r" Value of the field as raw bits"] @@ -408,10 +382,8 @@ impl LMSZR { #[doc = "Possible values of the field `LMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZHR { - #[doc = "LMEMn is a power-of-2 capacity."] - _0, - #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] - _1, + #[doc = "LMEMn is a power-of-2 capacity."] _0, + #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] _1, } impl LMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -455,10 +427,8 @@ impl LMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "LMEMn is not present."] - _0, - #[doc = "LMEMn is present."] - _1, + #[doc = "LMEMn is not present."] _0, + #[doc = "LMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -531,10 +501,8 @@ impl<'a> _CF1W<'a> { } #[doc = "Values that can be written to the field `LOCK`"] pub enum LOCKW { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKW { #[allow(missing_docs)] diff --git a/src/mcm/lmdr2/mod.rs b/src/mcm/lmdr2/mod.rs index 62674a3..3b55a9c 100644 --- a/src/mcm/lmdr2/mod.rs +++ b/src/mcm/lmdr2/mod.rs @@ -22,7 +22,9 @@ impl super::LMDR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl CF1R { #[doc = "Possible values of the field `MT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MTR { - #[doc = "PC Cache"] - _010, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PC Cache"] _010, + #[doc = r" Reserved"] _Reserved(u8), } impl MTR { #[doc = r" Value of the field as raw bits"] @@ -86,10 +86,8 @@ impl MTR { #[doc = "Possible values of the field `LOCK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCKR { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -133,12 +131,9 @@ impl LOCKR { #[doc = "Possible values of the field `DPW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DPWR { - #[doc = "LMEMn 32-bits wide"] - _010, - #[doc = "LMEMn 64-bits wide"] - _011, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "LMEMn 32-bits wide"] _010, + #[doc = "LMEMn 64-bits wide"] _011, + #[doc = r" Reserved"] _Reserved(u8), } impl DPWR { #[doc = r" Value of the field as raw bits"] @@ -174,14 +169,10 @@ impl DPWR { #[doc = "Possible values of the field `WY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WYR { - #[doc = "No Cache"] - _0000, - #[doc = "2-Way Set Associative"] - _0010, - #[doc = "4-Way Set Associative"] - _0100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No Cache"] _0000, + #[doc = "2-Way Set Associative"] _0010, + #[doc = "4-Way Set Associative"] _0100, + #[doc = r" Reserved"] _Reserved(u8), } impl WYR { #[doc = r" Value of the field as raw bits"] @@ -224,10 +215,8 @@ impl WYR { #[doc = "Possible values of the field `LMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZR { - #[doc = "4 KB LMEMn"] - _0100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "4 KB LMEMn"] _0100, + #[doc = r" Reserved"] _Reserved(u8), } impl LMSZR { #[doc = r" Value of the field as raw bits"] @@ -256,10 +245,8 @@ impl LMSZR { #[doc = "Possible values of the field `LMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LMSZHR { - #[doc = "LMEMn is a power-of-2 capacity."] - _0, - #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] - _1, + #[doc = "LMEMn is a power-of-2 capacity."] _0, + #[doc = "LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ."] _1, } impl LMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -303,10 +290,8 @@ impl LMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "LMEMn is not present."] - _0, - #[doc = "LMEMn is present."] - _1, + #[doc = "LMEMn is not present."] _0, + #[doc = "LMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -364,10 +349,8 @@ impl<'a> _CF1W<'a> { } #[doc = "Values that can be written to the field `LOCK`"] pub enum LOCKW { - #[doc = "Writes to the LMDRn[7:0] are allowed."] - _0, - #[doc = "Writes to the LMDRn[7:0] are ignored."] - _1, + #[doc = "Writes to the LMDRn[7:0] are allowed."] _0, + #[doc = "Writes to the LMDRn[7:0] are ignored."] _1, } impl LOCKW { #[allow(missing_docs)] diff --git a/src/mcm/lmfar/mod.rs b/src/mcm/lmfar/mod.rs index b5a70df..40524bd 100644 --- a/src/mcm/lmfar/mod.rs +++ b/src/mcm/lmfar/mod.rs @@ -6,7 +6,9 @@ impl super::LMFAR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mcm/lmfatr/mod.rs b/src/mcm/lmfatr/mod.rs index b9255f0..6ed16e5 100644 --- a/src/mcm/lmfatr/mod.rs +++ b/src/mcm/lmfatr/mod.rs @@ -6,7 +6,9 @@ impl super::LMFATR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,16 +25,11 @@ impl PEFPRTR { #[doc = "Possible values of the field `PEFSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PEFSIZER { - #[doc = "8-bit access"] - _000, - #[doc = "16-bit access"] - _001, - #[doc = "32-bit access"] - _010, - #[doc = "64-bit access"] - _011, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "8-bit access"] _000, + #[doc = "16-bit access"] _001, + #[doc = "32-bit access"] _010, + #[doc = "64-bit access"] _011, + #[doc = r" Reserved"] _Reserved(u8), } impl PEFSIZER { #[doc = r" Value of the field as raw bits"] diff --git a/src/mcm/lmfdhr/mod.rs b/src/mcm/lmfdhr/mod.rs index e111108..5caa968 100644 --- a/src/mcm/lmfdhr/mod.rs +++ b/src/mcm/lmfdhr/mod.rs @@ -6,7 +6,9 @@ impl super::LMFDHR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mcm/lmfdlr/mod.rs b/src/mcm/lmfdlr/mod.rs index 1edadd1..1b9a1b6 100644 --- a/src/mcm/lmfdlr/mod.rs +++ b/src/mcm/lmfdlr/mod.rs @@ -6,7 +6,9 @@ impl super::LMFDLR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mcm/lmpecr/mod.rs b/src/mcm/lmpecr/mod.rs index 382f7fd..ee98616 100644 --- a/src/mcm/lmpecr/mod.rs +++ b/src/mcm/lmpecr/mod.rs @@ -22,7 +22,9 @@ impl super::LMPECR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LMPECR { #[doc = "Possible values of the field `ERNCR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERNCRR { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ERNCRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl ERNCRR { #[doc = "Possible values of the field `ER1BR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ER1BRR { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ER1BRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl ER1BRR { #[doc = "Possible values of the field `ECPR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECPRR { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ECPRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -183,10 +179,8 @@ impl ECPRR { } #[doc = "Values that can be written to the field `ERNCR`"] pub enum ERNCRW { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ERNCRW { #[allow(missing_docs)] @@ -241,10 +235,8 @@ impl<'a> _ERNCRW<'a> { } #[doc = "Values that can be written to the field `ER1BR`"] pub enum ER1BRW { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ER1BRW { #[allow(missing_docs)] @@ -299,10 +291,8 @@ impl<'a> _ER1BRW<'a> { } #[doc = "Values that can be written to the field `ECPR`"] pub enum ECPRW { - #[doc = "Reporting disabled"] - _0, - #[doc = "Reporting enabled"] - _1, + #[doc = "Reporting disabled"] _0, + #[doc = "Reporting enabled"] _1, } impl ECPRW { #[allow(missing_docs)] diff --git a/src/mcm/lmpeir/mod.rs b/src/mcm/lmpeir/mod.rs index 12dc377..bc4b009 100644 --- a/src/mcm/lmpeir/mod.rs +++ b/src/mcm/lmpeir/mod.rs @@ -22,7 +22,9 @@ impl super::LMPEIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -76,12 +78,9 @@ impl PER { #[doc = "Possible values of the field `PEELOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PEELOCR { - #[doc = "Non-correctable ECC event from SRAM_L"] - _00, - #[doc = "Non-correctable ECC event from SRAM_U"] - _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Non-correctable ECC event from SRAM_L"] _00, + #[doc = "Non-correctable ECC event from SRAM_U"] _01, + #[doc = r" Reserved"] _Reserved(u8), } impl PEELOCR { #[doc = r" Value of the field as raw bits"] diff --git a/src/mcm/mod.rs b/src/mcm/mod.rs index 4ab9f7a..8702700 100644 --- a/src/mcm/mod.rs +++ b/src/mcm/mod.rs @@ -3,43 +3,28 @@ use vcell::VolatileCell; #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 8usize], - #[doc = "0x08 - Crossbar Switch (AXBS) Slave Configuration"] - pub plasc: PLASC, - #[doc = "0x0a - Crossbar Switch (AXBS) Master Configuration"] - pub plamc: PLAMC, - #[doc = "0x0c - Core Platform Control Register"] - pub cpcr: CPCR, - #[doc = "0x10 - Interrupt Status and Control Register"] - pub iscr: ISCR, + #[doc = "0x08 - Crossbar Switch (AXBS) Slave Configuration"] pub plasc: PLASC, + #[doc = "0x0a - Crossbar Switch (AXBS) Master Configuration"] pub plamc: PLAMC, + #[doc = "0x0c - Core Platform Control Register"] pub cpcr: CPCR, + #[doc = "0x10 - Interrupt Status and Control Register"] pub iscr: ISCR, _reserved1: [u8; 28usize], - #[doc = "0x30 - Process ID Register"] - pub pid: PID, + #[doc = "0x30 - Process ID Register"] pub pid: PID, _reserved2: [u8; 12usize], - #[doc = "0x40 - Compute Operation Control Register"] - pub cpo: CPO, + #[doc = "0x40 - Compute Operation Control Register"] pub cpo: CPO, _reserved3: [u8; 956usize], - #[doc = "0x400 - Local Memory Descriptor Register"] - pub lmdr0: LMDR0, - #[doc = "0x404 - Local Memory Descriptor Register"] - pub lmdr1: LMDR1, - #[doc = "0x408 - Local Memory Descriptor Register2"] - pub lmdr2: LMDR2, + #[doc = "0x400 - Local Memory Descriptor Register"] pub lmdr0: LMDR0, + #[doc = "0x404 - Local Memory Descriptor Register"] pub lmdr1: LMDR1, + #[doc = "0x408 - Local Memory Descriptor Register2"] pub lmdr2: LMDR2, _reserved4: [u8; 116usize], - #[doc = "0x480 - LMEM Parity and ECC Control Register"] - pub lmpecr: LMPECR, + #[doc = "0x480 - LMEM Parity and ECC Control Register"] pub lmpecr: LMPECR, _reserved5: [u8; 4usize], - #[doc = "0x488 - LMEM Parity and ECC Interrupt Register"] - pub lmpeir: LMPEIR, + #[doc = "0x488 - LMEM Parity and ECC Interrupt Register"] pub lmpeir: LMPEIR, _reserved6: [u8; 4usize], - #[doc = "0x490 - LMEM Fault Address Register"] - pub lmfar: LMFAR, - #[doc = "0x494 - LMEM Fault Attribute Register"] - pub lmfatr: LMFATR, + #[doc = "0x490 - LMEM Fault Address Register"] pub lmfar: LMFAR, + #[doc = "0x494 - LMEM Fault Attribute Register"] pub lmfatr: LMFATR, _reserved7: [u8; 8usize], - #[doc = "0x4a0 - LMEM Fault Data High Register"] - pub lmfdhr: LMFDHR, - #[doc = "0x4a4 - LMEM Fault Data Low Register"] - pub lmfdlr: LMFDLR, + #[doc = "0x4a0 - LMEM Fault Data High Register"] pub lmfdhr: LMFDHR, + #[doc = "0x4a4 - LMEM Fault Data Low Register"] pub lmfdlr: LMFDLR, } #[doc = "Crossbar Switch (AXBS) Slave Configuration"] pub struct PLASC { diff --git a/src/mcm/pid/mod.rs b/src/mcm/pid/mod.rs index 1a95439..830a2fb 100644 --- a/src/mcm/pid/mod.rs +++ b/src/mcm/pid/mod.rs @@ -22,7 +22,9 @@ impl super::PID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/mcm/plamc/mod.rs b/src/mcm/plamc/mod.rs index 8e0a7c4..5f76230 100644 --- a/src/mcm/plamc/mod.rs +++ b/src/mcm/plamc/mod.rs @@ -6,18 +6,17 @@ impl super::PLAMC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `AMC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AMCR { - #[doc = "A bus master connection to AXBS input port n is absent"] - _0, - #[doc = "A bus master connection to AXBS input port n is present"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "A bus master connection to AXBS input port n is absent"] _0, + #[doc = "A bus master connection to AXBS input port n is present"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl AMCR { #[doc = r" Value of the field as raw bits"] diff --git a/src/mcm/plasc/mod.rs b/src/mcm/plasc/mod.rs index 8f29dd5..6a73abd 100644 --- a/src/mcm/plasc/mod.rs +++ b/src/mcm/plasc/mod.rs @@ -6,18 +6,17 @@ impl super::PLASC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `ASC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ASCR { - #[doc = "A bus slave connection to AXBS input port n is absent"] - _0, - #[doc = "A bus slave connection to AXBS input port n is present"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "A bus slave connection to AXBS input port n is absent"] _0, + #[doc = "A bus slave connection to AXBS input port n is present"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl ASCR { #[doc = r" Value of the field as raw bits"] diff --git a/src/mscm/cp0cfg0/mod.rs b/src/mscm/cp0cfg0/mod.rs index 55e243d..1e341e2 100644 --- a/src/mscm/cp0cfg0/mod.rs +++ b/src/mscm/cp0cfg0/mod.rs @@ -6,7 +6,9 @@ impl super::CP0CFG0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0cfg1/mod.rs b/src/mscm/cp0cfg1/mod.rs index b5b6eaa..fbbd968 100644 --- a/src/mscm/cp0cfg1/mod.rs +++ b/src/mscm/cp0cfg1/mod.rs @@ -6,7 +6,9 @@ impl super::CP0CFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0cfg2/mod.rs b/src/mscm/cp0cfg2/mod.rs index 8162124..fd3b36b 100644 --- a/src/mscm/cp0cfg2/mod.rs +++ b/src/mscm/cp0cfg2/mod.rs @@ -6,7 +6,9 @@ impl super::CP0CFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0cfg3/mod.rs b/src/mscm/cp0cfg3/mod.rs index 2a0b026..670ad5e 100644 --- a/src/mscm/cp0cfg3/mod.rs +++ b/src/mscm/cp0cfg3/mod.rs @@ -6,16 +6,16 @@ impl super::CP0CFG3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FPU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FPUR { - #[doc = "FPU support is not included."] - _0, - #[doc = "FPU support is included."] - _1, + #[doc = "FPU support is not included."] _0, + #[doc = "FPU support is included."] _1, } impl FPUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl FPUR { #[doc = "Possible values of the field `SIMD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIMDR { - #[doc = "SIMD/NEON support is not included."] - _0, - #[doc = "SIMD/NEON support is included."] - _1, + #[doc = "SIMD/NEON support is not included."] _0, + #[doc = "SIMD/NEON support is included."] _1, } impl SIMDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl SIMDR { #[doc = "Possible values of the field `JAZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum JAZR { - #[doc = "Jazelle support is not included."] - _0, - #[doc = "Jazelle support is included."] - _1, + #[doc = "Jazelle support is not included."] _0, + #[doc = "Jazelle support is included."] _1, } impl JAZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl JAZR { #[doc = "Possible values of the field `MMU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MMUR { - #[doc = "MMU support is not included."] - _0, - #[doc = "MMU support is included."] - _1, + #[doc = "MMU support is not included."] _0, + #[doc = "MMU support is included."] _1, } impl MMUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl MMUR { #[doc = "Possible values of the field `TZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TZR { - #[doc = "Trust Zone support is not included."] - _0, - #[doc = "Trust Zone support is included."] - _1, + #[doc = "Trust Zone support is not included."] _0, + #[doc = "Trust Zone support is included."] _1, } impl TZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl TZR { #[doc = "Possible values of the field `CMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CMPR { - #[doc = "Core Memory Protection is not included."] - _0, - #[doc = "Core Memory Protection is included."] - _1, + #[doc = "Core Memory Protection is not included."] _0, + #[doc = "Core Memory Protection is included."] _1, } impl CMPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CMPR { #[doc = "Possible values of the field `BB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBR { - #[doc = "Bit Banding is not supported."] - _0, - #[doc = "Bit Banding is supported."] - _1, + #[doc = "Bit Banding is not supported."] _0, + #[doc = "Bit Banding is supported."] _1, } impl BBR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/mscm/cp0count/mod.rs b/src/mscm/cp0count/mod.rs index 8d96faf..3787b86 100644 --- a/src/mscm/cp0count/mod.rs +++ b/src/mscm/cp0count/mod.rs @@ -6,7 +6,9 @@ impl super::CP0COUNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0master/mod.rs b/src/mscm/cp0master/mod.rs index 81bab13..67a3215 100644 --- a/src/mscm/cp0master/mod.rs +++ b/src/mscm/cp0master/mod.rs @@ -6,7 +6,9 @@ impl super::CP0MASTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0num/mod.rs b/src/mscm/cp0num/mod.rs index 77b3391..9160ead 100644 --- a/src/mscm/cp0num/mod.rs +++ b/src/mscm/cp0num/mod.rs @@ -6,7 +6,9 @@ impl super::CP0NUM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cp0type/mod.rs b/src/mscm/cp0type/mod.rs index 7d5efa1..da7ba66 100644 --- a/src/mscm/cp0type/mod.rs +++ b/src/mscm/cp0type/mod.rs @@ -6,7 +6,9 @@ impl super::CP0TYPE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_cfg0/mod.rs b/src/mscm/cpx_cfg0/mod.rs index 35844af..767cf8c 100644 --- a/src/mscm/cpx_cfg0/mod.rs +++ b/src/mscm/cpx_cfg0/mod.rs @@ -6,7 +6,9 @@ impl super::CPXCFG0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_cfg1/mod.rs b/src/mscm/cpx_cfg1/mod.rs index d6d4007..b976370 100644 --- a/src/mscm/cpx_cfg1/mod.rs +++ b/src/mscm/cpx_cfg1/mod.rs @@ -6,7 +6,9 @@ impl super::CPXCFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_cfg2/mod.rs b/src/mscm/cpx_cfg2/mod.rs index 972dad2..134a35e 100644 --- a/src/mscm/cpx_cfg2/mod.rs +++ b/src/mscm/cpx_cfg2/mod.rs @@ -6,7 +6,9 @@ impl super::CPXCFG2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_cfg3/mod.rs b/src/mscm/cpx_cfg3/mod.rs index 40cc94f..9b16803 100644 --- a/src/mscm/cpx_cfg3/mod.rs +++ b/src/mscm/cpx_cfg3/mod.rs @@ -6,16 +6,16 @@ impl super::CPXCFG3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FPU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FPUR { - #[doc = "FPU support is not included."] - _0, - #[doc = "FPU support is included."] - _1, + #[doc = "FPU support is not included."] _0, + #[doc = "FPU support is included."] _1, } impl FPUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl FPUR { #[doc = "Possible values of the field `SIMD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIMDR { - #[doc = "SIMD/NEON support is not included."] - _0, - #[doc = "SIMD/NEON support is included."] - _1, + #[doc = "SIMD/NEON support is not included."] _0, + #[doc = "SIMD/NEON support is included."] _1, } impl SIMDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl SIMDR { #[doc = "Possible values of the field `JAZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum JAZR { - #[doc = "Jazelle support is not included."] - _0, - #[doc = "Jazelle support is included."] - _1, + #[doc = "Jazelle support is not included."] _0, + #[doc = "Jazelle support is included."] _1, } impl JAZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl JAZR { #[doc = "Possible values of the field `MMU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MMUR { - #[doc = "MMU support is not included."] - _0, - #[doc = "MMU support is included."] - _1, + #[doc = "MMU support is not included."] _0, + #[doc = "MMU support is included."] _1, } impl MMUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl MMUR { #[doc = "Possible values of the field `TZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TZR { - #[doc = "Trust Zone support is not included."] - _0, - #[doc = "Trust Zone support is included."] - _1, + #[doc = "Trust Zone support is not included."] _0, + #[doc = "Trust Zone support is included."] _1, } impl TZR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl TZR { #[doc = "Possible values of the field `CMP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CMPR { - #[doc = "Core Memory Protection is not included."] - _0, - #[doc = "Core Memory Protection is included."] - _1, + #[doc = "Core Memory Protection is not included."] _0, + #[doc = "Core Memory Protection is included."] _1, } impl CMPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl CMPR { #[doc = "Possible values of the field `BB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBR { - #[doc = "Bit Banding is not supported."] - _0, - #[doc = "Bit Banding is supported."] - _1, + #[doc = "Bit Banding is not supported."] _0, + #[doc = "Bit Banding is supported."] _1, } impl BBR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/mscm/cpx_count/mod.rs b/src/mscm/cpx_count/mod.rs index b732c04..d957eb0 100644 --- a/src/mscm/cpx_count/mod.rs +++ b/src/mscm/cpx_count/mod.rs @@ -6,7 +6,9 @@ impl super::CPXCOUNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_master/mod.rs b/src/mscm/cpx_master/mod.rs index 05f7ca3..6ba7381 100644 --- a/src/mscm/cpx_master/mod.rs +++ b/src/mscm/cpx_master/mod.rs @@ -6,7 +6,9 @@ impl super::CPXMASTER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_num/mod.rs b/src/mscm/cpx_num/mod.rs index f0e6fef..19c7a10 100644 --- a/src/mscm/cpx_num/mod.rs +++ b/src/mscm/cpx_num/mod.rs @@ -6,7 +6,9 @@ impl super::CPXNUM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/cpx_type/mod.rs b/src/mscm/cpx_type/mod.rs index c14e9c2..562a2b1 100644 --- a/src/mscm/cpx_type/mod.rs +++ b/src/mscm/cpx_type/mod.rs @@ -6,7 +6,9 @@ impl super::CPXTYPE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/mscm/mod.rs b/src/mscm/mod.rs index 668c657..3428ce3 100644 --- a/src/mscm/mod.rs +++ b/src/mscm/mod.rs @@ -2,47 +2,27 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Processor X Type Register"] - pub cpx_type: CPXTYPE, - #[doc = "0x04 - Processor X Number Register"] - pub cpx_num: CPXNUM, - #[doc = "0x08 - Processor X Master Register"] - pub cpx_master: CPXMASTER, - #[doc = "0x0c - Processor X Count Register"] - pub cpx_count: CPXCOUNT, - #[doc = "0x10 - Processor X Configuration Register 0"] - pub cpx_cfg0: CPXCFG0, - #[doc = "0x14 - Processor X Configuration Register 1"] - pub cpx_cfg1: CPXCFG1, - #[doc = "0x18 - Processor X Configuration Register 2"] - pub cpx_cfg2: CPXCFG2, - #[doc = "0x1c - Processor X Configuration Register 3"] - pub cpx_cfg3: CPXCFG3, - #[doc = "0x20 - Processor 0 Type Register"] - pub cp0type: CP0TYPE, - #[doc = "0x24 - Processor 0 Number Register"] - pub cp0num: CP0NUM, - #[doc = "0x28 - Processor 0 Master Register"] - pub cp0master: CP0MASTER, - #[doc = "0x2c - Processor 0 Count Register"] - pub cp0count: CP0COUNT, - #[doc = "0x30 - Processor 0 Configuration Register 0"] - pub cp0cfg0: CP0CFG0, - #[doc = "0x34 - Processor 0 Configuration Register 1"] - pub cp0cfg1: CP0CFG1, - #[doc = "0x38 - Processor 0 Configuration Register 2"] - pub cp0cfg2: CP0CFG2, - #[doc = "0x3c - Processor 0 Configuration Register 3"] - pub cp0cfg3: CP0CFG3, + #[doc = "0x00 - Processor X Type Register"] pub cpx_type: CPXTYPE, + #[doc = "0x04 - Processor X Number Register"] pub cpx_num: CPXNUM, + #[doc = "0x08 - Processor X Master Register"] pub cpx_master: CPXMASTER, + #[doc = "0x0c - Processor X Count Register"] pub cpx_count: CPXCOUNT, + #[doc = "0x10 - Processor X Configuration Register 0"] pub cpx_cfg0: CPXCFG0, + #[doc = "0x14 - Processor X Configuration Register 1"] pub cpx_cfg1: CPXCFG1, + #[doc = "0x18 - Processor X Configuration Register 2"] pub cpx_cfg2: CPXCFG2, + #[doc = "0x1c - Processor X Configuration Register 3"] pub cpx_cfg3: CPXCFG3, + #[doc = "0x20 - Processor 0 Type Register"] pub cp0type: CP0TYPE, + #[doc = "0x24 - Processor 0 Number Register"] pub cp0num: CP0NUM, + #[doc = "0x28 - Processor 0 Master Register"] pub cp0master: CP0MASTER, + #[doc = "0x2c - Processor 0 Count Register"] pub cp0count: CP0COUNT, + #[doc = "0x30 - Processor 0 Configuration Register 0"] pub cp0cfg0: CP0CFG0, + #[doc = "0x34 - Processor 0 Configuration Register 1"] pub cp0cfg1: CP0CFG1, + #[doc = "0x38 - Processor 0 Configuration Register 2"] pub cp0cfg2: CP0CFG2, + #[doc = "0x3c - Processor 0 Configuration Register 3"] pub cp0cfg3: CP0CFG3, _reserved0: [u8; 960usize], - #[doc = "0x400 - On-Chip Memory Descriptor Register"] - pub ocmdr0: OCMDR0, - #[doc = "0x404 - On-Chip Memory Descriptor Register"] - pub ocmdr1: OCMDR1, - #[doc = "0x408 - On-Chip Memory Descriptor Register"] - pub ocmdr2: OCMDR2, - #[doc = "0x40c - On-Chip Memory Descriptor Register"] - pub ocmdr3: OCMDR3, + #[doc = "0x400 - On-Chip Memory Descriptor Register"] pub ocmdr0: OCMDR0, + #[doc = "0x404 - On-Chip Memory Descriptor Register"] pub ocmdr1: OCMDR1, + #[doc = "0x408 - On-Chip Memory Descriptor Register"] pub ocmdr2: OCMDR2, + #[doc = "0x40c - On-Chip Memory Descriptor Register"] pub ocmdr3: OCMDR3, } #[doc = "Processor X Type Register"] pub struct CPXTYPE { diff --git a/src/mscm/ocmdr0/mod.rs b/src/mscm/ocmdr0/mod.rs index ffd855d..be71108 100644 --- a/src/mscm/ocmdr0/mod.rs +++ b/src/mscm/ocmdr0/mod.rs @@ -22,7 +22,9 @@ impl super::OCMDR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -97,20 +99,13 @@ impl OCMPUR { #[doc = "Possible values of the field `OCMT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMTR { - #[doc = "OCMEMn is a System RAM."] - _000, - #[doc = "OCMEMn is a Graphics RAM."] - _001, - #[doc = "OCMEMn is a ROM."] - _011, - #[doc = "OCMEMn is a Program Flash."] - _100, - #[doc = "OCMEMn is a Data Flash."] - _101, - #[doc = "OCMEMn is an EEE."] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn is a System RAM."] _000, + #[doc = "OCMEMn is a Graphics RAM."] _001, + #[doc = "OCMEMn is a ROM."] _011, + #[doc = "OCMEMn is a Program Flash."] _100, + #[doc = "OCMEMn is a Data Flash."] _101, + #[doc = "OCMEMn is an EEE."] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMTR { #[doc = r" Value of the field as raw bits"] @@ -174,10 +169,8 @@ impl OCMTR { #[doc = "Possible values of the field `RO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ROR { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,16 +214,11 @@ impl ROR { #[doc = "Possible values of the field `OCMW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMWR { - #[doc = "OCMEMn 32-bits wide"] - _010, - #[doc = "OCMEMn 64-bits wide"] - _011, - #[doc = "OCMEMn 128-bits wide"] - _100, - #[doc = "OCMEMn 256-bits wide"] - _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn 32-bits wide"] _010, + #[doc = "OCMEMn 64-bits wide"] _011, + #[doc = "OCMEMn 128-bits wide"] _100, + #[doc = "OCMEMn 256-bits wide"] _101, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMWR { #[doc = r" Value of the field as raw bits"] @@ -280,38 +268,22 @@ impl OCMWR { #[doc = "Possible values of the field `OCMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZR { - #[doc = "no OCMEMn"] - _0000, - #[doc = "1KB OCMEMn"] - _0001, - #[doc = "2KB OCMEMn"] - _0010, - #[doc = "4KB OCMEMn"] - _0011, - #[doc = "8KB OCMEMn"] - _0100, - #[doc = "16KB OCMEMn"] - _0101, - #[doc = "32KB OCMEMn"] - _0110, - #[doc = "64KB OCMEMn"] - _0111, - #[doc = "128KB OCMEMn"] - _1000, - #[doc = "256KB OCMEMn"] - _1001, - #[doc = "512KB OCMEMn"] - _1010, - #[doc = "1MB OCMEMn"] - _1011, - #[doc = "2MB OCMEMn"] - _1100, - #[doc = "4MB OCMEMn"] - _1101, - #[doc = "8MB OCMEMn"] - _1110, - #[doc = "16MB OCMEMn"] - _1111, + #[doc = "no OCMEMn"] _0000, + #[doc = "1KB OCMEMn"] _0001, + #[doc = "2KB OCMEMn"] _0010, + #[doc = "4KB OCMEMn"] _0011, + #[doc = "8KB OCMEMn"] _0100, + #[doc = "16KB OCMEMn"] _0101, + #[doc = "32KB OCMEMn"] _0110, + #[doc = "64KB OCMEMn"] _0111, + #[doc = "128KB OCMEMn"] _1000, + #[doc = "256KB OCMEMn"] _1001, + #[doc = "512KB OCMEMn"] _1010, + #[doc = "1MB OCMEMn"] _1011, + #[doc = "2MB OCMEMn"] _1100, + #[doc = "4MB OCMEMn"] _1101, + #[doc = "8MB OCMEMn"] _1110, + #[doc = "16MB OCMEMn"] _1111, } impl OCMSZR { #[doc = r" Value of the field as raw bits"] @@ -444,10 +416,8 @@ impl OCMSZR { #[doc = "Possible values of the field `OCMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZHR { - #[doc = "OCMEMn is a power-of-2 capacity."] - _0, - #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] - _1, + #[doc = "OCMEMn is a power-of-2 capacity."] _0, + #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] _1, } impl OCMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -491,10 +461,8 @@ impl OCMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "OCMEMn is not present."] - _0, - #[doc = "OCMEMn is present."] - _1, + #[doc = "OCMEMn is not present."] _0, + #[doc = "OCMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -582,10 +550,8 @@ impl<'a> _OCM2W<'a> { } #[doc = "Values that can be written to the field `RO`"] pub enum ROW { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROW { #[allow(missing_docs)] diff --git a/src/mscm/ocmdr1/mod.rs b/src/mscm/ocmdr1/mod.rs index 1c67f29..153791e 100644 --- a/src/mscm/ocmdr1/mod.rs +++ b/src/mscm/ocmdr1/mod.rs @@ -22,7 +22,9 @@ impl super::OCMDR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -97,20 +99,13 @@ impl OCMPUR { #[doc = "Possible values of the field `OCMT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMTR { - #[doc = "OCMEMn is a System RAM."] - _000, - #[doc = "OCMEMn is a Graphics RAM."] - _001, - #[doc = "OCMEMn is a ROM."] - _011, - #[doc = "OCMEMn is a Program Flash."] - _100, - #[doc = "OCMEMn is a Data Flash."] - _101, - #[doc = "OCMEMn is an EEE."] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn is a System RAM."] _000, + #[doc = "OCMEMn is a Graphics RAM."] _001, + #[doc = "OCMEMn is a ROM."] _011, + #[doc = "OCMEMn is a Program Flash."] _100, + #[doc = "OCMEMn is a Data Flash."] _101, + #[doc = "OCMEMn is an EEE."] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMTR { #[doc = r" Value of the field as raw bits"] @@ -174,10 +169,8 @@ impl OCMTR { #[doc = "Possible values of the field `RO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ROR { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,16 +214,11 @@ impl ROR { #[doc = "Possible values of the field `OCMW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMWR { - #[doc = "OCMEMn 32-bits wide"] - _010, - #[doc = "OCMEMn 64-bits wide"] - _011, - #[doc = "OCMEMn 128-bits wide"] - _100, - #[doc = "OCMEMn 256-bits wide"] - _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn 32-bits wide"] _010, + #[doc = "OCMEMn 64-bits wide"] _011, + #[doc = "OCMEMn 128-bits wide"] _100, + #[doc = "OCMEMn 256-bits wide"] _101, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMWR { #[doc = r" Value of the field as raw bits"] @@ -280,38 +268,22 @@ impl OCMWR { #[doc = "Possible values of the field `OCMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZR { - #[doc = "no OCMEMn"] - _0000, - #[doc = "1KB OCMEMn"] - _0001, - #[doc = "2KB OCMEMn"] - _0010, - #[doc = "4KB OCMEMn"] - _0011, - #[doc = "8KB OCMEMn"] - _0100, - #[doc = "16KB OCMEMn"] - _0101, - #[doc = "32KB OCMEMn"] - _0110, - #[doc = "64KB OCMEMn"] - _0111, - #[doc = "128KB OCMEMn"] - _1000, - #[doc = "256KB OCMEMn"] - _1001, - #[doc = "512KB OCMEMn"] - _1010, - #[doc = "1MB OCMEMn"] - _1011, - #[doc = "2MB OCMEMn"] - _1100, - #[doc = "4MB OCMEMn"] - _1101, - #[doc = "8MB OCMEMn"] - _1110, - #[doc = "16MB OCMEMn"] - _1111, + #[doc = "no OCMEMn"] _0000, + #[doc = "1KB OCMEMn"] _0001, + #[doc = "2KB OCMEMn"] _0010, + #[doc = "4KB OCMEMn"] _0011, + #[doc = "8KB OCMEMn"] _0100, + #[doc = "16KB OCMEMn"] _0101, + #[doc = "32KB OCMEMn"] _0110, + #[doc = "64KB OCMEMn"] _0111, + #[doc = "128KB OCMEMn"] _1000, + #[doc = "256KB OCMEMn"] _1001, + #[doc = "512KB OCMEMn"] _1010, + #[doc = "1MB OCMEMn"] _1011, + #[doc = "2MB OCMEMn"] _1100, + #[doc = "4MB OCMEMn"] _1101, + #[doc = "8MB OCMEMn"] _1110, + #[doc = "16MB OCMEMn"] _1111, } impl OCMSZR { #[doc = r" Value of the field as raw bits"] @@ -444,10 +416,8 @@ impl OCMSZR { #[doc = "Possible values of the field `OCMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZHR { - #[doc = "OCMEMn is a power-of-2 capacity."] - _0, - #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] - _1, + #[doc = "OCMEMn is a power-of-2 capacity."] _0, + #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] _1, } impl OCMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -491,10 +461,8 @@ impl OCMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "OCMEMn is not present."] - _0, - #[doc = "OCMEMn is present."] - _1, + #[doc = "OCMEMn is not present."] _0, + #[doc = "OCMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -582,10 +550,8 @@ impl<'a> _OCM2W<'a> { } #[doc = "Values that can be written to the field `RO`"] pub enum ROW { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROW { #[allow(missing_docs)] diff --git a/src/mscm/ocmdr2/mod.rs b/src/mscm/ocmdr2/mod.rs index e013858..3a06a11 100644 --- a/src/mscm/ocmdr2/mod.rs +++ b/src/mscm/ocmdr2/mod.rs @@ -22,7 +22,9 @@ impl super::OCMDR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -97,20 +99,13 @@ impl OCMPUR { #[doc = "Possible values of the field `OCMT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMTR { - #[doc = "OCMEMn is a System RAM."] - _000, - #[doc = "OCMEMn is a Graphics RAM."] - _001, - #[doc = "OCMEMn is a ROM."] - _011, - #[doc = "OCMEMn is a Program Flash."] - _100, - #[doc = "OCMEMn is a Data Flash."] - _101, - #[doc = "OCMEMn is an EEE."] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn is a System RAM."] _000, + #[doc = "OCMEMn is a Graphics RAM."] _001, + #[doc = "OCMEMn is a ROM."] _011, + #[doc = "OCMEMn is a Program Flash."] _100, + #[doc = "OCMEMn is a Data Flash."] _101, + #[doc = "OCMEMn is an EEE."] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMTR { #[doc = r" Value of the field as raw bits"] @@ -174,10 +169,8 @@ impl OCMTR { #[doc = "Possible values of the field `RO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ROR { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,16 +214,11 @@ impl ROR { #[doc = "Possible values of the field `OCMW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMWR { - #[doc = "OCMEMn 32-bits wide"] - _010, - #[doc = "OCMEMn 64-bits wide"] - _011, - #[doc = "OCMEMn 128-bits wide"] - _100, - #[doc = "OCMEMn 256-bits wide"] - _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn 32-bits wide"] _010, + #[doc = "OCMEMn 64-bits wide"] _011, + #[doc = "OCMEMn 128-bits wide"] _100, + #[doc = "OCMEMn 256-bits wide"] _101, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMWR { #[doc = r" Value of the field as raw bits"] @@ -280,38 +268,22 @@ impl OCMWR { #[doc = "Possible values of the field `OCMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZR { - #[doc = "no OCMEMn"] - _0000, - #[doc = "1KB OCMEMn"] - _0001, - #[doc = "2KB OCMEMn"] - _0010, - #[doc = "4KB OCMEMn"] - _0011, - #[doc = "8KB OCMEMn"] - _0100, - #[doc = "16KB OCMEMn"] - _0101, - #[doc = "32KB OCMEMn"] - _0110, - #[doc = "64KB OCMEMn"] - _0111, - #[doc = "128KB OCMEMn"] - _1000, - #[doc = "256KB OCMEMn"] - _1001, - #[doc = "512KB OCMEMn"] - _1010, - #[doc = "1MB OCMEMn"] - _1011, - #[doc = "2MB OCMEMn"] - _1100, - #[doc = "4MB OCMEMn"] - _1101, - #[doc = "8MB OCMEMn"] - _1110, - #[doc = "16MB OCMEMn"] - _1111, + #[doc = "no OCMEMn"] _0000, + #[doc = "1KB OCMEMn"] _0001, + #[doc = "2KB OCMEMn"] _0010, + #[doc = "4KB OCMEMn"] _0011, + #[doc = "8KB OCMEMn"] _0100, + #[doc = "16KB OCMEMn"] _0101, + #[doc = "32KB OCMEMn"] _0110, + #[doc = "64KB OCMEMn"] _0111, + #[doc = "128KB OCMEMn"] _1000, + #[doc = "256KB OCMEMn"] _1001, + #[doc = "512KB OCMEMn"] _1010, + #[doc = "1MB OCMEMn"] _1011, + #[doc = "2MB OCMEMn"] _1100, + #[doc = "4MB OCMEMn"] _1101, + #[doc = "8MB OCMEMn"] _1110, + #[doc = "16MB OCMEMn"] _1111, } impl OCMSZR { #[doc = r" Value of the field as raw bits"] @@ -444,10 +416,8 @@ impl OCMSZR { #[doc = "Possible values of the field `OCMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZHR { - #[doc = "OCMEMn is a power-of-2 capacity."] - _0, - #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] - _1, + #[doc = "OCMEMn is a power-of-2 capacity."] _0, + #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] _1, } impl OCMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -491,10 +461,8 @@ impl OCMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "OCMEMn is not present."] - _0, - #[doc = "OCMEMn is present."] - _1, + #[doc = "OCMEMn is not present."] _0, + #[doc = "OCMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -582,10 +550,8 @@ impl<'a> _OCM2W<'a> { } #[doc = "Values that can be written to the field `RO`"] pub enum ROW { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROW { #[allow(missing_docs)] diff --git a/src/mscm/ocmdr3/mod.rs b/src/mscm/ocmdr3/mod.rs index d774e2e..5d994c2 100644 --- a/src/mscm/ocmdr3/mod.rs +++ b/src/mscm/ocmdr3/mod.rs @@ -22,7 +22,9 @@ impl super::OCMDR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -97,20 +99,13 @@ impl OCMPUR { #[doc = "Possible values of the field `OCMT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMTR { - #[doc = "OCMEMn is a System RAM."] - _000, - #[doc = "OCMEMn is a Graphics RAM."] - _001, - #[doc = "OCMEMn is a ROM."] - _011, - #[doc = "OCMEMn is a Program Flash."] - _100, - #[doc = "OCMEMn is a Data Flash."] - _101, - #[doc = "OCMEMn is an EEE."] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn is a System RAM."] _000, + #[doc = "OCMEMn is a Graphics RAM."] _001, + #[doc = "OCMEMn is a ROM."] _011, + #[doc = "OCMEMn is a Program Flash."] _100, + #[doc = "OCMEMn is a Data Flash."] _101, + #[doc = "OCMEMn is an EEE."] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMTR { #[doc = r" Value of the field as raw bits"] @@ -174,10 +169,8 @@ impl OCMTR { #[doc = "Possible values of the field `RO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ROR { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -221,16 +214,11 @@ impl ROR { #[doc = "Possible values of the field `OCMW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMWR { - #[doc = "OCMEMn 32-bits wide"] - _010, - #[doc = "OCMEMn 64-bits wide"] - _011, - #[doc = "OCMEMn 128-bits wide"] - _100, - #[doc = "OCMEMn 256-bits wide"] - _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "OCMEMn 32-bits wide"] _010, + #[doc = "OCMEMn 64-bits wide"] _011, + #[doc = "OCMEMn 128-bits wide"] _100, + #[doc = "OCMEMn 256-bits wide"] _101, + #[doc = r" Reserved"] _Reserved(u8), } impl OCMWR { #[doc = r" Value of the field as raw bits"] @@ -280,38 +268,22 @@ impl OCMWR { #[doc = "Possible values of the field `OCMSZ`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZR { - #[doc = "no OCMEMn"] - _0000, - #[doc = "1KB OCMEMn"] - _0001, - #[doc = "2KB OCMEMn"] - _0010, - #[doc = "4KB OCMEMn"] - _0011, - #[doc = "8KB OCMEMn"] - _0100, - #[doc = "16KB OCMEMn"] - _0101, - #[doc = "32KB OCMEMn"] - _0110, - #[doc = "64KB OCMEMn"] - _0111, - #[doc = "128KB OCMEMn"] - _1000, - #[doc = "256KB OCMEMn"] - _1001, - #[doc = "512KB OCMEMn"] - _1010, - #[doc = "1MB OCMEMn"] - _1011, - #[doc = "2MB OCMEMn"] - _1100, - #[doc = "4MB OCMEMn"] - _1101, - #[doc = "8MB OCMEMn"] - _1110, - #[doc = "16MB OCMEMn"] - _1111, + #[doc = "no OCMEMn"] _0000, + #[doc = "1KB OCMEMn"] _0001, + #[doc = "2KB OCMEMn"] _0010, + #[doc = "4KB OCMEMn"] _0011, + #[doc = "8KB OCMEMn"] _0100, + #[doc = "16KB OCMEMn"] _0101, + #[doc = "32KB OCMEMn"] _0110, + #[doc = "64KB OCMEMn"] _0111, + #[doc = "128KB OCMEMn"] _1000, + #[doc = "256KB OCMEMn"] _1001, + #[doc = "512KB OCMEMn"] _1010, + #[doc = "1MB OCMEMn"] _1011, + #[doc = "2MB OCMEMn"] _1100, + #[doc = "4MB OCMEMn"] _1101, + #[doc = "8MB OCMEMn"] _1110, + #[doc = "16MB OCMEMn"] _1111, } impl OCMSZR { #[doc = r" Value of the field as raw bits"] @@ -444,10 +416,8 @@ impl OCMSZR { #[doc = "Possible values of the field `OCMSZH`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OCMSZHR { - #[doc = "OCMEMn is a power-of-2 capacity."] - _0, - #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] - _1, + #[doc = "OCMEMn is a power-of-2 capacity."] _0, + #[doc = "OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ."] _1, } impl OCMSZHR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -491,10 +461,8 @@ impl OCMSZHR { #[doc = "Possible values of the field `V`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VR { - #[doc = "OCMEMn is not present."] - _0, - #[doc = "OCMEMn is present."] - _1, + #[doc = "OCMEMn is not present."] _0, + #[doc = "OCMEMn is present."] _1, } impl VR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -582,10 +550,8 @@ impl<'a> _OCM2W<'a> { } #[doc = "Values that can be written to the field `RO`"] pub enum ROW { - #[doc = "Writes to the OCMDRn[11:0] are allowed"] - _0, - #[doc = "Writes to the OCMDRn[11:0] are ignored"] - _1, + #[doc = "Writes to the OCMDRn[11:0] are allowed"] _0, + #[doc = "Writes to the OCMDRn[11:0] are ignored"] _1, } impl ROW { #[allow(missing_docs)] diff --git a/src/pcc/mod.rs b/src/pcc/mod.rs index cd86265..b66ae1b 100644 --- a/src/pcc/mod.rs +++ b/src/pcc/mod.rs @@ -2,238 +2,122 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - PCC Reserved Register 0"] - pub pccdummy0: PCCDUMMY0, - #[doc = "0x04 - PCC Reserved Register 1"] - pub pccdummy1: PCCDUMMY1, - #[doc = "0x08 - PCC Reserved Register 2"] - pub pccdummy2: PCCDUMMY2, - #[doc = "0x0c - PCC Reserved Register 3"] - pub pccdummy3: PCCDUMMY3, - #[doc = "0x10 - PCC Reserved Register 4"] - pub pccdummy4: PCCDUMMY4, - #[doc = "0x14 - PCC Reserved Register 5"] - pub pccdummy5: PCCDUMMY5, - #[doc = "0x18 - PCC Reserved Register 6"] - pub pccdummy6: PCCDUMMY6, - #[doc = "0x1c - PCC Reserved Register 7"] - pub pccdummy7: PCCDUMMY7, - #[doc = "0x20 - PCC Reserved Register 8"] - pub pccdummy8: PCCDUMMY8, - #[doc = "0x24 - PCC Reserved Register 9"] - pub pccdummy9: PCCDUMMY9, - #[doc = "0x28 - PCC Reserved Register 10"] - pub pccdummy10: PCCDUMMY10, - #[doc = "0x2c - PCC Reserved Register 11"] - pub pccdummy11: PCCDUMMY11, - #[doc = "0x30 - PCC Reserved Register 12"] - pub pccdummy12: PCCDUMMY12, - #[doc = "0x34 - PCC Reserved Register 13"] - pub pccdummy13: PCCDUMMY13, - #[doc = "0x38 - PCC Reserved Register 14"] - pub pccdummy14: PCCDUMMY14, - #[doc = "0x3c - PCC Reserved Register 15"] - pub pccdummy15: PCCDUMMY15, - #[doc = "0x40 - PCC Reserved Register 16"] - pub pccdummy16: PCCDUMMY16, - #[doc = "0x44 - PCC Reserved Register 17"] - pub pccdummy17: PCCDUMMY17, - #[doc = "0x48 - PCC Reserved Register 18"] - pub pccdummy18: PCCDUMMY18, - #[doc = "0x4c - PCC Reserved Register 19"] - pub pccdummy19: PCCDUMMY19, - #[doc = "0x50 - PCC Reserved Register 20"] - pub pccdummy20: PCCDUMMY20, - #[doc = "0x54 - PCC Reserved Register 21"] - pub pccdummy21: PCCDUMMY21, - #[doc = "0x58 - PCC Reserved Register 22"] - pub pccdummy22: PCCDUMMY22, - #[doc = "0x5c - PCC Reserved Register 23"] - pub pccdummy23: PCCDUMMY23, - #[doc = "0x60 - PCC Reserved Register 24"] - pub pccdummy24: PCCDUMMY24, - #[doc = "0x64 - PCC Reserved Register 25"] - pub pccdummy25: PCCDUMMY25, - #[doc = "0x68 - PCC Reserved Register 26"] - pub pccdummy26: PCCDUMMY26, - #[doc = "0x6c - PCC Reserved Register 27"] - pub pccdummy27: PCCDUMMY27, - #[doc = "0x70 - PCC Reserved Register 28"] - pub pccdummy28: PCCDUMMY28, - #[doc = "0x74 - PCC Reserved Register 29"] - pub pccdummy29: PCCDUMMY29, - #[doc = "0x78 - PCC Reserved Register 30"] - pub pccdummy30: PCCDUMMY30, - #[doc = "0x7c - PCC Reserved Register 31"] - pub pccdummy31: PCCDUMMY31, - #[doc = "0x80 - PCC FTFC Register"] - pub pcc_ftfc: PCC_FTFC, - #[doc = "0x84 - PCC DMAMUX Register"] - pub pcc_dmamux: PCC_DMAMUX, - #[doc = "0x88 - PCC Reserved Register 34"] - pub pccdummy34: PCCDUMMY34, - #[doc = "0x8c - PCC Reserved Register 35"] - pub pccdummy35: PCCDUMMY35, - #[doc = "0x90 - PCC FlexCAN0 Register"] - pub pcc_flex_can0: PCC_FLEXCAN0, - #[doc = "0x94 - PCC FlexCAN1 Register"] - pub pcc_flex_can1: PCC_FLEXCAN1, - #[doc = "0x98 - PCC FTM3 Register"] - pub pcc_ftm3: PCC_FTM3, - #[doc = "0x9c - PCC ADC1 Register"] - pub pcc_adc1: PCC_ADC1, - #[doc = "0xa0 - PCC Reserved Register 40"] - pub pccdummy40: PCCDUMMY40, - #[doc = "0xa4 - PCC Reserved Register 41"] - pub pccdummy41: PCCDUMMY41, - #[doc = "0xa8 - PCC Reserved Register 42"] - pub pccdummy42: PCCDUMMY42, - #[doc = "0xac - PCC FlexCAN2 Register"] - pub pcc_flex_can2: PCC_FLEXCAN2, - #[doc = "0xb0 - PCC LPSPI0 Register"] - pub pcc_lpspi0: PCC_LPSPI0, - #[doc = "0xb4 - PCC LPSPI1 Register"] - pub pcc_lpspi1: PCC_LPSPI1, - #[doc = "0xb8 - PCC LPSPI2 Register"] - pub pcc_lpspi2: PCC_LPSPI2, - #[doc = "0xbc - PCC Reserved Register 47"] - pub pccdummy47: PCCDUMMY47, - #[doc = "0xc0 - PCC Reserved Register 48"] - pub pccdummy48: PCCDUMMY48, - #[doc = "0xc4 - PCC PDB1 Register"] - pub pcc_pdb1: PCC_PDB1, - #[doc = "0xc8 - PCC CRC Register"] - pub pcc_crc: PCC_CRC, - #[doc = "0xcc - PCC Reserved Register 51"] - pub pccdummy51: PCCDUMMY51, - #[doc = "0xd0 - PCC Reserved Register 52"] - pub pccdummy52: PCCDUMMY52, - #[doc = "0xd4 - PCC Reserved Register 53"] - pub pccdummy53: PCCDUMMY53, - #[doc = "0xd8 - PCC PDB0 Register"] - pub pcc_pdb0: PCC_PDB0, - #[doc = "0xdc - PCC LPIT Register"] - pub pcc_lpit: PCC_LPIT, - #[doc = "0xe0 - PCC FTM0 Register"] - pub pcc_ftm0: PCC_FTM0, - #[doc = "0xe4 - PCC FTM1 Register"] - pub pcc_ftm1: PCC_FTM1, - #[doc = "0xe8 - PCC FTM2 Register"] - pub pcc_ftm2: PCC_FTM2, - #[doc = "0xec - PCC ADC0 Register"] - pub pcc_adc0: PCC_ADC0, - #[doc = "0xf0 - PCC Reserved Register 60"] - pub pccdummy60: PCCDUMMY60, - #[doc = "0xf4 - PCC RTC Register"] - pub pcc_rtc: PCC_RTC, - #[doc = "0xf8 - PCC Reserved Register 62"] - pub pccdummy62: PCCDUMMY62, - #[doc = "0xfc - PCC Reserved Register 63"] - pub pccdummy63: PCCDUMMY63, - #[doc = "0x100 - PCC LPTMR0 Register"] - pub pcc_lptmr0: PCC_LPTMR0, - #[doc = "0x104 - PCC Reserved Register 65"] - pub pccdummy65: PCCDUMMY65, - #[doc = "0x108 - PCC Reserved Register 66"] - pub pccdummy66: PCCDUMMY66, - #[doc = "0x10c - PCC Reserved Register 67"] - pub pccdummy67: PCCDUMMY67, - #[doc = "0x110 - PCC Reserved Register 68"] - pub pccdummy68: PCCDUMMY68, - #[doc = "0x114 - PCC Reserved Register 69"] - pub pccdummy69: PCCDUMMY69, - #[doc = "0x118 - PCC Reserved Register 70"] - pub pccdummy70: PCCDUMMY70, - #[doc = "0x11c - PCC Reserved Register 71"] - pub pccdummy71: PCCDUMMY71, - #[doc = "0x120 - PCC Reserved Register 72"] - pub pccdummy72: PCCDUMMY72, - #[doc = "0x124 - PCC PORTA Register"] - pub pcc_porta: PCC_PORTA, - #[doc = "0x128 - PCC PORTB Register"] - pub pcc_portb: PCC_PORTB, - #[doc = "0x12c - PCC PORTC Register"] - pub pcc_portc: PCC_PORTC, - #[doc = "0x130 - PCC PORTD Register"] - pub pcc_portd: PCC_PORTD, - #[doc = "0x134 - PCC PORTE Register"] - pub pcc_porte: PCC_PORTE, - #[doc = "0x138 - PCC Reserved Register 78"] - pub pccdummy78: PCCDUMMY78, - #[doc = "0x13c - PCC Reserved Register 79"] - pub pccdummy79: PCCDUMMY79, - #[doc = "0x140 - PCC Reserved Register 80"] - pub pccdummy80: PCCDUMMY80, - #[doc = "0x144 - PCC Reserved Register 81"] - pub pccdummy81: PCCDUMMY81, - #[doc = "0x148 - PCC Reserved Register 82"] - pub pccdummy82: PCCDUMMY82, - #[doc = "0x14c - PCC Reserved Register 83"] - pub pccdummy83: PCCDUMMY83, - #[doc = "0x150 - PCC Reserved Register 84"] - pub pccdummy84: PCCDUMMY84, - #[doc = "0x154 - PCC Reserved Register 85"] - pub pccdummy85: PCCDUMMY85, - #[doc = "0x158 - PCC Reserved Register 86"] - pub pccdummy86: PCCDUMMY86, - #[doc = "0x15c - PCC Reserved Register 87"] - pub pccdummy87: PCCDUMMY87, - #[doc = "0x160 - PCC Reserved Register 88"] - pub pccdummy88: PCCDUMMY88, - #[doc = "0x164 - PCC Reserved Register 89"] - pub pccdummy89: PCCDUMMY89, - #[doc = "0x168 - PCC FlexIO Register"] - pub pcc_flexio: PCC_FLEXIO, - #[doc = "0x16c - PCC Reserved Register 91"] - pub pccdummy91: PCCDUMMY91, - #[doc = "0x170 - PCC Reserved Register 92"] - pub pccdummy92: PCCDUMMY92, - #[doc = "0x174 - PCC Reserved Register 93"] - pub pccdummy93: PCCDUMMY93, - #[doc = "0x178 - PCC Reserved Register 94"] - pub pccdummy94: PCCDUMMY94, - #[doc = "0x17c - PCC Reserved Register 95"] - pub pccdummy95: PCCDUMMY95, - #[doc = "0x180 - PCC Reserved Register 96"] - pub pccdummy96: PCCDUMMY96, - #[doc = "0x184 - PCC EWM Register"] - pub pcc_ewm: PCC_EWM, - #[doc = "0x188 - PCC Reserved Register 98"] - pub pccdummy98: PCCDUMMY98, - #[doc = "0x18c - PCC Reserved Register 99"] - pub pccdummy99: PCCDUMMY99, - #[doc = "0x190 - PCC Reserved Register 100"] - pub pccdummy100: PCCDUMMY100, - #[doc = "0x194 - PCC Reserved Register 101"] - pub pccdummy101: PCCDUMMY101, - #[doc = "0x198 - PCC LPI2C0 Register"] - pub pcc_lpi2c0: PCC_LPI2C0, - #[doc = "0x19c - PCC Reserved Register 103"] - pub pccdummy103: PCCDUMMY103, - #[doc = "0x1a0 - PCC Reserved Register 104"] - pub pccdummy104: PCCDUMMY104, - #[doc = "0x1a4 - PCC Reserved Register 105"] - pub pccdummy105: PCCDUMMY105, - #[doc = "0x1a8 - PCC LPUART0 Register"] - pub pcc_lpuart0: PCC_LPUART0, - #[doc = "0x1ac - PCC LPUART1 Register"] - pub pcc_lpuart1: PCC_LPUART1, - #[doc = "0x1b0 - PCC LPUART2 Register"] - pub pcc_lpuart2: PCC_LPUART2, - #[doc = "0x1b4 - PCC Reserved Register 109"] - pub pccdummy109: PCCDUMMY109, - #[doc = "0x1b8 - PCC Reserved Register 110"] - pub pccdummy110: PCCDUMMY110, - #[doc = "0x1bc - PCC Reserved Register 111"] - pub pccdummy111: PCCDUMMY111, - #[doc = "0x1c0 - PCC Reserved Register 112"] - pub pccdummy112: PCCDUMMY112, - #[doc = "0x1c4 - PCC Reserved Register 113"] - pub pccdummy113: PCCDUMMY113, - #[doc = "0x1c8 - PCC Reserved Register 114"] - pub pccdummy114: PCCDUMMY114, - #[doc = "0x1cc - PCC CMP0 Register"] - pub pcc_cmp0: PCC_CMP0, + #[doc = "0x00 - PCC Reserved Register 0"] pub pccdummy0: PCCDUMMY0, + #[doc = "0x04 - PCC Reserved Register 1"] pub pccdummy1: PCCDUMMY1, + #[doc = "0x08 - PCC Reserved Register 2"] pub pccdummy2: PCCDUMMY2, + #[doc = "0x0c - PCC Reserved Register 3"] pub pccdummy3: PCCDUMMY3, + #[doc = "0x10 - PCC Reserved Register 4"] pub pccdummy4: PCCDUMMY4, + #[doc = "0x14 - PCC Reserved Register 5"] pub pccdummy5: PCCDUMMY5, + #[doc = "0x18 - PCC Reserved Register 6"] pub pccdummy6: PCCDUMMY6, + #[doc = "0x1c - PCC Reserved Register 7"] pub pccdummy7: PCCDUMMY7, + #[doc = "0x20 - PCC Reserved Register 8"] pub pccdummy8: PCCDUMMY8, + #[doc = "0x24 - PCC Reserved Register 9"] pub pccdummy9: PCCDUMMY9, + #[doc = "0x28 - PCC Reserved Register 10"] pub pccdummy10: PCCDUMMY10, + #[doc = "0x2c - PCC Reserved Register 11"] pub pccdummy11: PCCDUMMY11, + #[doc = "0x30 - PCC Reserved Register 12"] pub pccdummy12: PCCDUMMY12, + #[doc = "0x34 - PCC Reserved Register 13"] pub pccdummy13: PCCDUMMY13, + #[doc = "0x38 - PCC Reserved Register 14"] pub pccdummy14: PCCDUMMY14, + #[doc = "0x3c - PCC Reserved Register 15"] pub pccdummy15: PCCDUMMY15, + #[doc = "0x40 - PCC Reserved Register 16"] pub pccdummy16: PCCDUMMY16, + #[doc = "0x44 - PCC Reserved Register 17"] pub pccdummy17: PCCDUMMY17, + #[doc = "0x48 - PCC Reserved Register 18"] pub pccdummy18: PCCDUMMY18, + #[doc = "0x4c - PCC Reserved Register 19"] pub pccdummy19: PCCDUMMY19, + #[doc = "0x50 - PCC Reserved Register 20"] pub pccdummy20: PCCDUMMY20, + #[doc = "0x54 - PCC Reserved Register 21"] pub pccdummy21: PCCDUMMY21, + #[doc = "0x58 - PCC Reserved Register 22"] pub pccdummy22: PCCDUMMY22, + #[doc = "0x5c - PCC Reserved Register 23"] pub pccdummy23: PCCDUMMY23, + #[doc = "0x60 - PCC Reserved Register 24"] pub pccdummy24: PCCDUMMY24, + #[doc = "0x64 - PCC Reserved Register 25"] pub pccdummy25: PCCDUMMY25, + #[doc = "0x68 - PCC Reserved Register 26"] pub pccdummy26: PCCDUMMY26, + #[doc = "0x6c - PCC Reserved Register 27"] pub pccdummy27: PCCDUMMY27, + #[doc = "0x70 - PCC Reserved Register 28"] pub pccdummy28: PCCDUMMY28, + #[doc = "0x74 - PCC Reserved Register 29"] pub pccdummy29: PCCDUMMY29, + #[doc = "0x78 - PCC Reserved Register 30"] pub pccdummy30: PCCDUMMY30, + #[doc = "0x7c - PCC Reserved Register 31"] pub pccdummy31: PCCDUMMY31, + #[doc = "0x80 - PCC FTFC Register"] pub pcc_ftfc: PCC_FTFC, + #[doc = "0x84 - PCC DMAMUX Register"] pub pcc_dmamux: PCC_DMAMUX, + #[doc = "0x88 - PCC Reserved Register 34"] pub pccdummy34: PCCDUMMY34, + #[doc = "0x8c - PCC Reserved Register 35"] pub pccdummy35: PCCDUMMY35, + #[doc = "0x90 - PCC FlexCAN0 Register"] pub pcc_flex_can0: PCC_FLEXCAN0, + #[doc = "0x94 - PCC FlexCAN1 Register"] pub pcc_flex_can1: PCC_FLEXCAN1, + #[doc = "0x98 - PCC FTM3 Register"] pub pcc_ftm3: PCC_FTM3, + #[doc = "0x9c - PCC ADC1 Register"] pub pcc_adc1: PCC_ADC1, + #[doc = "0xa0 - PCC Reserved Register 40"] pub pccdummy40: PCCDUMMY40, + #[doc = "0xa4 - PCC Reserved Register 41"] pub pccdummy41: PCCDUMMY41, + #[doc = "0xa8 - PCC Reserved Register 42"] pub pccdummy42: PCCDUMMY42, + #[doc = "0xac - PCC FlexCAN2 Register"] pub pcc_flex_can2: PCC_FLEXCAN2, + #[doc = "0xb0 - PCC LPSPI0 Register"] pub pcc_lpspi0: PCC_LPSPI0, + #[doc = "0xb4 - PCC LPSPI1 Register"] pub pcc_lpspi1: PCC_LPSPI1, + #[doc = "0xb8 - PCC LPSPI2 Register"] pub pcc_lpspi2: PCC_LPSPI2, + #[doc = "0xbc - PCC Reserved Register 47"] pub pccdummy47: PCCDUMMY47, + #[doc = "0xc0 - PCC Reserved Register 48"] pub pccdummy48: PCCDUMMY48, + #[doc = "0xc4 - PCC PDB1 Register"] pub pcc_pdb1: PCC_PDB1, + #[doc = "0xc8 - PCC CRC Register"] pub pcc_crc: PCC_CRC, + #[doc = "0xcc - PCC Reserved Register 51"] pub pccdummy51: PCCDUMMY51, + #[doc = "0xd0 - PCC Reserved Register 52"] pub pccdummy52: PCCDUMMY52, + #[doc = "0xd4 - PCC Reserved Register 53"] pub pccdummy53: PCCDUMMY53, + #[doc = "0xd8 - PCC PDB0 Register"] pub pcc_pdb0: PCC_PDB0, + #[doc = "0xdc - PCC LPIT Register"] pub pcc_lpit: PCC_LPIT, + #[doc = "0xe0 - PCC FTM0 Register"] pub pcc_ftm0: PCC_FTM0, + #[doc = "0xe4 - PCC FTM1 Register"] pub pcc_ftm1: PCC_FTM1, + #[doc = "0xe8 - PCC FTM2 Register"] pub pcc_ftm2: PCC_FTM2, + #[doc = "0xec - PCC ADC0 Register"] pub pcc_adc0: PCC_ADC0, + #[doc = "0xf0 - PCC Reserved Register 60"] pub pccdummy60: PCCDUMMY60, + #[doc = "0xf4 - PCC RTC Register"] pub pcc_rtc: PCC_RTC, + #[doc = "0xf8 - PCC Reserved Register 62"] pub pccdummy62: PCCDUMMY62, + #[doc = "0xfc - PCC Reserved Register 63"] pub pccdummy63: PCCDUMMY63, + #[doc = "0x100 - PCC LPTMR0 Register"] pub pcc_lptmr0: PCC_LPTMR0, + #[doc = "0x104 - PCC Reserved Register 65"] pub pccdummy65: PCCDUMMY65, + #[doc = "0x108 - PCC Reserved Register 66"] pub pccdummy66: PCCDUMMY66, + #[doc = "0x10c - PCC Reserved Register 67"] pub pccdummy67: PCCDUMMY67, + #[doc = "0x110 - PCC Reserved Register 68"] pub pccdummy68: PCCDUMMY68, + #[doc = "0x114 - PCC Reserved Register 69"] pub pccdummy69: PCCDUMMY69, + #[doc = "0x118 - PCC Reserved Register 70"] pub pccdummy70: PCCDUMMY70, + #[doc = "0x11c - PCC Reserved Register 71"] pub pccdummy71: PCCDUMMY71, + #[doc = "0x120 - PCC Reserved Register 72"] pub pccdummy72: PCCDUMMY72, + #[doc = "0x124 - PCC PORTA Register"] pub pcc_porta: PCC_PORTA, + #[doc = "0x128 - PCC PORTB Register"] pub pcc_portb: PCC_PORTB, + #[doc = "0x12c - PCC PORTC Register"] pub pcc_portc: PCC_PORTC, + #[doc = "0x130 - PCC PORTD Register"] pub pcc_portd: PCC_PORTD, + #[doc = "0x134 - PCC PORTE Register"] pub pcc_porte: PCC_PORTE, + #[doc = "0x138 - PCC Reserved Register 78"] pub pccdummy78: PCCDUMMY78, + #[doc = "0x13c - PCC Reserved Register 79"] pub pccdummy79: PCCDUMMY79, + #[doc = "0x140 - PCC Reserved Register 80"] pub pccdummy80: PCCDUMMY80, + #[doc = "0x144 - PCC Reserved Register 81"] pub pccdummy81: PCCDUMMY81, + #[doc = "0x148 - PCC Reserved Register 82"] pub pccdummy82: PCCDUMMY82, + #[doc = "0x14c - PCC Reserved Register 83"] pub pccdummy83: PCCDUMMY83, + #[doc = "0x150 - PCC Reserved Register 84"] pub pccdummy84: PCCDUMMY84, + #[doc = "0x154 - PCC Reserved Register 85"] pub pccdummy85: PCCDUMMY85, + #[doc = "0x158 - PCC Reserved Register 86"] pub pccdummy86: PCCDUMMY86, + #[doc = "0x15c - PCC Reserved Register 87"] pub pccdummy87: PCCDUMMY87, + #[doc = "0x160 - PCC Reserved Register 88"] pub pccdummy88: PCCDUMMY88, + #[doc = "0x164 - PCC Reserved Register 89"] pub pccdummy89: PCCDUMMY89, + #[doc = "0x168 - PCC FlexIO Register"] pub pcc_flexio: PCC_FLEXIO, + #[doc = "0x16c - PCC Reserved Register 91"] pub pccdummy91: PCCDUMMY91, + #[doc = "0x170 - PCC Reserved Register 92"] pub pccdummy92: PCCDUMMY92, + #[doc = "0x174 - PCC Reserved Register 93"] pub pccdummy93: PCCDUMMY93, + #[doc = "0x178 - PCC Reserved Register 94"] pub pccdummy94: PCCDUMMY94, + #[doc = "0x17c - PCC Reserved Register 95"] pub pccdummy95: PCCDUMMY95, + #[doc = "0x180 - PCC Reserved Register 96"] pub pccdummy96: PCCDUMMY96, + #[doc = "0x184 - PCC EWM Register"] pub pcc_ewm: PCC_EWM, + #[doc = "0x188 - PCC Reserved Register 98"] pub pccdummy98: PCCDUMMY98, + #[doc = "0x18c - PCC Reserved Register 99"] pub pccdummy99: PCCDUMMY99, + #[doc = "0x190 - PCC Reserved Register 100"] pub pccdummy100: PCCDUMMY100, + #[doc = "0x194 - PCC Reserved Register 101"] pub pccdummy101: PCCDUMMY101, + #[doc = "0x198 - PCC LPI2C0 Register"] pub pcc_lpi2c0: PCC_LPI2C0, + #[doc = "0x19c - PCC Reserved Register 103"] pub pccdummy103: PCCDUMMY103, + #[doc = "0x1a0 - PCC Reserved Register 104"] pub pccdummy104: PCCDUMMY104, + #[doc = "0x1a4 - PCC Reserved Register 105"] pub pccdummy105: PCCDUMMY105, + #[doc = "0x1a8 - PCC LPUART0 Register"] pub pcc_lpuart0: PCC_LPUART0, + #[doc = "0x1ac - PCC LPUART1 Register"] pub pcc_lpuart1: PCC_LPUART1, + #[doc = "0x1b0 - PCC LPUART2 Register"] pub pcc_lpuart2: PCC_LPUART2, + #[doc = "0x1b4 - PCC Reserved Register 109"] pub pccdummy109: PCCDUMMY109, + #[doc = "0x1b8 - PCC Reserved Register 110"] pub pccdummy110: PCCDUMMY110, + #[doc = "0x1bc - PCC Reserved Register 111"] pub pccdummy111: PCCDUMMY111, + #[doc = "0x1c0 - PCC Reserved Register 112"] pub pccdummy112: PCCDUMMY112, + #[doc = "0x1c4 - PCC Reserved Register 113"] pub pccdummy113: PCCDUMMY113, + #[doc = "0x1c8 - PCC Reserved Register 114"] pub pccdummy114: PCCDUMMY114, + #[doc = "0x1cc - PCC CMP0 Register"] pub pcc_cmp0: PCC_CMP0, } #[doc = "PCC Reserved Register 0"] pub struct PCCDUMMY0 { diff --git a/src/pcc/pcc_adc0/mod.rs b/src/pcc/pcc_adc0/mod.rs index 88444d8..c99cf33 100644 --- a/src/pcc/pcc_adc0/mod.rs +++ b/src/pcc/pcc_adc0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_ADC0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_ADC0 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_adc1/mod.rs b/src/pcc/pcc_adc1/mod.rs index 8cb081e..a348625 100644 --- a/src/pcc/pcc_adc1/mod.rs +++ b/src/pcc/pcc_adc1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_ADC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_ADC1 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_cmp0/mod.rs b/src/pcc/pcc_cmp0/mod.rs index 0c3508e..8c06d17 100644 --- a/src/pcc/pcc_cmp0/mod.rs +++ b/src/pcc/pcc_cmp0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_CMP0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_CMP0 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_crc/mod.rs b/src/pcc/pcc_crc/mod.rs index e5f251e..9d735ad 100644 --- a/src/pcc/pcc_crc/mod.rs +++ b/src/pcc/pcc_crc/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_CRC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_CRC { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_dmamux/mod.rs b/src/pcc/pcc_dmamux/mod.rs index a7f7f29..8018455 100644 --- a/src/pcc/pcc_dmamux/mod.rs +++ b/src/pcc/pcc_dmamux/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_DMAMUX { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_DMAMUX { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ewm/mod.rs b/src/pcc/pcc_ewm/mod.rs index 97556b0..effc35b 100644 --- a/src/pcc/pcc_ewm/mod.rs +++ b/src/pcc/pcc_ewm/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_EWM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_EWM { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_flex_can0/mod.rs b/src/pcc/pcc_flex_can0/mod.rs index b083ba0..4114222 100644 --- a/src/pcc/pcc_flex_can0/mod.rs +++ b/src/pcc/pcc_flex_can0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN0 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_flex_can1/mod.rs b/src/pcc/pcc_flex_can1/mod.rs index 6f60753..5c5a84e 100644 --- a/src/pcc/pcc_flex_can1/mod.rs +++ b/src/pcc/pcc_flex_can1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN1 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_flex_can2/mod.rs b/src/pcc/pcc_flex_can2/mod.rs index af5834f..e21e3bf 100644 --- a/src/pcc/pcc_flex_can2/mod.rs +++ b/src/pcc/pcc_flex_can2/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN2 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_flexio/mod.rs b/src/pcc/pcc_flexio/mod.rs index 1047226..96cda78 100644 --- a/src/pcc/pcc_flexio/mod.rs +++ b/src/pcc/pcc_flexio/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FLEXIO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_FLEXIO { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ftfc/mod.rs b/src/pcc/pcc_ftfc/mod.rs index fd5b6a6..20a88f3 100644 --- a/src/pcc/pcc_ftfc/mod.rs +++ b/src/pcc/pcc_ftfc/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FTFC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_FTFC { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ftm0/mod.rs b/src/pcc/pcc_ftm0/mod.rs index b5912f1..518fd15 100644 --- a/src/pcc/pcc_ftm0/mod.rs +++ b/src/pcc/pcc_ftm0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FTM0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_FTM0 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ftm1/mod.rs b/src/pcc/pcc_ftm1/mod.rs index c413c96..029df73 100644 --- a/src/pcc/pcc_ftm1/mod.rs +++ b/src/pcc/pcc_ftm1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FTM1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_FTM1 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ftm2/mod.rs b/src/pcc/pcc_ftm2/mod.rs index 49d4c19..bfe71e6 100644 --- a/src/pcc/pcc_ftm2/mod.rs +++ b/src/pcc/pcc_ftm2/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FTM2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_FTM2 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_ftm3/mod.rs b/src/pcc/pcc_ftm3/mod.rs index 74cc666..7981604 100644 --- a/src/pcc/pcc_ftm3/mod.rs +++ b/src/pcc/pcc_ftm3/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_FTM3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_FTM3 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off. An external clock can be enabled for this peripheral."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpi2c0/mod.rs b/src/pcc/pcc_lpi2c0/mod.rs index 324fcf1..d39e1ae 100644 --- a/src/pcc/pcc_lpi2c0/mod.rs +++ b/src/pcc/pcc_lpi2c0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPI2C0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPI2C0 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpit/mod.rs b/src/pcc/pcc_lpit/mod.rs index f77ee89..f560be9 100644 --- a/src/pcc/pcc_lpit/mod.rs +++ b/src/pcc/pcc_lpit/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPIT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPIT { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpspi0/mod.rs b/src/pcc/pcc_lpspi0/mod.rs index 7786cca..5de4050 100644 --- a/src/pcc/pcc_lpspi0/mod.rs +++ b/src/pcc/pcc_lpspi0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPSPI0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPSPI0 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpspi1/mod.rs b/src/pcc/pcc_lpspi1/mod.rs index 70114cc..084997c 100644 --- a/src/pcc/pcc_lpspi1/mod.rs +++ b/src/pcc/pcc_lpspi1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPSPI1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPSPI1 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpspi2/mod.rs b/src/pcc/pcc_lpspi2/mod.rs index 2affbd4..ba1a126 100644 --- a/src/pcc/pcc_lpspi2/mod.rs +++ b/src/pcc/pcc_lpspi2/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPSPI2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPSPI2 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lptmr0/mod.rs b/src/pcc/pcc_lptmr0/mod.rs index cfbc3a2..a14f93b 100644 --- a/src/pcc/pcc_lptmr0/mod.rs +++ b/src/pcc/pcc_lptmr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPTMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPTMR0 { #[doc = "Possible values of the field `PCD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCDR { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 3."] - _010, - #[doc = "Divide by 4."] - _011, - #[doc = "Divide by 5."] - _100, - #[doc = "Divide by 6."] - _101, - #[doc = "Divide by 7."] - _110, - #[doc = "Divide by 8."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 3."] _010, + #[doc = "Divide by 4."] _011, + #[doc = "Divide by 5."] _100, + #[doc = "Divide by 6."] _101, + #[doc = "Divide by 7."] _110, + #[doc = "Divide by 8."] _111, } impl PCDR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCDR { #[doc = "Possible values of the field `FRAC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FRACR { - #[doc = "Fractional value is 0."] - _0, - #[doc = "Fractional value is 1."] - _1, + #[doc = "Fractional value is 0."] _0, + #[doc = "Fractional value is 1."] _1, } impl FRACR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,22 +174,14 @@ impl FRACR { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -274,10 +258,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -321,10 +303,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -367,22 +347,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCD`"] pub enum PCDW { - #[doc = "Divide by 1."] - _000, - #[doc = "Divide by 2."] - _001, - #[doc = "Divide by 3."] - _010, - #[doc = "Divide by 4."] - _011, - #[doc = "Divide by 5."] - _100, - #[doc = "Divide by 6."] - _101, - #[doc = "Divide by 7."] - _110, - #[doc = "Divide by 8."] - _111, + #[doc = "Divide by 1."] _000, + #[doc = "Divide by 2."] _001, + #[doc = "Divide by 3."] _010, + #[doc = "Divide by 4."] _011, + #[doc = "Divide by 5."] _100, + #[doc = "Divide by 6."] _101, + #[doc = "Divide by 7."] _110, + #[doc = "Divide by 8."] _111, } impl PCDW { #[allow(missing_docs)] @@ -465,10 +437,8 @@ impl<'a> _PCDW<'a> { } #[doc = "Values that can be written to the field `FRAC`"] pub enum FRACW { - #[doc = "Fractional value is 0."] - _0, - #[doc = "Fractional value is 1."] - _1, + #[doc = "Fractional value is 0."] _0, + #[doc = "Fractional value is 1."] _1, } impl FRACW { #[allow(missing_docs)] @@ -523,22 +493,14 @@ impl<'a> _FRACW<'a> { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -621,10 +583,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpuart0/mod.rs b/src/pcc/pcc_lpuart0/mod.rs index 71025d1..1afb911 100644 --- a/src/pcc/pcc_lpuart0/mod.rs +++ b/src/pcc/pcc_lpuart0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPUART0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPUART0 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpuart1/mod.rs b/src/pcc/pcc_lpuart1/mod.rs index e60974e..95a120f 100644 --- a/src/pcc/pcc_lpuart1/mod.rs +++ b/src/pcc/pcc_lpuart1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPUART1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPUART1 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_lpuart2/mod.rs b/src/pcc/pcc_lpuart2/mod.rs index 94b8686..5011f1f 100644 --- a/src/pcc/pcc_lpuart2/mod.rs +++ b/src/pcc/pcc_lpuart2/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_LPUART2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::PCC_LPUART2 { #[doc = "Possible values of the field `PCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PCSR { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSR { #[doc = r" Value of the field as raw bits"] @@ -135,10 +129,8 @@ impl PCSR { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -182,10 +174,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -228,22 +218,14 @@ impl PRR { } #[doc = "Values that can be written to the field `PCS`"] pub enum PCSW { - #[doc = "Clock is off."] - _000, - #[doc = "Clock option 1"] - _001, - #[doc = "Clock option 2"] - _010, - #[doc = "Clock option 3"] - _011, - #[doc = "Clock option 4"] - _100, - #[doc = "Clock option 5"] - _101, - #[doc = "Clock option 6"] - _110, - #[doc = "Clock option 7"] - _111, + #[doc = "Clock is off."] _000, + #[doc = "Clock option 1"] _001, + #[doc = "Clock option 2"] _010, + #[doc = "Clock option 3"] _011, + #[doc = "Clock option 4"] _100, + #[doc = "Clock option 5"] _101, + #[doc = "Clock option 6"] _110, + #[doc = "Clock option 7"] _111, } impl PCSW { #[allow(missing_docs)] @@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_pdb0/mod.rs b/src/pcc/pcc_pdb0/mod.rs index c8af01b..b811d6f 100644 --- a/src/pcc/pcc_pdb0/mod.rs +++ b/src/pcc/pcc_pdb0/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PDB0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PDB0 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_pdb1/mod.rs b/src/pcc/pcc_pdb1/mod.rs index ca82f25..eafd2f2 100644 --- a/src/pcc/pcc_pdb1/mod.rs +++ b/src/pcc/pcc_pdb1/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PDB1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PDB1 { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_porta/mod.rs b/src/pcc/pcc_porta/mod.rs index d468c45..6f66e6c 100644 --- a/src/pcc/pcc_porta/mod.rs +++ b/src/pcc/pcc_porta/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PORTA { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PORTA { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_portb/mod.rs b/src/pcc/pcc_portb/mod.rs index 56a4801..7f6361d 100644 --- a/src/pcc/pcc_portb/mod.rs +++ b/src/pcc/pcc_portb/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PORTB { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PORTB { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_portc/mod.rs b/src/pcc/pcc_portc/mod.rs index dd9c967..658b768 100644 --- a/src/pcc/pcc_portc/mod.rs +++ b/src/pcc/pcc_portc/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PORTC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PORTC { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_portd/mod.rs b/src/pcc/pcc_portd/mod.rs index 0ef57ca..b434f18 100644 --- a/src/pcc/pcc_portd/mod.rs +++ b/src/pcc/pcc_portd/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PORTD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PORTD { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_porte/mod.rs b/src/pcc/pcc_porte/mod.rs index ba82318..d802630 100644 --- a/src/pcc/pcc_porte/mod.rs +++ b/src/pcc/pcc_porte/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_PORTE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_PORTE { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pcc_rtc/mod.rs b/src/pcc/pcc_rtc/mod.rs index ade51ed..fc1dafc 100644 --- a/src/pcc/pcc_rtc/mod.rs +++ b/src/pcc/pcc_rtc/mod.rs @@ -22,7 +22,9 @@ impl super::PCC_RTC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PCC_RTC { #[doc = "Possible values of the field `CGC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCR { #[doc = "Possible values of the field `PR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRR { - #[doc = "Peripheral is not present."] - _0, - #[doc = "Peripheral is present."] - _1, + #[doc = "Peripheral is not present."] _0, + #[doc = "Peripheral is present."] _1, } impl PRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl PRR { } #[doc = "Values that can be written to the field `CGC`"] pub enum CGCW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled. The current clock selection and divider options are locked."] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled. The current clock selection and divider options are locked."] _1, } impl CGCW { #[allow(missing_docs)] diff --git a/src/pcc/pccdummy0/mod.rs b/src/pcc/pccdummy0/mod.rs index 3c83c64..e9dc16b 100644 --- a/src/pcc/pccdummy0/mod.rs +++ b/src/pcc/pccdummy0/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy1/mod.rs b/src/pcc/pccdummy1/mod.rs index 3533266..4eb8cec 100644 --- a/src/pcc/pccdummy1/mod.rs +++ b/src/pcc/pccdummy1/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy10/mod.rs b/src/pcc/pccdummy10/mod.rs index 96fd93f..234826a 100644 --- a/src/pcc/pccdummy10/mod.rs +++ b/src/pcc/pccdummy10/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy100/mod.rs b/src/pcc/pccdummy100/mod.rs index d2f1931..bc3fd8e 100644 --- a/src/pcc/pccdummy100/mod.rs +++ b/src/pcc/pccdummy100/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY100 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy101/mod.rs b/src/pcc/pccdummy101/mod.rs index 0309e8d..7ac6ecc 100644 --- a/src/pcc/pccdummy101/mod.rs +++ b/src/pcc/pccdummy101/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY101 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy103/mod.rs b/src/pcc/pccdummy103/mod.rs index fa5bd15..222a1b9 100644 --- a/src/pcc/pccdummy103/mod.rs +++ b/src/pcc/pccdummy103/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY103 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy104/mod.rs b/src/pcc/pccdummy104/mod.rs index d58b492..e6a18dc 100644 --- a/src/pcc/pccdummy104/mod.rs +++ b/src/pcc/pccdummy104/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY104 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy105/mod.rs b/src/pcc/pccdummy105/mod.rs index 0890270..e1b601e 100644 --- a/src/pcc/pccdummy105/mod.rs +++ b/src/pcc/pccdummy105/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY105 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy109/mod.rs b/src/pcc/pccdummy109/mod.rs index 9701f30..e6e9779 100644 --- a/src/pcc/pccdummy109/mod.rs +++ b/src/pcc/pccdummy109/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY109 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy11/mod.rs b/src/pcc/pccdummy11/mod.rs index ff2befb..557f82f 100644 --- a/src/pcc/pccdummy11/mod.rs +++ b/src/pcc/pccdummy11/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy110/mod.rs b/src/pcc/pccdummy110/mod.rs index df31512..1ed49b5 100644 --- a/src/pcc/pccdummy110/mod.rs +++ b/src/pcc/pccdummy110/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY110 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy111/mod.rs b/src/pcc/pccdummy111/mod.rs index 25c7c53..e4f6311 100644 --- a/src/pcc/pccdummy111/mod.rs +++ b/src/pcc/pccdummy111/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY111 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy112/mod.rs b/src/pcc/pccdummy112/mod.rs index bee8da4..7ed1a73 100644 --- a/src/pcc/pccdummy112/mod.rs +++ b/src/pcc/pccdummy112/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY112 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy113/mod.rs b/src/pcc/pccdummy113/mod.rs index 245e920..c492c16 100644 --- a/src/pcc/pccdummy113/mod.rs +++ b/src/pcc/pccdummy113/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY113 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy114/mod.rs b/src/pcc/pccdummy114/mod.rs index c4f243e..d5aeaca 100644 --- a/src/pcc/pccdummy114/mod.rs +++ b/src/pcc/pccdummy114/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY114 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy12/mod.rs b/src/pcc/pccdummy12/mod.rs index ab6bc6c..f4084e7 100644 --- a/src/pcc/pccdummy12/mod.rs +++ b/src/pcc/pccdummy12/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy13/mod.rs b/src/pcc/pccdummy13/mod.rs index d8ee838..00555db 100644 --- a/src/pcc/pccdummy13/mod.rs +++ b/src/pcc/pccdummy13/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy14/mod.rs b/src/pcc/pccdummy14/mod.rs index 5750153..9c344b4 100644 --- a/src/pcc/pccdummy14/mod.rs +++ b/src/pcc/pccdummy14/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy15/mod.rs b/src/pcc/pccdummy15/mod.rs index 8f5b6be..3f93733 100644 --- a/src/pcc/pccdummy15/mod.rs +++ b/src/pcc/pccdummy15/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy16/mod.rs b/src/pcc/pccdummy16/mod.rs index 1b2ae80..5d734ac 100644 --- a/src/pcc/pccdummy16/mod.rs +++ b/src/pcc/pccdummy16/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy17/mod.rs b/src/pcc/pccdummy17/mod.rs index 4eac626..f88b42e 100644 --- a/src/pcc/pccdummy17/mod.rs +++ b/src/pcc/pccdummy17/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy18/mod.rs b/src/pcc/pccdummy18/mod.rs index 4cc5f75..0477ba6 100644 --- a/src/pcc/pccdummy18/mod.rs +++ b/src/pcc/pccdummy18/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy19/mod.rs b/src/pcc/pccdummy19/mod.rs index 6fd8c8f..c745f32 100644 --- a/src/pcc/pccdummy19/mod.rs +++ b/src/pcc/pccdummy19/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy2/mod.rs b/src/pcc/pccdummy2/mod.rs index a5e4daa..3c4c555 100644 --- a/src/pcc/pccdummy2/mod.rs +++ b/src/pcc/pccdummy2/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy20/mod.rs b/src/pcc/pccdummy20/mod.rs index ca63749..73d2193 100644 --- a/src/pcc/pccdummy20/mod.rs +++ b/src/pcc/pccdummy20/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy21/mod.rs b/src/pcc/pccdummy21/mod.rs index 98ed05a..5937254 100644 --- a/src/pcc/pccdummy21/mod.rs +++ b/src/pcc/pccdummy21/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy22/mod.rs b/src/pcc/pccdummy22/mod.rs index 1e6aeb0..66326db 100644 --- a/src/pcc/pccdummy22/mod.rs +++ b/src/pcc/pccdummy22/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy23/mod.rs b/src/pcc/pccdummy23/mod.rs index 9b5ba8d..f5649bb 100644 --- a/src/pcc/pccdummy23/mod.rs +++ b/src/pcc/pccdummy23/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy24/mod.rs b/src/pcc/pccdummy24/mod.rs index 7e32874..32be090 100644 --- a/src/pcc/pccdummy24/mod.rs +++ b/src/pcc/pccdummy24/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy25/mod.rs b/src/pcc/pccdummy25/mod.rs index bce7704..bf65484 100644 --- a/src/pcc/pccdummy25/mod.rs +++ b/src/pcc/pccdummy25/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy26/mod.rs b/src/pcc/pccdummy26/mod.rs index 5750b3f..f3e1d3c 100644 --- a/src/pcc/pccdummy26/mod.rs +++ b/src/pcc/pccdummy26/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy27/mod.rs b/src/pcc/pccdummy27/mod.rs index 5a63a40..4e78842 100644 --- a/src/pcc/pccdummy27/mod.rs +++ b/src/pcc/pccdummy27/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy28/mod.rs b/src/pcc/pccdummy28/mod.rs index 7a9931c..4e7e52d 100644 --- a/src/pcc/pccdummy28/mod.rs +++ b/src/pcc/pccdummy28/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy29/mod.rs b/src/pcc/pccdummy29/mod.rs index 7a224e2..5720ad8 100644 --- a/src/pcc/pccdummy29/mod.rs +++ b/src/pcc/pccdummy29/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy3/mod.rs b/src/pcc/pccdummy3/mod.rs index 478f09b..3a71758 100644 --- a/src/pcc/pccdummy3/mod.rs +++ b/src/pcc/pccdummy3/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy30/mod.rs b/src/pcc/pccdummy30/mod.rs index 10ede8e..fcce31c 100644 --- a/src/pcc/pccdummy30/mod.rs +++ b/src/pcc/pccdummy30/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy31/mod.rs b/src/pcc/pccdummy31/mod.rs index 552ceb0..0a14c43 100644 --- a/src/pcc/pccdummy31/mod.rs +++ b/src/pcc/pccdummy31/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy34/mod.rs b/src/pcc/pccdummy34/mod.rs index c365f9e..8160289 100644 --- a/src/pcc/pccdummy34/mod.rs +++ b/src/pcc/pccdummy34/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY34 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy35/mod.rs b/src/pcc/pccdummy35/mod.rs index fc3df08..6ac5b9d 100644 --- a/src/pcc/pccdummy35/mod.rs +++ b/src/pcc/pccdummy35/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY35 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy4/mod.rs b/src/pcc/pccdummy4/mod.rs index 89ce362..e4c0061 100644 --- a/src/pcc/pccdummy4/mod.rs +++ b/src/pcc/pccdummy4/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy40/mod.rs b/src/pcc/pccdummy40/mod.rs index 870814d..6d57fba 100644 --- a/src/pcc/pccdummy40/mod.rs +++ b/src/pcc/pccdummy40/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY40 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy41/mod.rs b/src/pcc/pccdummy41/mod.rs index e720dbc..9a360c2 100644 --- a/src/pcc/pccdummy41/mod.rs +++ b/src/pcc/pccdummy41/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY41 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy42/mod.rs b/src/pcc/pccdummy42/mod.rs index ea43b06..44cd78d 100644 --- a/src/pcc/pccdummy42/mod.rs +++ b/src/pcc/pccdummy42/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY42 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy47/mod.rs b/src/pcc/pccdummy47/mod.rs index 4481abe..12513cd 100644 --- a/src/pcc/pccdummy47/mod.rs +++ b/src/pcc/pccdummy47/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY47 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy48/mod.rs b/src/pcc/pccdummy48/mod.rs index 1c83b00..b7302c8 100644 --- a/src/pcc/pccdummy48/mod.rs +++ b/src/pcc/pccdummy48/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY48 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy5/mod.rs b/src/pcc/pccdummy5/mod.rs index e2d6714..730e4f2 100644 --- a/src/pcc/pccdummy5/mod.rs +++ b/src/pcc/pccdummy5/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy51/mod.rs b/src/pcc/pccdummy51/mod.rs index 6b99388..e35fd67 100644 --- a/src/pcc/pccdummy51/mod.rs +++ b/src/pcc/pccdummy51/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY51 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy52/mod.rs b/src/pcc/pccdummy52/mod.rs index 29ed6c8..b9fdb75 100644 --- a/src/pcc/pccdummy52/mod.rs +++ b/src/pcc/pccdummy52/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY52 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy53/mod.rs b/src/pcc/pccdummy53/mod.rs index 8c50f1d..345ab31 100644 --- a/src/pcc/pccdummy53/mod.rs +++ b/src/pcc/pccdummy53/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY53 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy6/mod.rs b/src/pcc/pccdummy6/mod.rs index 3d83ff5..6a06f2b 100644 --- a/src/pcc/pccdummy6/mod.rs +++ b/src/pcc/pccdummy6/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy60/mod.rs b/src/pcc/pccdummy60/mod.rs index cdb035f..b7eb9d5 100644 --- a/src/pcc/pccdummy60/mod.rs +++ b/src/pcc/pccdummy60/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY60 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy62/mod.rs b/src/pcc/pccdummy62/mod.rs index 8eb49aa..0e76d87 100644 --- a/src/pcc/pccdummy62/mod.rs +++ b/src/pcc/pccdummy62/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY62 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy63/mod.rs b/src/pcc/pccdummy63/mod.rs index d6c36b3..f6bd38e 100644 --- a/src/pcc/pccdummy63/mod.rs +++ b/src/pcc/pccdummy63/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY63 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy65/mod.rs b/src/pcc/pccdummy65/mod.rs index 4fef671..68cc5bc 100644 --- a/src/pcc/pccdummy65/mod.rs +++ b/src/pcc/pccdummy65/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY65 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy66/mod.rs b/src/pcc/pccdummy66/mod.rs index 944727a..190bc4e 100644 --- a/src/pcc/pccdummy66/mod.rs +++ b/src/pcc/pccdummy66/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY66 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy67/mod.rs b/src/pcc/pccdummy67/mod.rs index 36fa626..3201c99 100644 --- a/src/pcc/pccdummy67/mod.rs +++ b/src/pcc/pccdummy67/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY67 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy68/mod.rs b/src/pcc/pccdummy68/mod.rs index 63b05a5..8b47de3 100644 --- a/src/pcc/pccdummy68/mod.rs +++ b/src/pcc/pccdummy68/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY68 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy69/mod.rs b/src/pcc/pccdummy69/mod.rs index 69522dc..c7efd68 100644 --- a/src/pcc/pccdummy69/mod.rs +++ b/src/pcc/pccdummy69/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY69 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy7/mod.rs b/src/pcc/pccdummy7/mod.rs index d643910..94f25cc 100644 --- a/src/pcc/pccdummy7/mod.rs +++ b/src/pcc/pccdummy7/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy70/mod.rs b/src/pcc/pccdummy70/mod.rs index b5cb2f1..90cc3c7 100644 --- a/src/pcc/pccdummy70/mod.rs +++ b/src/pcc/pccdummy70/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY70 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy71/mod.rs b/src/pcc/pccdummy71/mod.rs index af6319c..4815650 100644 --- a/src/pcc/pccdummy71/mod.rs +++ b/src/pcc/pccdummy71/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY71 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy72/mod.rs b/src/pcc/pccdummy72/mod.rs index a179ce0..a1151d8 100644 --- a/src/pcc/pccdummy72/mod.rs +++ b/src/pcc/pccdummy72/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY72 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy78/mod.rs b/src/pcc/pccdummy78/mod.rs index 68f6d14..8bd4e61 100644 --- a/src/pcc/pccdummy78/mod.rs +++ b/src/pcc/pccdummy78/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY78 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy79/mod.rs b/src/pcc/pccdummy79/mod.rs index e50e9d4..fb021ba 100644 --- a/src/pcc/pccdummy79/mod.rs +++ b/src/pcc/pccdummy79/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY79 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy8/mod.rs b/src/pcc/pccdummy8/mod.rs index 7db9589..9c91884 100644 --- a/src/pcc/pccdummy8/mod.rs +++ b/src/pcc/pccdummy8/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy80/mod.rs b/src/pcc/pccdummy80/mod.rs index babb7e7..2175490 100644 --- a/src/pcc/pccdummy80/mod.rs +++ b/src/pcc/pccdummy80/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY80 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy81/mod.rs b/src/pcc/pccdummy81/mod.rs index 64ee97f..7eaca81 100644 --- a/src/pcc/pccdummy81/mod.rs +++ b/src/pcc/pccdummy81/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY81 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy82/mod.rs b/src/pcc/pccdummy82/mod.rs index a661ea5..266c725 100644 --- a/src/pcc/pccdummy82/mod.rs +++ b/src/pcc/pccdummy82/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY82 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy83/mod.rs b/src/pcc/pccdummy83/mod.rs index 4c03849..dc62fd7 100644 --- a/src/pcc/pccdummy83/mod.rs +++ b/src/pcc/pccdummy83/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY83 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy84/mod.rs b/src/pcc/pccdummy84/mod.rs index e626e92..c7f691e 100644 --- a/src/pcc/pccdummy84/mod.rs +++ b/src/pcc/pccdummy84/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY84 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy85/mod.rs b/src/pcc/pccdummy85/mod.rs index c7e84cc..2dad194 100644 --- a/src/pcc/pccdummy85/mod.rs +++ b/src/pcc/pccdummy85/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY85 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy86/mod.rs b/src/pcc/pccdummy86/mod.rs index 83fbc24..a07bc89 100644 --- a/src/pcc/pccdummy86/mod.rs +++ b/src/pcc/pccdummy86/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY86 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy87/mod.rs b/src/pcc/pccdummy87/mod.rs index af9518d..2b2e3fb 100644 --- a/src/pcc/pccdummy87/mod.rs +++ b/src/pcc/pccdummy87/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY87 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy88/mod.rs b/src/pcc/pccdummy88/mod.rs index 72d95cf..68843a8 100644 --- a/src/pcc/pccdummy88/mod.rs +++ b/src/pcc/pccdummy88/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY88 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy89/mod.rs b/src/pcc/pccdummy89/mod.rs index a2ca022..1523276 100644 --- a/src/pcc/pccdummy89/mod.rs +++ b/src/pcc/pccdummy89/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY89 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy9/mod.rs b/src/pcc/pccdummy9/mod.rs index 4b7c337..80172e5 100644 --- a/src/pcc/pccdummy9/mod.rs +++ b/src/pcc/pccdummy9/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy91/mod.rs b/src/pcc/pccdummy91/mod.rs index 88d798d..a8bd6bb 100644 --- a/src/pcc/pccdummy91/mod.rs +++ b/src/pcc/pccdummy91/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY91 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy92/mod.rs b/src/pcc/pccdummy92/mod.rs index 30ae348..8d6b3a8 100644 --- a/src/pcc/pccdummy92/mod.rs +++ b/src/pcc/pccdummy92/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY92 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy93/mod.rs b/src/pcc/pccdummy93/mod.rs index 6f9d995..c559e1a 100644 --- a/src/pcc/pccdummy93/mod.rs +++ b/src/pcc/pccdummy93/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY93 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy94/mod.rs b/src/pcc/pccdummy94/mod.rs index 8ceff76..f2d564f 100644 --- a/src/pcc/pccdummy94/mod.rs +++ b/src/pcc/pccdummy94/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY94 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy95/mod.rs b/src/pcc/pccdummy95/mod.rs index 2070980..8436ffc 100644 --- a/src/pcc/pccdummy95/mod.rs +++ b/src/pcc/pccdummy95/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY95 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy96/mod.rs b/src/pcc/pccdummy96/mod.rs index 33d6700..81f0d9c 100644 --- a/src/pcc/pccdummy96/mod.rs +++ b/src/pcc/pccdummy96/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY96 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy98/mod.rs b/src/pcc/pccdummy98/mod.rs index 92a00da..3341b48 100644 --- a/src/pcc/pccdummy98/mod.rs +++ b/src/pcc/pccdummy98/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY98 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pcc/pccdummy99/mod.rs b/src/pcc/pccdummy99/mod.rs index 92d58af..e76f0f3 100644 --- a/src/pcc/pccdummy99/mod.rs +++ b/src/pcc/pccdummy99/mod.rs @@ -22,7 +22,9 @@ impl super::PCCDUMMY99 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chc1/mod.rs b/src/pdb0/chc1/mod.rs index 454762d..0c21c15 100644 --- a/src/pdb0/chc1/mod.rs +++ b/src/pdb0/chc1/mod.rs @@ -22,7 +22,9 @@ impl super::CHC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::CHC1 { #[doc = "Possible values of the field `EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENR { - #[doc = "PDB channel's corresponding pre-trigger disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger enabled."] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB channel's corresponding pre-trigger disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger enabled."] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl ENR { #[doc = r" Value of the field as raw bits"] @@ -88,8 +87,7 @@ pub enum TOSR { _0, #[doc = "PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1."] _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl TOSR { #[doc = r" Value of the field as raw bits"] @@ -125,12 +123,9 @@ impl TOSR { #[doc = "Possible values of the field `BB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBR { - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl BBR { #[doc = r" Value of the field as raw bits"] @@ -165,10 +160,8 @@ impl BBR { } #[doc = "Values that can be written to the field `EN`"] pub enum ENW { - #[doc = "PDB channel's corresponding pre-trigger disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger enabled."] - _1, + #[doc = "PDB channel's corresponding pre-trigger disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger enabled."] _1, } impl ENW { #[allow(missing_docs)] @@ -261,10 +254,8 @@ impl<'a> _TOSW<'a> { } #[doc = "Values that can be written to the field `BB`"] pub enum BBW { - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] - _1, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] _1, } impl BBW { #[allow(missing_docs)] diff --git a/src/pdb0/chdly0/mod.rs b/src/pdb0/chdly0/mod.rs index 03e96f4..7a105cf 100644 --- a/src/pdb0/chdly0/mod.rs +++ b/src/pdb0/chdly0/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly1/mod.rs b/src/pdb0/chdly1/mod.rs index f03872e..25208c6 100644 --- a/src/pdb0/chdly1/mod.rs +++ b/src/pdb0/chdly1/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly2/mod.rs b/src/pdb0/chdly2/mod.rs index ab947dc..055214e 100644 --- a/src/pdb0/chdly2/mod.rs +++ b/src/pdb0/chdly2/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly3/mod.rs b/src/pdb0/chdly3/mod.rs index 507fda5..c6b77eb 100644 --- a/src/pdb0/chdly3/mod.rs +++ b/src/pdb0/chdly3/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly4/mod.rs b/src/pdb0/chdly4/mod.rs index 28b8e56..1658732 100644 --- a/src/pdb0/chdly4/mod.rs +++ b/src/pdb0/chdly4/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly5/mod.rs b/src/pdb0/chdly5/mod.rs index c17ea2e..6695334 100644 --- a/src/pdb0/chdly5/mod.rs +++ b/src/pdb0/chdly5/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly6/mod.rs b/src/pdb0/chdly6/mod.rs index 5bc5095..8108832 100644 --- a/src/pdb0/chdly6/mod.rs +++ b/src/pdb0/chdly6/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chdly7/mod.rs b/src/pdb0/chdly7/mod.rs index 9bd9e6c..f5aab24 100644 --- a/src/pdb0/chdly7/mod.rs +++ b/src/pdb0/chdly7/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/chs/mod.rs b/src/pdb0/chs/mod.rs index f0b68df..9340e1e 100644 --- a/src/pdb0/chs/mod.rs +++ b/src/pdb0/chs/mod.rs @@ -22,7 +22,9 @@ impl super::CHS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::CHS { #[doc = "Possible values of the field `ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRR { - #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] - _0, + #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] _0, #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags."] _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl ERRR { #[doc = r" Value of the field as raw bits"] @@ -94,8 +94,7 @@ impl CFR { } #[doc = "Values that can be written to the field `ERR`"] pub enum ERRW { - #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] - _0, + #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] _0, #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags."] _1, } diff --git a/src/pdb0/cnt/mod.rs b/src/pdb0/cnt/mod.rs index 637988a..44d938e 100644 --- a/src/pdb0/cnt/mod.rs +++ b/src/pdb0/cnt/mod.rs @@ -6,7 +6,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/pdb0/dly1/mod.rs b/src/pdb0/dly1/mod.rs index f5e8be0..4b110ab 100644 --- a/src/pdb0/dly1/mod.rs +++ b/src/pdb0/dly1/mod.rs @@ -22,7 +22,9 @@ impl super::DLY1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/dly2/mod.rs b/src/pdb0/dly2/mod.rs index 695515b..9cb45bb 100644 --- a/src/pdb0/dly2/mod.rs +++ b/src/pdb0/dly2/mod.rs @@ -22,7 +22,9 @@ impl super::DLY2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/idly/mod.rs b/src/pdb0/idly/mod.rs index 1a60e8c..cc6adde 100644 --- a/src/pdb0/idly/mod.rs +++ b/src/pdb0/idly/mod.rs @@ -22,7 +22,9 @@ impl super::IDLY { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/mod.rs b/src/pdb0/mod.rs index 6386ab8..6a291b7 100644 --- a/src/pdb0/mod.rs +++ b/src/pdb0/mod.rs @@ -2,59 +2,33 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status and Control register"] - pub sc: SC, - #[doc = "0x04 - Modulus register"] - pub mod_: MOD, - #[doc = "0x08 - Counter register"] - pub cnt: CNT, - #[doc = "0x0c - Interrupt Delay register"] - pub idly: IDLY, - #[doc = "0x10 - Channel n Control register 1"] - pub ch0c1: CHC1, - #[doc = "0x14 - Channel n Status register"] - pub ch0s: CHS, - #[doc = "0x18 - Channel n Delay 0 register"] - pub ch0dly0: CHDLY0, - #[doc = "0x1c - Channel n Delay 1 register"] - pub ch0dly1: CHDLY1, - #[doc = "0x20 - Channel n Delay 2 register"] - pub ch0dly2: CHDLY2, - #[doc = "0x24 - Channel n Delay 3 register"] - pub ch0dly3: CHDLY3, - #[doc = "0x28 - Channel n Delay 4 register"] - pub ch0dly4: CHDLY4, - #[doc = "0x2c - Channel n Delay 5 register"] - pub ch0dly5: CHDLY5, - #[doc = "0x30 - Channel n Delay 6 register"] - pub ch0dly6: CHDLY6, - #[doc = "0x34 - Channel n Delay 7 register"] - pub ch0dly7: CHDLY7, - #[doc = "0x38 - Channel n Control register 1"] - pub ch1c1: CHC1, - #[doc = "0x3c - Channel n Status register"] - pub ch1s: CHS, - #[doc = "0x40 - Channel n Delay 0 register"] - pub ch1dly0: CHDLY0, - #[doc = "0x44 - Channel n Delay 1 register"] - pub ch1dly1: CHDLY1, - #[doc = "0x48 - Channel n Delay 2 register"] - pub ch1dly2: CHDLY2, - #[doc = "0x4c - Channel n Delay 3 register"] - pub ch1dly3: CHDLY3, - #[doc = "0x50 - Channel n Delay 4 register"] - pub ch1dly4: CHDLY4, - #[doc = "0x54 - Channel n Delay 5 register"] - pub ch1dly5: CHDLY5, - #[doc = "0x58 - Channel n Delay 6 register"] - pub ch1dly6: CHDLY6, - #[doc = "0x5c - Channel n Delay 7 register"] - pub ch1dly7: CHDLY7, + #[doc = "0x00 - Status and Control register"] pub sc: SC, + #[doc = "0x04 - Modulus register"] pub mod_: MOD, + #[doc = "0x08 - Counter register"] pub cnt: CNT, + #[doc = "0x0c - Interrupt Delay register"] pub idly: IDLY, + #[doc = "0x10 - Channel n Control register 1"] pub ch0c1: CHC1, + #[doc = "0x14 - Channel n Status register"] pub ch0s: CHS, + #[doc = "0x18 - Channel n Delay 0 register"] pub ch0dly0: CHDLY0, + #[doc = "0x1c - Channel n Delay 1 register"] pub ch0dly1: CHDLY1, + #[doc = "0x20 - Channel n Delay 2 register"] pub ch0dly2: CHDLY2, + #[doc = "0x24 - Channel n Delay 3 register"] pub ch0dly3: CHDLY3, + #[doc = "0x28 - Channel n Delay 4 register"] pub ch0dly4: CHDLY4, + #[doc = "0x2c - Channel n Delay 5 register"] pub ch0dly5: CHDLY5, + #[doc = "0x30 - Channel n Delay 6 register"] pub ch0dly6: CHDLY6, + #[doc = "0x34 - Channel n Delay 7 register"] pub ch0dly7: CHDLY7, + #[doc = "0x38 - Channel n Control register 1"] pub ch1c1: CHC1, + #[doc = "0x3c - Channel n Status register"] pub ch1s: CHS, + #[doc = "0x40 - Channel n Delay 0 register"] pub ch1dly0: CHDLY0, + #[doc = "0x44 - Channel n Delay 1 register"] pub ch1dly1: CHDLY1, + #[doc = "0x48 - Channel n Delay 2 register"] pub ch1dly2: CHDLY2, + #[doc = "0x4c - Channel n Delay 3 register"] pub ch1dly3: CHDLY3, + #[doc = "0x50 - Channel n Delay 4 register"] pub ch1dly4: CHDLY4, + #[doc = "0x54 - Channel n Delay 5 register"] pub ch1dly5: CHDLY5, + #[doc = "0x58 - Channel n Delay 6 register"] pub ch1dly6: CHDLY6, + #[doc = "0x5c - Channel n Delay 7 register"] pub ch1dly7: CHDLY7, _reserved0: [u8; 304usize], - #[doc = "0x190 - Pulse-Out n Enable register"] - pub poen: POEN, - #[doc = "0x194 - Pulse-Out n Delay register"] - pub podly: PODLY, + #[doc = "0x190 - Pulse-Out n Enable register"] pub poen: POEN, + #[doc = "0x194 - Pulse-Out n Delay register"] pub podly: PODLY, } #[doc = "Status and Control register"] pub struct SC { diff --git a/src/pdb0/mod_/mod.rs b/src/pdb0/mod_/mod.rs index d3d37ae..df4afa2 100644 --- a/src/pdb0/mod_/mod.rs +++ b/src/pdb0/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/podly/mod.rs b/src/pdb0/podly/mod.rs index 31aee6b..bd14225 100644 --- a/src/pdb0/podly/mod.rs +++ b/src/pdb0/podly/mod.rs @@ -22,7 +22,9 @@ impl super::PODLY { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb0/poen/mod.rs b/src/pdb0/poen/mod.rs index 0758137..84d48ef 100644 --- a/src/pdb0/poen/mod.rs +++ b/src/pdb0/poen/mod.rs @@ -22,7 +22,9 @@ impl super::POEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::POEN { #[doc = "Possible values of the field `POEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POENR { - #[doc = "PDB Pulse-Out disabled"] - _0, - #[doc = "PDB Pulse-Out enabled"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB Pulse-Out disabled"] _0, + #[doc = "PDB Pulse-Out enabled"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl POENR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl POENR { } #[doc = "Values that can be written to the field `POEN`"] pub enum POENW { - #[doc = "PDB Pulse-Out disabled"] - _0, - #[doc = "PDB Pulse-Out enabled"] - _1, + #[doc = "PDB Pulse-Out disabled"] _0, + #[doc = "PDB Pulse-Out enabled"] _1, } impl POENW { #[allow(missing_docs)] diff --git a/src/pdb0/sc/mod.rs b/src/pdb0/sc/mod.rs index cfb5582..246d0fb 100644 --- a/src/pdb0/sc/mod.rs +++ b/src/pdb0/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl LDOKR { #[doc = "Possible values of the field `CONT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTR { - #[doc = "PDB operation in One-Shot mode"] - _0, - #[doc = "PDB operation in Continuous mode"] - _1, + #[doc = "PDB operation in One-Shot mode"] _0, + #[doc = "PDB operation in Continuous mode"] _1, } impl CONTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -111,14 +111,10 @@ impl CONTR { #[doc = "Possible values of the field `MULT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MULTR { - #[doc = "Multiplication factor is 1."] - _00, - #[doc = "Multiplication factor is 10."] - _01, - #[doc = "Multiplication factor is 20."] - _10, - #[doc = "Multiplication factor is 40."] - _11, + #[doc = "Multiplication factor is 1."] _00, + #[doc = "Multiplication factor is 10."] _01, + #[doc = "Multiplication factor is 20."] _10, + #[doc = "Multiplication factor is 40."] _11, } impl MULTR { #[doc = r" Value of the field as raw bits"] @@ -167,10 +163,8 @@ impl MULTR { #[doc = "Possible values of the field `PDBIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBIER { - #[doc = "PDB interrupt disabled."] - _0, - #[doc = "PDB interrupt enabled."] - _1, + #[doc = "PDB interrupt disabled."] _0, + #[doc = "PDB interrupt enabled."] _1, } impl PDBIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -235,10 +229,8 @@ impl PDBIFR { #[doc = "Possible values of the field `PDBEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBENR { - #[doc = "PDB disabled. Counter is off."] - _0, - #[doc = "PDB enabled."] - _1, + #[doc = "PDB disabled. Counter is off."] _0, + #[doc = "PDB enabled."] _1, } impl PDBENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,38 +274,22 @@ impl PDBENR { #[doc = "Possible values of the field `TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSELR { - #[doc = "Trigger-In 0 is selected."] - _0000, - #[doc = "Trigger-In 1 is selected."] - _0001, - #[doc = "Trigger-In 2 is selected."] - _0010, - #[doc = "Trigger-In 3 is selected."] - _0011, - #[doc = "Trigger-In 4 is selected."] - _0100, - #[doc = "Trigger-In 5 is selected."] - _0101, - #[doc = "Trigger-In 6 is selected."] - _0110, - #[doc = "Trigger-In 7 is selected."] - _0111, - #[doc = "Trigger-In 8 is selected."] - _1000, - #[doc = "Trigger-In 9 is selected."] - _1001, - #[doc = "Trigger-In 10 is selected."] - _1010, - #[doc = "Trigger-In 11 is selected."] - _1011, - #[doc = "Trigger-In 12 is selected."] - _1100, - #[doc = "Trigger-In 13 is selected."] - _1101, - #[doc = "Trigger-In 14 is selected."] - _1110, - #[doc = "Software trigger is selected."] - _1111, + #[doc = "Trigger-In 0 is selected."] _0000, + #[doc = "Trigger-In 1 is selected."] _0001, + #[doc = "Trigger-In 2 is selected."] _0010, + #[doc = "Trigger-In 3 is selected."] _0011, + #[doc = "Trigger-In 4 is selected."] _0100, + #[doc = "Trigger-In 5 is selected."] _0101, + #[doc = "Trigger-In 6 is selected."] _0110, + #[doc = "Trigger-In 7 is selected."] _0111, + #[doc = "Trigger-In 8 is selected."] _1000, + #[doc = "Trigger-In 9 is selected."] _1001, + #[doc = "Trigger-In 10 is selected."] _1010, + #[doc = "Trigger-In 11 is selected."] _1011, + #[doc = "Trigger-In 12 is selected."] _1100, + #[doc = "Trigger-In 13 is selected."] _1101, + #[doc = "Trigger-In 14 is selected."] _1110, + #[doc = "Software trigger is selected."] _1111, } impl TRGSELR { #[doc = r" Value of the field as raw bits"] @@ -446,8 +422,7 @@ impl TRGSELR { #[doc = "Possible values of the field `PRESCALER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALERR { - #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] - _000, + #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] _000, #[doc = "Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor)."] _001, #[doc = "Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor)."] @@ -538,10 +513,8 @@ impl PRESCALERR { #[doc = "Possible values of the field `DMAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAENR { - #[doc = "DMA disabled."] - _0, - #[doc = "DMA enabled."] - _1, + #[doc = "DMA disabled."] _0, + #[doc = "DMA enabled."] _1, } impl DMAENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -585,10 +558,8 @@ impl DMAENR { #[doc = "Possible values of the field `PDBEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBEIER { - #[doc = "PDB sequence error interrupt disabled."] - _0, - #[doc = "PDB sequence error interrupt enabled."] - _1, + #[doc = "PDB sequence error interrupt disabled."] _0, + #[doc = "PDB sequence error interrupt enabled."] _1, } impl PDBEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -710,10 +681,8 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `CONT`"] pub enum CONTW { - #[doc = "PDB operation in One-Shot mode"] - _0, - #[doc = "PDB operation in Continuous mode"] - _1, + #[doc = "PDB operation in One-Shot mode"] _0, + #[doc = "PDB operation in Continuous mode"] _1, } impl CONTW { #[allow(missing_docs)] @@ -768,14 +737,10 @@ impl<'a> _CONTW<'a> { } #[doc = "Values that can be written to the field `MULT`"] pub enum MULTW { - #[doc = "Multiplication factor is 1."] - _00, - #[doc = "Multiplication factor is 10."] - _01, - #[doc = "Multiplication factor is 20."] - _10, - #[doc = "Multiplication factor is 40."] - _11, + #[doc = "Multiplication factor is 1."] _00, + #[doc = "Multiplication factor is 10."] _01, + #[doc = "Multiplication factor is 20."] _10, + #[doc = "Multiplication factor is 40."] _11, } impl MULTW { #[allow(missing_docs)] @@ -834,10 +799,8 @@ impl<'a> _MULTW<'a> { } #[doc = "Values that can be written to the field `PDBIE`"] pub enum PDBIEW { - #[doc = "PDB interrupt disabled."] - _0, - #[doc = "PDB interrupt enabled."] - _1, + #[doc = "PDB interrupt disabled."] _0, + #[doc = "PDB interrupt enabled."] _1, } impl PDBIEW { #[allow(missing_docs)] @@ -915,10 +878,8 @@ impl<'a> _PDBIFW<'a> { } #[doc = "Values that can be written to the field `PDBEN`"] pub enum PDBENW { - #[doc = "PDB disabled. Counter is off."] - _0, - #[doc = "PDB enabled."] - _1, + #[doc = "PDB disabled. Counter is off."] _0, + #[doc = "PDB enabled."] _1, } impl PDBENW { #[allow(missing_docs)] @@ -973,38 +934,22 @@ impl<'a> _PDBENW<'a> { } #[doc = "Values that can be written to the field `TRGSEL`"] pub enum TRGSELW { - #[doc = "Trigger-In 0 is selected."] - _0000, - #[doc = "Trigger-In 1 is selected."] - _0001, - #[doc = "Trigger-In 2 is selected."] - _0010, - #[doc = "Trigger-In 3 is selected."] - _0011, - #[doc = "Trigger-In 4 is selected."] - _0100, - #[doc = "Trigger-In 5 is selected."] - _0101, - #[doc = "Trigger-In 6 is selected."] - _0110, - #[doc = "Trigger-In 7 is selected."] - _0111, - #[doc = "Trigger-In 8 is selected."] - _1000, - #[doc = "Trigger-In 9 is selected."] - _1001, - #[doc = "Trigger-In 10 is selected."] - _1010, - #[doc = "Trigger-In 11 is selected."] - _1011, - #[doc = "Trigger-In 12 is selected."] - _1100, - #[doc = "Trigger-In 13 is selected."] - _1101, - #[doc = "Trigger-In 14 is selected."] - _1110, - #[doc = "Software trigger is selected."] - _1111, + #[doc = "Trigger-In 0 is selected."] _0000, + #[doc = "Trigger-In 1 is selected."] _0001, + #[doc = "Trigger-In 2 is selected."] _0010, + #[doc = "Trigger-In 3 is selected."] _0011, + #[doc = "Trigger-In 4 is selected."] _0100, + #[doc = "Trigger-In 5 is selected."] _0101, + #[doc = "Trigger-In 6 is selected."] _0110, + #[doc = "Trigger-In 7 is selected."] _0111, + #[doc = "Trigger-In 8 is selected."] _1000, + #[doc = "Trigger-In 9 is selected."] _1001, + #[doc = "Trigger-In 10 is selected."] _1010, + #[doc = "Trigger-In 11 is selected."] _1011, + #[doc = "Trigger-In 12 is selected."] _1100, + #[doc = "Trigger-In 13 is selected."] _1101, + #[doc = "Trigger-In 14 is selected."] _1110, + #[doc = "Software trigger is selected."] _1111, } impl TRGSELW { #[allow(missing_docs)] @@ -1135,8 +1080,7 @@ impl<'a> _TRGSELW<'a> { } #[doc = "Values that can be written to the field `PRESCALER`"] pub enum PRESCALERW { - #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] - _000, + #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] _000, #[doc = "Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor)."] _001, #[doc = "Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor)."] @@ -1233,10 +1177,8 @@ impl<'a> _PRESCALERW<'a> { } #[doc = "Values that can be written to the field `DMAEN`"] pub enum DMAENW { - #[doc = "DMA disabled."] - _0, - #[doc = "DMA enabled."] - _1, + #[doc = "DMA disabled."] _0, + #[doc = "DMA enabled."] _1, } impl DMAENW { #[allow(missing_docs)] @@ -1314,10 +1256,8 @@ impl<'a> _SWTRIGW<'a> { } #[doc = "Values that can be written to the field `PDBEIE`"] pub enum PDBEIEW { - #[doc = "PDB sequence error interrupt disabled."] - _0, - #[doc = "PDB sequence error interrupt enabled."] - _1, + #[doc = "PDB sequence error interrupt disabled."] _0, + #[doc = "PDB sequence error interrupt enabled."] _1, } impl PDBEIEW { #[allow(missing_docs)] diff --git a/src/pdb1/chc1/mod.rs b/src/pdb1/chc1/mod.rs index 454762d..0c21c15 100644 --- a/src/pdb1/chc1/mod.rs +++ b/src/pdb1/chc1/mod.rs @@ -22,7 +22,9 @@ impl super::CHC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::CHC1 { #[doc = "Possible values of the field `EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENR { - #[doc = "PDB channel's corresponding pre-trigger disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger enabled."] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB channel's corresponding pre-trigger disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger enabled."] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl ENR { #[doc = r" Value of the field as raw bits"] @@ -88,8 +87,7 @@ pub enum TOSR { _0, #[doc = "PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1."] _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl TOSR { #[doc = r" Value of the field as raw bits"] @@ -125,12 +123,9 @@ impl TOSR { #[doc = "Possible values of the field `BB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BBR { - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl BBR { #[doc = r" Value of the field as raw bits"] @@ -165,10 +160,8 @@ impl BBR { } #[doc = "Values that can be written to the field `EN`"] pub enum ENW { - #[doc = "PDB channel's corresponding pre-trigger disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger enabled."] - _1, + #[doc = "PDB channel's corresponding pre-trigger disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger enabled."] _1, } impl ENW { #[allow(missing_docs)] @@ -261,10 +254,8 @@ impl<'a> _TOSW<'a> { } #[doc = "Values that can be written to the field `BB`"] pub enum BBW { - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] - _0, - #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] - _1, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation disabled."] _0, + #[doc = "PDB channel's corresponding pre-trigger back-to-back operation enabled."] _1, } impl BBW { #[allow(missing_docs)] diff --git a/src/pdb1/chdly0/mod.rs b/src/pdb1/chdly0/mod.rs index 03e96f4..7a105cf 100644 --- a/src/pdb1/chdly0/mod.rs +++ b/src/pdb1/chdly0/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly1/mod.rs b/src/pdb1/chdly1/mod.rs index f03872e..25208c6 100644 --- a/src/pdb1/chdly1/mod.rs +++ b/src/pdb1/chdly1/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly2/mod.rs b/src/pdb1/chdly2/mod.rs index ab947dc..055214e 100644 --- a/src/pdb1/chdly2/mod.rs +++ b/src/pdb1/chdly2/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly3/mod.rs b/src/pdb1/chdly3/mod.rs index 507fda5..c6b77eb 100644 --- a/src/pdb1/chdly3/mod.rs +++ b/src/pdb1/chdly3/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly4/mod.rs b/src/pdb1/chdly4/mod.rs index 28b8e56..1658732 100644 --- a/src/pdb1/chdly4/mod.rs +++ b/src/pdb1/chdly4/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly5/mod.rs b/src/pdb1/chdly5/mod.rs index c17ea2e..6695334 100644 --- a/src/pdb1/chdly5/mod.rs +++ b/src/pdb1/chdly5/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly6/mod.rs b/src/pdb1/chdly6/mod.rs index 5bc5095..8108832 100644 --- a/src/pdb1/chdly6/mod.rs +++ b/src/pdb1/chdly6/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chdly7/mod.rs b/src/pdb1/chdly7/mod.rs index 9bd9e6c..f5aab24 100644 --- a/src/pdb1/chdly7/mod.rs +++ b/src/pdb1/chdly7/mod.rs @@ -22,7 +22,9 @@ impl super::CHDLY7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/chs/mod.rs b/src/pdb1/chs/mod.rs index f0b68df..9340e1e 100644 --- a/src/pdb1/chs/mod.rs +++ b/src/pdb1/chs/mod.rs @@ -22,7 +22,9 @@ impl super::CHS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::CHS { #[doc = "Possible values of the field `ERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ERRR { - #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] - _0, + #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] _0, #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags."] _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = r" Reserved"] _Reserved(u8), } impl ERRR { #[doc = r" Value of the field as raw bits"] @@ -94,8 +94,7 @@ impl CFR { } #[doc = "Values that can be written to the field `ERR`"] pub enum ERRW { - #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] - _0, + #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."] _0, #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags."] _1, } diff --git a/src/pdb1/cnt/mod.rs b/src/pdb1/cnt/mod.rs index 637988a..44d938e 100644 --- a/src/pdb1/cnt/mod.rs +++ b/src/pdb1/cnt/mod.rs @@ -6,7 +6,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/pdb1/dly1/mod.rs b/src/pdb1/dly1/mod.rs index f5e8be0..4b110ab 100644 --- a/src/pdb1/dly1/mod.rs +++ b/src/pdb1/dly1/mod.rs @@ -22,7 +22,9 @@ impl super::DLY1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/dly2/mod.rs b/src/pdb1/dly2/mod.rs index 695515b..9cb45bb 100644 --- a/src/pdb1/dly2/mod.rs +++ b/src/pdb1/dly2/mod.rs @@ -22,7 +22,9 @@ impl super::DLY2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/idly/mod.rs b/src/pdb1/idly/mod.rs index 1a60e8c..cc6adde 100644 --- a/src/pdb1/idly/mod.rs +++ b/src/pdb1/idly/mod.rs @@ -22,7 +22,9 @@ impl super::IDLY { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/mod.rs b/src/pdb1/mod.rs index b343b4f..ca23344 100644 --- a/src/pdb1/mod.rs +++ b/src/pdb1/mod.rs @@ -2,59 +2,33 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Status and Control register"] - pub sc: SC, - #[doc = "0x04 - Modulus register"] - pub mod_: MOD, - #[doc = "0x08 - Counter register"] - pub cnt: CNT, - #[doc = "0x0c - Interrupt Delay register"] - pub idly: IDLY, - #[doc = "0x10 - Channel n Control register 1"] - pub ch0c1: CHC1, - #[doc = "0x14 - Channel n Status register"] - pub ch0s: CHS, - #[doc = "0x18 - Channel n Delay 0 register"] - pub ch0dly0: CHDLY0, - #[doc = "0x1c - Channel n Delay 1 register"] - pub ch0dly1: CHDLY1, - #[doc = "0x20 - Channel n Delay 2 register"] - pub ch0dly2: CHDLY2, - #[doc = "0x24 - Channel n Delay 3 register"] - pub ch0dly3: CHDLY3, - #[doc = "0x28 - Channel n Delay 4 register"] - pub ch0dly4: CHDLY4, - #[doc = "0x2c - Channel n Delay 5 register"] - pub ch0dly5: CHDLY5, - #[doc = "0x30 - Channel n Delay 6 register"] - pub ch0dly6: CHDLY6, - #[doc = "0x34 - Channel n Delay 7 register"] - pub ch0dly7: CHDLY7, - #[doc = "0x38 - Channel n Control register 1"] - pub ch1c1: CHC1, - #[doc = "0x3c - Channel n Status register"] - pub ch1s: CHS, - #[doc = "0x40 - Channel n Delay 0 register"] - pub ch1dly0: CHDLY0, - #[doc = "0x44 - Channel n Delay 1 register"] - pub ch1dly1: CHDLY1, - #[doc = "0x48 - Channel n Delay 2 register"] - pub ch1dly2: CHDLY2, - #[doc = "0x4c - Channel n Delay 3 register"] - pub ch1dly3: CHDLY3, - #[doc = "0x50 - Channel n Delay 4 register"] - pub ch1dly4: CHDLY4, - #[doc = "0x54 - Channel n Delay 5 register"] - pub ch1dly5: CHDLY5, - #[doc = "0x58 - Channel n Delay 6 register"] - pub ch1dly6: CHDLY6, - #[doc = "0x5c - Channel n Delay 7 register"] - pub ch1dly7: CHDLY7, + #[doc = "0x00 - Status and Control register"] pub sc: SC, + #[doc = "0x04 - Modulus register"] pub mod_: MOD, + #[doc = "0x08 - Counter register"] pub cnt: CNT, + #[doc = "0x0c - Interrupt Delay register"] pub idly: IDLY, + #[doc = "0x10 - Channel n Control register 1"] pub ch0c1: CHC1, + #[doc = "0x14 - Channel n Status register"] pub ch0s: CHS, + #[doc = "0x18 - Channel n Delay 0 register"] pub ch0dly0: CHDLY0, + #[doc = "0x1c - Channel n Delay 1 register"] pub ch0dly1: CHDLY1, + #[doc = "0x20 - Channel n Delay 2 register"] pub ch0dly2: CHDLY2, + #[doc = "0x24 - Channel n Delay 3 register"] pub ch0dly3: CHDLY3, + #[doc = "0x28 - Channel n Delay 4 register"] pub ch0dly4: CHDLY4, + #[doc = "0x2c - Channel n Delay 5 register"] pub ch0dly5: CHDLY5, + #[doc = "0x30 - Channel n Delay 6 register"] pub ch0dly6: CHDLY6, + #[doc = "0x34 - Channel n Delay 7 register"] pub ch0dly7: CHDLY7, + #[doc = "0x38 - Channel n Control register 1"] pub ch1c1: CHC1, + #[doc = "0x3c - Channel n Status register"] pub ch1s: CHS, + #[doc = "0x40 - Channel n Delay 0 register"] pub ch1dly0: CHDLY0, + #[doc = "0x44 - Channel n Delay 1 register"] pub ch1dly1: CHDLY1, + #[doc = "0x48 - Channel n Delay 2 register"] pub ch1dly2: CHDLY2, + #[doc = "0x4c - Channel n Delay 3 register"] pub ch1dly3: CHDLY3, + #[doc = "0x50 - Channel n Delay 4 register"] pub ch1dly4: CHDLY4, + #[doc = "0x54 - Channel n Delay 5 register"] pub ch1dly5: CHDLY5, + #[doc = "0x58 - Channel n Delay 6 register"] pub ch1dly6: CHDLY6, + #[doc = "0x5c - Channel n Delay 7 register"] pub ch1dly7: CHDLY7, _reserved0: [u8; 304usize], - #[doc = "0x190 - Pulse-Out n Enable register"] - pub poen: POEN, - #[doc = "0x194 - Pulse-Out n Delay register"] - pub podly: PODLY, + #[doc = "0x190 - Pulse-Out n Enable register"] pub poen: POEN, + #[doc = "0x194 - Pulse-Out n Delay register"] pub podly: PODLY, } #[doc = "Status and Control register"] pub struct SC { diff --git a/src/pdb1/mod_/mod.rs b/src/pdb1/mod_/mod.rs index d3d37ae..df4afa2 100644 --- a/src/pdb1/mod_/mod.rs +++ b/src/pdb1/mod_/mod.rs @@ -22,7 +22,9 @@ impl super::MOD { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/podly/mod.rs b/src/pdb1/podly/mod.rs index 31aee6b..bd14225 100644 --- a/src/pdb1/podly/mod.rs +++ b/src/pdb1/podly/mod.rs @@ -22,7 +22,9 @@ impl super::PODLY { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pdb1/poen/mod.rs b/src/pdb1/poen/mod.rs index 0758137..84d48ef 100644 --- a/src/pdb1/poen/mod.rs +++ b/src/pdb1/poen/mod.rs @@ -22,7 +22,9 @@ impl super::POEN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::POEN { #[doc = "Possible values of the field `POEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum POENR { - #[doc = "PDB Pulse-Out disabled"] - _0, - #[doc = "PDB Pulse-Out enabled"] - _1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB Pulse-Out disabled"] _0, + #[doc = "PDB Pulse-Out enabled"] _1, + #[doc = r" Reserved"] _Reserved(u8), } impl POENR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl POENR { } #[doc = "Values that can be written to the field `POEN`"] pub enum POENW { - #[doc = "PDB Pulse-Out disabled"] - _0, - #[doc = "PDB Pulse-Out enabled"] - _1, + #[doc = "PDB Pulse-Out disabled"] _0, + #[doc = "PDB Pulse-Out enabled"] _1, } impl POENW { #[allow(missing_docs)] diff --git a/src/pdb1/sc/mod.rs b/src/pdb1/sc/mod.rs index cfb5582..246d0fb 100644 --- a/src/pdb1/sc/mod.rs +++ b/src/pdb1/sc/mod.rs @@ -22,7 +22,9 @@ impl super::SC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -64,10 +66,8 @@ impl LDOKR { #[doc = "Possible values of the field `CONT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CONTR { - #[doc = "PDB operation in One-Shot mode"] - _0, - #[doc = "PDB operation in Continuous mode"] - _1, + #[doc = "PDB operation in One-Shot mode"] _0, + #[doc = "PDB operation in Continuous mode"] _1, } impl CONTR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -111,14 +111,10 @@ impl CONTR { #[doc = "Possible values of the field `MULT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MULTR { - #[doc = "Multiplication factor is 1."] - _00, - #[doc = "Multiplication factor is 10."] - _01, - #[doc = "Multiplication factor is 20."] - _10, - #[doc = "Multiplication factor is 40."] - _11, + #[doc = "Multiplication factor is 1."] _00, + #[doc = "Multiplication factor is 10."] _01, + #[doc = "Multiplication factor is 20."] _10, + #[doc = "Multiplication factor is 40."] _11, } impl MULTR { #[doc = r" Value of the field as raw bits"] @@ -167,10 +163,8 @@ impl MULTR { #[doc = "Possible values of the field `PDBIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBIER { - #[doc = "PDB interrupt disabled."] - _0, - #[doc = "PDB interrupt enabled."] - _1, + #[doc = "PDB interrupt disabled."] _0, + #[doc = "PDB interrupt enabled."] _1, } impl PDBIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -235,10 +229,8 @@ impl PDBIFR { #[doc = "Possible values of the field `PDBEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBENR { - #[doc = "PDB disabled. Counter is off."] - _0, - #[doc = "PDB enabled."] - _1, + #[doc = "PDB disabled. Counter is off."] _0, + #[doc = "PDB enabled."] _1, } impl PDBENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -282,38 +274,22 @@ impl PDBENR { #[doc = "Possible values of the field `TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRGSELR { - #[doc = "Trigger-In 0 is selected."] - _0000, - #[doc = "Trigger-In 1 is selected."] - _0001, - #[doc = "Trigger-In 2 is selected."] - _0010, - #[doc = "Trigger-In 3 is selected."] - _0011, - #[doc = "Trigger-In 4 is selected."] - _0100, - #[doc = "Trigger-In 5 is selected."] - _0101, - #[doc = "Trigger-In 6 is selected."] - _0110, - #[doc = "Trigger-In 7 is selected."] - _0111, - #[doc = "Trigger-In 8 is selected."] - _1000, - #[doc = "Trigger-In 9 is selected."] - _1001, - #[doc = "Trigger-In 10 is selected."] - _1010, - #[doc = "Trigger-In 11 is selected."] - _1011, - #[doc = "Trigger-In 12 is selected."] - _1100, - #[doc = "Trigger-In 13 is selected."] - _1101, - #[doc = "Trigger-In 14 is selected."] - _1110, - #[doc = "Software trigger is selected."] - _1111, + #[doc = "Trigger-In 0 is selected."] _0000, + #[doc = "Trigger-In 1 is selected."] _0001, + #[doc = "Trigger-In 2 is selected."] _0010, + #[doc = "Trigger-In 3 is selected."] _0011, + #[doc = "Trigger-In 4 is selected."] _0100, + #[doc = "Trigger-In 5 is selected."] _0101, + #[doc = "Trigger-In 6 is selected."] _0110, + #[doc = "Trigger-In 7 is selected."] _0111, + #[doc = "Trigger-In 8 is selected."] _1000, + #[doc = "Trigger-In 9 is selected."] _1001, + #[doc = "Trigger-In 10 is selected."] _1010, + #[doc = "Trigger-In 11 is selected."] _1011, + #[doc = "Trigger-In 12 is selected."] _1100, + #[doc = "Trigger-In 13 is selected."] _1101, + #[doc = "Trigger-In 14 is selected."] _1110, + #[doc = "Software trigger is selected."] _1111, } impl TRGSELR { #[doc = r" Value of the field as raw bits"] @@ -446,8 +422,7 @@ impl TRGSELR { #[doc = "Possible values of the field `PRESCALER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESCALERR { - #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] - _000, + #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] _000, #[doc = "Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor)."] _001, #[doc = "Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor)."] @@ -538,10 +513,8 @@ impl PRESCALERR { #[doc = "Possible values of the field `DMAEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DMAENR { - #[doc = "DMA disabled."] - _0, - #[doc = "DMA enabled."] - _1, + #[doc = "DMA disabled."] _0, + #[doc = "DMA enabled."] _1, } impl DMAENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -585,10 +558,8 @@ impl DMAENR { #[doc = "Possible values of the field `PDBEIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PDBEIER { - #[doc = "PDB sequence error interrupt disabled."] - _0, - #[doc = "PDB sequence error interrupt enabled."] - _1, + #[doc = "PDB sequence error interrupt disabled."] _0, + #[doc = "PDB sequence error interrupt enabled."] _1, } impl PDBEIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -710,10 +681,8 @@ impl<'a> _LDOKW<'a> { } #[doc = "Values that can be written to the field `CONT`"] pub enum CONTW { - #[doc = "PDB operation in One-Shot mode"] - _0, - #[doc = "PDB operation in Continuous mode"] - _1, + #[doc = "PDB operation in One-Shot mode"] _0, + #[doc = "PDB operation in Continuous mode"] _1, } impl CONTW { #[allow(missing_docs)] @@ -768,14 +737,10 @@ impl<'a> _CONTW<'a> { } #[doc = "Values that can be written to the field `MULT`"] pub enum MULTW { - #[doc = "Multiplication factor is 1."] - _00, - #[doc = "Multiplication factor is 10."] - _01, - #[doc = "Multiplication factor is 20."] - _10, - #[doc = "Multiplication factor is 40."] - _11, + #[doc = "Multiplication factor is 1."] _00, + #[doc = "Multiplication factor is 10."] _01, + #[doc = "Multiplication factor is 20."] _10, + #[doc = "Multiplication factor is 40."] _11, } impl MULTW { #[allow(missing_docs)] @@ -834,10 +799,8 @@ impl<'a> _MULTW<'a> { } #[doc = "Values that can be written to the field `PDBIE`"] pub enum PDBIEW { - #[doc = "PDB interrupt disabled."] - _0, - #[doc = "PDB interrupt enabled."] - _1, + #[doc = "PDB interrupt disabled."] _0, + #[doc = "PDB interrupt enabled."] _1, } impl PDBIEW { #[allow(missing_docs)] @@ -915,10 +878,8 @@ impl<'a> _PDBIFW<'a> { } #[doc = "Values that can be written to the field `PDBEN`"] pub enum PDBENW { - #[doc = "PDB disabled. Counter is off."] - _0, - #[doc = "PDB enabled."] - _1, + #[doc = "PDB disabled. Counter is off."] _0, + #[doc = "PDB enabled."] _1, } impl PDBENW { #[allow(missing_docs)] @@ -973,38 +934,22 @@ impl<'a> _PDBENW<'a> { } #[doc = "Values that can be written to the field `TRGSEL`"] pub enum TRGSELW { - #[doc = "Trigger-In 0 is selected."] - _0000, - #[doc = "Trigger-In 1 is selected."] - _0001, - #[doc = "Trigger-In 2 is selected."] - _0010, - #[doc = "Trigger-In 3 is selected."] - _0011, - #[doc = "Trigger-In 4 is selected."] - _0100, - #[doc = "Trigger-In 5 is selected."] - _0101, - #[doc = "Trigger-In 6 is selected."] - _0110, - #[doc = "Trigger-In 7 is selected."] - _0111, - #[doc = "Trigger-In 8 is selected."] - _1000, - #[doc = "Trigger-In 9 is selected."] - _1001, - #[doc = "Trigger-In 10 is selected."] - _1010, - #[doc = "Trigger-In 11 is selected."] - _1011, - #[doc = "Trigger-In 12 is selected."] - _1100, - #[doc = "Trigger-In 13 is selected."] - _1101, - #[doc = "Trigger-In 14 is selected."] - _1110, - #[doc = "Software trigger is selected."] - _1111, + #[doc = "Trigger-In 0 is selected."] _0000, + #[doc = "Trigger-In 1 is selected."] _0001, + #[doc = "Trigger-In 2 is selected."] _0010, + #[doc = "Trigger-In 3 is selected."] _0011, + #[doc = "Trigger-In 4 is selected."] _0100, + #[doc = "Trigger-In 5 is selected."] _0101, + #[doc = "Trigger-In 6 is selected."] _0110, + #[doc = "Trigger-In 7 is selected."] _0111, + #[doc = "Trigger-In 8 is selected."] _1000, + #[doc = "Trigger-In 9 is selected."] _1001, + #[doc = "Trigger-In 10 is selected."] _1010, + #[doc = "Trigger-In 11 is selected."] _1011, + #[doc = "Trigger-In 12 is selected."] _1100, + #[doc = "Trigger-In 13 is selected."] _1101, + #[doc = "Trigger-In 14 is selected."] _1110, + #[doc = "Software trigger is selected."] _1111, } impl TRGSELW { #[allow(missing_docs)] @@ -1135,8 +1080,7 @@ impl<'a> _TRGSELW<'a> { } #[doc = "Values that can be written to the field `PRESCALER`"] pub enum PRESCALERW { - #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] - _000, + #[doc = "Counting uses the peripheral clock divided by MULT (the multiplication factor)."] _000, #[doc = "Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor)."] _001, #[doc = "Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor)."] @@ -1233,10 +1177,8 @@ impl<'a> _PRESCALERW<'a> { } #[doc = "Values that can be written to the field `DMAEN`"] pub enum DMAENW { - #[doc = "DMA disabled."] - _0, - #[doc = "DMA enabled."] - _1, + #[doc = "DMA disabled."] _0, + #[doc = "DMA enabled."] _1, } impl DMAENW { #[allow(missing_docs)] @@ -1314,10 +1256,8 @@ impl<'a> _SWTRIGW<'a> { } #[doc = "Values that can be written to the field `PDBEIE`"] pub enum PDBEIEW { - #[doc = "PDB sequence error interrupt disabled."] - _0, - #[doc = "PDB sequence error interrupt enabled."] - _1, + #[doc = "PDB sequence error interrupt disabled."] _0, + #[doc = "PDB sequence error interrupt enabled."] _1, } impl PDBEIEW { #[allow(missing_docs)] diff --git a/src/pmc/lpotrim/mod.rs b/src/pmc/lpotrim/mod.rs index 1dc928c..e086af7 100644 --- a/src/pmc/lpotrim/mod.rs +++ b/src/pmc/lpotrim/mod.rs @@ -22,7 +22,9 @@ impl super::LPOTRIM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pmc/lvdsc1/mod.rs b/src/pmc/lvdsc1/mod.rs index 312ab46..52b22e2 100644 --- a/src/pmc/lvdsc1/mod.rs +++ b/src/pmc/lvdsc1/mod.rs @@ -22,7 +22,9 @@ impl super::LVDSC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LVDSC1 { #[doc = "Possible values of the field `LVDRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVDRER { - #[doc = "No system resets on low voltage detect events."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "No system resets on low voltage detect events."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl LVDRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -85,10 +85,8 @@ impl LVDRER { #[doc = "Possible values of the field `LVDIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVDIER { - #[doc = "Hardware interrupt disabled (use polling)"] - _0, - #[doc = "Request a hardware interrupt when LVDF = 1"] - _1, + #[doc = "Hardware interrupt disabled (use polling)"] _0, + #[doc = "Request a hardware interrupt when LVDF = 1"] _1, } impl LVDIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +130,8 @@ impl LVDIER { #[doc = "Possible values of the field `LVDF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVDFR { - #[doc = "Low-voltage event not detected"] - _0, - #[doc = "Low-voltage event detected"] - _1, + #[doc = "Low-voltage event not detected"] _0, + #[doc = "Low-voltage event detected"] _1, } impl LVDFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -178,8 +174,7 @@ impl LVDFR { } #[doc = "Values that can be written to the field `LVDRE`"] pub enum LVDREW { - #[doc = "No system resets on low voltage detect events."] - _0, + #[doc = "No system resets on low voltage detect events."] _0, } impl LVDREW { #[allow(missing_docs)] @@ -228,10 +223,8 @@ impl<'a> _LVDREW<'a> { } #[doc = "Values that can be written to the field `LVDIE`"] pub enum LVDIEW { - #[doc = "Hardware interrupt disabled (use polling)"] - _0, - #[doc = "Request a hardware interrupt when LVDF = 1"] - _1, + #[doc = "Hardware interrupt disabled (use polling)"] _0, + #[doc = "Request a hardware interrupt when LVDF = 1"] _1, } impl LVDIEW { #[allow(missing_docs)] diff --git a/src/pmc/lvdsc2/mod.rs b/src/pmc/lvdsc2/mod.rs index 89e2a9d..48aa6c3 100644 --- a/src/pmc/lvdsc2/mod.rs +++ b/src/pmc/lvdsc2/mod.rs @@ -22,7 +22,9 @@ impl super::LVDSC2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LVDSC2 { #[doc = "Possible values of the field `LVWIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVWIER { - #[doc = "Hardware interrupt disabled (use polling)"] - _0, - #[doc = "Request a hardware interrupt when LVWF=1"] - _1, + #[doc = "Hardware interrupt disabled (use polling)"] _0, + #[doc = "Request a hardware interrupt when LVWF=1"] _1, } impl LVWIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl LVWIER { #[doc = "Possible values of the field `LVWF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVWFR { - #[doc = "Low-voltage warning event not detected"] - _0, - #[doc = "Low-voltage warning event detected"] - _1, + #[doc = "Low-voltage warning event not detected"] _0, + #[doc = "Low-voltage warning event detected"] _1, } impl LVWFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl LVWFR { } #[doc = "Values that can be written to the field `LVWIE`"] pub enum LVWIEW { - #[doc = "Hardware interrupt disabled (use polling)"] - _0, - #[doc = "Request a hardware interrupt when LVWF=1"] - _1, + #[doc = "Hardware interrupt disabled (use polling)"] _0, + #[doc = "Request a hardware interrupt when LVWF=1"] _1, } impl LVWIEW { #[allow(missing_docs)] diff --git a/src/pmc/mod.rs b/src/pmc/mod.rs index b1864e9..0a08d85 100644 --- a/src/pmc/mod.rs +++ b/src/pmc/mod.rs @@ -2,15 +2,11 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Low Voltage Detect Status and Control 1 Register"] - pub lvdsc1: LVDSC1, - #[doc = "0x01 - Low Voltage Detect Status and Control 2 Register"] - pub lvdsc2: LVDSC2, - #[doc = "0x02 - Regulator Status and Control Register"] - pub regsc: REGSC, + #[doc = "0x00 - Low Voltage Detect Status and Control 1 Register"] pub lvdsc1: LVDSC1, + #[doc = "0x01 - Low Voltage Detect Status and Control 2 Register"] pub lvdsc2: LVDSC2, + #[doc = "0x02 - Regulator Status and Control Register"] pub regsc: REGSC, _reserved0: [u8; 1usize], - #[doc = "0x04 - Low Power Oscillator Trim Register"] - pub lpotrim: LPOTRIM, + #[doc = "0x04 - Low Power Oscillator Trim Register"] pub lpotrim: LPOTRIM, } #[doc = "Low Voltage Detect Status and Control 1 Register"] pub struct LVDSC1 { diff --git a/src/pmc/regsc/mod.rs b/src/pmc/regsc/mod.rs index 474fb91..a0f77a6 100644 --- a/src/pmc/regsc/mod.rs +++ b/src/pmc/regsc/mod.rs @@ -22,7 +22,9 @@ impl super::REGSC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,8 +45,7 @@ impl super::REGSC { #[doc = "Possible values of the field `BIASEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum BIASENR { - #[doc = "Biasing disabled, core logic can run in full performance"] - _0, + #[doc = "Biasing disabled, core logic can run in full performance"] _0, #[doc = "Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details)"] _1, } @@ -90,8 +91,7 @@ impl BIASENR { #[doc = "Possible values of the field `CLKBIASDIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKBIASDISR { - #[doc = "No effect"] - _0, + #[doc = "No effect"] _0, #[doc = "In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)"] _1, } @@ -137,10 +137,8 @@ impl CLKBIASDISR { #[doc = "Possible values of the field `REGFPM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum REGFPMR { - #[doc = "Regulator is in low power mode or transition to/from"] - _0, - #[doc = "Regulator is in full performance mode"] - _1, + #[doc = "Regulator is in low power mode or transition to/from"] _0, + #[doc = "Regulator is in full performance mode"] _1, } impl REGFPMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +182,8 @@ impl REGFPMR { #[doc = "Possible values of the field `LPOSTAT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPOSTATR { - #[doc = "Low power oscillator in low phase"] - _0, - #[doc = "Low power oscillator in high phase"] - _1, + #[doc = "Low power oscillator in low phase"] _0, + #[doc = "Low power oscillator in high phase"] _1, } impl LPOSTATR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +227,8 @@ impl LPOSTATR { #[doc = "Possible values of the field `LPODIS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPODISR { - #[doc = "Low power oscillator enabled"] - _0, - #[doc = "Low power oscillator disabled"] - _1, + #[doc = "Low power oscillator enabled"] _0, + #[doc = "Low power oscillator disabled"] _1, } impl LPODISR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,8 +271,7 @@ impl LPODISR { } #[doc = "Values that can be written to the field `BIASEN`"] pub enum BIASENW { - #[doc = "Biasing disabled, core logic can run in full performance"] - _0, + #[doc = "Biasing disabled, core logic can run in full performance"] _0, #[doc = "Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details)"] _1, } @@ -335,8 +328,7 @@ impl<'a> _BIASENW<'a> { } #[doc = "Values that can be written to the field `CLKBIASDIS`"] pub enum CLKBIASDISW { - #[doc = "No effect"] - _0, + #[doc = "No effect"] _0, #[doc = "In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)"] _1, } @@ -393,10 +385,8 @@ impl<'a> _CLKBIASDISW<'a> { } #[doc = "Values that can be written to the field `LPODIS`"] pub enum LPODISW { - #[doc = "Low power oscillator enabled"] - _0, - #[doc = "Low power oscillator disabled"] - _1, + #[doc = "Low power oscillator enabled"] _0, + #[doc = "Low power oscillator disabled"] _1, } impl LPODISW { #[allow(missing_docs)] diff --git a/src/porta/dfcr/mod.rs b/src/porta/dfcr/mod.rs index 4e0e5ae..b77fb96 100644 --- a/src/porta/dfcr/mod.rs +++ b/src/porta/dfcr/mod.rs @@ -22,7 +22,9 @@ impl super::DFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DFCR { #[doc = "Possible values of the field `CS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CSR { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl CSR { } #[doc = "Values that can be written to the field `CS`"] pub enum CSW { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSW { #[allow(missing_docs)] diff --git a/src/porta/dfer/mod.rs b/src/porta/dfer/mod.rs index a80865b..1f1a9d7 100644 --- a/src/porta/dfer/mod.rs +++ b/src/porta/dfer/mod.rs @@ -22,7 +22,9 @@ impl super::DFER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -47,8 +49,7 @@ pub enum DFER { _0, #[doc = "Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl DFER { #[doc = r" Value of the field as raw bits"] diff --git a/src/porta/dfwr/mod.rs b/src/porta/dfwr/mod.rs index bed0a1c..1fb2234 100644 --- a/src/porta/dfwr/mod.rs +++ b/src/porta/dfwr/mod.rs @@ -22,7 +22,9 @@ impl super::DFWR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/porta/gpchr/mod.rs b/src/porta/gpchr/mod.rs index dcd6928..04bdd2a 100644 --- a/src/porta/gpchr/mod.rs +++ b/src/porta/gpchr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/porta/gpclr/mod.rs b/src/porta/gpclr/mod.rs index fca1209..e570701 100644 --- a/src/porta/gpclr/mod.rs +++ b/src/porta/gpclr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/porta/isfr/mod.rs b/src/porta/isfr/mod.rs index e343374..97dcc02 100644 --- a/src/porta/isfr/mod.rs +++ b/src/porta/isfr/mod.rs @@ -22,7 +22,9 @@ impl super::ISFR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::ISFR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] @@ -83,8 +83,7 @@ impl ISFR { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/mod.rs b/src/porta/mod.rs index 07f3550..9801527 100644 --- a/src/porta/mod.rs +++ b/src/porta/mod.rs @@ -2,84 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Pin Control Register n"] - pub pcr0: PCR0, - #[doc = "0x04 - Pin Control Register n"] - pub pcr1: PCR1, - #[doc = "0x08 - Pin Control Register n"] - pub pcr2: PCR2, - #[doc = "0x0c - Pin Control Register n"] - pub pcr3: PCR3, - #[doc = "0x10 - Pin Control Register n"] - pub pcr4: PCR4, - #[doc = "0x14 - Pin Control Register n"] - pub pcr5: PCR5, - #[doc = "0x18 - Pin Control Register n"] - pub pcr6: PCR6, - #[doc = "0x1c - Pin Control Register n"] - pub pcr7: PCR7, - #[doc = "0x20 - Pin Control Register n"] - pub pcr8: PCR8, - #[doc = "0x24 - Pin Control Register n"] - pub pcr9: PCR9, - #[doc = "0x28 - Pin Control Register n"] - pub pcr10: PCR10, - #[doc = "0x2c - Pin Control Register n"] - pub pcr11: PCR11, - #[doc = "0x30 - Pin Control Register n"] - pub pcr12: PCR12, - #[doc = "0x34 - Pin Control Register n"] - pub pcr13: PCR13, - #[doc = "0x38 - Pin Control Register n"] - pub pcr14: PCR14, - #[doc = "0x3c - Pin Control Register n"] - pub pcr15: PCR15, - #[doc = "0x40 - Pin Control Register n"] - pub pcr16: PCR16, - #[doc = "0x44 - Pin Control Register n"] - pub pcr17: PCR17, - #[doc = "0x48 - Pin Control Register n"] - pub pcr18: PCR18, - #[doc = "0x4c - Pin Control Register n"] - pub pcr19: PCR19, - #[doc = "0x50 - Pin Control Register n"] - pub pcr20: PCR20, - #[doc = "0x54 - Pin Control Register n"] - pub pcr21: PCR21, - #[doc = "0x58 - Pin Control Register n"] - pub pcr22: PCR22, - #[doc = "0x5c - Pin Control Register n"] - pub pcr23: PCR23, - #[doc = "0x60 - Pin Control Register n"] - pub pcr24: PCR24, - #[doc = "0x64 - Pin Control Register n"] - pub pcr25: PCR25, - #[doc = "0x68 - Pin Control Register n"] - pub pcr26: PCR26, - #[doc = "0x6c - Pin Control Register n"] - pub pcr27: PCR27, - #[doc = "0x70 - Pin Control Register n"] - pub pcr28: PCR28, - #[doc = "0x74 - Pin Control Register n"] - pub pcr29: PCR29, - #[doc = "0x78 - Pin Control Register n"] - pub pcr30: PCR30, - #[doc = "0x7c - Pin Control Register n"] - pub pcr31: PCR31, - #[doc = "0x80 - Global Pin Control Low Register"] - pub gpclr: GPCLR, - #[doc = "0x84 - Global Pin Control High Register"] - pub gpchr: GPCHR, + #[doc = "0x00 - Pin Control Register n"] pub pcr0: PCR0, + #[doc = "0x04 - Pin Control Register n"] pub pcr1: PCR1, + #[doc = "0x08 - Pin Control Register n"] pub pcr2: PCR2, + #[doc = "0x0c - Pin Control Register n"] pub pcr3: PCR3, + #[doc = "0x10 - Pin Control Register n"] pub pcr4: PCR4, + #[doc = "0x14 - Pin Control Register n"] pub pcr5: PCR5, + #[doc = "0x18 - Pin Control Register n"] pub pcr6: PCR6, + #[doc = "0x1c - Pin Control Register n"] pub pcr7: PCR7, + #[doc = "0x20 - Pin Control Register n"] pub pcr8: PCR8, + #[doc = "0x24 - Pin Control Register n"] pub pcr9: PCR9, + #[doc = "0x28 - Pin Control Register n"] pub pcr10: PCR10, + #[doc = "0x2c - Pin Control Register n"] pub pcr11: PCR11, + #[doc = "0x30 - Pin Control Register n"] pub pcr12: PCR12, + #[doc = "0x34 - Pin Control Register n"] pub pcr13: PCR13, + #[doc = "0x38 - Pin Control Register n"] pub pcr14: PCR14, + #[doc = "0x3c - Pin Control Register n"] pub pcr15: PCR15, + #[doc = "0x40 - Pin Control Register n"] pub pcr16: PCR16, + #[doc = "0x44 - Pin Control Register n"] pub pcr17: PCR17, + #[doc = "0x48 - Pin Control Register n"] pub pcr18: PCR18, + #[doc = "0x4c - Pin Control Register n"] pub pcr19: PCR19, + #[doc = "0x50 - Pin Control Register n"] pub pcr20: PCR20, + #[doc = "0x54 - Pin Control Register n"] pub pcr21: PCR21, + #[doc = "0x58 - Pin Control Register n"] pub pcr22: PCR22, + #[doc = "0x5c - Pin Control Register n"] pub pcr23: PCR23, + #[doc = "0x60 - Pin Control Register n"] pub pcr24: PCR24, + #[doc = "0x64 - Pin Control Register n"] pub pcr25: PCR25, + #[doc = "0x68 - Pin Control Register n"] pub pcr26: PCR26, + #[doc = "0x6c - Pin Control Register n"] pub pcr27: PCR27, + #[doc = "0x70 - Pin Control Register n"] pub pcr28: PCR28, + #[doc = "0x74 - Pin Control Register n"] pub pcr29: PCR29, + #[doc = "0x78 - Pin Control Register n"] pub pcr30: PCR30, + #[doc = "0x7c - Pin Control Register n"] pub pcr31: PCR31, + #[doc = "0x80 - Global Pin Control Low Register"] pub gpclr: GPCLR, + #[doc = "0x84 - Global Pin Control High Register"] pub gpchr: GPCHR, _reserved0: [u8; 24usize], - #[doc = "0xa0 - Interrupt Status Flag Register"] - pub isfr: ISFR, + #[doc = "0xa0 - Interrupt Status Flag Register"] pub isfr: ISFR, _reserved1: [u8; 28usize], - #[doc = "0xc0 - Digital Filter Enable Register"] - pub dfer: DFER, - #[doc = "0xc4 - Digital Filter Clock Register"] - pub dfcr: DFCR, - #[doc = "0xc8 - Digital Filter Width Register"] - pub dfwr: DFWR, + #[doc = "0xc0 - Digital Filter Enable Register"] pub dfer: DFER, + #[doc = "0xc4 - Digital Filter Clock Register"] pub dfcr: DFCR, + #[doc = "0xc8 - Digital Filter Width Register"] pub dfwr: DFWR, } #[doc = "Pin Control Register n"] pub struct PCR0 { diff --git a/src/porta/pcr0/mod.rs b/src/porta/pcr0/mod.rs index b7ac782..beb91de 100644 --- a/src/porta/pcr0/mod.rs +++ b/src/porta/pcr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr1/mod.rs b/src/porta/pcr1/mod.rs index 54d202b..d455463 100644 --- a/src/porta/pcr1/mod.rs +++ b/src/porta/pcr1/mod.rs @@ -22,7 +22,9 @@ impl super::PCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr10/mod.rs b/src/porta/pcr10/mod.rs index 59df419..cb4a75c 100644 --- a/src/porta/pcr10/mod.rs +++ b/src/porta/pcr10/mod.rs @@ -22,7 +22,9 @@ impl super::PCR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr11/mod.rs b/src/porta/pcr11/mod.rs index 9eec901..3b4f036 100644 --- a/src/porta/pcr11/mod.rs +++ b/src/porta/pcr11/mod.rs @@ -22,7 +22,9 @@ impl super::PCR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr12/mod.rs b/src/porta/pcr12/mod.rs index b16e5be..5a18667 100644 --- a/src/porta/pcr12/mod.rs +++ b/src/porta/pcr12/mod.rs @@ -22,7 +22,9 @@ impl super::PCR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr13/mod.rs b/src/porta/pcr13/mod.rs index 5780ce5..0dc615f 100644 --- a/src/porta/pcr13/mod.rs +++ b/src/porta/pcr13/mod.rs @@ -22,7 +22,9 @@ impl super::PCR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr14/mod.rs b/src/porta/pcr14/mod.rs index 85fddf4..ccdafa6 100644 --- a/src/porta/pcr14/mod.rs +++ b/src/porta/pcr14/mod.rs @@ -22,7 +22,9 @@ impl super::PCR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr15/mod.rs b/src/porta/pcr15/mod.rs index eb78706..f7e2144 100644 --- a/src/porta/pcr15/mod.rs +++ b/src/porta/pcr15/mod.rs @@ -22,7 +22,9 @@ impl super::PCR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr16/mod.rs b/src/porta/pcr16/mod.rs index 539a3ca..45761b1 100644 --- a/src/porta/pcr16/mod.rs +++ b/src/porta/pcr16/mod.rs @@ -22,7 +22,9 @@ impl super::PCR16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr17/mod.rs b/src/porta/pcr17/mod.rs index e17dc3b..8f6705c 100644 --- a/src/porta/pcr17/mod.rs +++ b/src/porta/pcr17/mod.rs @@ -22,7 +22,9 @@ impl super::PCR17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr18/mod.rs b/src/porta/pcr18/mod.rs index 6a7fcc9..7075910 100644 --- a/src/porta/pcr18/mod.rs +++ b/src/porta/pcr18/mod.rs @@ -22,7 +22,9 @@ impl super::PCR18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr19/mod.rs b/src/porta/pcr19/mod.rs index 4bf42ab..9e63ce2 100644 --- a/src/porta/pcr19/mod.rs +++ b/src/porta/pcr19/mod.rs @@ -22,7 +22,9 @@ impl super::PCR19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr2/mod.rs b/src/porta/pcr2/mod.rs index 4b10d77..a0faa9f 100644 --- a/src/porta/pcr2/mod.rs +++ b/src/porta/pcr2/mod.rs @@ -22,7 +22,9 @@ impl super::PCR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr20/mod.rs b/src/porta/pcr20/mod.rs index 1bd7323..a50d2db 100644 --- a/src/porta/pcr20/mod.rs +++ b/src/porta/pcr20/mod.rs @@ -22,7 +22,9 @@ impl super::PCR20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr21/mod.rs b/src/porta/pcr21/mod.rs index 7225469..757c5af 100644 --- a/src/porta/pcr21/mod.rs +++ b/src/porta/pcr21/mod.rs @@ -22,7 +22,9 @@ impl super::PCR21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr22/mod.rs b/src/porta/pcr22/mod.rs index e627370..4604d44 100644 --- a/src/porta/pcr22/mod.rs +++ b/src/porta/pcr22/mod.rs @@ -22,7 +22,9 @@ impl super::PCR22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr23/mod.rs b/src/porta/pcr23/mod.rs index febbc63..9cd6a20 100644 --- a/src/porta/pcr23/mod.rs +++ b/src/porta/pcr23/mod.rs @@ -22,7 +22,9 @@ impl super::PCR23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr24/mod.rs b/src/porta/pcr24/mod.rs index cd996e7..c34c180 100644 --- a/src/porta/pcr24/mod.rs +++ b/src/porta/pcr24/mod.rs @@ -22,7 +22,9 @@ impl super::PCR24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr25/mod.rs b/src/porta/pcr25/mod.rs index 5166cfe..f8bd273 100644 --- a/src/porta/pcr25/mod.rs +++ b/src/porta/pcr25/mod.rs @@ -22,7 +22,9 @@ impl super::PCR25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr26/mod.rs b/src/porta/pcr26/mod.rs index 5214b91..5da8351 100644 --- a/src/porta/pcr26/mod.rs +++ b/src/porta/pcr26/mod.rs @@ -22,7 +22,9 @@ impl super::PCR26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr27/mod.rs b/src/porta/pcr27/mod.rs index b903934..a03d4e4 100644 --- a/src/porta/pcr27/mod.rs +++ b/src/porta/pcr27/mod.rs @@ -22,7 +22,9 @@ impl super::PCR27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr28/mod.rs b/src/porta/pcr28/mod.rs index ca0644f..2cc98e1 100644 --- a/src/porta/pcr28/mod.rs +++ b/src/porta/pcr28/mod.rs @@ -22,7 +22,9 @@ impl super::PCR28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr29/mod.rs b/src/porta/pcr29/mod.rs index 8f37f93..9474292 100644 --- a/src/porta/pcr29/mod.rs +++ b/src/porta/pcr29/mod.rs @@ -22,7 +22,9 @@ impl super::PCR29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr3/mod.rs b/src/porta/pcr3/mod.rs index aa0bb6a..f5fa8b0 100644 --- a/src/porta/pcr3/mod.rs +++ b/src/porta/pcr3/mod.rs @@ -22,7 +22,9 @@ impl super::PCR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr30/mod.rs b/src/porta/pcr30/mod.rs index b97fecd..211b766 100644 --- a/src/porta/pcr30/mod.rs +++ b/src/porta/pcr30/mod.rs @@ -22,7 +22,9 @@ impl super::PCR30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr31/mod.rs b/src/porta/pcr31/mod.rs index 0d571dd..b31068c 100644 --- a/src/porta/pcr31/mod.rs +++ b/src/porta/pcr31/mod.rs @@ -22,7 +22,9 @@ impl super::PCR31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr4/mod.rs b/src/porta/pcr4/mod.rs index 0c2ad52..83e7f6b 100644 --- a/src/porta/pcr4/mod.rs +++ b/src/porta/pcr4/mod.rs @@ -22,7 +22,9 @@ impl super::PCR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr5/mod.rs b/src/porta/pcr5/mod.rs index 101f334..2985ee0 100644 --- a/src/porta/pcr5/mod.rs +++ b/src/porta/pcr5/mod.rs @@ -22,7 +22,9 @@ impl super::PCR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,8 +138,7 @@ impl PER { #[doc = "Possible values of the field `PFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PFER { - #[doc = "Passive input filter is disabled on the corresponding pin."] - _0, + #[doc = "Passive input filter is disabled on the corresponding pin."] _0, #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."] _1, } @@ -184,22 +184,14 @@ impl PFER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +268,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +314,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +408,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +511,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -589,8 +568,7 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `PFE`"] pub enum PFEW { - #[doc = "Passive input filter is disabled on the corresponding pin."] - _0, + #[doc = "Passive input filter is disabled on the corresponding pin."] _0, #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."] _1, } @@ -647,22 +625,14 @@ impl<'a> _PFEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +715,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +772,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +867,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr6/mod.rs b/src/porta/pcr6/mod.rs index 4f75772..1217b1e 100644 --- a/src/porta/pcr6/mod.rs +++ b/src/porta/pcr6/mod.rs @@ -22,7 +22,9 @@ impl super::PCR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr7/mod.rs b/src/porta/pcr7/mod.rs index 2d04668..a31bba1 100644 --- a/src/porta/pcr7/mod.rs +++ b/src/porta/pcr7/mod.rs @@ -22,7 +22,9 @@ impl super::PCR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr8/mod.rs b/src/porta/pcr8/mod.rs index 7e48cee..e7d43ee 100644 --- a/src/porta/pcr8/mod.rs +++ b/src/porta/pcr8/mod.rs @@ -22,7 +22,9 @@ impl super::PCR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porta/pcr9/mod.rs b/src/porta/pcr9/mod.rs index 897f16c..10896f1 100644 --- a/src/porta/pcr9/mod.rs +++ b/src/porta/pcr9/mod.rs @@ -22,7 +22,9 @@ impl super::PCR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/dfcr/mod.rs b/src/portb/dfcr/mod.rs index 4e0e5ae..b77fb96 100644 --- a/src/portb/dfcr/mod.rs +++ b/src/portb/dfcr/mod.rs @@ -22,7 +22,9 @@ impl super::DFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DFCR { #[doc = "Possible values of the field `CS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CSR { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl CSR { } #[doc = "Values that can be written to the field `CS`"] pub enum CSW { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSW { #[allow(missing_docs)] diff --git a/src/portb/dfer/mod.rs b/src/portb/dfer/mod.rs index a80865b..1f1a9d7 100644 --- a/src/portb/dfer/mod.rs +++ b/src/portb/dfer/mod.rs @@ -22,7 +22,9 @@ impl super::DFER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -47,8 +49,7 @@ pub enum DFER { _0, #[doc = "Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl DFER { #[doc = r" Value of the field as raw bits"] diff --git a/src/portb/dfwr/mod.rs b/src/portb/dfwr/mod.rs index bed0a1c..1fb2234 100644 --- a/src/portb/dfwr/mod.rs +++ b/src/portb/dfwr/mod.rs @@ -22,7 +22,9 @@ impl super::DFWR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/portb/gpchr/mod.rs b/src/portb/gpchr/mod.rs index dcd6928..04bdd2a 100644 --- a/src/portb/gpchr/mod.rs +++ b/src/portb/gpchr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portb/gpclr/mod.rs b/src/portb/gpclr/mod.rs index fca1209..e570701 100644 --- a/src/portb/gpclr/mod.rs +++ b/src/portb/gpclr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portb/isfr/mod.rs b/src/portb/isfr/mod.rs index e343374..97dcc02 100644 --- a/src/portb/isfr/mod.rs +++ b/src/portb/isfr/mod.rs @@ -22,7 +22,9 @@ impl super::ISFR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::ISFR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] @@ -83,8 +83,7 @@ impl ISFR { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/mod.rs b/src/portb/mod.rs index 07f3550..9801527 100644 --- a/src/portb/mod.rs +++ b/src/portb/mod.rs @@ -2,84 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Pin Control Register n"] - pub pcr0: PCR0, - #[doc = "0x04 - Pin Control Register n"] - pub pcr1: PCR1, - #[doc = "0x08 - Pin Control Register n"] - pub pcr2: PCR2, - #[doc = "0x0c - Pin Control Register n"] - pub pcr3: PCR3, - #[doc = "0x10 - Pin Control Register n"] - pub pcr4: PCR4, - #[doc = "0x14 - Pin Control Register n"] - pub pcr5: PCR5, - #[doc = "0x18 - Pin Control Register n"] - pub pcr6: PCR6, - #[doc = "0x1c - Pin Control Register n"] - pub pcr7: PCR7, - #[doc = "0x20 - Pin Control Register n"] - pub pcr8: PCR8, - #[doc = "0x24 - Pin Control Register n"] - pub pcr9: PCR9, - #[doc = "0x28 - Pin Control Register n"] - pub pcr10: PCR10, - #[doc = "0x2c - Pin Control Register n"] - pub pcr11: PCR11, - #[doc = "0x30 - Pin Control Register n"] - pub pcr12: PCR12, - #[doc = "0x34 - Pin Control Register n"] - pub pcr13: PCR13, - #[doc = "0x38 - Pin Control Register n"] - pub pcr14: PCR14, - #[doc = "0x3c - Pin Control Register n"] - pub pcr15: PCR15, - #[doc = "0x40 - Pin Control Register n"] - pub pcr16: PCR16, - #[doc = "0x44 - Pin Control Register n"] - pub pcr17: PCR17, - #[doc = "0x48 - Pin Control Register n"] - pub pcr18: PCR18, - #[doc = "0x4c - Pin Control Register n"] - pub pcr19: PCR19, - #[doc = "0x50 - Pin Control Register n"] - pub pcr20: PCR20, - #[doc = "0x54 - Pin Control Register n"] - pub pcr21: PCR21, - #[doc = "0x58 - Pin Control Register n"] - pub pcr22: PCR22, - #[doc = "0x5c - Pin Control Register n"] - pub pcr23: PCR23, - #[doc = "0x60 - Pin Control Register n"] - pub pcr24: PCR24, - #[doc = "0x64 - Pin Control Register n"] - pub pcr25: PCR25, - #[doc = "0x68 - Pin Control Register n"] - pub pcr26: PCR26, - #[doc = "0x6c - Pin Control Register n"] - pub pcr27: PCR27, - #[doc = "0x70 - Pin Control Register n"] - pub pcr28: PCR28, - #[doc = "0x74 - Pin Control Register n"] - pub pcr29: PCR29, - #[doc = "0x78 - Pin Control Register n"] - pub pcr30: PCR30, - #[doc = "0x7c - Pin Control Register n"] - pub pcr31: PCR31, - #[doc = "0x80 - Global Pin Control Low Register"] - pub gpclr: GPCLR, - #[doc = "0x84 - Global Pin Control High Register"] - pub gpchr: GPCHR, + #[doc = "0x00 - Pin Control Register n"] pub pcr0: PCR0, + #[doc = "0x04 - Pin Control Register n"] pub pcr1: PCR1, + #[doc = "0x08 - Pin Control Register n"] pub pcr2: PCR2, + #[doc = "0x0c - Pin Control Register n"] pub pcr3: PCR3, + #[doc = "0x10 - Pin Control Register n"] pub pcr4: PCR4, + #[doc = "0x14 - Pin Control Register n"] pub pcr5: PCR5, + #[doc = "0x18 - Pin Control Register n"] pub pcr6: PCR6, + #[doc = "0x1c - Pin Control Register n"] pub pcr7: PCR7, + #[doc = "0x20 - Pin Control Register n"] pub pcr8: PCR8, + #[doc = "0x24 - Pin Control Register n"] pub pcr9: PCR9, + #[doc = "0x28 - Pin Control Register n"] pub pcr10: PCR10, + #[doc = "0x2c - Pin Control Register n"] pub pcr11: PCR11, + #[doc = "0x30 - Pin Control Register n"] pub pcr12: PCR12, + #[doc = "0x34 - Pin Control Register n"] pub pcr13: PCR13, + #[doc = "0x38 - Pin Control Register n"] pub pcr14: PCR14, + #[doc = "0x3c - Pin Control Register n"] pub pcr15: PCR15, + #[doc = "0x40 - Pin Control Register n"] pub pcr16: PCR16, + #[doc = "0x44 - Pin Control Register n"] pub pcr17: PCR17, + #[doc = "0x48 - Pin Control Register n"] pub pcr18: PCR18, + #[doc = "0x4c - Pin Control Register n"] pub pcr19: PCR19, + #[doc = "0x50 - Pin Control Register n"] pub pcr20: PCR20, + #[doc = "0x54 - Pin Control Register n"] pub pcr21: PCR21, + #[doc = "0x58 - Pin Control Register n"] pub pcr22: PCR22, + #[doc = "0x5c - Pin Control Register n"] pub pcr23: PCR23, + #[doc = "0x60 - Pin Control Register n"] pub pcr24: PCR24, + #[doc = "0x64 - Pin Control Register n"] pub pcr25: PCR25, + #[doc = "0x68 - Pin Control Register n"] pub pcr26: PCR26, + #[doc = "0x6c - Pin Control Register n"] pub pcr27: PCR27, + #[doc = "0x70 - Pin Control Register n"] pub pcr28: PCR28, + #[doc = "0x74 - Pin Control Register n"] pub pcr29: PCR29, + #[doc = "0x78 - Pin Control Register n"] pub pcr30: PCR30, + #[doc = "0x7c - Pin Control Register n"] pub pcr31: PCR31, + #[doc = "0x80 - Global Pin Control Low Register"] pub gpclr: GPCLR, + #[doc = "0x84 - Global Pin Control High Register"] pub gpchr: GPCHR, _reserved0: [u8; 24usize], - #[doc = "0xa0 - Interrupt Status Flag Register"] - pub isfr: ISFR, + #[doc = "0xa0 - Interrupt Status Flag Register"] pub isfr: ISFR, _reserved1: [u8; 28usize], - #[doc = "0xc0 - Digital Filter Enable Register"] - pub dfer: DFER, - #[doc = "0xc4 - Digital Filter Clock Register"] - pub dfcr: DFCR, - #[doc = "0xc8 - Digital Filter Width Register"] - pub dfwr: DFWR, + #[doc = "0xc0 - Digital Filter Enable Register"] pub dfer: DFER, + #[doc = "0xc4 - Digital Filter Clock Register"] pub dfcr: DFCR, + #[doc = "0xc8 - Digital Filter Width Register"] pub dfwr: DFWR, } #[doc = "Pin Control Register n"] pub struct PCR0 { diff --git a/src/portb/pcr0/mod.rs b/src/portb/pcr0/mod.rs index 53f3ef7..0f6ced6 100644 --- a/src/portb/pcr0/mod.rs +++ b/src/portb/pcr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr1/mod.rs b/src/portb/pcr1/mod.rs index d76fcca..078273a 100644 --- a/src/portb/pcr1/mod.rs +++ b/src/portb/pcr1/mod.rs @@ -22,7 +22,9 @@ impl super::PCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr10/mod.rs b/src/portb/pcr10/mod.rs index 948f328..28aeb16 100644 --- a/src/portb/pcr10/mod.rs +++ b/src/portb/pcr10/mod.rs @@ -22,7 +22,9 @@ impl super::PCR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr11/mod.rs b/src/portb/pcr11/mod.rs index 9eec901..3b4f036 100644 --- a/src/portb/pcr11/mod.rs +++ b/src/portb/pcr11/mod.rs @@ -22,7 +22,9 @@ impl super::PCR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr12/mod.rs b/src/portb/pcr12/mod.rs index b16e5be..5a18667 100644 --- a/src/portb/pcr12/mod.rs +++ b/src/portb/pcr12/mod.rs @@ -22,7 +22,9 @@ impl super::PCR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr13/mod.rs b/src/portb/pcr13/mod.rs index 5780ce5..0dc615f 100644 --- a/src/portb/pcr13/mod.rs +++ b/src/portb/pcr13/mod.rs @@ -22,7 +22,9 @@ impl super::PCR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr14/mod.rs b/src/portb/pcr14/mod.rs index 85fddf4..ccdafa6 100644 --- a/src/portb/pcr14/mod.rs +++ b/src/portb/pcr14/mod.rs @@ -22,7 +22,9 @@ impl super::PCR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr15/mod.rs b/src/portb/pcr15/mod.rs index eb78706..f7e2144 100644 --- a/src/portb/pcr15/mod.rs +++ b/src/portb/pcr15/mod.rs @@ -22,7 +22,9 @@ impl super::PCR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr16/mod.rs b/src/portb/pcr16/mod.rs index 539a3ca..45761b1 100644 --- a/src/portb/pcr16/mod.rs +++ b/src/portb/pcr16/mod.rs @@ -22,7 +22,9 @@ impl super::PCR16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr17/mod.rs b/src/portb/pcr17/mod.rs index e17dc3b..8f6705c 100644 --- a/src/portb/pcr17/mod.rs +++ b/src/portb/pcr17/mod.rs @@ -22,7 +22,9 @@ impl super::PCR17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr18/mod.rs b/src/portb/pcr18/mod.rs index 6a7fcc9..7075910 100644 --- a/src/portb/pcr18/mod.rs +++ b/src/portb/pcr18/mod.rs @@ -22,7 +22,9 @@ impl super::PCR18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr19/mod.rs b/src/portb/pcr19/mod.rs index 4bf42ab..9e63ce2 100644 --- a/src/portb/pcr19/mod.rs +++ b/src/portb/pcr19/mod.rs @@ -22,7 +22,9 @@ impl super::PCR19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr2/mod.rs b/src/portb/pcr2/mod.rs index 8743cfc..5f6321c 100644 --- a/src/portb/pcr2/mod.rs +++ b/src/portb/pcr2/mod.rs @@ -22,7 +22,9 @@ impl super::PCR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr20/mod.rs b/src/portb/pcr20/mod.rs index 1bd7323..a50d2db 100644 --- a/src/portb/pcr20/mod.rs +++ b/src/portb/pcr20/mod.rs @@ -22,7 +22,9 @@ impl super::PCR20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr21/mod.rs b/src/portb/pcr21/mod.rs index 7225469..757c5af 100644 --- a/src/portb/pcr21/mod.rs +++ b/src/portb/pcr21/mod.rs @@ -22,7 +22,9 @@ impl super::PCR21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr22/mod.rs b/src/portb/pcr22/mod.rs index e627370..4604d44 100644 --- a/src/portb/pcr22/mod.rs +++ b/src/portb/pcr22/mod.rs @@ -22,7 +22,9 @@ impl super::PCR22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr23/mod.rs b/src/portb/pcr23/mod.rs index febbc63..9cd6a20 100644 --- a/src/portb/pcr23/mod.rs +++ b/src/portb/pcr23/mod.rs @@ -22,7 +22,9 @@ impl super::PCR23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr24/mod.rs b/src/portb/pcr24/mod.rs index cd996e7..c34c180 100644 --- a/src/portb/pcr24/mod.rs +++ b/src/portb/pcr24/mod.rs @@ -22,7 +22,9 @@ impl super::PCR24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr25/mod.rs b/src/portb/pcr25/mod.rs index 5166cfe..f8bd273 100644 --- a/src/portb/pcr25/mod.rs +++ b/src/portb/pcr25/mod.rs @@ -22,7 +22,9 @@ impl super::PCR25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr26/mod.rs b/src/portb/pcr26/mod.rs index 5214b91..5da8351 100644 --- a/src/portb/pcr26/mod.rs +++ b/src/portb/pcr26/mod.rs @@ -22,7 +22,9 @@ impl super::PCR26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr27/mod.rs b/src/portb/pcr27/mod.rs index b903934..a03d4e4 100644 --- a/src/portb/pcr27/mod.rs +++ b/src/portb/pcr27/mod.rs @@ -22,7 +22,9 @@ impl super::PCR27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr28/mod.rs b/src/portb/pcr28/mod.rs index ca0644f..2cc98e1 100644 --- a/src/portb/pcr28/mod.rs +++ b/src/portb/pcr28/mod.rs @@ -22,7 +22,9 @@ impl super::PCR28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr29/mod.rs b/src/portb/pcr29/mod.rs index 8f37f93..9474292 100644 --- a/src/portb/pcr29/mod.rs +++ b/src/portb/pcr29/mod.rs @@ -22,7 +22,9 @@ impl super::PCR29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr3/mod.rs b/src/portb/pcr3/mod.rs index 35283c4..189aabd 100644 --- a/src/portb/pcr3/mod.rs +++ b/src/portb/pcr3/mod.rs @@ -22,7 +22,9 @@ impl super::PCR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr30/mod.rs b/src/portb/pcr30/mod.rs index b97fecd..211b766 100644 --- a/src/portb/pcr30/mod.rs +++ b/src/portb/pcr30/mod.rs @@ -22,7 +22,9 @@ impl super::PCR30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr31/mod.rs b/src/portb/pcr31/mod.rs index 0d571dd..b31068c 100644 --- a/src/portb/pcr31/mod.rs +++ b/src/portb/pcr31/mod.rs @@ -22,7 +22,9 @@ impl super::PCR31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr4/mod.rs b/src/portb/pcr4/mod.rs index fe3703f..2acee03 100644 --- a/src/portb/pcr4/mod.rs +++ b/src/portb/pcr4/mod.rs @@ -22,7 +22,9 @@ impl super::PCR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr5/mod.rs b/src/portb/pcr5/mod.rs index e13d19b..4dacf4a 100644 --- a/src/portb/pcr5/mod.rs +++ b/src/portb/pcr5/mod.rs @@ -22,7 +22,9 @@ impl super::PCR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr6/mod.rs b/src/portb/pcr6/mod.rs index 4f75772..1217b1e 100644 --- a/src/portb/pcr6/mod.rs +++ b/src/portb/pcr6/mod.rs @@ -22,7 +22,9 @@ impl super::PCR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr7/mod.rs b/src/portb/pcr7/mod.rs index 2d04668..a31bba1 100644 --- a/src/portb/pcr7/mod.rs +++ b/src/portb/pcr7/mod.rs @@ -22,7 +22,9 @@ impl super::PCR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr8/mod.rs b/src/portb/pcr8/mod.rs index 7e48cee..e7d43ee 100644 --- a/src/portb/pcr8/mod.rs +++ b/src/portb/pcr8/mod.rs @@ -22,7 +22,9 @@ impl super::PCR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portb/pcr9/mod.rs b/src/portb/pcr9/mod.rs index 897f16c..10896f1 100644 --- a/src/portb/pcr9/mod.rs +++ b/src/portb/pcr9/mod.rs @@ -22,7 +22,9 @@ impl super::PCR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/dfcr/mod.rs b/src/portc/dfcr/mod.rs index 4e0e5ae..b77fb96 100644 --- a/src/portc/dfcr/mod.rs +++ b/src/portc/dfcr/mod.rs @@ -22,7 +22,9 @@ impl super::DFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DFCR { #[doc = "Possible values of the field `CS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CSR { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl CSR { } #[doc = "Values that can be written to the field `CS`"] pub enum CSW { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSW { #[allow(missing_docs)] diff --git a/src/portc/dfer/mod.rs b/src/portc/dfer/mod.rs index a80865b..1f1a9d7 100644 --- a/src/portc/dfer/mod.rs +++ b/src/portc/dfer/mod.rs @@ -22,7 +22,9 @@ impl super::DFER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -47,8 +49,7 @@ pub enum DFER { _0, #[doc = "Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl DFER { #[doc = r" Value of the field as raw bits"] diff --git a/src/portc/dfwr/mod.rs b/src/portc/dfwr/mod.rs index bed0a1c..1fb2234 100644 --- a/src/portc/dfwr/mod.rs +++ b/src/portc/dfwr/mod.rs @@ -22,7 +22,9 @@ impl super::DFWR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/portc/gpchr/mod.rs b/src/portc/gpchr/mod.rs index dcd6928..04bdd2a 100644 --- a/src/portc/gpchr/mod.rs +++ b/src/portc/gpchr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portc/gpclr/mod.rs b/src/portc/gpclr/mod.rs index fca1209..e570701 100644 --- a/src/portc/gpclr/mod.rs +++ b/src/portc/gpclr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portc/isfr/mod.rs b/src/portc/isfr/mod.rs index e343374..97dcc02 100644 --- a/src/portc/isfr/mod.rs +++ b/src/portc/isfr/mod.rs @@ -22,7 +22,9 @@ impl super::ISFR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::ISFR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] @@ -83,8 +83,7 @@ impl ISFR { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/mod.rs b/src/portc/mod.rs index 07f3550..9801527 100644 --- a/src/portc/mod.rs +++ b/src/portc/mod.rs @@ -2,84 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Pin Control Register n"] - pub pcr0: PCR0, - #[doc = "0x04 - Pin Control Register n"] - pub pcr1: PCR1, - #[doc = "0x08 - Pin Control Register n"] - pub pcr2: PCR2, - #[doc = "0x0c - Pin Control Register n"] - pub pcr3: PCR3, - #[doc = "0x10 - Pin Control Register n"] - pub pcr4: PCR4, - #[doc = "0x14 - Pin Control Register n"] - pub pcr5: PCR5, - #[doc = "0x18 - Pin Control Register n"] - pub pcr6: PCR6, - #[doc = "0x1c - Pin Control Register n"] - pub pcr7: PCR7, - #[doc = "0x20 - Pin Control Register n"] - pub pcr8: PCR8, - #[doc = "0x24 - Pin Control Register n"] - pub pcr9: PCR9, - #[doc = "0x28 - Pin Control Register n"] - pub pcr10: PCR10, - #[doc = "0x2c - Pin Control Register n"] - pub pcr11: PCR11, - #[doc = "0x30 - Pin Control Register n"] - pub pcr12: PCR12, - #[doc = "0x34 - Pin Control Register n"] - pub pcr13: PCR13, - #[doc = "0x38 - Pin Control Register n"] - pub pcr14: PCR14, - #[doc = "0x3c - Pin Control Register n"] - pub pcr15: PCR15, - #[doc = "0x40 - Pin Control Register n"] - pub pcr16: PCR16, - #[doc = "0x44 - Pin Control Register n"] - pub pcr17: PCR17, - #[doc = "0x48 - Pin Control Register n"] - pub pcr18: PCR18, - #[doc = "0x4c - Pin Control Register n"] - pub pcr19: PCR19, - #[doc = "0x50 - Pin Control Register n"] - pub pcr20: PCR20, - #[doc = "0x54 - Pin Control Register n"] - pub pcr21: PCR21, - #[doc = "0x58 - Pin Control Register n"] - pub pcr22: PCR22, - #[doc = "0x5c - Pin Control Register n"] - pub pcr23: PCR23, - #[doc = "0x60 - Pin Control Register n"] - pub pcr24: PCR24, - #[doc = "0x64 - Pin Control Register n"] - pub pcr25: PCR25, - #[doc = "0x68 - Pin Control Register n"] - pub pcr26: PCR26, - #[doc = "0x6c - Pin Control Register n"] - pub pcr27: PCR27, - #[doc = "0x70 - Pin Control Register n"] - pub pcr28: PCR28, - #[doc = "0x74 - Pin Control Register n"] - pub pcr29: PCR29, - #[doc = "0x78 - Pin Control Register n"] - pub pcr30: PCR30, - #[doc = "0x7c - Pin Control Register n"] - pub pcr31: PCR31, - #[doc = "0x80 - Global Pin Control Low Register"] - pub gpclr: GPCLR, - #[doc = "0x84 - Global Pin Control High Register"] - pub gpchr: GPCHR, + #[doc = "0x00 - Pin Control Register n"] pub pcr0: PCR0, + #[doc = "0x04 - Pin Control Register n"] pub pcr1: PCR1, + #[doc = "0x08 - Pin Control Register n"] pub pcr2: PCR2, + #[doc = "0x0c - Pin Control Register n"] pub pcr3: PCR3, + #[doc = "0x10 - Pin Control Register n"] pub pcr4: PCR4, + #[doc = "0x14 - Pin Control Register n"] pub pcr5: PCR5, + #[doc = "0x18 - Pin Control Register n"] pub pcr6: PCR6, + #[doc = "0x1c - Pin Control Register n"] pub pcr7: PCR7, + #[doc = "0x20 - Pin Control Register n"] pub pcr8: PCR8, + #[doc = "0x24 - Pin Control Register n"] pub pcr9: PCR9, + #[doc = "0x28 - Pin Control Register n"] pub pcr10: PCR10, + #[doc = "0x2c - Pin Control Register n"] pub pcr11: PCR11, + #[doc = "0x30 - Pin Control Register n"] pub pcr12: PCR12, + #[doc = "0x34 - Pin Control Register n"] pub pcr13: PCR13, + #[doc = "0x38 - Pin Control Register n"] pub pcr14: PCR14, + #[doc = "0x3c - Pin Control Register n"] pub pcr15: PCR15, + #[doc = "0x40 - Pin Control Register n"] pub pcr16: PCR16, + #[doc = "0x44 - Pin Control Register n"] pub pcr17: PCR17, + #[doc = "0x48 - Pin Control Register n"] pub pcr18: PCR18, + #[doc = "0x4c - Pin Control Register n"] pub pcr19: PCR19, + #[doc = "0x50 - Pin Control Register n"] pub pcr20: PCR20, + #[doc = "0x54 - Pin Control Register n"] pub pcr21: PCR21, + #[doc = "0x58 - Pin Control Register n"] pub pcr22: PCR22, + #[doc = "0x5c - Pin Control Register n"] pub pcr23: PCR23, + #[doc = "0x60 - Pin Control Register n"] pub pcr24: PCR24, + #[doc = "0x64 - Pin Control Register n"] pub pcr25: PCR25, + #[doc = "0x68 - Pin Control Register n"] pub pcr26: PCR26, + #[doc = "0x6c - Pin Control Register n"] pub pcr27: PCR27, + #[doc = "0x70 - Pin Control Register n"] pub pcr28: PCR28, + #[doc = "0x74 - Pin Control Register n"] pub pcr29: PCR29, + #[doc = "0x78 - Pin Control Register n"] pub pcr30: PCR30, + #[doc = "0x7c - Pin Control Register n"] pub pcr31: PCR31, + #[doc = "0x80 - Global Pin Control Low Register"] pub gpclr: GPCLR, + #[doc = "0x84 - Global Pin Control High Register"] pub gpchr: GPCHR, _reserved0: [u8; 24usize], - #[doc = "0xa0 - Interrupt Status Flag Register"] - pub isfr: ISFR, + #[doc = "0xa0 - Interrupt Status Flag Register"] pub isfr: ISFR, _reserved1: [u8; 28usize], - #[doc = "0xc0 - Digital Filter Enable Register"] - pub dfer: DFER, - #[doc = "0xc4 - Digital Filter Clock Register"] - pub dfcr: DFCR, - #[doc = "0xc8 - Digital Filter Width Register"] - pub dfwr: DFWR, + #[doc = "0xc0 - Digital Filter Enable Register"] pub dfer: DFER, + #[doc = "0xc4 - Digital Filter Clock Register"] pub dfcr: DFCR, + #[doc = "0xc8 - Digital Filter Width Register"] pub dfwr: DFWR, } #[doc = "Pin Control Register n"] pub struct PCR0 { diff --git a/src/portc/pcr0/mod.rs b/src/portc/pcr0/mod.rs index 53f3ef7..0f6ced6 100644 --- a/src/portc/pcr0/mod.rs +++ b/src/portc/pcr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr1/mod.rs b/src/portc/pcr1/mod.rs index d76fcca..078273a 100644 --- a/src/portc/pcr1/mod.rs +++ b/src/portc/pcr1/mod.rs @@ -22,7 +22,9 @@ impl super::PCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr10/mod.rs b/src/portc/pcr10/mod.rs index 948f328..28aeb16 100644 --- a/src/portc/pcr10/mod.rs +++ b/src/portc/pcr10/mod.rs @@ -22,7 +22,9 @@ impl super::PCR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr11/mod.rs b/src/portc/pcr11/mod.rs index 9eec901..3b4f036 100644 --- a/src/portc/pcr11/mod.rs +++ b/src/portc/pcr11/mod.rs @@ -22,7 +22,9 @@ impl super::PCR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr12/mod.rs b/src/portc/pcr12/mod.rs index b16e5be..5a18667 100644 --- a/src/portc/pcr12/mod.rs +++ b/src/portc/pcr12/mod.rs @@ -22,7 +22,9 @@ impl super::PCR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr13/mod.rs b/src/portc/pcr13/mod.rs index 5780ce5..0dc615f 100644 --- a/src/portc/pcr13/mod.rs +++ b/src/portc/pcr13/mod.rs @@ -22,7 +22,9 @@ impl super::PCR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr14/mod.rs b/src/portc/pcr14/mod.rs index 85fddf4..ccdafa6 100644 --- a/src/portc/pcr14/mod.rs +++ b/src/portc/pcr14/mod.rs @@ -22,7 +22,9 @@ impl super::PCR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr15/mod.rs b/src/portc/pcr15/mod.rs index eb78706..f7e2144 100644 --- a/src/portc/pcr15/mod.rs +++ b/src/portc/pcr15/mod.rs @@ -22,7 +22,9 @@ impl super::PCR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr16/mod.rs b/src/portc/pcr16/mod.rs index 539a3ca..45761b1 100644 --- a/src/portc/pcr16/mod.rs +++ b/src/portc/pcr16/mod.rs @@ -22,7 +22,9 @@ impl super::PCR16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr17/mod.rs b/src/portc/pcr17/mod.rs index e17dc3b..8f6705c 100644 --- a/src/portc/pcr17/mod.rs +++ b/src/portc/pcr17/mod.rs @@ -22,7 +22,9 @@ impl super::PCR17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr18/mod.rs b/src/portc/pcr18/mod.rs index 6a7fcc9..7075910 100644 --- a/src/portc/pcr18/mod.rs +++ b/src/portc/pcr18/mod.rs @@ -22,7 +22,9 @@ impl super::PCR18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr19/mod.rs b/src/portc/pcr19/mod.rs index 4bf42ab..9e63ce2 100644 --- a/src/portc/pcr19/mod.rs +++ b/src/portc/pcr19/mod.rs @@ -22,7 +22,9 @@ impl super::PCR19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr2/mod.rs b/src/portc/pcr2/mod.rs index 8743cfc..5f6321c 100644 --- a/src/portc/pcr2/mod.rs +++ b/src/portc/pcr2/mod.rs @@ -22,7 +22,9 @@ impl super::PCR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr20/mod.rs b/src/portc/pcr20/mod.rs index 1bd7323..a50d2db 100644 --- a/src/portc/pcr20/mod.rs +++ b/src/portc/pcr20/mod.rs @@ -22,7 +22,9 @@ impl super::PCR20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr21/mod.rs b/src/portc/pcr21/mod.rs index 7225469..757c5af 100644 --- a/src/portc/pcr21/mod.rs +++ b/src/portc/pcr21/mod.rs @@ -22,7 +22,9 @@ impl super::PCR21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr22/mod.rs b/src/portc/pcr22/mod.rs index e627370..4604d44 100644 --- a/src/portc/pcr22/mod.rs +++ b/src/portc/pcr22/mod.rs @@ -22,7 +22,9 @@ impl super::PCR22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr23/mod.rs b/src/portc/pcr23/mod.rs index febbc63..9cd6a20 100644 --- a/src/portc/pcr23/mod.rs +++ b/src/portc/pcr23/mod.rs @@ -22,7 +22,9 @@ impl super::PCR23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr24/mod.rs b/src/portc/pcr24/mod.rs index cd996e7..c34c180 100644 --- a/src/portc/pcr24/mod.rs +++ b/src/portc/pcr24/mod.rs @@ -22,7 +22,9 @@ impl super::PCR24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr25/mod.rs b/src/portc/pcr25/mod.rs index 5166cfe..f8bd273 100644 --- a/src/portc/pcr25/mod.rs +++ b/src/portc/pcr25/mod.rs @@ -22,7 +22,9 @@ impl super::PCR25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr26/mod.rs b/src/portc/pcr26/mod.rs index 5214b91..5da8351 100644 --- a/src/portc/pcr26/mod.rs +++ b/src/portc/pcr26/mod.rs @@ -22,7 +22,9 @@ impl super::PCR26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr27/mod.rs b/src/portc/pcr27/mod.rs index b903934..a03d4e4 100644 --- a/src/portc/pcr27/mod.rs +++ b/src/portc/pcr27/mod.rs @@ -22,7 +22,9 @@ impl super::PCR27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr28/mod.rs b/src/portc/pcr28/mod.rs index ca0644f..2cc98e1 100644 --- a/src/portc/pcr28/mod.rs +++ b/src/portc/pcr28/mod.rs @@ -22,7 +22,9 @@ impl super::PCR28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr29/mod.rs b/src/portc/pcr29/mod.rs index 8f37f93..9474292 100644 --- a/src/portc/pcr29/mod.rs +++ b/src/portc/pcr29/mod.rs @@ -22,7 +22,9 @@ impl super::PCR29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr3/mod.rs b/src/portc/pcr3/mod.rs index 35283c4..189aabd 100644 --- a/src/portc/pcr3/mod.rs +++ b/src/portc/pcr3/mod.rs @@ -22,7 +22,9 @@ impl super::PCR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr30/mod.rs b/src/portc/pcr30/mod.rs index b97fecd..211b766 100644 --- a/src/portc/pcr30/mod.rs +++ b/src/portc/pcr30/mod.rs @@ -22,7 +22,9 @@ impl super::PCR30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr31/mod.rs b/src/portc/pcr31/mod.rs index 0d571dd..b31068c 100644 --- a/src/portc/pcr31/mod.rs +++ b/src/portc/pcr31/mod.rs @@ -22,7 +22,9 @@ impl super::PCR31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr4/mod.rs b/src/portc/pcr4/mod.rs index 39e8120..e3e80a0 100644 --- a/src/portc/pcr4/mod.rs +++ b/src/portc/pcr4/mod.rs @@ -22,7 +22,9 @@ impl super::PCR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr5/mod.rs b/src/portc/pcr5/mod.rs index cdfceb0..a87c177 100644 --- a/src/portc/pcr5/mod.rs +++ b/src/portc/pcr5/mod.rs @@ -22,7 +22,9 @@ impl super::PCR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr6/mod.rs b/src/portc/pcr6/mod.rs index 4f75772..1217b1e 100644 --- a/src/portc/pcr6/mod.rs +++ b/src/portc/pcr6/mod.rs @@ -22,7 +22,9 @@ impl super::PCR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr7/mod.rs b/src/portc/pcr7/mod.rs index 2d04668..a31bba1 100644 --- a/src/portc/pcr7/mod.rs +++ b/src/portc/pcr7/mod.rs @@ -22,7 +22,9 @@ impl super::PCR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr8/mod.rs b/src/portc/pcr8/mod.rs index 7e48cee..e7d43ee 100644 --- a/src/portc/pcr8/mod.rs +++ b/src/portc/pcr8/mod.rs @@ -22,7 +22,9 @@ impl super::PCR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portc/pcr9/mod.rs b/src/portc/pcr9/mod.rs index 897f16c..10896f1 100644 --- a/src/portc/pcr9/mod.rs +++ b/src/portc/pcr9/mod.rs @@ -22,7 +22,9 @@ impl super::PCR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/dfcr/mod.rs b/src/portd/dfcr/mod.rs index 4e0e5ae..b77fb96 100644 --- a/src/portd/dfcr/mod.rs +++ b/src/portd/dfcr/mod.rs @@ -22,7 +22,9 @@ impl super::DFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DFCR { #[doc = "Possible values of the field `CS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CSR { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl CSR { } #[doc = "Values that can be written to the field `CS`"] pub enum CSW { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSW { #[allow(missing_docs)] diff --git a/src/portd/dfer/mod.rs b/src/portd/dfer/mod.rs index a80865b..1f1a9d7 100644 --- a/src/portd/dfer/mod.rs +++ b/src/portd/dfer/mod.rs @@ -22,7 +22,9 @@ impl super::DFER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -47,8 +49,7 @@ pub enum DFER { _0, #[doc = "Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl DFER { #[doc = r" Value of the field as raw bits"] diff --git a/src/portd/dfwr/mod.rs b/src/portd/dfwr/mod.rs index bed0a1c..1fb2234 100644 --- a/src/portd/dfwr/mod.rs +++ b/src/portd/dfwr/mod.rs @@ -22,7 +22,9 @@ impl super::DFWR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/portd/gpchr/mod.rs b/src/portd/gpchr/mod.rs index dcd6928..04bdd2a 100644 --- a/src/portd/gpchr/mod.rs +++ b/src/portd/gpchr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portd/gpclr/mod.rs b/src/portd/gpclr/mod.rs index fca1209..e570701 100644 --- a/src/portd/gpclr/mod.rs +++ b/src/portd/gpclr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/portd/isfr/mod.rs b/src/portd/isfr/mod.rs index e343374..97dcc02 100644 --- a/src/portd/isfr/mod.rs +++ b/src/portd/isfr/mod.rs @@ -22,7 +22,9 @@ impl super::ISFR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::ISFR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] @@ -83,8 +83,7 @@ impl ISFR { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/mod.rs b/src/portd/mod.rs index 07f3550..9801527 100644 --- a/src/portd/mod.rs +++ b/src/portd/mod.rs @@ -2,84 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Pin Control Register n"] - pub pcr0: PCR0, - #[doc = "0x04 - Pin Control Register n"] - pub pcr1: PCR1, - #[doc = "0x08 - Pin Control Register n"] - pub pcr2: PCR2, - #[doc = "0x0c - Pin Control Register n"] - pub pcr3: PCR3, - #[doc = "0x10 - Pin Control Register n"] - pub pcr4: PCR4, - #[doc = "0x14 - Pin Control Register n"] - pub pcr5: PCR5, - #[doc = "0x18 - Pin Control Register n"] - pub pcr6: PCR6, - #[doc = "0x1c - Pin Control Register n"] - pub pcr7: PCR7, - #[doc = "0x20 - Pin Control Register n"] - pub pcr8: PCR8, - #[doc = "0x24 - Pin Control Register n"] - pub pcr9: PCR9, - #[doc = "0x28 - Pin Control Register n"] - pub pcr10: PCR10, - #[doc = "0x2c - Pin Control Register n"] - pub pcr11: PCR11, - #[doc = "0x30 - Pin Control Register n"] - pub pcr12: PCR12, - #[doc = "0x34 - Pin Control Register n"] - pub pcr13: PCR13, - #[doc = "0x38 - Pin Control Register n"] - pub pcr14: PCR14, - #[doc = "0x3c - Pin Control Register n"] - pub pcr15: PCR15, - #[doc = "0x40 - Pin Control Register n"] - pub pcr16: PCR16, - #[doc = "0x44 - Pin Control Register n"] - pub pcr17: PCR17, - #[doc = "0x48 - Pin Control Register n"] - pub pcr18: PCR18, - #[doc = "0x4c - Pin Control Register n"] - pub pcr19: PCR19, - #[doc = "0x50 - Pin Control Register n"] - pub pcr20: PCR20, - #[doc = "0x54 - Pin Control Register n"] - pub pcr21: PCR21, - #[doc = "0x58 - Pin Control Register n"] - pub pcr22: PCR22, - #[doc = "0x5c - Pin Control Register n"] - pub pcr23: PCR23, - #[doc = "0x60 - Pin Control Register n"] - pub pcr24: PCR24, - #[doc = "0x64 - Pin Control Register n"] - pub pcr25: PCR25, - #[doc = "0x68 - Pin Control Register n"] - pub pcr26: PCR26, - #[doc = "0x6c - Pin Control Register n"] - pub pcr27: PCR27, - #[doc = "0x70 - Pin Control Register n"] - pub pcr28: PCR28, - #[doc = "0x74 - Pin Control Register n"] - pub pcr29: PCR29, - #[doc = "0x78 - Pin Control Register n"] - pub pcr30: PCR30, - #[doc = "0x7c - Pin Control Register n"] - pub pcr31: PCR31, - #[doc = "0x80 - Global Pin Control Low Register"] - pub gpclr: GPCLR, - #[doc = "0x84 - Global Pin Control High Register"] - pub gpchr: GPCHR, + #[doc = "0x00 - Pin Control Register n"] pub pcr0: PCR0, + #[doc = "0x04 - Pin Control Register n"] pub pcr1: PCR1, + #[doc = "0x08 - Pin Control Register n"] pub pcr2: PCR2, + #[doc = "0x0c - Pin Control Register n"] pub pcr3: PCR3, + #[doc = "0x10 - Pin Control Register n"] pub pcr4: PCR4, + #[doc = "0x14 - Pin Control Register n"] pub pcr5: PCR5, + #[doc = "0x18 - Pin Control Register n"] pub pcr6: PCR6, + #[doc = "0x1c - Pin Control Register n"] pub pcr7: PCR7, + #[doc = "0x20 - Pin Control Register n"] pub pcr8: PCR8, + #[doc = "0x24 - Pin Control Register n"] pub pcr9: PCR9, + #[doc = "0x28 - Pin Control Register n"] pub pcr10: PCR10, + #[doc = "0x2c - Pin Control Register n"] pub pcr11: PCR11, + #[doc = "0x30 - Pin Control Register n"] pub pcr12: PCR12, + #[doc = "0x34 - Pin Control Register n"] pub pcr13: PCR13, + #[doc = "0x38 - Pin Control Register n"] pub pcr14: PCR14, + #[doc = "0x3c - Pin Control Register n"] pub pcr15: PCR15, + #[doc = "0x40 - Pin Control Register n"] pub pcr16: PCR16, + #[doc = "0x44 - Pin Control Register n"] pub pcr17: PCR17, + #[doc = "0x48 - Pin Control Register n"] pub pcr18: PCR18, + #[doc = "0x4c - Pin Control Register n"] pub pcr19: PCR19, + #[doc = "0x50 - Pin Control Register n"] pub pcr20: PCR20, + #[doc = "0x54 - Pin Control Register n"] pub pcr21: PCR21, + #[doc = "0x58 - Pin Control Register n"] pub pcr22: PCR22, + #[doc = "0x5c - Pin Control Register n"] pub pcr23: PCR23, + #[doc = "0x60 - Pin Control Register n"] pub pcr24: PCR24, + #[doc = "0x64 - Pin Control Register n"] pub pcr25: PCR25, + #[doc = "0x68 - Pin Control Register n"] pub pcr26: PCR26, + #[doc = "0x6c - Pin Control Register n"] pub pcr27: PCR27, + #[doc = "0x70 - Pin Control Register n"] pub pcr28: PCR28, + #[doc = "0x74 - Pin Control Register n"] pub pcr29: PCR29, + #[doc = "0x78 - Pin Control Register n"] pub pcr30: PCR30, + #[doc = "0x7c - Pin Control Register n"] pub pcr31: PCR31, + #[doc = "0x80 - Global Pin Control Low Register"] pub gpclr: GPCLR, + #[doc = "0x84 - Global Pin Control High Register"] pub gpchr: GPCHR, _reserved0: [u8; 24usize], - #[doc = "0xa0 - Interrupt Status Flag Register"] - pub isfr: ISFR, + #[doc = "0xa0 - Interrupt Status Flag Register"] pub isfr: ISFR, _reserved1: [u8; 28usize], - #[doc = "0xc0 - Digital Filter Enable Register"] - pub dfer: DFER, - #[doc = "0xc4 - Digital Filter Clock Register"] - pub dfcr: DFCR, - #[doc = "0xc8 - Digital Filter Width Register"] - pub dfwr: DFWR, + #[doc = "0xc0 - Digital Filter Enable Register"] pub dfer: DFER, + #[doc = "0xc4 - Digital Filter Clock Register"] pub dfcr: DFCR, + #[doc = "0xc8 - Digital Filter Width Register"] pub dfwr: DFWR, } #[doc = "Pin Control Register n"] pub struct PCR0 { diff --git a/src/portd/pcr0/mod.rs b/src/portd/pcr0/mod.rs index 0939dbe..5bd2a00 100644 --- a/src/portd/pcr0/mod.rs +++ b/src/portd/pcr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr1/mod.rs b/src/portd/pcr1/mod.rs index 1e49167..a752aed 100644 --- a/src/portd/pcr1/mod.rs +++ b/src/portd/pcr1/mod.rs @@ -22,7 +22,9 @@ impl super::PCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr10/mod.rs b/src/portd/pcr10/mod.rs index 948f328..28aeb16 100644 --- a/src/portd/pcr10/mod.rs +++ b/src/portd/pcr10/mod.rs @@ -22,7 +22,9 @@ impl super::PCR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr11/mod.rs b/src/portd/pcr11/mod.rs index 9eec901..3b4f036 100644 --- a/src/portd/pcr11/mod.rs +++ b/src/portd/pcr11/mod.rs @@ -22,7 +22,9 @@ impl super::PCR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr12/mod.rs b/src/portd/pcr12/mod.rs index b16e5be..5a18667 100644 --- a/src/portd/pcr12/mod.rs +++ b/src/portd/pcr12/mod.rs @@ -22,7 +22,9 @@ impl super::PCR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr13/mod.rs b/src/portd/pcr13/mod.rs index 5780ce5..0dc615f 100644 --- a/src/portd/pcr13/mod.rs +++ b/src/portd/pcr13/mod.rs @@ -22,7 +22,9 @@ impl super::PCR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr14/mod.rs b/src/portd/pcr14/mod.rs index 85fddf4..ccdafa6 100644 --- a/src/portd/pcr14/mod.rs +++ b/src/portd/pcr14/mod.rs @@ -22,7 +22,9 @@ impl super::PCR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr15/mod.rs b/src/portd/pcr15/mod.rs index 271cafa..e6ac9f2 100644 --- a/src/portd/pcr15/mod.rs +++ b/src/portd/pcr15/mod.rs @@ -22,7 +22,9 @@ impl super::PCR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr16/mod.rs b/src/portd/pcr16/mod.rs index a9bbadb..0cebfc5 100644 --- a/src/portd/pcr16/mod.rs +++ b/src/portd/pcr16/mod.rs @@ -22,7 +22,9 @@ impl super::PCR16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr17/mod.rs b/src/portd/pcr17/mod.rs index e17dc3b..8f6705c 100644 --- a/src/portd/pcr17/mod.rs +++ b/src/portd/pcr17/mod.rs @@ -22,7 +22,9 @@ impl super::PCR17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr18/mod.rs b/src/portd/pcr18/mod.rs index 6a7fcc9..7075910 100644 --- a/src/portd/pcr18/mod.rs +++ b/src/portd/pcr18/mod.rs @@ -22,7 +22,9 @@ impl super::PCR18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr19/mod.rs b/src/portd/pcr19/mod.rs index 4bf42ab..9e63ce2 100644 --- a/src/portd/pcr19/mod.rs +++ b/src/portd/pcr19/mod.rs @@ -22,7 +22,9 @@ impl super::PCR19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr2/mod.rs b/src/portd/pcr2/mod.rs index 8743cfc..5f6321c 100644 --- a/src/portd/pcr2/mod.rs +++ b/src/portd/pcr2/mod.rs @@ -22,7 +22,9 @@ impl super::PCR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr20/mod.rs b/src/portd/pcr20/mod.rs index 1bd7323..a50d2db 100644 --- a/src/portd/pcr20/mod.rs +++ b/src/portd/pcr20/mod.rs @@ -22,7 +22,9 @@ impl super::PCR20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr21/mod.rs b/src/portd/pcr21/mod.rs index 7225469..757c5af 100644 --- a/src/portd/pcr21/mod.rs +++ b/src/portd/pcr21/mod.rs @@ -22,7 +22,9 @@ impl super::PCR21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr22/mod.rs b/src/portd/pcr22/mod.rs index e627370..4604d44 100644 --- a/src/portd/pcr22/mod.rs +++ b/src/portd/pcr22/mod.rs @@ -22,7 +22,9 @@ impl super::PCR22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr23/mod.rs b/src/portd/pcr23/mod.rs index febbc63..9cd6a20 100644 --- a/src/portd/pcr23/mod.rs +++ b/src/portd/pcr23/mod.rs @@ -22,7 +22,9 @@ impl super::PCR23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr24/mod.rs b/src/portd/pcr24/mod.rs index cd996e7..c34c180 100644 --- a/src/portd/pcr24/mod.rs +++ b/src/portd/pcr24/mod.rs @@ -22,7 +22,9 @@ impl super::PCR24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr25/mod.rs b/src/portd/pcr25/mod.rs index 5166cfe..f8bd273 100644 --- a/src/portd/pcr25/mod.rs +++ b/src/portd/pcr25/mod.rs @@ -22,7 +22,9 @@ impl super::PCR25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr26/mod.rs b/src/portd/pcr26/mod.rs index 5214b91..5da8351 100644 --- a/src/portd/pcr26/mod.rs +++ b/src/portd/pcr26/mod.rs @@ -22,7 +22,9 @@ impl super::PCR26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr27/mod.rs b/src/portd/pcr27/mod.rs index b903934..a03d4e4 100644 --- a/src/portd/pcr27/mod.rs +++ b/src/portd/pcr27/mod.rs @@ -22,7 +22,9 @@ impl super::PCR27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr28/mod.rs b/src/portd/pcr28/mod.rs index ca0644f..2cc98e1 100644 --- a/src/portd/pcr28/mod.rs +++ b/src/portd/pcr28/mod.rs @@ -22,7 +22,9 @@ impl super::PCR28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr29/mod.rs b/src/portd/pcr29/mod.rs index 8f37f93..9474292 100644 --- a/src/portd/pcr29/mod.rs +++ b/src/portd/pcr29/mod.rs @@ -22,7 +22,9 @@ impl super::PCR29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr3/mod.rs b/src/portd/pcr3/mod.rs index 37a3f3f..1a8583e 100644 --- a/src/portd/pcr3/mod.rs +++ b/src/portd/pcr3/mod.rs @@ -22,7 +22,9 @@ impl super::PCR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,8 +138,7 @@ impl PER { #[doc = "Possible values of the field `PFE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PFER { - #[doc = "Passive input filter is disabled on the corresponding pin."] - _0, + #[doc = "Passive input filter is disabled on the corresponding pin."] _0, #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."] _1, } @@ -184,22 +184,14 @@ impl PFER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +268,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +314,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +408,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +511,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -589,8 +568,7 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `PFE`"] pub enum PFEW { - #[doc = "Passive input filter is disabled on the corresponding pin."] - _0, + #[doc = "Passive input filter is disabled on the corresponding pin."] _0, #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."] _1, } @@ -647,22 +625,14 @@ impl<'a> _PFEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +715,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +772,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +867,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr30/mod.rs b/src/portd/pcr30/mod.rs index b97fecd..211b766 100644 --- a/src/portd/pcr30/mod.rs +++ b/src/portd/pcr30/mod.rs @@ -22,7 +22,9 @@ impl super::PCR30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr31/mod.rs b/src/portd/pcr31/mod.rs index 0d571dd..b31068c 100644 --- a/src/portd/pcr31/mod.rs +++ b/src/portd/pcr31/mod.rs @@ -22,7 +22,9 @@ impl super::PCR31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr4/mod.rs b/src/portd/pcr4/mod.rs index 56a72fc..7b6c5cb 100644 --- a/src/portd/pcr4/mod.rs +++ b/src/portd/pcr4/mod.rs @@ -22,7 +22,9 @@ impl super::PCR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr5/mod.rs b/src/portd/pcr5/mod.rs index 753c0b9..b2356cd 100644 --- a/src/portd/pcr5/mod.rs +++ b/src/portd/pcr5/mod.rs @@ -22,7 +22,9 @@ impl super::PCR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr6/mod.rs b/src/portd/pcr6/mod.rs index 4f75772..1217b1e 100644 --- a/src/portd/pcr6/mod.rs +++ b/src/portd/pcr6/mod.rs @@ -22,7 +22,9 @@ impl super::PCR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr7/mod.rs b/src/portd/pcr7/mod.rs index 2d04668..a31bba1 100644 --- a/src/portd/pcr7/mod.rs +++ b/src/portd/pcr7/mod.rs @@ -22,7 +22,9 @@ impl super::PCR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr8/mod.rs b/src/portd/pcr8/mod.rs index 7e48cee..e7d43ee 100644 --- a/src/portd/pcr8/mod.rs +++ b/src/portd/pcr8/mod.rs @@ -22,7 +22,9 @@ impl super::PCR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/portd/pcr9/mod.rs b/src/portd/pcr9/mod.rs index 897f16c..10896f1 100644 --- a/src/portd/pcr9/mod.rs +++ b/src/portd/pcr9/mod.rs @@ -22,7 +22,9 @@ impl super::PCR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/dfcr/mod.rs b/src/porte/dfcr/mod.rs index 4e0e5ae..b77fb96 100644 --- a/src/porte/dfcr/mod.rs +++ b/src/porte/dfcr/mod.rs @@ -22,7 +22,9 @@ impl super::DFCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::DFCR { #[doc = "Possible values of the field `CS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CSR { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl CSR { } #[doc = "Values that can be written to the field `CS`"] pub enum CSW { - #[doc = "Digital filters are clocked by the bus clock."] - _0, - #[doc = "Digital filters are clocked by the LPO clock."] - _1, + #[doc = "Digital filters are clocked by the bus clock."] _0, + #[doc = "Digital filters are clocked by the LPO clock."] _1, } impl CSW { #[allow(missing_docs)] diff --git a/src/porte/dfer/mod.rs b/src/porte/dfer/mod.rs index a80865b..1f1a9d7 100644 --- a/src/porte/dfer/mod.rs +++ b/src/porte/dfer/mod.rs @@ -22,7 +22,9 @@ impl super::DFER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -47,8 +49,7 @@ pub enum DFER { _0, #[doc = "Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl DFER { #[doc = r" Value of the field as raw bits"] diff --git a/src/porte/dfwr/mod.rs b/src/porte/dfwr/mod.rs index bed0a1c..1fb2234 100644 --- a/src/porte/dfwr/mod.rs +++ b/src/porte/dfwr/mod.rs @@ -22,7 +22,9 @@ impl super::DFWR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/porte/gpchr/mod.rs b/src/porte/gpchr/mod.rs index dcd6928..04bdd2a 100644 --- a/src/porte/gpchr/mod.rs +++ b/src/porte/gpchr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/porte/gpclr/mod.rs b/src/porte/gpclr/mod.rs index fca1209..e570701 100644 --- a/src/porte/gpclr/mod.rs +++ b/src/porte/gpclr/mod.rs @@ -31,10 +31,8 @@ impl<'a> _GPWDW<'a> { } #[doc = "Values that can be written to the field `GPWE`"] pub enum GPWEW { - #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] - _0, - #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] - _1, + #[doc = "Corresponding Pin Control Register is not updated with the value in GPWD."] _0, + #[doc = "Corresponding Pin Control Register is updated with the value in GPWD."] _1, } impl GPWEW { #[allow(missing_docs)] diff --git a/src/porte/isfr/mod.rs b/src/porte/isfr/mod.rs index e343374..97dcc02 100644 --- a/src/porte/isfr/mod.rs +++ b/src/porte/isfr/mod.rs @@ -22,7 +22,9 @@ impl super::ISFR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,10 @@ impl super::ISFR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, - #[doc = r" Reserved"] - _Reserved(u32), + #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] @@ -83,8 +83,7 @@ impl ISFR { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/mod.rs b/src/porte/mod.rs index 07f3550..9801527 100644 --- a/src/porte/mod.rs +++ b/src/porte/mod.rs @@ -2,84 +2,46 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Pin Control Register n"] - pub pcr0: PCR0, - #[doc = "0x04 - Pin Control Register n"] - pub pcr1: PCR1, - #[doc = "0x08 - Pin Control Register n"] - pub pcr2: PCR2, - #[doc = "0x0c - Pin Control Register n"] - pub pcr3: PCR3, - #[doc = "0x10 - Pin Control Register n"] - pub pcr4: PCR4, - #[doc = "0x14 - Pin Control Register n"] - pub pcr5: PCR5, - #[doc = "0x18 - Pin Control Register n"] - pub pcr6: PCR6, - #[doc = "0x1c - Pin Control Register n"] - pub pcr7: PCR7, - #[doc = "0x20 - Pin Control Register n"] - pub pcr8: PCR8, - #[doc = "0x24 - Pin Control Register n"] - pub pcr9: PCR9, - #[doc = "0x28 - Pin Control Register n"] - pub pcr10: PCR10, - #[doc = "0x2c - Pin Control Register n"] - pub pcr11: PCR11, - #[doc = "0x30 - Pin Control Register n"] - pub pcr12: PCR12, - #[doc = "0x34 - Pin Control Register n"] - pub pcr13: PCR13, - #[doc = "0x38 - Pin Control Register n"] - pub pcr14: PCR14, - #[doc = "0x3c - Pin Control Register n"] - pub pcr15: PCR15, - #[doc = "0x40 - Pin Control Register n"] - pub pcr16: PCR16, - #[doc = "0x44 - Pin Control Register n"] - pub pcr17: PCR17, - #[doc = "0x48 - Pin Control Register n"] - pub pcr18: PCR18, - #[doc = "0x4c - Pin Control Register n"] - pub pcr19: PCR19, - #[doc = "0x50 - Pin Control Register n"] - pub pcr20: PCR20, - #[doc = "0x54 - Pin Control Register n"] - pub pcr21: PCR21, - #[doc = "0x58 - Pin Control Register n"] - pub pcr22: PCR22, - #[doc = "0x5c - Pin Control Register n"] - pub pcr23: PCR23, - #[doc = "0x60 - Pin Control Register n"] - pub pcr24: PCR24, - #[doc = "0x64 - Pin Control Register n"] - pub pcr25: PCR25, - #[doc = "0x68 - Pin Control Register n"] - pub pcr26: PCR26, - #[doc = "0x6c - Pin Control Register n"] - pub pcr27: PCR27, - #[doc = "0x70 - Pin Control Register n"] - pub pcr28: PCR28, - #[doc = "0x74 - Pin Control Register n"] - pub pcr29: PCR29, - #[doc = "0x78 - Pin Control Register n"] - pub pcr30: PCR30, - #[doc = "0x7c - Pin Control Register n"] - pub pcr31: PCR31, - #[doc = "0x80 - Global Pin Control Low Register"] - pub gpclr: GPCLR, - #[doc = "0x84 - Global Pin Control High Register"] - pub gpchr: GPCHR, + #[doc = "0x00 - Pin Control Register n"] pub pcr0: PCR0, + #[doc = "0x04 - Pin Control Register n"] pub pcr1: PCR1, + #[doc = "0x08 - Pin Control Register n"] pub pcr2: PCR2, + #[doc = "0x0c - Pin Control Register n"] pub pcr3: PCR3, + #[doc = "0x10 - Pin Control Register n"] pub pcr4: PCR4, + #[doc = "0x14 - Pin Control Register n"] pub pcr5: PCR5, + #[doc = "0x18 - Pin Control Register n"] pub pcr6: PCR6, + #[doc = "0x1c - Pin Control Register n"] pub pcr7: PCR7, + #[doc = "0x20 - Pin Control Register n"] pub pcr8: PCR8, + #[doc = "0x24 - Pin Control Register n"] pub pcr9: PCR9, + #[doc = "0x28 - Pin Control Register n"] pub pcr10: PCR10, + #[doc = "0x2c - Pin Control Register n"] pub pcr11: PCR11, + #[doc = "0x30 - Pin Control Register n"] pub pcr12: PCR12, + #[doc = "0x34 - Pin Control Register n"] pub pcr13: PCR13, + #[doc = "0x38 - Pin Control Register n"] pub pcr14: PCR14, + #[doc = "0x3c - Pin Control Register n"] pub pcr15: PCR15, + #[doc = "0x40 - Pin Control Register n"] pub pcr16: PCR16, + #[doc = "0x44 - Pin Control Register n"] pub pcr17: PCR17, + #[doc = "0x48 - Pin Control Register n"] pub pcr18: PCR18, + #[doc = "0x4c - Pin Control Register n"] pub pcr19: PCR19, + #[doc = "0x50 - Pin Control Register n"] pub pcr20: PCR20, + #[doc = "0x54 - Pin Control Register n"] pub pcr21: PCR21, + #[doc = "0x58 - Pin Control Register n"] pub pcr22: PCR22, + #[doc = "0x5c - Pin Control Register n"] pub pcr23: PCR23, + #[doc = "0x60 - Pin Control Register n"] pub pcr24: PCR24, + #[doc = "0x64 - Pin Control Register n"] pub pcr25: PCR25, + #[doc = "0x68 - Pin Control Register n"] pub pcr26: PCR26, + #[doc = "0x6c - Pin Control Register n"] pub pcr27: PCR27, + #[doc = "0x70 - Pin Control Register n"] pub pcr28: PCR28, + #[doc = "0x74 - Pin Control Register n"] pub pcr29: PCR29, + #[doc = "0x78 - Pin Control Register n"] pub pcr30: PCR30, + #[doc = "0x7c - Pin Control Register n"] pub pcr31: PCR31, + #[doc = "0x80 - Global Pin Control Low Register"] pub gpclr: GPCLR, + #[doc = "0x84 - Global Pin Control High Register"] pub gpchr: GPCHR, _reserved0: [u8; 24usize], - #[doc = "0xa0 - Interrupt Status Flag Register"] - pub isfr: ISFR, + #[doc = "0xa0 - Interrupt Status Flag Register"] pub isfr: ISFR, _reserved1: [u8; 28usize], - #[doc = "0xc0 - Digital Filter Enable Register"] - pub dfer: DFER, - #[doc = "0xc4 - Digital Filter Clock Register"] - pub dfcr: DFCR, - #[doc = "0xc8 - Digital Filter Width Register"] - pub dfwr: DFWR, + #[doc = "0xc0 - Digital Filter Enable Register"] pub dfer: DFER, + #[doc = "0xc4 - Digital Filter Clock Register"] pub dfcr: DFCR, + #[doc = "0xc8 - Digital Filter Width Register"] pub dfwr: DFWR, } #[doc = "Pin Control Register n"] pub struct PCR0 { diff --git a/src/porte/pcr0/mod.rs b/src/porte/pcr0/mod.rs index 0939dbe..5bd2a00 100644 --- a/src/porte/pcr0/mod.rs +++ b/src/porte/pcr0/mod.rs @@ -22,7 +22,9 @@ impl super::PCR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr1/mod.rs b/src/porte/pcr1/mod.rs index 1e49167..a752aed 100644 --- a/src/porte/pcr1/mod.rs +++ b/src/porte/pcr1/mod.rs @@ -22,7 +22,9 @@ impl super::PCR1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -184,22 +185,14 @@ impl DSER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -276,8 +269,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -323,26 +315,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -427,8 +409,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -531,8 +512,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -647,22 +627,14 @@ impl<'a> _DSEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -745,8 +717,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -803,24 +774,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -907,8 +869,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr10/mod.rs b/src/porte/pcr10/mod.rs index 948f328..28aeb16 100644 --- a/src/porte/pcr10/mod.rs +++ b/src/porte/pcr10/mod.rs @@ -22,7 +22,9 @@ impl super::PCR10 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr11/mod.rs b/src/porte/pcr11/mod.rs index 9eec901..3b4f036 100644 --- a/src/porte/pcr11/mod.rs +++ b/src/porte/pcr11/mod.rs @@ -22,7 +22,9 @@ impl super::PCR11 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr12/mod.rs b/src/porte/pcr12/mod.rs index b16e5be..5a18667 100644 --- a/src/porte/pcr12/mod.rs +++ b/src/porte/pcr12/mod.rs @@ -22,7 +22,9 @@ impl super::PCR12 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr13/mod.rs b/src/porte/pcr13/mod.rs index 5780ce5..0dc615f 100644 --- a/src/porte/pcr13/mod.rs +++ b/src/porte/pcr13/mod.rs @@ -22,7 +22,9 @@ impl super::PCR13 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr14/mod.rs b/src/porte/pcr14/mod.rs index 85fddf4..ccdafa6 100644 --- a/src/porte/pcr14/mod.rs +++ b/src/porte/pcr14/mod.rs @@ -22,7 +22,9 @@ impl super::PCR14 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr15/mod.rs b/src/porte/pcr15/mod.rs index eb78706..f7e2144 100644 --- a/src/porte/pcr15/mod.rs +++ b/src/porte/pcr15/mod.rs @@ -22,7 +22,9 @@ impl super::PCR15 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr16/mod.rs b/src/porte/pcr16/mod.rs index 539a3ca..45761b1 100644 --- a/src/porte/pcr16/mod.rs +++ b/src/porte/pcr16/mod.rs @@ -22,7 +22,9 @@ impl super::PCR16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr17/mod.rs b/src/porte/pcr17/mod.rs index e17dc3b..8f6705c 100644 --- a/src/porte/pcr17/mod.rs +++ b/src/porte/pcr17/mod.rs @@ -22,7 +22,9 @@ impl super::PCR17 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr18/mod.rs b/src/porte/pcr18/mod.rs index 6a7fcc9..7075910 100644 --- a/src/porte/pcr18/mod.rs +++ b/src/porte/pcr18/mod.rs @@ -22,7 +22,9 @@ impl super::PCR18 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr19/mod.rs b/src/porte/pcr19/mod.rs index 4bf42ab..9e63ce2 100644 --- a/src/porte/pcr19/mod.rs +++ b/src/porte/pcr19/mod.rs @@ -22,7 +22,9 @@ impl super::PCR19 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr2/mod.rs b/src/porte/pcr2/mod.rs index 8743cfc..5f6321c 100644 --- a/src/porte/pcr2/mod.rs +++ b/src/porte/pcr2/mod.rs @@ -22,7 +22,9 @@ impl super::PCR2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr20/mod.rs b/src/porte/pcr20/mod.rs index 1bd7323..a50d2db 100644 --- a/src/porte/pcr20/mod.rs +++ b/src/porte/pcr20/mod.rs @@ -22,7 +22,9 @@ impl super::PCR20 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr21/mod.rs b/src/porte/pcr21/mod.rs index 7225469..757c5af 100644 --- a/src/porte/pcr21/mod.rs +++ b/src/porte/pcr21/mod.rs @@ -22,7 +22,9 @@ impl super::PCR21 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr22/mod.rs b/src/porte/pcr22/mod.rs index e627370..4604d44 100644 --- a/src/porte/pcr22/mod.rs +++ b/src/porte/pcr22/mod.rs @@ -22,7 +22,9 @@ impl super::PCR22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr23/mod.rs b/src/porte/pcr23/mod.rs index febbc63..9cd6a20 100644 --- a/src/porte/pcr23/mod.rs +++ b/src/porte/pcr23/mod.rs @@ -22,7 +22,9 @@ impl super::PCR23 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr24/mod.rs b/src/porte/pcr24/mod.rs index cd996e7..c34c180 100644 --- a/src/porte/pcr24/mod.rs +++ b/src/porte/pcr24/mod.rs @@ -22,7 +22,9 @@ impl super::PCR24 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr25/mod.rs b/src/porte/pcr25/mod.rs index 5166cfe..f8bd273 100644 --- a/src/porte/pcr25/mod.rs +++ b/src/porte/pcr25/mod.rs @@ -22,7 +22,9 @@ impl super::PCR25 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr26/mod.rs b/src/porte/pcr26/mod.rs index 5214b91..5da8351 100644 --- a/src/porte/pcr26/mod.rs +++ b/src/porte/pcr26/mod.rs @@ -22,7 +22,9 @@ impl super::PCR26 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr27/mod.rs b/src/porte/pcr27/mod.rs index b903934..a03d4e4 100644 --- a/src/porte/pcr27/mod.rs +++ b/src/porte/pcr27/mod.rs @@ -22,7 +22,9 @@ impl super::PCR27 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr28/mod.rs b/src/porte/pcr28/mod.rs index ca0644f..2cc98e1 100644 --- a/src/porte/pcr28/mod.rs +++ b/src/porte/pcr28/mod.rs @@ -22,7 +22,9 @@ impl super::PCR28 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr29/mod.rs b/src/porte/pcr29/mod.rs index 8f37f93..9474292 100644 --- a/src/porte/pcr29/mod.rs +++ b/src/porte/pcr29/mod.rs @@ -22,7 +22,9 @@ impl super::PCR29 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr3/mod.rs b/src/porte/pcr3/mod.rs index 35283c4..189aabd 100644 --- a/src/porte/pcr3/mod.rs +++ b/src/porte/pcr3/mod.rs @@ -22,7 +22,9 @@ impl super::PCR3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr30/mod.rs b/src/porte/pcr30/mod.rs index b97fecd..211b766 100644 --- a/src/porte/pcr30/mod.rs +++ b/src/porte/pcr30/mod.rs @@ -22,7 +22,9 @@ impl super::PCR30 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr31/mod.rs b/src/porte/pcr31/mod.rs index 0d571dd..b31068c 100644 --- a/src/porte/pcr31/mod.rs +++ b/src/porte/pcr31/mod.rs @@ -22,7 +22,9 @@ impl super::PCR31 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr4/mod.rs b/src/porte/pcr4/mod.rs index 56a72fc..7b6c5cb 100644 --- a/src/porte/pcr4/mod.rs +++ b/src/porte/pcr4/mod.rs @@ -22,7 +22,9 @@ impl super::PCR4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr5/mod.rs b/src/porte/pcr5/mod.rs index 753c0b9..b2356cd 100644 --- a/src/porte/pcr5/mod.rs +++ b/src/porte/pcr5/mod.rs @@ -22,7 +22,9 @@ impl super::PCR5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr6/mod.rs b/src/porte/pcr6/mod.rs index 4f75772..1217b1e 100644 --- a/src/porte/pcr6/mod.rs +++ b/src/porte/pcr6/mod.rs @@ -22,7 +22,9 @@ impl super::PCR6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr7/mod.rs b/src/porte/pcr7/mod.rs index 2d04668..a31bba1 100644 --- a/src/porte/pcr7/mod.rs +++ b/src/porte/pcr7/mod.rs @@ -22,7 +22,9 @@ impl super::PCR7 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr8/mod.rs b/src/porte/pcr8/mod.rs index 7e48cee..e7d43ee 100644 --- a/src/porte/pcr8/mod.rs +++ b/src/porte/pcr8/mod.rs @@ -22,7 +22,9 @@ impl super::PCR8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/porte/pcr9/mod.rs b/src/porte/pcr9/mod.rs index 897f16c..10896f1 100644 --- a/src/porte/pcr9/mod.rs +++ b/src/porte/pcr9/mod.rs @@ -22,7 +22,9 @@ impl super::PCR9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -90,8 +92,7 @@ impl PSR { #[doc = "Possible values of the field `PE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PER { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -137,22 +138,14 @@ impl PER { #[doc = "Possible values of the field `MUX`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MUXR { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXR { #[doc = r" Value of the field as raw bits"] @@ -229,8 +222,7 @@ impl MUXR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -276,26 +268,16 @@ impl LKR { #[doc = "Possible values of the field `IRQC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum IRQCR { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, + #[doc = r" Reserved"] _Reserved(u8), } impl IRQCR { #[doc = r" Value of the field as raw bits"] @@ -380,8 +362,7 @@ impl IRQCR { #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } @@ -484,8 +465,7 @@ impl<'a> _PSW<'a> { } #[doc = "Values that can be written to the field `PE`"] pub enum PEW { - #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] - _0, + #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."] _0, #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."] _1, } @@ -542,22 +522,14 @@ impl<'a> _PEW<'a> { } #[doc = "Values that can be written to the field `MUX`"] pub enum MUXW { - #[doc = "Pin disabled (Alternative 0) (analog)."] - _000, - #[doc = "Alternative 1 (GPIO)."] - _001, - #[doc = "Alternative 2 (chip-specific)."] - _010, - #[doc = "Alternative 3 (chip-specific)."] - _011, - #[doc = "Alternative 4 (chip-specific)."] - _100, - #[doc = "Alternative 5 (chip-specific)."] - _101, - #[doc = "Alternative 6 (chip-specific)."] - _110, - #[doc = "Alternative 7 (chip-specific)."] - _111, + #[doc = "Pin disabled (Alternative 0) (analog)."] _000, + #[doc = "Alternative 1 (GPIO)."] _001, + #[doc = "Alternative 2 (chip-specific)."] _010, + #[doc = "Alternative 3 (chip-specific)."] _011, + #[doc = "Alternative 4 (chip-specific)."] _100, + #[doc = "Alternative 5 (chip-specific)."] _101, + #[doc = "Alternative 6 (chip-specific)."] _110, + #[doc = "Alternative 7 (chip-specific)."] _111, } impl MUXW { #[allow(missing_docs)] @@ -640,8 +612,7 @@ impl<'a> _MUXW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Pin Control Register fields [15:0] are not locked."] - _0, + #[doc = "Pin Control Register fields [15:0] are not locked."] _0, #[doc = "Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset."] _1, } @@ -698,24 +669,15 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `IRQC`"] pub enum IRQCW { - #[doc = "Interrupt Status Flag (ISF) is disabled."] - _0000, - #[doc = "ISF flag and DMA request on rising edge."] - _0001, - #[doc = "ISF flag and DMA request on falling edge."] - _0010, - #[doc = "ISF flag and DMA request on either edge."] - _0011, - #[doc = "ISF flag and Interrupt when logic 0."] - _1000, - #[doc = "ISF flag and Interrupt on rising-edge."] - _1001, - #[doc = "ISF flag and Interrupt on falling-edge."] - _1010, - #[doc = "ISF flag and Interrupt on either edge."] - _1011, - #[doc = "ISF flag and Interrupt when logic 1."] - _1100, + #[doc = "Interrupt Status Flag (ISF) is disabled."] _0000, + #[doc = "ISF flag and DMA request on rising edge."] _0001, + #[doc = "ISF flag and DMA request on falling edge."] _0010, + #[doc = "ISF flag and DMA request on either edge."] _0011, + #[doc = "ISF flag and Interrupt when logic 0."] _1000, + #[doc = "ISF flag and Interrupt on rising-edge."] _1001, + #[doc = "ISF flag and Interrupt on falling-edge."] _1010, + #[doc = "ISF flag and Interrupt on either edge."] _1011, + #[doc = "ISF flag and Interrupt when logic 1."] _1100, } impl IRQCW { #[allow(missing_docs)] @@ -802,8 +764,7 @@ impl<'a> _IRQCW<'a> { } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { - #[doc = "Configured interrupt is not detected."] - _0, + #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } diff --git a/src/pta/mod.rs b/src/pta/mod.rs index c510f0a..8916eb9 100644 --- a/src/pta/mod.rs +++ b/src/pta/mod.rs @@ -2,20 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Port Data Output Register"] - pub pdor: PDOR, - #[doc = "0x04 - Port Set Output Register"] - pub psor: PSOR, - #[doc = "0x08 - Port Clear Output Register"] - pub pcor: PCOR, - #[doc = "0x0c - Port Toggle Output Register"] - pub ptor: PTOR, - #[doc = "0x10 - Port Data Input Register"] - pub pdir: PDIR, - #[doc = "0x14 - Port Data Direction Register"] - pub pddr: PDDR, - #[doc = "0x18 - Port Input Disable Register"] - pub pidr: PIDR, + #[doc = "0x00 - Port Data Output Register"] pub pdor: PDOR, + #[doc = "0x04 - Port Set Output Register"] pub psor: PSOR, + #[doc = "0x08 - Port Clear Output Register"] pub pcor: PCOR, + #[doc = "0x0c - Port Toggle Output Register"] pub ptor: PTOR, + #[doc = "0x10 - Port Data Input Register"] pub pdir: PDIR, + #[doc = "0x14 - Port Data Direction Register"] pub pddr: PDDR, + #[doc = "0x18 - Port Input Disable Register"] pub pidr: PIDR, } #[doc = "Port Data Output Register"] pub struct PDOR { diff --git a/src/pta/pddr/mod.rs b/src/pta/pddr/mod.rs index b663fac..838a3cb 100644 --- a/src/pta/pddr/mod.rs +++ b/src/pta/pddr/mod.rs @@ -22,7 +22,9 @@ impl super::PDDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pta/pdir/mod.rs b/src/pta/pdir/mod.rs index cc72443..a637e15 100644 --- a/src/pta/pdir/mod.rs +++ b/src/pta/pdir/mod.rs @@ -6,7 +6,9 @@ impl super::PDIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/pta/pdor/mod.rs b/src/pta/pdor/mod.rs index 7cd5f5c..95b6135 100644 --- a/src/pta/pdor/mod.rs +++ b/src/pta/pdor/mod.rs @@ -22,7 +22,9 @@ impl super::PDOR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pta/pidr/mod.rs b/src/pta/pidr/mod.rs index b1f3b22..776e7b9 100644 --- a/src/pta/pidr/mod.rs +++ b/src/pta/pidr/mod.rs @@ -22,7 +22,9 @@ impl super::PIDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptb/mod.rs b/src/ptb/mod.rs index c510f0a..8916eb9 100644 --- a/src/ptb/mod.rs +++ b/src/ptb/mod.rs @@ -2,20 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Port Data Output Register"] - pub pdor: PDOR, - #[doc = "0x04 - Port Set Output Register"] - pub psor: PSOR, - #[doc = "0x08 - Port Clear Output Register"] - pub pcor: PCOR, - #[doc = "0x0c - Port Toggle Output Register"] - pub ptor: PTOR, - #[doc = "0x10 - Port Data Input Register"] - pub pdir: PDIR, - #[doc = "0x14 - Port Data Direction Register"] - pub pddr: PDDR, - #[doc = "0x18 - Port Input Disable Register"] - pub pidr: PIDR, + #[doc = "0x00 - Port Data Output Register"] pub pdor: PDOR, + #[doc = "0x04 - Port Set Output Register"] pub psor: PSOR, + #[doc = "0x08 - Port Clear Output Register"] pub pcor: PCOR, + #[doc = "0x0c - Port Toggle Output Register"] pub ptor: PTOR, + #[doc = "0x10 - Port Data Input Register"] pub pdir: PDIR, + #[doc = "0x14 - Port Data Direction Register"] pub pddr: PDDR, + #[doc = "0x18 - Port Input Disable Register"] pub pidr: PIDR, } #[doc = "Port Data Output Register"] pub struct PDOR { diff --git a/src/ptb/pddr/mod.rs b/src/ptb/pddr/mod.rs index b663fac..838a3cb 100644 --- a/src/ptb/pddr/mod.rs +++ b/src/ptb/pddr/mod.rs @@ -22,7 +22,9 @@ impl super::PDDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptb/pdir/mod.rs b/src/ptb/pdir/mod.rs index cc72443..a637e15 100644 --- a/src/ptb/pdir/mod.rs +++ b/src/ptb/pdir/mod.rs @@ -6,7 +6,9 @@ impl super::PDIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/ptb/pdor/mod.rs b/src/ptb/pdor/mod.rs index 7cd5f5c..95b6135 100644 --- a/src/ptb/pdor/mod.rs +++ b/src/ptb/pdor/mod.rs @@ -22,7 +22,9 @@ impl super::PDOR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptb/pidr/mod.rs b/src/ptb/pidr/mod.rs index b1f3b22..776e7b9 100644 --- a/src/ptb/pidr/mod.rs +++ b/src/ptb/pidr/mod.rs @@ -22,7 +22,9 @@ impl super::PIDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptc/mod.rs b/src/ptc/mod.rs index c510f0a..8916eb9 100644 --- a/src/ptc/mod.rs +++ b/src/ptc/mod.rs @@ -2,20 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Port Data Output Register"] - pub pdor: PDOR, - #[doc = "0x04 - Port Set Output Register"] - pub psor: PSOR, - #[doc = "0x08 - Port Clear Output Register"] - pub pcor: PCOR, - #[doc = "0x0c - Port Toggle Output Register"] - pub ptor: PTOR, - #[doc = "0x10 - Port Data Input Register"] - pub pdir: PDIR, - #[doc = "0x14 - Port Data Direction Register"] - pub pddr: PDDR, - #[doc = "0x18 - Port Input Disable Register"] - pub pidr: PIDR, + #[doc = "0x00 - Port Data Output Register"] pub pdor: PDOR, + #[doc = "0x04 - Port Set Output Register"] pub psor: PSOR, + #[doc = "0x08 - Port Clear Output Register"] pub pcor: PCOR, + #[doc = "0x0c - Port Toggle Output Register"] pub ptor: PTOR, + #[doc = "0x10 - Port Data Input Register"] pub pdir: PDIR, + #[doc = "0x14 - Port Data Direction Register"] pub pddr: PDDR, + #[doc = "0x18 - Port Input Disable Register"] pub pidr: PIDR, } #[doc = "Port Data Output Register"] pub struct PDOR { diff --git a/src/ptc/pddr/mod.rs b/src/ptc/pddr/mod.rs index b663fac..838a3cb 100644 --- a/src/ptc/pddr/mod.rs +++ b/src/ptc/pddr/mod.rs @@ -22,7 +22,9 @@ impl super::PDDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptc/pdir/mod.rs b/src/ptc/pdir/mod.rs index cc72443..a637e15 100644 --- a/src/ptc/pdir/mod.rs +++ b/src/ptc/pdir/mod.rs @@ -6,7 +6,9 @@ impl super::PDIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/ptc/pdor/mod.rs b/src/ptc/pdor/mod.rs index 7cd5f5c..95b6135 100644 --- a/src/ptc/pdor/mod.rs +++ b/src/ptc/pdor/mod.rs @@ -22,7 +22,9 @@ impl super::PDOR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptc/pidr/mod.rs b/src/ptc/pidr/mod.rs index b1f3b22..776e7b9 100644 --- a/src/ptc/pidr/mod.rs +++ b/src/ptc/pidr/mod.rs @@ -22,7 +22,9 @@ impl super::PIDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptd/mod.rs b/src/ptd/mod.rs index c510f0a..8916eb9 100644 --- a/src/ptd/mod.rs +++ b/src/ptd/mod.rs @@ -2,20 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Port Data Output Register"] - pub pdor: PDOR, - #[doc = "0x04 - Port Set Output Register"] - pub psor: PSOR, - #[doc = "0x08 - Port Clear Output Register"] - pub pcor: PCOR, - #[doc = "0x0c - Port Toggle Output Register"] - pub ptor: PTOR, - #[doc = "0x10 - Port Data Input Register"] - pub pdir: PDIR, - #[doc = "0x14 - Port Data Direction Register"] - pub pddr: PDDR, - #[doc = "0x18 - Port Input Disable Register"] - pub pidr: PIDR, + #[doc = "0x00 - Port Data Output Register"] pub pdor: PDOR, + #[doc = "0x04 - Port Set Output Register"] pub psor: PSOR, + #[doc = "0x08 - Port Clear Output Register"] pub pcor: PCOR, + #[doc = "0x0c - Port Toggle Output Register"] pub ptor: PTOR, + #[doc = "0x10 - Port Data Input Register"] pub pdir: PDIR, + #[doc = "0x14 - Port Data Direction Register"] pub pddr: PDDR, + #[doc = "0x18 - Port Input Disable Register"] pub pidr: PIDR, } #[doc = "Port Data Output Register"] pub struct PDOR { diff --git a/src/ptd/pddr/mod.rs b/src/ptd/pddr/mod.rs index b663fac..838a3cb 100644 --- a/src/ptd/pddr/mod.rs +++ b/src/ptd/pddr/mod.rs @@ -22,7 +22,9 @@ impl super::PDDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptd/pdir/mod.rs b/src/ptd/pdir/mod.rs index cc72443..a637e15 100644 --- a/src/ptd/pdir/mod.rs +++ b/src/ptd/pdir/mod.rs @@ -6,7 +6,9 @@ impl super::PDIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/ptd/pdor/mod.rs b/src/ptd/pdor/mod.rs index 7cd5f5c..95b6135 100644 --- a/src/ptd/pdor/mod.rs +++ b/src/ptd/pdor/mod.rs @@ -22,7 +22,9 @@ impl super::PDOR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/ptd/pidr/mod.rs b/src/ptd/pidr/mod.rs index b1f3b22..776e7b9 100644 --- a/src/ptd/pidr/mod.rs +++ b/src/ptd/pidr/mod.rs @@ -22,7 +22,9 @@ impl super::PIDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pte/mod.rs b/src/pte/mod.rs index c510f0a..8916eb9 100644 --- a/src/pte/mod.rs +++ b/src/pte/mod.rs @@ -2,20 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Port Data Output Register"] - pub pdor: PDOR, - #[doc = "0x04 - Port Set Output Register"] - pub psor: PSOR, - #[doc = "0x08 - Port Clear Output Register"] - pub pcor: PCOR, - #[doc = "0x0c - Port Toggle Output Register"] - pub ptor: PTOR, - #[doc = "0x10 - Port Data Input Register"] - pub pdir: PDIR, - #[doc = "0x14 - Port Data Direction Register"] - pub pddr: PDDR, - #[doc = "0x18 - Port Input Disable Register"] - pub pidr: PIDR, + #[doc = "0x00 - Port Data Output Register"] pub pdor: PDOR, + #[doc = "0x04 - Port Set Output Register"] pub psor: PSOR, + #[doc = "0x08 - Port Clear Output Register"] pub pcor: PCOR, + #[doc = "0x0c - Port Toggle Output Register"] pub ptor: PTOR, + #[doc = "0x10 - Port Data Input Register"] pub pdir: PDIR, + #[doc = "0x14 - Port Data Direction Register"] pub pddr: PDDR, + #[doc = "0x18 - Port Input Disable Register"] pub pidr: PIDR, } #[doc = "Port Data Output Register"] pub struct PDOR { diff --git a/src/pte/pddr/mod.rs b/src/pte/pddr/mod.rs index b663fac..838a3cb 100644 --- a/src/pte/pddr/mod.rs +++ b/src/pte/pddr/mod.rs @@ -22,7 +22,9 @@ impl super::PDDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pte/pdir/mod.rs b/src/pte/pdir/mod.rs index cc72443..a637e15 100644 --- a/src/pte/pdir/mod.rs +++ b/src/pte/pdir/mod.rs @@ -6,7 +6,9 @@ impl super::PDIR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/pte/pdor/mod.rs b/src/pte/pdor/mod.rs index 7cd5f5c..95b6135 100644 --- a/src/pte/pdor/mod.rs +++ b/src/pte/pdor/mod.rs @@ -22,7 +22,9 @@ impl super::PDOR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/pte/pidr/mod.rs b/src/pte/pidr/mod.rs index b1f3b22..776e7b9 100644 --- a/src/pte/pidr/mod.rs +++ b/src/pte/pidr/mod.rs @@ -22,7 +22,9 @@ impl super::PIDR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/rcm/mod.rs b/src/rcm/mod.rs index cb2bc5c..c290025 100644 --- a/src/rcm/mod.rs +++ b/src/rcm/mod.rs @@ -2,19 +2,13 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - System Reset Status Register"] - pub srs: SRS, - #[doc = "0x0c - Reset Pin Control register"] - pub rpc: RPC, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, + #[doc = "0x08 - System Reset Status Register"] pub srs: SRS, + #[doc = "0x0c - Reset Pin Control register"] pub rpc: RPC, _reserved0: [u8; 8usize], - #[doc = "0x18 - Sticky System Reset Status Register"] - pub ssrs: SSRS, - #[doc = "0x1c - System Reset Interrupt Enable Register"] - pub srie: SRIE, + #[doc = "0x18 - Sticky System Reset Status Register"] pub ssrs: SSRS, + #[doc = "0x1c - System Reset Interrupt Enable Register"] pub srie: SRIE, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/rcm/param/mod.rs b/src/rcm/param/mod.rs index 12b00be..0104392 100644 --- a/src/rcm/param/mod.rs +++ b/src/rcm/param/mod.rs @@ -6,16 +6,16 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `EWAKEUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EWAKEUPR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EWAKEUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl EWAKEUPR { #[doc = "Possible values of the field `ELVD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELVDR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELVDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl ELVDR { #[doc = "Possible values of the field `ELOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELOCR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl ELOCR { #[doc = "Possible values of the field `ELOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELOLR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl ELOLR { #[doc = "Possible values of the field `EWDOG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EWDOGR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EWDOGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl EWDOGR { #[doc = "Possible values of the field `EPIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EPINR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EPINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl EPINR { #[doc = "Possible values of the field `EPOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EPORR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EPORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl EPORR { #[doc = "Possible values of the field `EJTAG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EJTAGR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EJTAGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -388,10 +374,8 @@ impl EJTAGR { #[doc = "Possible values of the field `ELOCKUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELOCKUPR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELOCKUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -435,10 +419,8 @@ impl ELOCKUPR { #[doc = "Possible values of the field `ESW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESWR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ESWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -482,10 +464,8 @@ impl ESWR { #[doc = "Possible values of the field `EMDM_AP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EMDM_APR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EMDM_APR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -529,10 +509,8 @@ impl EMDM_APR { #[doc = "Possible values of the field `ESACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ESACKERRR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ESACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -576,10 +554,8 @@ impl ESACKERRR { #[doc = "Possible values of the field `ETAMPER`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ETAMPERR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ETAMPERR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -623,10 +599,8 @@ impl ETAMPERR { #[doc = "Possible values of the field `ECORE1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ECORE1R { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ECORE1R { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/rcm/rpc/mod.rs b/src/rcm/rpc/mod.rs index 348dd82..b8106b1 100644 --- a/src/rcm/rpc/mod.rs +++ b/src/rcm/rpc/mod.rs @@ -22,7 +22,9 @@ impl super::RPC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::RPC { #[doc = "Possible values of the field `RSTFLTSRW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTFLTSRWR { - #[doc = "All filtering disabled"] - _00, - #[doc = "Bus clock filter enabled for normal operation"] - _01, - #[doc = "LPO clock filter enabled for normal operation"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "All filtering disabled"] _00, + #[doc = "Bus clock filter enabled for normal operation"] _01, + #[doc = "LPO clock filter enabled for normal operation"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl RSTFLTSRWR { #[doc = r" Value of the field as raw bits"] @@ -93,10 +91,8 @@ impl RSTFLTSRWR { #[doc = "Possible values of the field `RSTFLTSS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RSTFLTSSR { - #[doc = "All filtering disabled"] - _0, - #[doc = "LPO clock filter enabled"] - _1, + #[doc = "All filtering disabled"] _0, + #[doc = "LPO clock filter enabled"] _1, } impl RSTFLTSSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -150,12 +146,9 @@ impl RSTFLTSELR { } #[doc = "Values that can be written to the field `RSTFLTSRW`"] pub enum RSTFLTSRWW { - #[doc = "All filtering disabled"] - _00, - #[doc = "Bus clock filter enabled for normal operation"] - _01, - #[doc = "LPO clock filter enabled for normal operation"] - _10, + #[doc = "All filtering disabled"] _00, + #[doc = "Bus clock filter enabled for normal operation"] _01, + #[doc = "LPO clock filter enabled for normal operation"] _10, } impl RSTFLTSRWW { #[allow(missing_docs)] @@ -206,10 +199,8 @@ impl<'a> _RSTFLTSRWW<'a> { } #[doc = "Values that can be written to the field `RSTFLTSS`"] pub enum RSTFLTSSW { - #[doc = "All filtering disabled"] - _0, - #[doc = "LPO clock filter enabled"] - _1, + #[doc = "All filtering disabled"] _0, + #[doc = "LPO clock filter enabled"] _1, } impl RSTFLTSSW { #[allow(missing_docs)] diff --git a/src/rcm/srie/mod.rs b/src/rcm/srie/mod.rs index 53ca120..d310650 100644 --- a/src/rcm/srie/mod.rs +++ b/src/rcm/srie/mod.rs @@ -22,7 +22,9 @@ impl super::SRIE { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::SRIE { #[doc = "Possible values of the field `DELAY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DELAYR { - #[doc = "10 LPO cycles"] - _00, - #[doc = "34 LPO cycles"] - _01, - #[doc = "130 LPO cycles"] - _10, - #[doc = "514 LPO cycles"] - _11, + #[doc = "10 LPO cycles"] _00, + #[doc = "34 LPO cycles"] _01, + #[doc = "130 LPO cycles"] _10, + #[doc = "514 LPO cycles"] _11, } impl DELAYR { #[doc = r" Value of the field as raw bits"] @@ -99,10 +97,8 @@ impl DELAYR { #[doc = "Possible values of the field `LOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -146,10 +142,8 @@ impl LOCR { #[doc = "Possible values of the field `LOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOLR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +187,8 @@ impl LOLR { #[doc = "Possible values of the field `WDOG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDOGR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WDOGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -240,10 +232,8 @@ impl WDOGR { #[doc = "Possible values of the field `PIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINR { - #[doc = "Reset not caused by external reset pin"] - _0, - #[doc = "Reset caused by external reset pin"] - _1, + #[doc = "Reset not caused by external reset pin"] _0, + #[doc = "Reset caused by external reset pin"] _1, } impl PINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -287,8 +277,7 @@ impl PINR { #[doc = "Possible values of the field `GIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GIER { - #[doc = "All interrupt sources disabled."] - _0, + #[doc = "All interrupt sources disabled."] _0, #[doc = "All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts."] _1, } @@ -334,10 +323,8 @@ impl GIER { #[doc = "Possible values of the field `JTAG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum JTAGR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl JTAGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -381,10 +368,8 @@ impl JTAGR { #[doc = "Possible values of the field `LOCKUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCKUPR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOCKUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -428,10 +413,8 @@ impl LOCKUPR { #[doc = "Possible values of the field `SW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -475,10 +458,8 @@ impl SWR { #[doc = "Possible values of the field `MDM_AP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MDM_APR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl MDM_APR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -522,10 +503,8 @@ impl MDM_APR { #[doc = "Possible values of the field `SACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SACKERRR { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -568,14 +547,10 @@ impl SACKERRR { } #[doc = "Values that can be written to the field `DELAY`"] pub enum DELAYW { - #[doc = "10 LPO cycles"] - _00, - #[doc = "34 LPO cycles"] - _01, - #[doc = "130 LPO cycles"] - _10, - #[doc = "514 LPO cycles"] - _11, + #[doc = "10 LPO cycles"] _00, + #[doc = "34 LPO cycles"] _01, + #[doc = "130 LPO cycles"] _10, + #[doc = "514 LPO cycles"] _11, } impl DELAYW { #[allow(missing_docs)] @@ -634,10 +609,8 @@ impl<'a> _DELAYW<'a> { } #[doc = "Values that can be written to the field `LOC`"] pub enum LOCW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOCW { #[allow(missing_docs)] @@ -692,10 +665,8 @@ impl<'a> _LOCW<'a> { } #[doc = "Values that can be written to the field `LOL`"] pub enum LOLW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOLW { #[allow(missing_docs)] @@ -750,10 +721,8 @@ impl<'a> _LOLW<'a> { } #[doc = "Values that can be written to the field `WDOG`"] pub enum WDOGW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl WDOGW { #[allow(missing_docs)] @@ -808,10 +777,8 @@ impl<'a> _WDOGW<'a> { } #[doc = "Values that can be written to the field `PIN`"] pub enum PINW { - #[doc = "Reset not caused by external reset pin"] - _0, - #[doc = "Reset caused by external reset pin"] - _1, + #[doc = "Reset not caused by external reset pin"] _0, + #[doc = "Reset caused by external reset pin"] _1, } impl PINW { #[allow(missing_docs)] @@ -866,8 +833,7 @@ impl<'a> _PINW<'a> { } #[doc = "Values that can be written to the field `GIE`"] pub enum GIEW { - #[doc = "All interrupt sources disabled."] - _0, + #[doc = "All interrupt sources disabled."] _0, #[doc = "All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts."] _1, } @@ -924,10 +890,8 @@ impl<'a> _GIEW<'a> { } #[doc = "Values that can be written to the field `JTAG`"] pub enum JTAGW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl JTAGW { #[allow(missing_docs)] @@ -982,10 +946,8 @@ impl<'a> _JTAGW<'a> { } #[doc = "Values that can be written to the field `LOCKUP`"] pub enum LOCKUPW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl LOCKUPW { #[allow(missing_docs)] @@ -1040,10 +1002,8 @@ impl<'a> _LOCKUPW<'a> { } #[doc = "Values that can be written to the field `SW`"] pub enum SWW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SWW { #[allow(missing_docs)] @@ -1098,10 +1058,8 @@ impl<'a> _SWW<'a> { } #[doc = "Values that can be written to the field `MDM_AP`"] pub enum MDM_APW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl MDM_APW { #[allow(missing_docs)] @@ -1156,10 +1114,8 @@ impl<'a> _MDM_APW<'a> { } #[doc = "Values that can be written to the field `SACKERR`"] pub enum SACKERRW { - #[doc = "Interrupt disabled."] - _0, - #[doc = "Interrupt enabled."] - _1, + #[doc = "Interrupt disabled."] _0, + #[doc = "Interrupt enabled."] _1, } impl SACKERRW { #[allow(missing_docs)] diff --git a/src/rcm/srs/mod.rs b/src/rcm/srs/mod.rs index 3a73c2a..577a5fd 100644 --- a/src/rcm/srs/mod.rs +++ b/src/rcm/srs/mod.rs @@ -6,16 +6,16 @@ impl super::SRS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `LVD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LVDR { - #[doc = "Reset not caused by LVD trip, HVD trip or POR"] - _0, - #[doc = "Reset caused by LVD trip, HVD trip or POR"] - _1, + #[doc = "Reset not caused by LVD trip, HVD trip or POR"] _0, + #[doc = "Reset caused by LVD trip, HVD trip or POR"] _1, } impl LVDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl LVDR { #[doc = "Possible values of the field `LOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCR { - #[doc = "Reset not caused by a loss of external clock."] - _0, - #[doc = "Reset caused by a loss of external clock."] - _1, + #[doc = "Reset not caused by a loss of external clock."] _0, + #[doc = "Reset caused by a loss of external clock."] _1, } impl LOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl LOCR { #[doc = "Possible values of the field `LOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOLR { - #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] - _0, - #[doc = "Reset caused by a loss of lock in the PLL/FLL"] - _1, + #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] _0, + #[doc = "Reset caused by a loss of lock in the PLL/FLL"] _1, } impl LOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl LOLR { #[doc = "Possible values of the field `WDOG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDOGR { - #[doc = "Reset not caused by watchdog timeout"] - _0, - #[doc = "Reset caused by watchdog timeout"] - _1, + #[doc = "Reset not caused by watchdog timeout"] _0, + #[doc = "Reset caused by watchdog timeout"] _1, } impl WDOGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -200,10 +194,8 @@ impl WDOGR { #[doc = "Possible values of the field `PIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PINR { - #[doc = "Reset not caused by external reset pin"] - _0, - #[doc = "Reset caused by external reset pin"] - _1, + #[doc = "Reset not caused by external reset pin"] _0, + #[doc = "Reset caused by external reset pin"] _1, } impl PINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -247,10 +239,8 @@ impl PINR { #[doc = "Possible values of the field `POR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PORR { - #[doc = "Reset not caused by POR"] - _0, - #[doc = "Reset caused by POR"] - _1, + #[doc = "Reset not caused by POR"] _0, + #[doc = "Reset caused by POR"] _1, } impl PORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -294,10 +284,8 @@ impl PORR { #[doc = "Possible values of the field `JTAG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum JTAGR { - #[doc = "Reset not caused by JTAG"] - _0, - #[doc = "Reset caused by JTAG"] - _1, + #[doc = "Reset not caused by JTAG"] _0, + #[doc = "Reset caused by JTAG"] _1, } impl JTAGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -341,10 +329,8 @@ impl JTAGR { #[doc = "Possible values of the field `LOCKUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LOCKUPR { - #[doc = "Reset not caused by core LOCKUP event"] - _0, - #[doc = "Reset caused by core LOCKUP event"] - _1, + #[doc = "Reset not caused by core LOCKUP event"] _0, + #[doc = "Reset caused by core LOCKUP event"] _1, } impl LOCKUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -388,10 +374,8 @@ impl LOCKUPR { #[doc = "Possible values of the field `SW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWR { - #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] - _0, - #[doc = "Reset caused by software setting of SYSRESETREQ bit"] - _1, + #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] _0, + #[doc = "Reset caused by software setting of SYSRESETREQ bit"] _1, } impl SWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -437,8 +421,7 @@ impl SWR { pub enum MDM_APR { #[doc = "Reset was not caused by host debugger system setting of the System Reset Request bit"] _0, - #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] - _1, + #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] _1, } impl MDM_APR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -482,10 +465,8 @@ impl MDM_APR { #[doc = "Possible values of the field `SACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SACKERRR { - #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] - _0, - #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] - _1, + #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] _0, + #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] _1, } impl SACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/rcm/ssrs/mod.rs b/src/rcm/ssrs/mod.rs index e23b9dc..f0fca74 100644 --- a/src/rcm/ssrs/mod.rs +++ b/src/rcm/ssrs/mod.rs @@ -22,7 +22,9 @@ impl super::SSRS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SSRS { #[doc = "Possible values of the field `SLVD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SLVDR { - #[doc = "Reset not caused by LVD trip or POR"] - _0, - #[doc = "Reset caused by LVD trip or POR"] - _1, + #[doc = "Reset not caused by LVD trip or POR"] _0, + #[doc = "Reset caused by LVD trip or POR"] _1, } impl SLVDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SLVDR { #[doc = "Possible values of the field `SLOC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SLOCR { - #[doc = "Reset not caused by a loss of external clock."] - _0, - #[doc = "Reset caused by a loss of external clock."] - _1, + #[doc = "Reset not caused by a loss of external clock."] _0, + #[doc = "Reset caused by a loss of external clock."] _1, } impl SLOCR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SLOCR { #[doc = "Possible values of the field `SLOL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SLOLR { - #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] - _0, - #[doc = "Reset caused by a loss of lock in the PLL/FLL"] - _1, + #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] _0, + #[doc = "Reset caused by a loss of lock in the PLL/FLL"] _1, } impl SLOLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SLOLR { #[doc = "Possible values of the field `SWDOG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWDOGR { - #[doc = "Reset not caused by watchdog timeout"] - _0, - #[doc = "Reset caused by watchdog timeout"] - _1, + #[doc = "Reset not caused by watchdog timeout"] _0, + #[doc = "Reset caused by watchdog timeout"] _1, } impl SWDOGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl SWDOGR { #[doc = "Possible values of the field `SPIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPINR { - #[doc = "Reset not caused by external reset pin"] - _0, - #[doc = "Reset caused by external reset pin"] - _1, + #[doc = "Reset not caused by external reset pin"] _0, + #[doc = "Reset caused by external reset pin"] _1, } impl SPINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl SPINR { #[doc = "Possible values of the field `SPOR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPORR { - #[doc = "Reset not caused by POR"] - _0, - #[doc = "Reset caused by POR"] - _1, + #[doc = "Reset not caused by POR"] _0, + #[doc = "Reset caused by POR"] _1, } impl SPORR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SPORR { #[doc = "Possible values of the field `SJTAG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SJTAGR { - #[doc = "Reset not caused by JTAG"] - _0, - #[doc = "Reset caused by JTAG"] - _1, + #[doc = "Reset not caused by JTAG"] _0, + #[doc = "Reset caused by JTAG"] _1, } impl SJTAGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -372,10 +360,8 @@ impl SJTAGR { #[doc = "Possible values of the field `SLOCKUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SLOCKUPR { - #[doc = "Reset not caused by core LOCKUP event"] - _0, - #[doc = "Reset caused by core LOCKUP event"] - _1, + #[doc = "Reset not caused by core LOCKUP event"] _0, + #[doc = "Reset caused by core LOCKUP event"] _1, } impl SLOCKUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -419,10 +405,8 @@ impl SLOCKUPR { #[doc = "Possible values of the field `SSW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSWR { - #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] - _0, - #[doc = "Reset caused by software setting of SYSRESETREQ bit"] - _1, + #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] _0, + #[doc = "Reset caused by software setting of SYSRESETREQ bit"] _1, } impl SSWR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -468,8 +452,7 @@ impl SSWR { pub enum SMDM_APR { #[doc = "Reset was not caused by host debugger system setting of the System Reset Request bit"] _0, - #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] - _1, + #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] _1, } impl SMDM_APR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -513,10 +496,8 @@ impl SMDM_APR { #[doc = "Possible values of the field `SSACKERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SSACKERRR { - #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] - _0, - #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] - _1, + #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] _0, + #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] _1, } impl SSACKERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -559,10 +540,8 @@ impl SSACKERRR { } #[doc = "Values that can be written to the field `SLVD`"] pub enum SLVDW { - #[doc = "Reset not caused by LVD trip or POR"] - _0, - #[doc = "Reset caused by LVD trip or POR"] - _1, + #[doc = "Reset not caused by LVD trip or POR"] _0, + #[doc = "Reset caused by LVD trip or POR"] _1, } impl SLVDW { #[allow(missing_docs)] @@ -617,10 +596,8 @@ impl<'a> _SLVDW<'a> { } #[doc = "Values that can be written to the field `SLOC`"] pub enum SLOCW { - #[doc = "Reset not caused by a loss of external clock."] - _0, - #[doc = "Reset caused by a loss of external clock."] - _1, + #[doc = "Reset not caused by a loss of external clock."] _0, + #[doc = "Reset caused by a loss of external clock."] _1, } impl SLOCW { #[allow(missing_docs)] @@ -675,10 +652,8 @@ impl<'a> _SLOCW<'a> { } #[doc = "Values that can be written to the field `SLOL`"] pub enum SLOLW { - #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] - _0, - #[doc = "Reset caused by a loss of lock in the PLL/FLL"] - _1, + #[doc = "Reset not caused by a loss of lock in the PLL/FLL"] _0, + #[doc = "Reset caused by a loss of lock in the PLL/FLL"] _1, } impl SLOLW { #[allow(missing_docs)] @@ -733,10 +708,8 @@ impl<'a> _SLOLW<'a> { } #[doc = "Values that can be written to the field `SWDOG`"] pub enum SWDOGW { - #[doc = "Reset not caused by watchdog timeout"] - _0, - #[doc = "Reset caused by watchdog timeout"] - _1, + #[doc = "Reset not caused by watchdog timeout"] _0, + #[doc = "Reset caused by watchdog timeout"] _1, } impl SWDOGW { #[allow(missing_docs)] @@ -791,10 +764,8 @@ impl<'a> _SWDOGW<'a> { } #[doc = "Values that can be written to the field `SPIN`"] pub enum SPINW { - #[doc = "Reset not caused by external reset pin"] - _0, - #[doc = "Reset caused by external reset pin"] - _1, + #[doc = "Reset not caused by external reset pin"] _0, + #[doc = "Reset caused by external reset pin"] _1, } impl SPINW { #[allow(missing_docs)] @@ -849,10 +820,8 @@ impl<'a> _SPINW<'a> { } #[doc = "Values that can be written to the field `SPOR`"] pub enum SPORW { - #[doc = "Reset not caused by POR"] - _0, - #[doc = "Reset caused by POR"] - _1, + #[doc = "Reset not caused by POR"] _0, + #[doc = "Reset caused by POR"] _1, } impl SPORW { #[allow(missing_docs)] @@ -907,10 +876,8 @@ impl<'a> _SPORW<'a> { } #[doc = "Values that can be written to the field `SJTAG`"] pub enum SJTAGW { - #[doc = "Reset not caused by JTAG"] - _0, - #[doc = "Reset caused by JTAG"] - _1, + #[doc = "Reset not caused by JTAG"] _0, + #[doc = "Reset caused by JTAG"] _1, } impl SJTAGW { #[allow(missing_docs)] @@ -965,10 +932,8 @@ impl<'a> _SJTAGW<'a> { } #[doc = "Values that can be written to the field `SLOCKUP`"] pub enum SLOCKUPW { - #[doc = "Reset not caused by core LOCKUP event"] - _0, - #[doc = "Reset caused by core LOCKUP event"] - _1, + #[doc = "Reset not caused by core LOCKUP event"] _0, + #[doc = "Reset caused by core LOCKUP event"] _1, } impl SLOCKUPW { #[allow(missing_docs)] @@ -1023,10 +988,8 @@ impl<'a> _SLOCKUPW<'a> { } #[doc = "Values that can be written to the field `SSW`"] pub enum SSWW { - #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] - _0, - #[doc = "Reset caused by software setting of SYSRESETREQ bit"] - _1, + #[doc = "Reset not caused by software setting of SYSRESETREQ bit"] _0, + #[doc = "Reset caused by software setting of SYSRESETREQ bit"] _1, } impl SSWW { #[allow(missing_docs)] @@ -1083,8 +1046,7 @@ impl<'a> _SSWW<'a> { pub enum SMDM_APW { #[doc = "Reset was not caused by host debugger system setting of the System Reset Request bit"] _0, - #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] - _1, + #[doc = "Reset was caused by host debugger system setting of the System Reset Request bit"] _1, } impl SMDM_APW { #[allow(missing_docs)] @@ -1139,10 +1101,8 @@ impl<'a> _SMDM_APW<'a> { } #[doc = "Values that can be written to the field `SSACKERR`"] pub enum SSACKERRW { - #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] - _0, - #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] - _1, + #[doc = "Reset not caused by peripheral failure to acknowledge attempt to enter stop mode"] _0, + #[doc = "Reset caused by peripheral failure to acknowledge attempt to enter stop mode"] _1, } impl SSACKERRW { #[allow(missing_docs)] diff --git a/src/rcm/verid/mod.rs b/src/rcm/verid/mod.rs index fb4ef38..bd928d6 100644 --- a/src/rcm/verid/mod.rs +++ b/src/rcm/verid/mod.rs @@ -6,16 +6,16 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard feature set."] - _11, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard feature set."] _11, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/rtc/cr/mod.rs b/src/rtc/cr/mod.rs index 1dcda34..befa0c9 100644 --- a/src/rtc/cr/mod.rs +++ b/src/rtc/cr/mod.rs @@ -22,7 +22,9 @@ impl super::CR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CR { #[doc = "Possible values of the field `SWR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SWRR { - #[doc = "No effect."] - _0, - #[doc = r" Reserved"] - _Reserved(bool), + #[doc = "No effect."] _0, + #[doc = r" Reserved"] _Reserved(bool), } impl SWRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -85,10 +85,8 @@ impl SWRR { #[doc = "Possible values of the field `SUP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SUPR { - #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] - _0, - #[doc = "Non-supervisor mode write accesses are supported."] - _1, + #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0, + #[doc = "Non-supervisor mode write accesses are supported."] _1, } impl SUPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -132,10 +130,8 @@ impl SUPR { #[doc = "Possible values of the field `UM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum UMR { - #[doc = "Registers cannot be written when locked."] - _0, - #[doc = "Registers can be written when locked under limited conditions."] - _1, + #[doc = "Registers cannot be written when locked."] _0, + #[doc = "Registers can be written when locked under limited conditions."] _1, } impl UMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -179,8 +175,7 @@ impl UMR { #[doc = "Possible values of the field `CPS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPSR { - #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] - _0, + #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0, #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."] _1, } @@ -226,10 +221,8 @@ impl CPSR { #[doc = "Possible values of the field `LPOS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPOSR { - #[doc = "RTC prescaler increments using 32kHz crystal."] - _0, - #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] - _1, + #[doc = "RTC prescaler increments using 32kHz crystal."] _0, + #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1, } impl LPOSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -273,10 +266,8 @@ impl LPOSR { #[doc = "Possible values of the field `CPE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CPER { - #[doc = "Disable RTC_CLKOUT pin."] - _0, - #[doc = "Enable RTC_CLKOUT pin."] - _1, + #[doc = "Disable RTC_CLKOUT pin."] _0, + #[doc = "Enable RTC_CLKOUT pin."] _1, } impl CPER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -319,8 +310,7 @@ impl CPER { } #[doc = "Values that can be written to the field `SWR`"] pub enum SWRW { - #[doc = "No effect."] - _0, + #[doc = "No effect."] _0, } impl SWRW { #[allow(missing_docs)] @@ -369,10 +359,8 @@ impl<'a> _SWRW<'a> { } #[doc = "Values that can be written to the field `SUP`"] pub enum SUPW { - #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] - _0, - #[doc = "Non-supervisor mode write accesses are supported."] - _1, + #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0, + #[doc = "Non-supervisor mode write accesses are supported."] _1, } impl SUPW { #[allow(missing_docs)] @@ -427,10 +415,8 @@ impl<'a> _SUPW<'a> { } #[doc = "Values that can be written to the field `UM`"] pub enum UMW { - #[doc = "Registers cannot be written when locked."] - _0, - #[doc = "Registers can be written when locked under limited conditions."] - _1, + #[doc = "Registers cannot be written when locked."] _0, + #[doc = "Registers can be written when locked under limited conditions."] _1, } impl UMW { #[allow(missing_docs)] @@ -485,8 +471,7 @@ impl<'a> _UMW<'a> { } #[doc = "Values that can be written to the field `CPS`"] pub enum CPSW { - #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] - _0, + #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0, #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."] _1, } @@ -543,10 +528,8 @@ impl<'a> _CPSW<'a> { } #[doc = "Values that can be written to the field `LPOS`"] pub enum LPOSW { - #[doc = "RTC prescaler increments using 32kHz crystal."] - _0, - #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] - _1, + #[doc = "RTC prescaler increments using 32kHz crystal."] _0, + #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1, } impl LPOSW { #[allow(missing_docs)] @@ -601,10 +584,8 @@ impl<'a> _LPOSW<'a> { } #[doc = "Values that can be written to the field `CPE`"] pub enum CPEW { - #[doc = "Disable RTC_CLKOUT pin."] - _0, - #[doc = "Enable RTC_CLKOUT pin."] - _1, + #[doc = "Disable RTC_CLKOUT pin."] _0, + #[doc = "Enable RTC_CLKOUT pin."] _1, } impl CPEW { #[allow(missing_docs)] diff --git a/src/rtc/ier/mod.rs b/src/rtc/ier/mod.rs index b7cd733..2b6f544 100644 --- a/src/rtc/ier/mod.rs +++ b/src/rtc/ier/mod.rs @@ -22,7 +22,9 @@ impl super::IER { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::IER { #[doc = "Possible values of the field `TIIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIIER { - #[doc = "Time invalid flag does not generate an interrupt."] - _0, - #[doc = "Time invalid flag does generate an interrupt."] - _1, + #[doc = "Time invalid flag does not generate an interrupt."] _0, + #[doc = "Time invalid flag does generate an interrupt."] _1, } impl TIIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TIIER { #[doc = "Possible values of the field `TOIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOIER { - #[doc = "Time overflow flag does not generate an interrupt."] - _0, - #[doc = "Time overflow flag does generate an interrupt."] - _1, + #[doc = "Time overflow flag does not generate an interrupt."] _0, + #[doc = "Time overflow flag does generate an interrupt."] _1, } impl TOIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl TOIER { #[doc = "Possible values of the field `TAIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TAIER { - #[doc = "Time alarm flag does not generate an interrupt."] - _0, - #[doc = "Time alarm flag does generate an interrupt."] - _1, + #[doc = "Time alarm flag does not generate an interrupt."] _0, + #[doc = "Time alarm flag does generate an interrupt."] _1, } impl TAIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl TAIER { #[doc = "Possible values of the field `TSIE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSIER { - #[doc = "Seconds interrupt is disabled."] - _0, - #[doc = "Seconds interrupt is enabled."] - _1, + #[doc = "Seconds interrupt is disabled."] _0, + #[doc = "Seconds interrupt is enabled."] _1, } impl TSIER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,22 +225,14 @@ impl TSIER { #[doc = "Possible values of the field `TSIC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSICR { - #[doc = "1 Hz."] - _000, - #[doc = "2 Hz."] - _001, - #[doc = "4 Hz."] - _010, - #[doc = "8 Hz."] - _011, - #[doc = "16 Hz."] - _100, - #[doc = "32 Hz."] - _101, - #[doc = "64 Hz."] - _110, - #[doc = "128 Hz."] - _111, + #[doc = "1 Hz."] _000, + #[doc = "2 Hz."] _001, + #[doc = "4 Hz."] _010, + #[doc = "8 Hz."] _011, + #[doc = "16 Hz."] _100, + #[doc = "32 Hz."] _101, + #[doc = "64 Hz."] _110, + #[doc = "128 Hz."] _111, } impl TSICR { #[doc = r" Value of the field as raw bits"] @@ -322,10 +308,8 @@ impl TSICR { } #[doc = "Values that can be written to the field `TIIE`"] pub enum TIIEW { - #[doc = "Time invalid flag does not generate an interrupt."] - _0, - #[doc = "Time invalid flag does generate an interrupt."] - _1, + #[doc = "Time invalid flag does not generate an interrupt."] _0, + #[doc = "Time invalid flag does generate an interrupt."] _1, } impl TIIEW { #[allow(missing_docs)] @@ -380,10 +364,8 @@ impl<'a> _TIIEW<'a> { } #[doc = "Values that can be written to the field `TOIE`"] pub enum TOIEW { - #[doc = "Time overflow flag does not generate an interrupt."] - _0, - #[doc = "Time overflow flag does generate an interrupt."] - _1, + #[doc = "Time overflow flag does not generate an interrupt."] _0, + #[doc = "Time overflow flag does generate an interrupt."] _1, } impl TOIEW { #[allow(missing_docs)] @@ -438,10 +420,8 @@ impl<'a> _TOIEW<'a> { } #[doc = "Values that can be written to the field `TAIE`"] pub enum TAIEW { - #[doc = "Time alarm flag does not generate an interrupt."] - _0, - #[doc = "Time alarm flag does generate an interrupt."] - _1, + #[doc = "Time alarm flag does not generate an interrupt."] _0, + #[doc = "Time alarm flag does generate an interrupt."] _1, } impl TAIEW { #[allow(missing_docs)] @@ -496,10 +476,8 @@ impl<'a> _TAIEW<'a> { } #[doc = "Values that can be written to the field `TSIE`"] pub enum TSIEW { - #[doc = "Seconds interrupt is disabled."] - _0, - #[doc = "Seconds interrupt is enabled."] - _1, + #[doc = "Seconds interrupt is disabled."] _0, + #[doc = "Seconds interrupt is enabled."] _1, } impl TSIEW { #[allow(missing_docs)] @@ -554,22 +532,14 @@ impl<'a> _TSIEW<'a> { } #[doc = "Values that can be written to the field `TSIC`"] pub enum TSICW { - #[doc = "1 Hz."] - _000, - #[doc = "2 Hz."] - _001, - #[doc = "4 Hz."] - _010, - #[doc = "8 Hz."] - _011, - #[doc = "16 Hz."] - _100, - #[doc = "32 Hz."] - _101, - #[doc = "64 Hz."] - _110, - #[doc = "128 Hz."] - _111, + #[doc = "1 Hz."] _000, + #[doc = "2 Hz."] _001, + #[doc = "4 Hz."] _010, + #[doc = "8 Hz."] _011, + #[doc = "16 Hz."] _100, + #[doc = "32 Hz."] _101, + #[doc = "64 Hz."] _110, + #[doc = "128 Hz."] _111, } impl TSICW { #[allow(missing_docs)] diff --git a/src/rtc/lr/mod.rs b/src/rtc/lr/mod.rs index 4f72aa8..5515d3b 100644 --- a/src/rtc/lr/mod.rs +++ b/src/rtc/lr/mod.rs @@ -22,7 +22,9 @@ impl super::LR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LR { #[doc = "Possible values of the field `TCL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCLR { - #[doc = "Time Compensation Register is locked and writes are ignored."] - _0, - #[doc = "Time Compensation Register is not locked and writes complete as normal."] - _1, + #[doc = "Time Compensation Register is locked and writes are ignored."] _0, + #[doc = "Time Compensation Register is not locked and writes complete as normal."] _1, } impl TCLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TCLR { #[doc = "Possible values of the field `CRL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CRLR { - #[doc = "Control Register is locked and writes are ignored."] - _0, - #[doc = "Control Register is not locked and writes complete as normal."] - _1, + #[doc = "Control Register is locked and writes are ignored."] _0, + #[doc = "Control Register is not locked and writes complete as normal."] _1, } impl CRLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CRLR { #[doc = "Possible values of the field `SRL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRLR { - #[doc = "Status Register is locked and writes are ignored."] - _0, - #[doc = "Status Register is not locked and writes complete as normal."] - _1, + #[doc = "Status Register is locked and writes are ignored."] _0, + #[doc = "Status Register is not locked and writes complete as normal."] _1, } impl SRLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SRLR { #[doc = "Possible values of the field `LRL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LRLR { - #[doc = "Lock Register is locked and writes are ignored."] - _0, - #[doc = "Lock Register is not locked and writes complete as normal."] - _1, + #[doc = "Lock Register is locked and writes are ignored."] _0, + #[doc = "Lock Register is not locked and writes complete as normal."] _1, } impl LRLR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl LRLR { } #[doc = "Values that can be written to the field `TCL`"] pub enum TCLW { - #[doc = "Time Compensation Register is locked and writes are ignored."] - _0, - #[doc = "Time Compensation Register is not locked and writes complete as normal."] - _1, + #[doc = "Time Compensation Register is locked and writes are ignored."] _0, + #[doc = "Time Compensation Register is not locked and writes complete as normal."] _1, } impl TCLW { #[allow(missing_docs)] @@ -288,10 +280,8 @@ impl<'a> _TCLW<'a> { } #[doc = "Values that can be written to the field `CRL`"] pub enum CRLW { - #[doc = "Control Register is locked and writes are ignored."] - _0, - #[doc = "Control Register is not locked and writes complete as normal."] - _1, + #[doc = "Control Register is locked and writes are ignored."] _0, + #[doc = "Control Register is not locked and writes complete as normal."] _1, } impl CRLW { #[allow(missing_docs)] @@ -346,10 +336,8 @@ impl<'a> _CRLW<'a> { } #[doc = "Values that can be written to the field `SRL`"] pub enum SRLW { - #[doc = "Status Register is locked and writes are ignored."] - _0, - #[doc = "Status Register is not locked and writes complete as normal."] - _1, + #[doc = "Status Register is locked and writes are ignored."] _0, + #[doc = "Status Register is not locked and writes complete as normal."] _1, } impl SRLW { #[allow(missing_docs)] @@ -404,10 +392,8 @@ impl<'a> _SRLW<'a> { } #[doc = "Values that can be written to the field `LRL`"] pub enum LRLW { - #[doc = "Lock Register is locked and writes are ignored."] - _0, - #[doc = "Lock Register is not locked and writes complete as normal."] - _1, + #[doc = "Lock Register is locked and writes are ignored."] _0, + #[doc = "Lock Register is not locked and writes complete as normal."] _1, } impl LRLW { #[allow(missing_docs)] diff --git a/src/rtc/mod.rs b/src/rtc/mod.rs index 6e41adf..210bbb6 100644 --- a/src/rtc/mod.rs +++ b/src/rtc/mod.rs @@ -2,22 +2,14 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - RTC Time Seconds Register"] - pub tsr: TSR, - #[doc = "0x04 - RTC Time Prescaler Register"] - pub tpr: TPR, - #[doc = "0x08 - RTC Time Alarm Register"] - pub tar: TAR, - #[doc = "0x0c - RTC Time Compensation Register"] - pub tcr: TCR, - #[doc = "0x10 - RTC Control Register"] - pub cr: CR, - #[doc = "0x14 - RTC Status Register"] - pub sr: SR, - #[doc = "0x18 - RTC Lock Register"] - pub lr: LR, - #[doc = "0x1c - RTC Interrupt Enable Register"] - pub ier: IER, + #[doc = "0x00 - RTC Time Seconds Register"] pub tsr: TSR, + #[doc = "0x04 - RTC Time Prescaler Register"] pub tpr: TPR, + #[doc = "0x08 - RTC Time Alarm Register"] pub tar: TAR, + #[doc = "0x0c - RTC Time Compensation Register"] pub tcr: TCR, + #[doc = "0x10 - RTC Control Register"] pub cr: CR, + #[doc = "0x14 - RTC Status Register"] pub sr: SR, + #[doc = "0x18 - RTC Lock Register"] pub lr: LR, + #[doc = "0x1c - RTC Interrupt Enable Register"] pub ier: IER, } #[doc = "RTC Time Seconds Register"] pub struct TSR { diff --git a/src/rtc/sr/mod.rs b/src/rtc/sr/mod.rs index 5daa947..bf39ba0 100644 --- a/src/rtc/sr/mod.rs +++ b/src/rtc/sr/mod.rs @@ -22,7 +22,9 @@ impl super::SR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SR { #[doc = "Possible values of the field `TIF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIFR { - #[doc = "Time is valid."] - _0, - #[doc = "Time is invalid and time counter is read as zero."] - _1, + #[doc = "Time is valid."] _0, + #[doc = "Time is invalid and time counter is read as zero."] _1, } impl TIFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl TIFR { #[doc = "Possible values of the field `TOF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TOFR { - #[doc = "Time overflow has not occurred."] - _0, - #[doc = "Time overflow has occurred and time counter is read as zero."] - _1, + #[doc = "Time overflow has not occurred."] _0, + #[doc = "Time overflow has occurred and time counter is read as zero."] _1, } impl TOFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl TOFR { #[doc = "Possible values of the field `TAF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TAFR { - #[doc = "Time alarm has not occurred."] - _0, - #[doc = "Time alarm has occurred."] - _1, + #[doc = "Time alarm has not occurred."] _0, + #[doc = "Time alarm has occurred."] _1, } impl TAFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl TAFR { #[doc = "Possible values of the field `TCE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCER { - #[doc = "Time counter is disabled."] - _0, - #[doc = "Time counter is enabled."] - _1, + #[doc = "Time counter is disabled."] _0, + #[doc = "Time counter is enabled."] _1, } impl TCER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -230,10 +224,8 @@ impl TCER { } #[doc = "Values that can be written to the field `TCE`"] pub enum TCEW { - #[doc = "Time counter is disabled."] - _0, - #[doc = "Time counter is enabled."] - _1, + #[doc = "Time counter is disabled."] _0, + #[doc = "Time counter is enabled."] _1, } impl TCEW { #[allow(missing_docs)] diff --git a/src/rtc/tar/mod.rs b/src/rtc/tar/mod.rs index 10b2dce..76ab64a 100644 --- a/src/rtc/tar/mod.rs +++ b/src/rtc/tar/mod.rs @@ -22,7 +22,9 @@ impl super::TAR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/rtc/tcr/mod.rs b/src/rtc/tcr/mod.rs index 44938d7..3f097db 100644 --- a/src/rtc/tcr/mod.rs +++ b/src/rtc/tcr/mod.rs @@ -22,7 +22,9 @@ impl super::TCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::TCR { #[doc = "Possible values of the field `TCR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TCRR { - #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] - _10000000, - #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] - _10000001, - #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] - _11111111, - #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] - _00000000, - #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] - _00000001, - #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] - _01111110, - #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] - _01111111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000, + #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001, + #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111, + #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000, + #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001, + #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110, + #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111, + #[doc = r" Reserved"] _Reserved(u8), } impl TCRR { #[doc = r" Value of the field as raw bits"] @@ -161,20 +155,13 @@ impl CICR { } #[doc = "Values that can be written to the field `TCR`"] pub enum TCRW { - #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] - _10000000, - #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] - _10000001, - #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] - _11111111, - #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] - _00000000, - #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] - _00000001, - #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] - _01111110, - #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] - _01111111, + #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000, + #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001, + #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111, + #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000, + #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001, + #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110, + #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111, } impl TCRW { #[allow(missing_docs)] diff --git a/src/rtc/tpr/mod.rs b/src/rtc/tpr/mod.rs index 6088934..9a81c71 100644 --- a/src/rtc/tpr/mod.rs +++ b/src/rtc/tpr/mod.rs @@ -22,7 +22,9 @@ impl super::TPR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/rtc/tsr/mod.rs b/src/rtc/tsr/mod.rs index 3445cee..45ba113 100644 --- a/src/rtc/tsr/mod.rs +++ b/src/rtc/tsr/mod.rs @@ -22,7 +22,9 @@ impl super::TSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/scg/clkoutcnfg/mod.rs b/src/scg/clkoutcnfg/mod.rs index c0a8e23..03604dd 100644 --- a/src/scg/clkoutcnfg/mod.rs +++ b/src/scg/clkoutcnfg/mod.rs @@ -22,7 +22,9 @@ impl super::CLKOUTCNFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,18 +45,12 @@ impl super::CLKOUTCNFG { #[doc = "Possible values of the field `CLKOUTSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKOUTSELR { - #[doc = "SCG SLOW Clock"] - _0000, - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "SCG SLOW Clock"] _0000, + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, + #[doc = r" Reserved"] _Reserved(u8), } impl CLKOUTSELR { #[doc = r" Value of the field as raw bits"] @@ -110,16 +106,11 @@ impl CLKOUTSELR { } #[doc = "Values that can be written to the field `CLKOUTSEL`"] pub enum CLKOUTSELW { - #[doc = "SCG SLOW Clock"] - _0000, - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, + #[doc = "SCG SLOW Clock"] _0000, + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, } impl CLKOUTSELW { #[allow(missing_docs)] diff --git a/src/scg/csr/mod.rs b/src/scg/csr/mod.rs index 38bec82..03d89f6 100644 --- a/src/scg/csr/mod.rs +++ b/src/scg/csr/mod.rs @@ -6,30 +6,23 @@ impl super::CSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `DIVSLOW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVSLOWR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = r" Reserved"] _Reserved(u8), } impl DIVSLOWR { #[doc = r" Value of the field as raw bits"] @@ -107,38 +100,22 @@ impl DIVSLOWR { #[doc = "Possible values of the field `DIVBUS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVBUSR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSR { #[doc = r" Value of the field as raw bits"] @@ -271,38 +248,22 @@ impl DIVBUSR { #[doc = "Possible values of the field `DIVCORE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVCORER { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCORER { #[doc = r" Value of the field as raw bits"] @@ -435,16 +396,11 @@ impl DIVCORER { #[doc = "Possible values of the field `SCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SCSR { - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, + #[doc = r" Reserved"] _Reserved(u8), } impl SCSR { #[doc = r" Value of the field as raw bits"] diff --git a/src/scg/firccfg/mod.rs b/src/scg/firccfg/mod.rs index f6f35ce..c5337d2 100644 --- a/src/scg/firccfg/mod.rs +++ b/src/scg/firccfg/mod.rs @@ -22,7 +22,9 @@ impl super::FIRCCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::FIRCCFG { #[doc = "Possible values of the field `RANGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RANGER { - #[doc = "Fast IRC is trimmed to 48 MHz"] - _00, - #[doc = "Fast IRC is trimmed to 52 MHz"] - _01, - #[doc = "Fast IRC is trimmed to 56 MHz"] - _10, - #[doc = "Fast IRC is trimmed to 60 MHz"] - _11, + #[doc = "Fast IRC is trimmed to 48 MHz"] _00, + #[doc = "Fast IRC is trimmed to 52 MHz"] _01, + #[doc = "Fast IRC is trimmed to 56 MHz"] _10, + #[doc = "Fast IRC is trimmed to 60 MHz"] _11, } impl RANGER { #[doc = r" Value of the field as raw bits"] @@ -98,14 +96,10 @@ impl RANGER { } #[doc = "Values that can be written to the field `RANGE`"] pub enum RANGEW { - #[doc = "Fast IRC is trimmed to 48 MHz"] - _00, - #[doc = "Fast IRC is trimmed to 52 MHz"] - _01, - #[doc = "Fast IRC is trimmed to 56 MHz"] - _10, - #[doc = "Fast IRC is trimmed to 60 MHz"] - _11, + #[doc = "Fast IRC is trimmed to 48 MHz"] _00, + #[doc = "Fast IRC is trimmed to 52 MHz"] _01, + #[doc = "Fast IRC is trimmed to 56 MHz"] _10, + #[doc = "Fast IRC is trimmed to 60 MHz"] _11, } impl RANGEW { #[allow(missing_docs)] diff --git a/src/scg/firccsr/mod.rs b/src/scg/firccsr/mod.rs index 6618b23..57704dd 100644 --- a/src/scg/firccsr/mod.rs +++ b/src/scg/firccsr/mod.rs @@ -22,7 +22,9 @@ impl super::FIRCCSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::FIRCCSR { #[doc = "Possible values of the field `FIRCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCENR { - #[doc = "Fast IRC is disabled"] - _0, - #[doc = "Fast IRC is enabled"] - _1, + #[doc = "Fast IRC is disabled"] _0, + #[doc = "Fast IRC is enabled"] _1, } impl FIRCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl FIRCENR { #[doc = "Possible values of the field `FIRCREGOFF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCREGOFFR { - #[doc = "Fast IRC Regulator is enabled."] - _0, - #[doc = "Fast IRC Regulator is disabled."] - _1, + #[doc = "Fast IRC Regulator is enabled."] _0, + #[doc = "Fast IRC Regulator is disabled."] _1, } impl FIRCREGOFFR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl FIRCREGOFFR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,8 +180,7 @@ impl LKR { #[doc = "Possible values of the field `FIRCVLD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCVLDR { - #[doc = "Fast IRC is not enabled or clock is not valid."] - _0, + #[doc = "Fast IRC is not enabled or clock is not valid."] _0, #[doc = "Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog."] _1, } @@ -231,10 +226,8 @@ impl FIRCVLDR { #[doc = "Possible values of the field `FIRCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCSELR { - #[doc = "Fast IRC is not the system clock source"] - _0, - #[doc = "Fast IRC is the system clock source"] - _1, + #[doc = "Fast IRC is not the system clock source"] _0, + #[doc = "Fast IRC is the system clock source"] _1, } impl FIRCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +271,8 @@ impl FIRCSELR { #[doc = "Possible values of the field `FIRCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCERRR { - #[doc = "Error not detected with the Fast IRC trimming."] - _0, - #[doc = "Error detected with the Fast IRC trimming."] - _1, + #[doc = "Error not detected with the Fast IRC trimming."] _0, + #[doc = "Error detected with the Fast IRC trimming."] _1, } impl FIRCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -324,10 +315,8 @@ impl FIRCERRR { } #[doc = "Values that can be written to the field `FIRCEN`"] pub enum FIRCENW { - #[doc = "Fast IRC is disabled"] - _0, - #[doc = "Fast IRC is enabled"] - _1, + #[doc = "Fast IRC is disabled"] _0, + #[doc = "Fast IRC is enabled"] _1, } impl FIRCENW { #[allow(missing_docs)] @@ -382,10 +371,8 @@ impl<'a> _FIRCENW<'a> { } #[doc = "Values that can be written to the field `FIRCREGOFF`"] pub enum FIRCREGOFFW { - #[doc = "Fast IRC Regulator is enabled."] - _0, - #[doc = "Fast IRC Regulator is disabled."] - _1, + #[doc = "Fast IRC Regulator is enabled."] _0, + #[doc = "Fast IRC Regulator is disabled."] _1, } impl FIRCREGOFFW { #[allow(missing_docs)] @@ -440,10 +427,8 @@ impl<'a> _FIRCREGOFFW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKW { #[allow(missing_docs)] @@ -498,10 +483,8 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `FIRCERR`"] pub enum FIRCERRW { - #[doc = "Error not detected with the Fast IRC trimming."] - _0, - #[doc = "Error detected with the Fast IRC trimming."] - _1, + #[doc = "Error not detected with the Fast IRC trimming."] _0, + #[doc = "Error detected with the Fast IRC trimming."] _1, } impl FIRCERRW { #[allow(missing_docs)] diff --git a/src/scg/fircdiv/mod.rs b/src/scg/fircdiv/mod.rs index 1aaf428..b88f058 100644 --- a/src/scg/fircdiv/mod.rs +++ b/src/scg/fircdiv/mod.rs @@ -22,7 +22,9 @@ impl super::FIRCDIV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::FIRCDIV { #[doc = "Possible values of the field `FIRCDIV1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCDIV1R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl FIRCDIV1R { #[doc = r" Value of the field as raw bits"] @@ -135,22 +129,14 @@ impl FIRCDIV1R { #[doc = "Possible values of the field `FIRCDIV2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FIRCDIV2R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl FIRCDIV2R { #[doc = r" Value of the field as raw bits"] @@ -226,22 +212,14 @@ impl FIRCDIV2R { } #[doc = "Values that can be written to the field `FIRCDIV1`"] pub enum FIRCDIV1W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl FIRCDIV1W { #[allow(missing_docs)] @@ -324,22 +302,14 @@ impl<'a> _FIRCDIV1W<'a> { } #[doc = "Values that can be written to the field `FIRCDIV2`"] pub enum FIRCDIV2W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl FIRCDIV2W { #[allow(missing_docs)] diff --git a/src/scg/hccr/mod.rs b/src/scg/hccr/mod.rs index 0c73716..1c924d7 100644 --- a/src/scg/hccr/mod.rs +++ b/src/scg/hccr/mod.rs @@ -22,7 +22,9 @@ impl super::HCCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,24 +45,15 @@ impl super::HCCR { #[doc = "Possible values of the field `DIVSLOW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVSLOWR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = r" Reserved"] _Reserved(u8), } impl DIVSLOWR { #[doc = r" Value of the field as raw bits"] @@ -138,38 +131,22 @@ impl DIVSLOWR { #[doc = "Possible values of the field `DIVBUS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVBUSR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSR { #[doc = r" Value of the field as raw bits"] @@ -302,38 +279,22 @@ impl DIVBUSR { #[doc = "Possible values of the field `DIVCORE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVCORER { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCORER { #[doc = r" Value of the field as raw bits"] @@ -466,16 +427,11 @@ impl DIVCORER { #[doc = "Possible values of the field `SCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SCSR { - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, + #[doc = r" Reserved"] _Reserved(u8), } impl SCSR { #[doc = r" Value of the field as raw bits"] @@ -524,22 +480,14 @@ impl SCSR { } #[doc = "Values that can be written to the field `DIVSLOW`"] pub enum DIVSLOWW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, } impl DIVSLOWW { #[allow(missing_docs)] @@ -620,38 +568,22 @@ impl<'a> _DIVSLOWW<'a> { } #[doc = "Values that can be written to the field `DIVBUS`"] pub enum DIVBUSW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSW { #[allow(missing_docs)] @@ -782,38 +714,22 @@ impl<'a> _DIVBUSW<'a> { } #[doc = "Values that can be written to the field `DIVCORE`"] pub enum DIVCOREW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCOREW { #[allow(missing_docs)] @@ -944,14 +860,10 @@ impl<'a> _DIVCOREW<'a> { } #[doc = "Values that can be written to the field `SCS`"] pub enum SCSW { - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, } impl SCSW { #[allow(missing_docs)] diff --git a/src/scg/mod.rs b/src/scg/mod.rs index 446f3d3..e0c8bd2 100644 --- a/src/scg/mod.rs +++ b/src/scg/mod.rs @@ -2,49 +2,30 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - Parameter Register"] - pub param: PARAM, + #[doc = "0x00 - Version ID Register"] pub verid: VERID, + #[doc = "0x04 - Parameter Register"] pub param: PARAM, _reserved0: [u8; 8usize], - #[doc = "0x10 - Clock Status Register"] - pub csr: CSR, - #[doc = "0x14 - Run Clock Control Register"] - pub rccr: RCCR, - #[doc = "0x18 - VLPR Clock Control Register"] - pub vccr: VCCR, - #[doc = "0x1c - HSRUN Clock Control Register"] - pub hccr: HCCR, - #[doc = "0x20 - SCG CLKOUT Configuration Register"] - pub clkoutcnfg: CLKOUTCNFG, + #[doc = "0x10 - Clock Status Register"] pub csr: CSR, + #[doc = "0x14 - Run Clock Control Register"] pub rccr: RCCR, + #[doc = "0x18 - VLPR Clock Control Register"] pub vccr: VCCR, + #[doc = "0x1c - HSRUN Clock Control Register"] pub hccr: HCCR, + #[doc = "0x20 - SCG CLKOUT Configuration Register"] pub clkoutcnfg: CLKOUTCNFG, _reserved1: [u8; 220usize], - #[doc = "0x100 - System OSC Control Status Register"] - pub sosccsr: SOSCCSR, - #[doc = "0x104 - System OSC Divide Register"] - pub soscdiv: SOSCDIV, - #[doc = "0x108 - System Oscillator Configuration Register"] - pub sosccfg: SOSCCFG, + #[doc = "0x100 - System OSC Control Status Register"] pub sosccsr: SOSCCSR, + #[doc = "0x104 - System OSC Divide Register"] pub soscdiv: SOSCDIV, + #[doc = "0x108 - System Oscillator Configuration Register"] pub sosccfg: SOSCCFG, _reserved2: [u8; 244usize], - #[doc = "0x200 - Slow IRC Control Status Register"] - pub sirccsr: SIRCCSR, - #[doc = "0x204 - Slow IRC Divide Register"] - pub sircdiv: SIRCDIV, - #[doc = "0x208 - Slow IRC Configuration Register"] - pub sirccfg: SIRCCFG, + #[doc = "0x200 - Slow IRC Control Status Register"] pub sirccsr: SIRCCSR, + #[doc = "0x204 - Slow IRC Divide Register"] pub sircdiv: SIRCDIV, + #[doc = "0x208 - Slow IRC Configuration Register"] pub sirccfg: SIRCCFG, _reserved3: [u8; 244usize], - #[doc = "0x300 - Fast IRC Control Status Register"] - pub firccsr: FIRCCSR, - #[doc = "0x304 - Fast IRC Divide Register"] - pub fircdiv: FIRCDIV, - #[doc = "0x308 - Fast IRC Configuration Register"] - pub firccfg: FIRCCFG, + #[doc = "0x300 - Fast IRC Control Status Register"] pub firccsr: FIRCCSR, + #[doc = "0x304 - Fast IRC Divide Register"] pub fircdiv: FIRCDIV, + #[doc = "0x308 - Fast IRC Configuration Register"] pub firccfg: FIRCCFG, _reserved4: [u8; 756usize], - #[doc = "0x600 - System PLL Control Status Register"] - pub spllcsr: SPLLCSR, - #[doc = "0x604 - System PLL Divide Register"] - pub splldiv: SPLLDIV, - #[doc = "0x608 - System PLL Configuration Register"] - pub spllcfg: SPLLCFG, + #[doc = "0x600 - System PLL Control Status Register"] pub spllcsr: SPLLCSR, + #[doc = "0x604 - System PLL Divide Register"] pub splldiv: SPLLDIV, + #[doc = "0x608 - System PLL Configuration Register"] pub spllcfg: SPLLCFG, } #[doc = "Version ID Register"] pub struct VERID { diff --git a/src/scg/param/mod.rs b/src/scg/param/mod.rs index 3e7c750..53a351b 100644 --- a/src/scg/param/mod.rs +++ b/src/scg/param/mod.rs @@ -6,7 +6,9 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/scg/rccr/mod.rs b/src/scg/rccr/mod.rs index 8353b0f..f5952ec 100644 --- a/src/scg/rccr/mod.rs +++ b/src/scg/rccr/mod.rs @@ -22,7 +22,9 @@ impl super::RCCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,24 +45,15 @@ impl super::RCCR { #[doc = "Possible values of the field `DIVSLOW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVSLOWR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = r" Reserved"] _Reserved(u8), } impl DIVSLOWR { #[doc = r" Value of the field as raw bits"] @@ -138,38 +131,22 @@ impl DIVSLOWR { #[doc = "Possible values of the field `DIVBUS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVBUSR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSR { #[doc = r" Value of the field as raw bits"] @@ -302,38 +279,22 @@ impl DIVBUSR { #[doc = "Possible values of the field `DIVCORE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVCORER { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCORER { #[doc = r" Value of the field as raw bits"] @@ -466,16 +427,11 @@ impl DIVCORER { #[doc = "Possible values of the field `SCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SCSR { - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, + #[doc = r" Reserved"] _Reserved(u8), } impl SCSR { #[doc = r" Value of the field as raw bits"] @@ -524,22 +480,14 @@ impl SCSR { } #[doc = "Values that can be written to the field `DIVSLOW`"] pub enum DIVSLOWW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, } impl DIVSLOWW { #[allow(missing_docs)] @@ -620,38 +568,22 @@ impl<'a> _DIVSLOWW<'a> { } #[doc = "Values that can be written to the field `DIVBUS`"] pub enum DIVBUSW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSW { #[allow(missing_docs)] @@ -782,38 +714,22 @@ impl<'a> _DIVBUSW<'a> { } #[doc = "Values that can be written to the field `DIVCORE`"] pub enum DIVCOREW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCOREW { #[allow(missing_docs)] @@ -944,14 +860,10 @@ impl<'a> _DIVCOREW<'a> { } #[doc = "Values that can be written to the field `SCS`"] pub enum SCSW { - #[doc = "System OSC (SOSC_CLK)"] - _0001, - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = "Fast IRC (FIRC_CLK)"] - _0011, - #[doc = "System PLL (SPLL_CLK)"] - _0110, + #[doc = "System OSC (SOSC_CLK)"] _0001, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = "Fast IRC (FIRC_CLK)"] _0011, + #[doc = "System PLL (SPLL_CLK)"] _0110, } impl SCSW { #[allow(missing_docs)] diff --git a/src/scg/sirccfg/mod.rs b/src/scg/sirccfg/mod.rs index 0d7adab..296c75a 100644 --- a/src/scg/sirccfg/mod.rs +++ b/src/scg/sirccfg/mod.rs @@ -22,7 +22,9 @@ impl super::SIRCCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SIRCCFG { #[doc = "Possible values of the field `RANGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RANGER { - #[doc = "Slow IRC low range clock (2 MHz)"] - _0, - #[doc = "Slow IRC high range clock (8 MHz )"] - _1, + #[doc = "Slow IRC low range clock (2 MHz)"] _0, + #[doc = "Slow IRC high range clock (8 MHz )"] _1, } impl RANGER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -89,10 +89,8 @@ impl RANGER { } #[doc = "Values that can be written to the field `RANGE`"] pub enum RANGEW { - #[doc = "Slow IRC low range clock (2 MHz)"] - _0, - #[doc = "Slow IRC high range clock (8 MHz )"] - _1, + #[doc = "Slow IRC low range clock (2 MHz)"] _0, + #[doc = "Slow IRC high range clock (8 MHz )"] _1, } impl RANGEW { #[allow(missing_docs)] diff --git a/src/scg/sirccsr/mod.rs b/src/scg/sirccsr/mod.rs index e266c31..2778190 100644 --- a/src/scg/sirccsr/mod.rs +++ b/src/scg/sirccsr/mod.rs @@ -22,7 +22,9 @@ impl super::SIRCCSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SIRCCSR { #[doc = "Possible values of the field `SIRCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCENR { - #[doc = "Slow IRC is disabled"] - _0, - #[doc = "Slow IRC is enabled"] - _1, + #[doc = "Slow IRC is disabled"] _0, + #[doc = "Slow IRC is enabled"] _1, } impl SIRCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SIRCENR { #[doc = "Possible values of the field `SIRCSTEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCSTENR { - #[doc = "Slow IRC is disabled in supported Stop modes"] - _0, - #[doc = "Slow IRC is enabled in supported Stop modes"] - _1, + #[doc = "Slow IRC is disabled in supported Stop modes"] _0, + #[doc = "Slow IRC is enabled in supported Stop modes"] _1, } impl SIRCSTENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SIRCSTENR { #[doc = "Possible values of the field `SIRCLPEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCLPENR { - #[doc = "Slow IRC is disabled in VLP modes"] - _0, - #[doc = "Slow IRC is enabled in VLP modes"] - _1, + #[doc = "Slow IRC is disabled in VLP modes"] _0, + #[doc = "Slow IRC is enabled in VLP modes"] _1, } impl SIRCLPENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SIRCLPENR { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl LKR { #[doc = "Possible values of the field `SIRCVLD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCVLDR { - #[doc = "Slow IRC is not enabled or clock is not valid"] - _0, - #[doc = "Slow IRC is enabled and output clock is valid"] - _1, + #[doc = "Slow IRC is not enabled or clock is not valid"] _0, + #[doc = "Slow IRC is enabled and output clock is valid"] _1, } impl SIRCVLDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl SIRCVLDR { #[doc = "Possible values of the field `SIRCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCSELR { - #[doc = "Slow IRC is not the system clock source"] - _0, - #[doc = "Slow IRC is the system clock source"] - _1, + #[doc = "Slow IRC is not the system clock source"] _0, + #[doc = "Slow IRC is the system clock source"] _1, } impl SIRCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -324,10 +314,8 @@ impl SIRCSELR { } #[doc = "Values that can be written to the field `SIRCEN`"] pub enum SIRCENW { - #[doc = "Slow IRC is disabled"] - _0, - #[doc = "Slow IRC is enabled"] - _1, + #[doc = "Slow IRC is disabled"] _0, + #[doc = "Slow IRC is enabled"] _1, } impl SIRCENW { #[allow(missing_docs)] @@ -382,10 +370,8 @@ impl<'a> _SIRCENW<'a> { } #[doc = "Values that can be written to the field `SIRCSTEN`"] pub enum SIRCSTENW { - #[doc = "Slow IRC is disabled in supported Stop modes"] - _0, - #[doc = "Slow IRC is enabled in supported Stop modes"] - _1, + #[doc = "Slow IRC is disabled in supported Stop modes"] _0, + #[doc = "Slow IRC is enabled in supported Stop modes"] _1, } impl SIRCSTENW { #[allow(missing_docs)] @@ -440,10 +426,8 @@ impl<'a> _SIRCSTENW<'a> { } #[doc = "Values that can be written to the field `SIRCLPEN`"] pub enum SIRCLPENW { - #[doc = "Slow IRC is disabled in VLP modes"] - _0, - #[doc = "Slow IRC is enabled in VLP modes"] - _1, + #[doc = "Slow IRC is disabled in VLP modes"] _0, + #[doc = "Slow IRC is enabled in VLP modes"] _1, } impl SIRCLPENW { #[allow(missing_docs)] @@ -498,10 +482,8 @@ impl<'a> _SIRCLPENW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/scg/sircdiv/mod.rs b/src/scg/sircdiv/mod.rs index 262faaf..56b8db7 100644 --- a/src/scg/sircdiv/mod.rs +++ b/src/scg/sircdiv/mod.rs @@ -22,7 +22,9 @@ impl super::SIRCDIV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SIRCDIV { #[doc = "Possible values of the field `SIRCDIV1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCDIV1R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SIRCDIV1R { #[doc = r" Value of the field as raw bits"] @@ -135,22 +129,14 @@ impl SIRCDIV1R { #[doc = "Possible values of the field `SIRCDIV2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SIRCDIV2R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SIRCDIV2R { #[doc = r" Value of the field as raw bits"] @@ -226,22 +212,14 @@ impl SIRCDIV2R { } #[doc = "Values that can be written to the field `SIRCDIV1`"] pub enum SIRCDIV1W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SIRCDIV1W { #[allow(missing_docs)] @@ -324,22 +302,14 @@ impl<'a> _SIRCDIV1W<'a> { } #[doc = "Values that can be written to the field `SIRCDIV2`"] pub enum SIRCDIV2W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SIRCDIV2W { #[allow(missing_docs)] diff --git a/src/scg/sosccfg/mod.rs b/src/scg/sosccfg/mod.rs index 91234a2..bddef0f 100644 --- a/src/scg/sosccfg/mod.rs +++ b/src/scg/sosccfg/mod.rs @@ -22,7 +22,9 @@ impl super::SOSCCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SOSCCFG { #[doc = "Possible values of the field `EREFS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EREFSR { - #[doc = "External reference clock selected"] - _0, - #[doc = "Internal crystal oscillator of OSC selected."] - _1, + #[doc = "External reference clock selected"] _0, + #[doc = "Internal crystal oscillator of OSC selected."] _1, } impl EREFSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl EREFSR { #[doc = "Possible values of the field `HGO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HGOR { - #[doc = "Configure crystal oscillator for low-gain operation"] - _0, - #[doc = "Configure crystal oscillator for high-gain operation"] - _1, + #[doc = "Configure crystal oscillator for low-gain operation"] _0, + #[doc = "Configure crystal oscillator for high-gain operation"] _1, } impl HGOR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl HGOR { #[doc = "Possible values of the field `RANGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RANGER { - #[doc = "Low frequency range selected for the crystal oscillator"] - _01, - #[doc = "Medium frequency range selected for the crytstal oscillator"] - _10, - #[doc = "High frequency range selected for the crystal oscillator"] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Low frequency range selected for the crystal oscillator"] _01, + #[doc = "Medium frequency range selected for the crytstal oscillator"] _10, + #[doc = "High frequency range selected for the crystal oscillator"] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl RANGER { #[doc = r" Value of the field as raw bits"] @@ -186,10 +180,8 @@ impl RANGER { } #[doc = "Values that can be written to the field `EREFS`"] pub enum EREFSW { - #[doc = "External reference clock selected"] - _0, - #[doc = "Internal crystal oscillator of OSC selected."] - _1, + #[doc = "External reference clock selected"] _0, + #[doc = "Internal crystal oscillator of OSC selected."] _1, } impl EREFSW { #[allow(missing_docs)] @@ -244,10 +236,8 @@ impl<'a> _EREFSW<'a> { } #[doc = "Values that can be written to the field `HGO`"] pub enum HGOW { - #[doc = "Configure crystal oscillator for low-gain operation"] - _0, - #[doc = "Configure crystal oscillator for high-gain operation"] - _1, + #[doc = "Configure crystal oscillator for low-gain operation"] _0, + #[doc = "Configure crystal oscillator for high-gain operation"] _1, } impl HGOW { #[allow(missing_docs)] @@ -302,12 +292,9 @@ impl<'a> _HGOW<'a> { } #[doc = "Values that can be written to the field `RANGE`"] pub enum RANGEW { - #[doc = "Low frequency range selected for the crystal oscillator"] - _01, - #[doc = "Medium frequency range selected for the crytstal oscillator"] - _10, - #[doc = "High frequency range selected for the crystal oscillator"] - _11, + #[doc = "Low frequency range selected for the crystal oscillator"] _01, + #[doc = "Medium frequency range selected for the crytstal oscillator"] _10, + #[doc = "High frequency range selected for the crystal oscillator"] _11, } impl RANGEW { #[allow(missing_docs)] diff --git a/src/scg/sosccsr/mod.rs b/src/scg/sosccsr/mod.rs index f7be46d..35d1556 100644 --- a/src/scg/sosccsr/mod.rs +++ b/src/scg/sosccsr/mod.rs @@ -22,7 +22,9 @@ impl super::SOSCCSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SOSCCSR { #[doc = "Possible values of the field `SOSCEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCENR { - #[doc = "System OSC is disabled"] - _0, - #[doc = "System OSC is enabled"] - _1, + #[doc = "System OSC is disabled"] _0, + #[doc = "System OSC is enabled"] _1, } impl SOSCENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SOSCENR { #[doc = "Possible values of the field `SOSCCM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCCMR { - #[doc = "System OSC Clock Monitor is disabled"] - _0, - #[doc = "System OSC Clock Monitor is enabled"] - _1, + #[doc = "System OSC Clock Monitor is disabled"] _0, + #[doc = "System OSC Clock Monitor is enabled"] _1, } impl SOSCCMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SOSCCMR { #[doc = "Possible values of the field `SOSCCMRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCCMRER { - #[doc = "Clock Monitor generates interrupt when error detected"] - _0, - #[doc = "Clock Monitor generates reset when error detected"] - _1, + #[doc = "Clock Monitor generates interrupt when error detected"] _0, + #[doc = "Clock Monitor generates reset when error detected"] _1, } impl SOSCCMRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SOSCCMRER { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "This Control Status Register can be written."] - _0, - #[doc = "This Control Status Register cannot be written."] - _1, + #[doc = "This Control Status Register can be written."] _0, + #[doc = "This Control Status Register cannot be written."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl LKR { #[doc = "Possible values of the field `SOSCVLD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCVLDR { - #[doc = "System OSC is not enabled or clock is not valid"] - _0, - #[doc = "System OSC is enabled and output clock is valid"] - _1, + #[doc = "System OSC is not enabled or clock is not valid"] _0, + #[doc = "System OSC is enabled and output clock is valid"] _1, } impl SOSCVLDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl SOSCVLDR { #[doc = "Possible values of the field `SOSCSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCSELR { - #[doc = "System OSC is not the system clock source"] - _0, - #[doc = "System OSC is the system clock source"] - _1, + #[doc = "System OSC is not the system clock source"] _0, + #[doc = "System OSC is the system clock source"] _1, } impl SOSCSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,10 +315,8 @@ impl SOSCSELR { #[doc = "Possible values of the field `SOSCERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCERRR { - #[doc = "System OSC Clock Monitor is disabled or has not detected an error"] - _0, - #[doc = "System OSC Clock Monitor is enabled and detected an error"] - _1, + #[doc = "System OSC Clock Monitor is disabled or has not detected an error"] _0, + #[doc = "System OSC Clock Monitor is enabled and detected an error"] _1, } impl SOSCERRR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -371,10 +359,8 @@ impl SOSCERRR { } #[doc = "Values that can be written to the field `SOSCEN`"] pub enum SOSCENW { - #[doc = "System OSC is disabled"] - _0, - #[doc = "System OSC is enabled"] - _1, + #[doc = "System OSC is disabled"] _0, + #[doc = "System OSC is enabled"] _1, } impl SOSCENW { #[allow(missing_docs)] @@ -429,10 +415,8 @@ impl<'a> _SOSCENW<'a> { } #[doc = "Values that can be written to the field `SOSCCM`"] pub enum SOSCCMW { - #[doc = "System OSC Clock Monitor is disabled"] - _0, - #[doc = "System OSC Clock Monitor is enabled"] - _1, + #[doc = "System OSC Clock Monitor is disabled"] _0, + #[doc = "System OSC Clock Monitor is enabled"] _1, } impl SOSCCMW { #[allow(missing_docs)] @@ -487,10 +471,8 @@ impl<'a> _SOSCCMW<'a> { } #[doc = "Values that can be written to the field `SOSCCMRE`"] pub enum SOSCCMREW { - #[doc = "Clock Monitor generates interrupt when error detected"] - _0, - #[doc = "Clock Monitor generates reset when error detected"] - _1, + #[doc = "Clock Monitor generates interrupt when error detected"] _0, + #[doc = "Clock Monitor generates reset when error detected"] _1, } impl SOSCCMREW { #[allow(missing_docs)] @@ -545,10 +527,8 @@ impl<'a> _SOSCCMREW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "This Control Status Register can be written."] - _0, - #[doc = "This Control Status Register cannot be written."] - _1, + #[doc = "This Control Status Register can be written."] _0, + #[doc = "This Control Status Register cannot be written."] _1, } impl LKW { #[allow(missing_docs)] @@ -603,10 +583,8 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `SOSCERR`"] pub enum SOSCERRW { - #[doc = "System OSC Clock Monitor is disabled or has not detected an error"] - _0, - #[doc = "System OSC Clock Monitor is enabled and detected an error"] - _1, + #[doc = "System OSC Clock Monitor is disabled or has not detected an error"] _0, + #[doc = "System OSC Clock Monitor is enabled and detected an error"] _1, } impl SOSCERRW { #[allow(missing_docs)] diff --git a/src/scg/soscdiv/mod.rs b/src/scg/soscdiv/mod.rs index 28868d3..0c6036b 100644 --- a/src/scg/soscdiv/mod.rs +++ b/src/scg/soscdiv/mod.rs @@ -22,7 +22,9 @@ impl super::SOSCDIV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SOSCDIV { #[doc = "Possible values of the field `SOSCDIV1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCDIV1R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SOSCDIV1R { #[doc = r" Value of the field as raw bits"] @@ -135,22 +129,14 @@ impl SOSCDIV1R { #[doc = "Possible values of the field `SOSCDIV2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SOSCDIV2R { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SOSCDIV2R { #[doc = r" Value of the field as raw bits"] @@ -226,22 +212,14 @@ impl SOSCDIV2R { } #[doc = "Values that can be written to the field `SOSCDIV1`"] pub enum SOSCDIV1W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SOSCDIV1W { #[allow(missing_docs)] @@ -324,22 +302,14 @@ impl<'a> _SOSCDIV1W<'a> { } #[doc = "Values that can be written to the field `SOSCDIV2`"] pub enum SOSCDIV2W { - #[doc = "Output disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Output disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SOSCDIV2W { #[allow(missing_docs)] diff --git a/src/scg/spllcfg/mod.rs b/src/scg/spllcfg/mod.rs index c0ad664..c3b0203 100644 --- a/src/scg/spllcfg/mod.rs +++ b/src/scg/spllcfg/mod.rs @@ -22,7 +22,9 @@ impl super::SPLLCFG { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/scg/spllcsr/mod.rs b/src/scg/spllcsr/mod.rs index 8fd246e..912e40f 100644 --- a/src/scg/spllcsr/mod.rs +++ b/src/scg/spllcsr/mod.rs @@ -22,7 +22,9 @@ impl super::SPLLCSR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::SPLLCSR { #[doc = "Possible values of the field `SPLLEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLENR { - #[doc = "System PLL is disabled"] - _0, - #[doc = "System PLL is enabled"] - _1, + #[doc = "System PLL is disabled"] _0, + #[doc = "System PLL is enabled"] _1, } impl SPLLENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl SPLLENR { #[doc = "Possible values of the field `SPLLCM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLCMR { - #[doc = "System PLL Clock Monitor is disabled"] - _0, - #[doc = "System PLL Clock Monitor is enabled"] - _1, + #[doc = "System PLL Clock Monitor is disabled"] _0, + #[doc = "System PLL Clock Monitor is enabled"] _1, } impl SPLLCMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl SPLLCMR { #[doc = "Possible values of the field `SPLLCMRE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLCMRER { - #[doc = "Clock Monitor generates interrupt when error detected"] - _0, - #[doc = "Clock Monitor generates reset when error detected"] - _1, + #[doc = "Clock Monitor generates interrupt when error detected"] _0, + #[doc = "Clock Monitor generates reset when error detected"] _1, } impl SPLLCMRER { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl SPLLCMRER { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl LKR { #[doc = "Possible values of the field `SPLLVLD`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLVLDR { - #[doc = "System PLL is not enabled or clock is not valid"] - _0, - #[doc = "System PLL is enabled and output clock is valid"] - _1, + #[doc = "System PLL is not enabled or clock is not valid"] _0, + #[doc = "System PLL is enabled and output clock is valid"] _1, } impl SPLLVLDR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -278,10 +270,8 @@ impl SPLLVLDR { #[doc = "Possible values of the field `SPLLSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLSELR { - #[doc = "System PLL is not the system clock source"] - _0, - #[doc = "System PLL is the system clock source"] - _1, + #[doc = "System PLL is not the system clock source"] _0, + #[doc = "System PLL is the system clock source"] _1, } impl SPLLSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -325,8 +315,7 @@ impl SPLLSELR { #[doc = "Possible values of the field `SPLLERR`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLERRR { - #[doc = "System PLL Clock Monitor is disabled or has not detected an error"] - _0, + #[doc = "System PLL Clock Monitor is disabled or has not detected an error"] _0, #[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."] _1, } @@ -371,10 +360,8 @@ impl SPLLERRR { } #[doc = "Values that can be written to the field `SPLLEN`"] pub enum SPLLENW { - #[doc = "System PLL is disabled"] - _0, - #[doc = "System PLL is enabled"] - _1, + #[doc = "System PLL is disabled"] _0, + #[doc = "System PLL is enabled"] _1, } impl SPLLENW { #[allow(missing_docs)] @@ -429,10 +416,8 @@ impl<'a> _SPLLENW<'a> { } #[doc = "Values that can be written to the field `SPLLCM`"] pub enum SPLLCMW { - #[doc = "System PLL Clock Monitor is disabled"] - _0, - #[doc = "System PLL Clock Monitor is enabled"] - _1, + #[doc = "System PLL Clock Monitor is disabled"] _0, + #[doc = "System PLL Clock Monitor is enabled"] _1, } impl SPLLCMW { #[allow(missing_docs)] @@ -487,10 +472,8 @@ impl<'a> _SPLLCMW<'a> { } #[doc = "Values that can be written to the field `SPLLCMRE`"] pub enum SPLLCMREW { - #[doc = "Clock Monitor generates interrupt when error detected"] - _0, - #[doc = "Clock Monitor generates reset when error detected"] - _1, + #[doc = "Clock Monitor generates interrupt when error detected"] _0, + #[doc = "Clock Monitor generates reset when error detected"] _1, } impl SPLLCMREW { #[allow(missing_docs)] @@ -545,10 +528,8 @@ impl<'a> _SPLLCMREW<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Control Status Register can be written."] - _0, - #[doc = "Control Status Register cannot be written."] - _1, + #[doc = "Control Status Register can be written."] _0, + #[doc = "Control Status Register cannot be written."] _1, } impl LKW { #[allow(missing_docs)] @@ -603,8 +584,7 @@ impl<'a> _LKW<'a> { } #[doc = "Values that can be written to the field `SPLLERR`"] pub enum SPLLERRW { - #[doc = "System PLL Clock Monitor is disabled or has not detected an error"] - _0, + #[doc = "System PLL Clock Monitor is disabled or has not detected an error"] _0, #[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."] _1, } diff --git a/src/scg/splldiv/mod.rs b/src/scg/splldiv/mod.rs index 140fcb9..17b96bb 100644 --- a/src/scg/splldiv/mod.rs +++ b/src/scg/splldiv/mod.rs @@ -22,7 +22,9 @@ impl super::SPLLDIV { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,22 +45,14 @@ impl super::SPLLDIV { #[doc = "Possible values of the field `SPLLDIV1`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLDIV1R { - #[doc = "Clock disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Clock disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SPLLDIV1R { #[doc = r" Value of the field as raw bits"] @@ -135,22 +129,14 @@ impl SPLLDIV1R { #[doc = "Possible values of the field `SPLLDIV2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SPLLDIV2R { - #[doc = "Clock disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Clock disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SPLLDIV2R { #[doc = r" Value of the field as raw bits"] @@ -226,22 +212,14 @@ impl SPLLDIV2R { } #[doc = "Values that can be written to the field `SPLLDIV1`"] pub enum SPLLDIV1W { - #[doc = "Clock disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Clock disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SPLLDIV1W { #[allow(missing_docs)] @@ -324,22 +302,14 @@ impl<'a> _SPLLDIV1W<'a> { } #[doc = "Values that can be written to the field `SPLLDIV2`"] pub enum SPLLDIV2W { - #[doc = "Clock disabled"] - _000, - #[doc = "Divide by 1"] - _001, - #[doc = "Divide by 2"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 8"] - _100, - #[doc = "Divide by 16"] - _101, - #[doc = "Divide by 32"] - _110, - #[doc = "Divide by 64"] - _111, + #[doc = "Clock disabled"] _000, + #[doc = "Divide by 1"] _001, + #[doc = "Divide by 2"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 8"] _100, + #[doc = "Divide by 16"] _101, + #[doc = "Divide by 32"] _110, + #[doc = "Divide by 64"] _111, } impl SPLLDIV2W { #[allow(missing_docs)] diff --git a/src/scg/vccr/mod.rs b/src/scg/vccr/mod.rs index 00997bd..ec12bbc 100644 --- a/src/scg/vccr/mod.rs +++ b/src/scg/vccr/mod.rs @@ -22,7 +22,9 @@ impl super::VCCR { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,24 +45,15 @@ impl super::VCCR { #[doc = "Possible values of the field `DIVSLOW`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVSLOWR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = r" Reserved"] _Reserved(u8), } impl DIVSLOWR { #[doc = r" Value of the field as raw bits"] @@ -138,38 +131,22 @@ impl DIVSLOWR { #[doc = "Possible values of the field `DIVBUS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVBUSR { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSR { #[doc = r" Value of the field as raw bits"] @@ -302,38 +279,22 @@ impl DIVBUSR { #[doc = "Possible values of the field `DIVCORE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DIVCORER { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCORER { #[doc = r" Value of the field as raw bits"] @@ -466,10 +427,8 @@ impl DIVCORER { #[doc = "Possible values of the field `SCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SCSR { - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Slow IRC (SIRC_CLK)"] _0010, + #[doc = r" Reserved"] _Reserved(u8), } impl SCSR { #[doc = r" Value of the field as raw bits"] @@ -497,22 +456,14 @@ impl SCSR { } #[doc = "Values that can be written to the field `DIVSLOW`"] pub enum DIVSLOWW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, } impl DIVSLOWW { #[allow(missing_docs)] @@ -593,38 +544,22 @@ impl<'a> _DIVSLOWW<'a> { } #[doc = "Values that can be written to the field `DIVBUS`"] pub enum DIVBUSW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVBUSW { #[allow(missing_docs)] @@ -755,38 +690,22 @@ impl<'a> _DIVBUSW<'a> { } #[doc = "Values that can be written to the field `DIVCORE`"] pub enum DIVCOREW { - #[doc = "Divide-by-1"] - _0000, - #[doc = "Divide-by-2"] - _0001, - #[doc = "Divide-by-3"] - _0010, - #[doc = "Divide-by-4"] - _0011, - #[doc = "Divide-by-5"] - _0100, - #[doc = "Divide-by-6"] - _0101, - #[doc = "Divide-by-7"] - _0110, - #[doc = "Divide-by-8"] - _0111, - #[doc = "Divide-by-9"] - _1000, - #[doc = "Divide-by-10"] - _1001, - #[doc = "Divide-by-11"] - _1010, - #[doc = "Divide-by-12"] - _1011, - #[doc = "Divide-by-13"] - _1100, - #[doc = "Divide-by-14"] - _1101, - #[doc = "Divide-by-15"] - _1110, - #[doc = "Divide-by-16"] - _1111, + #[doc = "Divide-by-1"] _0000, + #[doc = "Divide-by-2"] _0001, + #[doc = "Divide-by-3"] _0010, + #[doc = "Divide-by-4"] _0011, + #[doc = "Divide-by-5"] _0100, + #[doc = "Divide-by-6"] _0101, + #[doc = "Divide-by-7"] _0110, + #[doc = "Divide-by-8"] _0111, + #[doc = "Divide-by-9"] _1000, + #[doc = "Divide-by-10"] _1001, + #[doc = "Divide-by-11"] _1010, + #[doc = "Divide-by-12"] _1011, + #[doc = "Divide-by-13"] _1100, + #[doc = "Divide-by-14"] _1101, + #[doc = "Divide-by-15"] _1110, + #[doc = "Divide-by-16"] _1111, } impl DIVCOREW { #[allow(missing_docs)] @@ -917,8 +836,7 @@ impl<'a> _DIVCOREW<'a> { } #[doc = "Values that can be written to the field `SCS`"] pub enum SCSW { - #[doc = "Slow IRC (SIRC_CLK)"] - _0010, + #[doc = "Slow IRC (SIRC_CLK)"] _0010, } impl SCSW { #[allow(missing_docs)] diff --git a/src/scg/verid/mod.rs b/src/scg/verid/mod.rs index abb4075..417e269 100644 --- a/src/scg/verid/mod.rs +++ b/src/scg/verid/mod.rs @@ -6,7 +6,9 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/sim/adcopt/mod.rs b/src/sim/adcopt/mod.rs index 388d234..b2e8af3 100644 --- a/src/sim/adcopt/mod.rs +++ b/src/sim/adcopt/mod.rs @@ -22,7 +22,9 @@ impl super::ADCOPT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::ADCOPT { #[doc = "Possible values of the field `ADC0TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC0TRGSELR { - #[doc = "PDB output"] - _0, - #[doc = "TRGMUX output"] - _1, + #[doc = "PDB output"] _0, + #[doc = "TRGMUX output"] _1, } impl ADC0TRGSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,22 +90,14 @@ impl ADC0TRGSELR { #[doc = "Possible values of the field `ADC0SWPRETRG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC0SWPRETRGR { - #[doc = "Software pretrigger disabled"] - _000, - #[doc = "Reserved (do not use)"] - _001, - #[doc = "Reserved (do not use)"] - _010, - #[doc = "Reserved (do not use)"] - _011, - #[doc = "Software pretrigger 0"] - _100, - #[doc = "Software pretrigger 1"] - _101, - #[doc = "Software pretrigger 2"] - _110, - #[doc = "Software pretrigger 3"] - _111, + #[doc = "Software pretrigger disabled"] _000, + #[doc = "Reserved (do not use)"] _001, + #[doc = "Reserved (do not use)"] _010, + #[doc = "Reserved (do not use)"] _011, + #[doc = "Software pretrigger 0"] _100, + #[doc = "Software pretrigger 1"] _101, + #[doc = "Software pretrigger 2"] _110, + #[doc = "Software pretrigger 3"] _111, } impl ADC0SWPRETRGR { #[doc = r" Value of the field as raw bits"] @@ -182,14 +174,10 @@ impl ADC0SWPRETRGR { #[doc = "Possible values of the field `ADC0PRETRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC0PRETRGSELR { - #[doc = "PDB pretrigger (default)"] - _00, - #[doc = "TRGMUX pretrigger"] - _01, - #[doc = "Software pretrigger"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB pretrigger (default)"] _00, + #[doc = "TRGMUX pretrigger"] _01, + #[doc = "Software pretrigger"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl ADC0PRETRGSELR { #[doc = r" Value of the field as raw bits"] @@ -232,10 +220,8 @@ impl ADC0PRETRGSELR { #[doc = "Possible values of the field `ADC1TRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC1TRGSELR { - #[doc = "PDB output"] - _0, - #[doc = "TRGMUX output"] - _1, + #[doc = "PDB output"] _0, + #[doc = "TRGMUX output"] _1, } impl ADC1TRGSELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -279,22 +265,14 @@ impl ADC1TRGSELR { #[doc = "Possible values of the field `ADC1SWPRETRG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC1SWPRETRGR { - #[doc = "Software pretrigger disabled"] - _000, - #[doc = "Reserved (do not use)"] - _001, - #[doc = "Reserved (do not use)"] - _010, - #[doc = "Reserved (do not use)"] - _011, - #[doc = "Software pretrigger 0"] - _100, - #[doc = "Software pretrigger 1"] - _101, - #[doc = "Software pretrigger 2"] - _110, - #[doc = "Software pretrigger 3"] - _111, + #[doc = "Software pretrigger disabled"] _000, + #[doc = "Reserved (do not use)"] _001, + #[doc = "Reserved (do not use)"] _010, + #[doc = "Reserved (do not use)"] _011, + #[doc = "Software pretrigger 0"] _100, + #[doc = "Software pretrigger 1"] _101, + #[doc = "Software pretrigger 2"] _110, + #[doc = "Software pretrigger 3"] _111, } impl ADC1SWPRETRGR { #[doc = r" Value of the field as raw bits"] @@ -371,14 +349,10 @@ impl ADC1SWPRETRGR { #[doc = "Possible values of the field `ADC1PRETRGSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC1PRETRGSELR { - #[doc = "PDB pretrigger (default)"] - _00, - #[doc = "TRGMUX pretrigger"] - _01, - #[doc = "Software pretrigger"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PDB pretrigger (default)"] _00, + #[doc = "TRGMUX pretrigger"] _01, + #[doc = "Software pretrigger"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl ADC1PRETRGSELR { #[doc = r" Value of the field as raw bits"] @@ -420,10 +394,8 @@ impl ADC1PRETRGSELR { } #[doc = "Values that can be written to the field `ADC0TRGSEL`"] pub enum ADC0TRGSELW { - #[doc = "PDB output"] - _0, - #[doc = "TRGMUX output"] - _1, + #[doc = "PDB output"] _0, + #[doc = "TRGMUX output"] _1, } impl ADC0TRGSELW { #[allow(missing_docs)] @@ -478,22 +450,14 @@ impl<'a> _ADC0TRGSELW<'a> { } #[doc = "Values that can be written to the field `ADC0SWPRETRG`"] pub enum ADC0SWPRETRGW { - #[doc = "Software pretrigger disabled"] - _000, - #[doc = "Reserved (do not use)"] - _001, - #[doc = "Reserved (do not use)"] - _010, - #[doc = "Reserved (do not use)"] - _011, - #[doc = "Software pretrigger 0"] - _100, - #[doc = "Software pretrigger 1"] - _101, - #[doc = "Software pretrigger 2"] - _110, - #[doc = "Software pretrigger 3"] - _111, + #[doc = "Software pretrigger disabled"] _000, + #[doc = "Reserved (do not use)"] _001, + #[doc = "Reserved (do not use)"] _010, + #[doc = "Reserved (do not use)"] _011, + #[doc = "Software pretrigger 0"] _100, + #[doc = "Software pretrigger 1"] _101, + #[doc = "Software pretrigger 2"] _110, + #[doc = "Software pretrigger 3"] _111, } impl ADC0SWPRETRGW { #[allow(missing_docs)] @@ -576,12 +540,9 @@ impl<'a> _ADC0SWPRETRGW<'a> { } #[doc = "Values that can be written to the field `ADC0PRETRGSEL`"] pub enum ADC0PRETRGSELW { - #[doc = "PDB pretrigger (default)"] - _00, - #[doc = "TRGMUX pretrigger"] - _01, - #[doc = "Software pretrigger"] - _10, + #[doc = "PDB pretrigger (default)"] _00, + #[doc = "TRGMUX pretrigger"] _01, + #[doc = "Software pretrigger"] _10, } impl ADC0PRETRGSELW { #[allow(missing_docs)] @@ -632,10 +593,8 @@ impl<'a> _ADC0PRETRGSELW<'a> { } #[doc = "Values that can be written to the field `ADC1TRGSEL`"] pub enum ADC1TRGSELW { - #[doc = "PDB output"] - _0, - #[doc = "TRGMUX output"] - _1, + #[doc = "PDB output"] _0, + #[doc = "TRGMUX output"] _1, } impl ADC1TRGSELW { #[allow(missing_docs)] @@ -690,22 +649,14 @@ impl<'a> _ADC1TRGSELW<'a> { } #[doc = "Values that can be written to the field `ADC1SWPRETRG`"] pub enum ADC1SWPRETRGW { - #[doc = "Software pretrigger disabled"] - _000, - #[doc = "Reserved (do not use)"] - _001, - #[doc = "Reserved (do not use)"] - _010, - #[doc = "Reserved (do not use)"] - _011, - #[doc = "Software pretrigger 0"] - _100, - #[doc = "Software pretrigger 1"] - _101, - #[doc = "Software pretrigger 2"] - _110, - #[doc = "Software pretrigger 3"] - _111, + #[doc = "Software pretrigger disabled"] _000, + #[doc = "Reserved (do not use)"] _001, + #[doc = "Reserved (do not use)"] _010, + #[doc = "Reserved (do not use)"] _011, + #[doc = "Software pretrigger 0"] _100, + #[doc = "Software pretrigger 1"] _101, + #[doc = "Software pretrigger 2"] _110, + #[doc = "Software pretrigger 3"] _111, } impl ADC1SWPRETRGW { #[allow(missing_docs)] @@ -788,12 +739,9 @@ impl<'a> _ADC1SWPRETRGW<'a> { } #[doc = "Values that can be written to the field `ADC1PRETRGSEL`"] pub enum ADC1PRETRGSELW { - #[doc = "PDB pretrigger (default)"] - _00, - #[doc = "TRGMUX pretrigger"] - _01, - #[doc = "Software pretrigger"] - _10, + #[doc = "PDB pretrigger (default)"] _00, + #[doc = "TRGMUX pretrigger"] _01, + #[doc = "Software pretrigger"] _10, } impl ADC1PRETRGSELW { #[allow(missing_docs)] diff --git a/src/sim/chipctl/mod.rs b/src/sim/chipctl/mod.rs index c8e82e8..3f7f536 100644 --- a/src/sim/chipctl/mod.rs +++ b/src/sim/chipctl/mod.rs @@ -22,7 +22,9 @@ impl super::CHIPCTL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -45,16 +47,11 @@ impl super::CHIPCTL { pub enum ADC_INTERLEAVE_ENR { #[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."] _0000, - #[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] - _1XXX, - #[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] - X1XX, - #[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] - XX1X, - #[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] - XXX1, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX, + #[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX, + #[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X, + #[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1, + #[doc = r" Reserved"] _Reserved(u8), } impl ADC_INTERLEAVE_ENR { #[doc = r" Value of the field as raw bits"] @@ -111,36 +108,22 @@ impl ADC_INTERLEAVE_ENR { #[doc = "Possible values of the field `CLKOUTSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKOUTSELR { - #[doc = "SCG CLKOUT"] - _0000, - #[doc = "SOSC DIV2 CLK"] - _0010, - #[doc = "SIRC DIV2 CLK"] - _0100, + #[doc = "SCG CLKOUT"] _0000, + #[doc = "SOSC DIV2 CLK"] _0010, + #[doc = "SIRC DIV2 CLK"] _0100, #[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"] _0101, - #[doc = "FIRC DIV2 CLK"] - _0110, - #[doc = "HCLK"] - _0111, - #[doc = "SPLL DIV2 CLK"] - _1000, - #[doc = "BUS_CLK"] - _1001, - #[doc = "LPO128K_CLK"] - _1010, - #[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] - _1011, - #[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] - _1100, - #[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] - _1101, - #[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] - _1110, - #[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] - _1111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FIRC DIV2 CLK"] _0110, + #[doc = "HCLK"] _0111, + #[doc = "SPLL DIV2 CLK"] _1000, + #[doc = "BUS_CLK"] _1001, + #[doc = "LPO128K_CLK"] _1010, + #[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011, + #[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100, + #[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101, + #[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110, + #[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111, + #[doc = r" Reserved"] _Reserved(u8), } impl CLKOUTSELR { #[doc = r" Value of the field as raw bits"] @@ -260,22 +243,14 @@ impl CLKOUTSELR { #[doc = "Possible values of the field `CLKOUTDIV`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKOUTDIVR { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 3"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 5"] - _100, - #[doc = "Divide by 6"] - _101, - #[doc = "Divide by 7"] - _110, - #[doc = "Divide by 8"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 3"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 5"] _100, + #[doc = "Divide by 6"] _101, + #[doc = "Divide by 7"] _110, + #[doc = "Divide by 8"] _111, } impl CLKOUTDIVR { #[doc = r" Value of the field as raw bits"] @@ -352,10 +327,8 @@ impl CLKOUTDIVR { #[doc = "Possible values of the field `CLKOUTEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKOUTENR { - #[doc = "Clockout disable"] - _0, - #[doc = "Clockout enable"] - _1, + #[doc = "Clockout disable"] _0, + #[doc = "Clockout enable"] _1, } impl CLKOUTENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -399,10 +372,8 @@ impl CLKOUTENR { #[doc = "Possible values of the field `TRACECLK_SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRACECLK_SELR { - #[doc = "Core clock"] - _0, - #[doc = "Platform clock"] - _1, + #[doc = "Core clock"] _0, + #[doc = "Platform clock"] _1, } impl TRACECLK_SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -448,8 +419,7 @@ impl TRACECLK_SELR { pub enum PDB_BB_SELR { #[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"] _0, - #[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] - _1, + #[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1, } impl PDB_BB_SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -493,20 +463,13 @@ impl PDB_BB_SELR { #[doc = "Possible values of the field `ADC_SUPPLY`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC_SUPPLYR { - #[doc = "5 V input VDD supply (VDD)"] - _000, - #[doc = "5 V input analog supply (VDDA)"] - _001, - #[doc = "ADC Reference Supply (VREFH)"] - _010, - #[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] - _011, - #[doc = "3.3 V flash regulator output (VDD_flash_3V)"] - _100, - #[doc = "1.2 V core regulator output (VDD_LV)"] - _101, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "5 V input VDD supply (VDD)"] _000, + #[doc = "5 V input analog supply (VDDA)"] _001, + #[doc = "ADC Reference Supply (VREFH)"] _010, + #[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011, + #[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100, + #[doc = "1.2 V core regulator output (VDD_LV)"] _101, + #[doc = r" Reserved"] _Reserved(u8), } impl ADC_SUPPLYR { #[doc = r" Value of the field as raw bits"] @@ -570,10 +533,8 @@ impl ADC_SUPPLYR { #[doc = "Possible values of the field `ADC_SUPPLYEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ADC_SUPPLYENR { - #[doc = "Disable internal supply monitoring"] - _0, - #[doc = "Enable internal supply monitoring"] - _1, + #[doc = "Disable internal supply monitoring"] _0, + #[doc = "Enable internal supply monitoring"] _1, } impl ADC_SUPPLYENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -617,10 +578,8 @@ impl ADC_SUPPLYENR { #[doc = "Possible values of the field `SRAMU_RETEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRAMU_RETENR { - #[doc = "SRAMU contents are retained across resets"] - _0, - #[doc = "No SRAMU retention"] - _1, + #[doc = "SRAMU contents are retained across resets"] _0, + #[doc = "No SRAMU retention"] _1, } impl SRAMU_RETENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -664,10 +623,8 @@ impl SRAMU_RETENR { #[doc = "Possible values of the field `SRAML_RETEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRAML_RETENR { - #[doc = "SRAML contents are retained across resets"] - _0, - #[doc = "No SRAML retention"] - _1, + #[doc = "SRAML contents are retained across resets"] _0, + #[doc = "No SRAML retention"] _1, } impl SRAML_RETENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -712,14 +669,10 @@ impl SRAML_RETENR { pub enum ADC_INTERLEAVE_ENW { #[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."] _0000, - #[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] - _1XXX, - #[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] - X1XX, - #[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] - XX1X, - #[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] - XXX1, + #[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX, + #[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX, + #[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X, + #[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1, } impl ADC_INTERLEAVE_ENW { #[allow(missing_docs)] @@ -782,34 +735,21 @@ impl<'a> _ADC_INTERLEAVE_ENW<'a> { } #[doc = "Values that can be written to the field `CLKOUTSEL`"] pub enum CLKOUTSELW { - #[doc = "SCG CLKOUT"] - _0000, - #[doc = "SOSC DIV2 CLK"] - _0010, - #[doc = "SIRC DIV2 CLK"] - _0100, + #[doc = "SCG CLKOUT"] _0000, + #[doc = "SOSC DIV2 CLK"] _0010, + #[doc = "SIRC DIV2 CLK"] _0100, #[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"] _0101, - #[doc = "FIRC DIV2 CLK"] - _0110, - #[doc = "HCLK"] - _0111, - #[doc = "SPLL DIV2 CLK"] - _1000, - #[doc = "BUS_CLK"] - _1001, - #[doc = "LPO128K_CLK"] - _1010, - #[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] - _1011, - #[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] - _1100, - #[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] - _1101, - #[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] - _1110, - #[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] - _1111, + #[doc = "FIRC DIV2 CLK"] _0110, + #[doc = "HCLK"] _0111, + #[doc = "SPLL DIV2 CLK"] _1000, + #[doc = "BUS_CLK"] _1001, + #[doc = "LPO128K_CLK"] _1010, + #[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011, + #[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100, + #[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101, + #[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110, + #[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111, } impl CLKOUTSELW { #[allow(missing_docs)] @@ -926,22 +866,14 @@ impl<'a> _CLKOUTSELW<'a> { } #[doc = "Values that can be written to the field `CLKOUTDIV`"] pub enum CLKOUTDIVW { - #[doc = "Divide by 1"] - _000, - #[doc = "Divide by 2"] - _001, - #[doc = "Divide by 3"] - _010, - #[doc = "Divide by 4"] - _011, - #[doc = "Divide by 5"] - _100, - #[doc = "Divide by 6"] - _101, - #[doc = "Divide by 7"] - _110, - #[doc = "Divide by 8"] - _111, + #[doc = "Divide by 1"] _000, + #[doc = "Divide by 2"] _001, + #[doc = "Divide by 3"] _010, + #[doc = "Divide by 4"] _011, + #[doc = "Divide by 5"] _100, + #[doc = "Divide by 6"] _101, + #[doc = "Divide by 7"] _110, + #[doc = "Divide by 8"] _111, } impl CLKOUTDIVW { #[allow(missing_docs)] @@ -1024,10 +956,8 @@ impl<'a> _CLKOUTDIVW<'a> { } #[doc = "Values that can be written to the field `CLKOUTEN`"] pub enum CLKOUTENW { - #[doc = "Clockout disable"] - _0, - #[doc = "Clockout enable"] - _1, + #[doc = "Clockout disable"] _0, + #[doc = "Clockout enable"] _1, } impl CLKOUTENW { #[allow(missing_docs)] @@ -1082,10 +1012,8 @@ impl<'a> _CLKOUTENW<'a> { } #[doc = "Values that can be written to the field `TRACECLK_SEL`"] pub enum TRACECLK_SELW { - #[doc = "Core clock"] - _0, - #[doc = "Platform clock"] - _1, + #[doc = "Core clock"] _0, + #[doc = "Platform clock"] _1, } impl TRACECLK_SELW { #[allow(missing_docs)] @@ -1142,8 +1070,7 @@ impl<'a> _TRACECLK_SELW<'a> { pub enum PDB_BB_SELW { #[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"] _0, - #[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] - _1, + #[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1, } impl PDB_BB_SELW { #[allow(missing_docs)] @@ -1198,18 +1125,12 @@ impl<'a> _PDB_BB_SELW<'a> { } #[doc = "Values that can be written to the field `ADC_SUPPLY`"] pub enum ADC_SUPPLYW { - #[doc = "5 V input VDD supply (VDD)"] - _000, - #[doc = "5 V input analog supply (VDDA)"] - _001, - #[doc = "ADC Reference Supply (VREFH)"] - _010, - #[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] - _011, - #[doc = "3.3 V flash regulator output (VDD_flash_3V)"] - _100, - #[doc = "1.2 V core regulator output (VDD_LV)"] - _101, + #[doc = "5 V input VDD supply (VDD)"] _000, + #[doc = "5 V input analog supply (VDDA)"] _001, + #[doc = "ADC Reference Supply (VREFH)"] _010, + #[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011, + #[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100, + #[doc = "1.2 V core regulator output (VDD_LV)"] _101, } impl ADC_SUPPLYW { #[allow(missing_docs)] @@ -1278,10 +1199,8 @@ impl<'a> _ADC_SUPPLYW<'a> { } #[doc = "Values that can be written to the field `ADC_SUPPLYEN`"] pub enum ADC_SUPPLYENW { - #[doc = "Disable internal supply monitoring"] - _0, - #[doc = "Enable internal supply monitoring"] - _1, + #[doc = "Disable internal supply monitoring"] _0, + #[doc = "Enable internal supply monitoring"] _1, } impl ADC_SUPPLYENW { #[allow(missing_docs)] @@ -1336,10 +1255,8 @@ impl<'a> _ADC_SUPPLYENW<'a> { } #[doc = "Values that can be written to the field `SRAMU_RETEN`"] pub enum SRAMU_RETENW { - #[doc = "SRAMU contents are retained across resets"] - _0, - #[doc = "No SRAMU retention"] - _1, + #[doc = "SRAMU contents are retained across resets"] _0, + #[doc = "No SRAMU retention"] _1, } impl SRAMU_RETENW { #[allow(missing_docs)] @@ -1394,10 +1311,8 @@ impl<'a> _SRAMU_RETENW<'a> { } #[doc = "Values that can be written to the field `SRAML_RETEN`"] pub enum SRAML_RETENW { - #[doc = "SRAML contents are retained across resets"] - _0, - #[doc = "No SRAML retention"] - _1, + #[doc = "SRAML contents are retained across resets"] _0, + #[doc = "No SRAML retention"] _1, } impl SRAML_RETENW { #[allow(missing_docs)] diff --git a/src/sim/clkdiv4/mod.rs b/src/sim/clkdiv4/mod.rs index 7b72d75..5caebda 100644 --- a/src/sim/clkdiv4/mod.rs +++ b/src/sim/clkdiv4/mod.rs @@ -22,7 +22,9 @@ impl super::CLKDIV4 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -75,10 +77,8 @@ impl TRACEDIVR { #[doc = "Possible values of the field `TRACEDIVEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TRACEDIVENR { - #[doc = "Debug trace divider disabled"] - _0, - #[doc = "Debug trace divider enabled"] - _1, + #[doc = "Debug trace divider disabled"] _0, + #[doc = "Debug trace divider enabled"] _1, } impl TRACEDIVENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -159,10 +159,8 @@ impl<'a> _TRACEDIVW<'a> { } #[doc = "Values that can be written to the field `TRACEDIVEN`"] pub enum TRACEDIVENW { - #[doc = "Debug trace divider disabled"] - _0, - #[doc = "Debug trace divider enabled"] - _1, + #[doc = "Debug trace divider disabled"] _0, + #[doc = "Debug trace divider enabled"] _1, } impl TRACEDIVENW { #[allow(missing_docs)] diff --git a/src/sim/fcfg1/mod.rs b/src/sim/fcfg1/mod.rs index e7f794d..743e7cf 100644 --- a/src/sim/fcfg1/mod.rs +++ b/src/sim/fcfg1/mod.rs @@ -22,7 +22,9 @@ impl super::FCFG1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,26 +56,16 @@ impl DEPARTR { #[doc = "Possible values of the field `EEERAMSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EEERAMSIZER { - #[doc = "4 KB"] - _0010, - #[doc = "2 KB"] - _0011, - #[doc = "1 KB"] - _0100, - #[doc = "512 Bytes"] - _0101, - #[doc = "256 Bytes"] - _0110, - #[doc = "128 Bytes"] - _0111, - #[doc = "64 Bytes"] - _1000, - #[doc = "32 Bytes"] - _1001, - #[doc = "0 Bytes"] - _1111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "4 KB"] _0010, + #[doc = "2 KB"] _0011, + #[doc = "1 KB"] _0100, + #[doc = "512 Bytes"] _0101, + #[doc = "256 Bytes"] _0110, + #[doc = "128 Bytes"] _0111, + #[doc = "64 Bytes"] _1000, + #[doc = "32 Bytes"] _1001, + #[doc = "0 Bytes"] _1111, + #[doc = r" Reserved"] _Reserved(u8), } impl EEERAMSIZER { #[doc = r" Value of the field as raw bits"] diff --git a/src/sim/ftmopt0/mod.rs b/src/sim/ftmopt0/mod.rs index 503a7b1..cd06174 100644 --- a/src/sim/ftmopt0/mod.rs +++ b/src/sim/ftmopt0/mod.rs @@ -22,7 +22,9 @@ impl super::FTMOPT0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::FTMOPT0 { #[doc = "Possible values of the field `FTM0FLTxSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM0FLTXSELR { - #[doc = "FTM0_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM0 out"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM0_FLTx pin"] _000, + #[doc = "TRGMUX_FTM0 out"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM0FLTXSELR { #[doc = r" Value of the field as raw bits"] @@ -84,12 +83,9 @@ impl FTM0FLTXSELR { #[doc = "Possible values of the field `FTM1FLTxSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM1FLTXSELR { - #[doc = "FTM1_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM1 out"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM1_FLTx pin"] _000, + #[doc = "TRGMUX_FTM1 out"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM1FLTXSELR { #[doc = r" Value of the field as raw bits"] @@ -125,12 +121,9 @@ impl FTM1FLTXSELR { #[doc = "Possible values of the field `FTM2FLTxSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM2FLTXSELR { - #[doc = "FTM2_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM2 out"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM2_FLTx pin"] _000, + #[doc = "TRGMUX_FTM2 out"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM2FLTXSELR { #[doc = r" Value of the field as raw bits"] @@ -166,12 +159,9 @@ impl FTM2FLTXSELR { #[doc = "Possible values of the field `FTM3FLTxSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM3FLTXSELR { - #[doc = "FTM3_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM3 out"] - _001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM3_FLTx pin"] _000, + #[doc = "TRGMUX_FTM3 out"] _001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM3FLTXSELR { #[doc = r" Value of the field as raw bits"] @@ -207,14 +197,10 @@ impl FTM3FLTXSELR { #[doc = "Possible values of the field `FTM0CLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM0CLKSELR { - #[doc = "FTM0 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM0 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM0 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM0 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM0 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM0 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM0CLKSELR { #[doc = r" Value of the field as raw bits"] @@ -263,14 +249,10 @@ impl FTM0CLKSELR { #[doc = "Possible values of the field `FTM1CLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM1CLKSELR { - #[doc = "FTM1 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM1 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM1 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM1 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM1 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM1 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM1CLKSELR { #[doc = r" Value of the field as raw bits"] @@ -319,14 +301,10 @@ impl FTM1CLKSELR { #[doc = "Possible values of the field `FTM2CLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM2CLKSELR { - #[doc = "FTM2 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM2 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM2 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM2 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM2 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM2 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM2CLKSELR { #[doc = r" Value of the field as raw bits"] @@ -375,14 +353,10 @@ impl FTM2CLKSELR { #[doc = "Possible values of the field `FTM3CLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM3CLKSELR { - #[doc = "FTM3 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM3 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM3 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM3 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM3 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM3 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM3CLKSELR { #[doc = r" Value of the field as raw bits"] @@ -430,10 +404,8 @@ impl FTM3CLKSELR { } #[doc = "Values that can be written to the field `FTM0FLTxSEL`"] pub enum FTM0FLTXSELW { - #[doc = "FTM0_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM0 out"] - _001, + #[doc = "FTM0_FLTx pin"] _000, + #[doc = "TRGMUX_FTM0 out"] _001, } impl FTM0FLTXSELW { #[allow(missing_docs)] @@ -478,10 +450,8 @@ impl<'a> _FTM0FLTXSELW<'a> { } #[doc = "Values that can be written to the field `FTM1FLTxSEL`"] pub enum FTM1FLTXSELW { - #[doc = "FTM1_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM1 out"] - _001, + #[doc = "FTM1_FLTx pin"] _000, + #[doc = "TRGMUX_FTM1 out"] _001, } impl FTM1FLTXSELW { #[allow(missing_docs)] @@ -526,10 +496,8 @@ impl<'a> _FTM1FLTXSELW<'a> { } #[doc = "Values that can be written to the field `FTM2FLTxSEL`"] pub enum FTM2FLTXSELW { - #[doc = "FTM2_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM2 out"] - _001, + #[doc = "FTM2_FLTx pin"] _000, + #[doc = "TRGMUX_FTM2 out"] _001, } impl FTM2FLTXSELW { #[allow(missing_docs)] @@ -574,10 +542,8 @@ impl<'a> _FTM2FLTXSELW<'a> { } #[doc = "Values that can be written to the field `FTM3FLTxSEL`"] pub enum FTM3FLTXSELW { - #[doc = "FTM3_FLTx pin"] - _000, - #[doc = "TRGMUX_FTM3 out"] - _001, + #[doc = "FTM3_FLTx pin"] _000, + #[doc = "TRGMUX_FTM3 out"] _001, } impl FTM3FLTXSELW { #[allow(missing_docs)] @@ -622,14 +588,10 @@ impl<'a> _FTM3FLTXSELW<'a> { } #[doc = "Values that can be written to the field `FTM0CLKSEL`"] pub enum FTM0CLKSELW { - #[doc = "FTM0 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM0 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM0 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM0 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM0 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM0 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM0CLKSELW { #[allow(missing_docs)] @@ -688,14 +650,10 @@ impl<'a> _FTM0CLKSELW<'a> { } #[doc = "Values that can be written to the field `FTM1CLKSEL`"] pub enum FTM1CLKSELW { - #[doc = "FTM1 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM1 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM1 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM1 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM1 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM1 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM1CLKSELW { #[allow(missing_docs)] @@ -754,14 +712,10 @@ impl<'a> _FTM1CLKSELW<'a> { } #[doc = "Values that can be written to the field `FTM2CLKSEL`"] pub enum FTM2CLKSELW { - #[doc = "FTM2 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM2 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM2 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM2 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM2 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM2 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM2CLKSELW { #[allow(missing_docs)] @@ -820,14 +774,10 @@ impl<'a> _FTM2CLKSELW<'a> { } #[doc = "Values that can be written to the field `FTM3CLKSEL`"] pub enum FTM3CLKSELW { - #[doc = "FTM3 external clock driven by TCLK0 pin."] - _00, - #[doc = "FTM3 external clock driven by TCLK1 pin."] - _01, - #[doc = "FTM3 external clock driven by TCLK2 pin."] - _10, - #[doc = "No clock input"] - _11, + #[doc = "FTM3 external clock driven by TCLK0 pin."] _00, + #[doc = "FTM3 external clock driven by TCLK1 pin."] _01, + #[doc = "FTM3 external clock driven by TCLK2 pin."] _10, + #[doc = "No clock input"] _11, } impl FTM3CLKSELW { #[allow(missing_docs)] diff --git a/src/sim/ftmopt1/mod.rs b/src/sim/ftmopt1/mod.rs index 9ce5b1f..0a489e7 100644 --- a/src/sim/ftmopt1/mod.rs +++ b/src/sim/ftmopt1/mod.rs @@ -22,7 +22,9 @@ impl super::FTMOPT1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -127,12 +129,9 @@ impl FTM3SYNCBITR { #[doc = "Possible values of the field `FTM1CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM1CH0SELR { - #[doc = "FTM1_CH0 input"] - _00, - #[doc = "CMP0 output"] - _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM1_CH0 input"] _00, + #[doc = "CMP0 output"] _01, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM1CH0SELR { #[doc = r" Value of the field as raw bits"] @@ -168,12 +167,9 @@ impl FTM1CH0SELR { #[doc = "Possible values of the field `FTM2CH0SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM2CH0SELR { - #[doc = "FTM2_CH0 input"] - _00, - #[doc = "CMP0 output"] - _01, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "FTM2_CH0 input"] _00, + #[doc = "CMP0 output"] _01, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM2CH0SELR { #[doc = r" Value of the field as raw bits"] @@ -209,10 +205,8 @@ impl FTM2CH0SELR { #[doc = "Possible values of the field `FTM2CH1SEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM2CH1SELR { - #[doc = "FTM2_CH1 input"] - _0, - #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] - _1, + #[doc = "FTM2_CH1 input"] _0, + #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1, } impl FTM2CH1SELR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -256,10 +250,8 @@ impl FTM2CH1SELR { #[doc = "Possible values of the field `FTMGLDOK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTMGLDOKR { - #[doc = "FTM Global load mechanism disabled."] - _0, - #[doc = "FTM Global load mechanism enabled"] - _1, + #[doc = "FTM Global load mechanism disabled."] _0, + #[doc = "FTM Global load mechanism enabled"] _1, } impl FTMGLDOKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -303,12 +295,9 @@ impl FTMGLDOKR { #[doc = "Possible values of the field `FTM0_OUTSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM0_OUTSELR { - #[doc = "No modulation with FTM1_CH1"] - _00000000, - #[doc = "Modulation with FTM1_CH1"] - _00000001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No modulation with FTM1_CH1"] _00000000, + #[doc = "Modulation with FTM1_CH1"] _00000001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM0_OUTSELR { #[doc = r" Value of the field as raw bits"] @@ -344,12 +333,9 @@ impl FTM0_OUTSELR { #[doc = "Possible values of the field `FTM3_OUTSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FTM3_OUTSELR { - #[doc = "No modulation with FTM2_CH1"] - _00000000, - #[doc = "Modulation with FTM2_CH1"] - _00000001, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "No modulation with FTM2_CH1"] _00000000, + #[doc = "Modulation with FTM2_CH1"] _00000001, + #[doc = r" Reserved"] _Reserved(u8), } impl FTM3_OUTSELR { #[doc = r" Value of the field as raw bits"] @@ -476,10 +462,8 @@ impl<'a> _FTM3SYNCBITW<'a> { } #[doc = "Values that can be written to the field `FTM1CH0SEL`"] pub enum FTM1CH0SELW { - #[doc = "FTM1_CH0 input"] - _00, - #[doc = "CMP0 output"] - _01, + #[doc = "FTM1_CH0 input"] _00, + #[doc = "CMP0 output"] _01, } impl FTM1CH0SELW { #[allow(missing_docs)] @@ -524,10 +508,8 @@ impl<'a> _FTM1CH0SELW<'a> { } #[doc = "Values that can be written to the field `FTM2CH0SEL`"] pub enum FTM2CH0SELW { - #[doc = "FTM2_CH0 input"] - _00, - #[doc = "CMP0 output"] - _01, + #[doc = "FTM2_CH0 input"] _00, + #[doc = "CMP0 output"] _01, } impl FTM2CH0SELW { #[allow(missing_docs)] @@ -572,10 +554,8 @@ impl<'a> _FTM2CH0SELW<'a> { } #[doc = "Values that can be written to the field `FTM2CH1SEL`"] pub enum FTM2CH1SELW { - #[doc = "FTM2_CH1 input"] - _0, - #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] - _1, + #[doc = "FTM2_CH1 input"] _0, + #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1, } impl FTM2CH1SELW { #[allow(missing_docs)] @@ -630,10 +610,8 @@ impl<'a> _FTM2CH1SELW<'a> { } #[doc = "Values that can be written to the field `FTMGLDOK`"] pub enum FTMGLDOKW { - #[doc = "FTM Global load mechanism disabled."] - _0, - #[doc = "FTM Global load mechanism enabled"] - _1, + #[doc = "FTM Global load mechanism disabled."] _0, + #[doc = "FTM Global load mechanism enabled"] _1, } impl FTMGLDOKW { #[allow(missing_docs)] @@ -688,10 +666,8 @@ impl<'a> _FTMGLDOKW<'a> { } #[doc = "Values that can be written to the field `FTM0_OUTSEL`"] pub enum FTM0_OUTSELW { - #[doc = "No modulation with FTM1_CH1"] - _00000000, - #[doc = "Modulation with FTM1_CH1"] - _00000001, + #[doc = "No modulation with FTM1_CH1"] _00000000, + #[doc = "Modulation with FTM1_CH1"] _00000001, } impl FTM0_OUTSELW { #[allow(missing_docs)] @@ -736,10 +712,8 @@ impl<'a> _FTM0_OUTSELW<'a> { } #[doc = "Values that can be written to the field `FTM3_OUTSEL`"] pub enum FTM3_OUTSELW { - #[doc = "No modulation with FTM2_CH1"] - _00000000, - #[doc = "Modulation with FTM2_CH1"] - _00000001, + #[doc = "No modulation with FTM2_CH1"] _00000000, + #[doc = "Modulation with FTM2_CH1"] _00000001, } impl FTM3_OUTSELW { #[allow(missing_docs)] diff --git a/src/sim/lpoclks/mod.rs b/src/sim/lpoclks/mod.rs index 50ec0d4..5010eec 100644 --- a/src/sim/lpoclks/mod.rs +++ b/src/sim/lpoclks/mod.rs @@ -22,7 +22,9 @@ impl super::LPOCLKS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::LPOCLKS { #[doc = "Possible values of the field `LPO1KCLKEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPO1KCLKENR { - #[doc = "Disable 1 kHz LPO_CLK output"] - _0, - #[doc = "Enable 1 kHz LPO_CLK output"] - _1, + #[doc = "Disable 1 kHz LPO_CLK output"] _0, + #[doc = "Enable 1 kHz LPO_CLK output"] _1, } impl LPO1KCLKENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl LPO1KCLKENR { #[doc = "Possible values of the field `LPO32KCLKEN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPO32KCLKENR { - #[doc = "Disable 32 kHz LPO_CLK output"] - _0, - #[doc = "Enable 32 kHz LPO_CLK output"] - _1, + #[doc = "Disable 32 kHz LPO_CLK output"] _0, + #[doc = "Enable 32 kHz LPO_CLK output"] _1, } impl LPO32KCLKENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,14 +135,10 @@ impl LPO32KCLKENR { #[doc = "Possible values of the field `LPOCLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LPOCLKSELR { - #[doc = "128 kHz LPO_CLK"] - _00, - #[doc = "No clock"] - _01, - #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] - _10, - #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] - _11, + #[doc = "128 kHz LPO_CLK"] _00, + #[doc = "No clock"] _01, + #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10, + #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11, } impl LPOCLKSELR { #[doc = r" Value of the field as raw bits"] @@ -193,14 +187,10 @@ impl LPOCLKSELR { #[doc = "Possible values of the field `RTCCLKSEL`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RTCCLKSELR { - #[doc = "SOSCDIV1_CLK"] - _00, - #[doc = "32 kHz LPO_CLK"] - _01, - #[doc = "RTC_CLKIN clock"] - _10, - #[doc = "FIRCDIV1_CLK"] - _11, + #[doc = "SOSCDIV1_CLK"] _00, + #[doc = "32 kHz LPO_CLK"] _01, + #[doc = "RTC_CLKIN clock"] _10, + #[doc = "FIRCDIV1_CLK"] _11, } impl RTCCLKSELR { #[doc = r" Value of the field as raw bits"] @@ -248,10 +238,8 @@ impl RTCCLKSELR { } #[doc = "Values that can be written to the field `LPO1KCLKEN`"] pub enum LPO1KCLKENW { - #[doc = "Disable 1 kHz LPO_CLK output"] - _0, - #[doc = "Enable 1 kHz LPO_CLK output"] - _1, + #[doc = "Disable 1 kHz LPO_CLK output"] _0, + #[doc = "Enable 1 kHz LPO_CLK output"] _1, } impl LPO1KCLKENW { #[allow(missing_docs)] @@ -306,10 +294,8 @@ impl<'a> _LPO1KCLKENW<'a> { } #[doc = "Values that can be written to the field `LPO32KCLKEN`"] pub enum LPO32KCLKENW { - #[doc = "Disable 32 kHz LPO_CLK output"] - _0, - #[doc = "Enable 32 kHz LPO_CLK output"] - _1, + #[doc = "Disable 32 kHz LPO_CLK output"] _0, + #[doc = "Enable 32 kHz LPO_CLK output"] _1, } impl LPO32KCLKENW { #[allow(missing_docs)] @@ -364,14 +350,10 @@ impl<'a> _LPO32KCLKENW<'a> { } #[doc = "Values that can be written to the field `LPOCLKSEL`"] pub enum LPOCLKSELW { - #[doc = "128 kHz LPO_CLK"] - _00, - #[doc = "No clock"] - _01, - #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] - _10, - #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] - _11, + #[doc = "128 kHz LPO_CLK"] _00, + #[doc = "No clock"] _01, + #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10, + #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11, } impl LPOCLKSELW { #[allow(missing_docs)] @@ -430,14 +412,10 @@ impl<'a> _LPOCLKSELW<'a> { } #[doc = "Values that can be written to the field `RTCCLKSEL`"] pub enum RTCCLKSELW { - #[doc = "SOSCDIV1_CLK"] - _00, - #[doc = "32 kHz LPO_CLK"] - _01, - #[doc = "RTC_CLKIN clock"] - _10, - #[doc = "FIRCDIV1_CLK"] - _11, + #[doc = "SOSCDIV1_CLK"] _00, + #[doc = "32 kHz LPO_CLK"] _01, + #[doc = "RTC_CLKIN clock"] _10, + #[doc = "FIRCDIV1_CLK"] _11, } impl RTCCLKSELW { #[allow(missing_docs)] diff --git a/src/sim/misctrl0/mod.rs b/src/sim/misctrl0/mod.rs index ee2c236..21f1544 100644 --- a/src/sim/misctrl0/mod.rs +++ b/src/sim/misctrl0/mod.rs @@ -22,7 +22,9 @@ impl super::MISCTRL0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/sim/misctrl1/mod.rs b/src/sim/misctrl1/mod.rs index 625a598..f5bc792 100644 --- a/src/sim/misctrl1/mod.rs +++ b/src/sim/misctrl1/mod.rs @@ -22,7 +22,9 @@ impl super::MISCTRL1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/sim/mod.rs b/src/sim/mod.rs index 647f29b..39b8259 100644 --- a/src/sim/mod.rs +++ b/src/sim/mod.rs @@ -3,42 +3,27 @@ use vcell::VolatileCell; #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 4usize], - #[doc = "0x04 - Chip Control register"] - pub chipctl: CHIPCTL, + #[doc = "0x04 - Chip Control register"] pub chipctl: CHIPCTL, _reserved1: [u8; 4usize], - #[doc = "0x0c - FTM Option Register 0"] - pub ftmopt0: FTMOPT0, - #[doc = "0x10 - LPO Clock Select Register"] - pub lpoclks: LPOCLKS, + #[doc = "0x0c - FTM Option Register 0"] pub ftmopt0: FTMOPT0, + #[doc = "0x10 - LPO Clock Select Register"] pub lpoclks: LPOCLKS, _reserved2: [u8; 4usize], - #[doc = "0x18 - ADC Options Register"] - pub adcopt: ADCOPT, - #[doc = "0x1c - FTM Option Register 1"] - pub ftmopt1: FTMOPT1, - #[doc = "0x20 - Miscellaneous control register 0"] - pub misctrl0: MISCTRL0, - #[doc = "0x24 - System Device Identification Register"] - pub sdid: SDID, + #[doc = "0x18 - ADC Options Register"] pub adcopt: ADCOPT, + #[doc = "0x1c - FTM Option Register 1"] pub ftmopt1: FTMOPT1, + #[doc = "0x20 - Miscellaneous control register 0"] pub misctrl0: MISCTRL0, + #[doc = "0x24 - System Device Identification Register"] pub sdid: SDID, _reserved3: [u8; 24usize], - #[doc = "0x40 - Platform Clock Gating Control Register"] - pub platcgc: PLATCGC, + #[doc = "0x40 - Platform Clock Gating Control Register"] pub platcgc: PLATCGC, _reserved4: [u8; 8usize], - #[doc = "0x4c - Flash Configuration Register 1"] - pub fcfg1: FCFG1, + #[doc = "0x4c - Flash Configuration Register 1"] pub fcfg1: FCFG1, _reserved5: [u8; 4usize], - #[doc = "0x54 - Unique Identification Register High"] - pub uidh: UIDH, - #[doc = "0x58 - Unique Identification Register Mid-High"] - pub uidmh: UIDMH, - #[doc = "0x5c - Unique Identification Register Mid Low"] - pub uidml: UIDML, - #[doc = "0x60 - Unique Identification Register Low"] - pub uidl: UIDL, + #[doc = "0x54 - Unique Identification Register High"] pub uidh: UIDH, + #[doc = "0x58 - Unique Identification Register Mid-High"] pub uidmh: UIDMH, + #[doc = "0x5c - Unique Identification Register Mid Low"] pub uidml: UIDML, + #[doc = "0x60 - Unique Identification Register Low"] pub uidl: UIDL, _reserved6: [u8; 4usize], - #[doc = "0x68 - System Clock Divider Register 4"] - pub clkdiv4: CLKDIV4, - #[doc = "0x6c - Miscellaneous Control register 1"] - pub misctrl1: MISCTRL1, + #[doc = "0x68 - System Clock Divider Register 4"] pub clkdiv4: CLKDIV4, + #[doc = "0x6c - Miscellaneous Control register 1"] pub misctrl1: MISCTRL1, } #[doc = "Chip Control register"] pub struct CHIPCTL { diff --git a/src/sim/platcgc/mod.rs b/src/sim/platcgc/mod.rs index a9e2c4c..4da6148 100644 --- a/src/sim/platcgc/mod.rs +++ b/src/sim/platcgc/mod.rs @@ -22,7 +22,9 @@ impl super::PLATCGC { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PLATCGC { #[doc = "Possible values of the field `CGCMSCM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCMSCMR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCMSCMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl CGCMSCMR { #[doc = "Possible values of the field `CGCMPU`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCMPUR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCMPUR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl CGCMPUR { #[doc = "Possible values of the field `CGCDMA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCDMAR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCDMAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,10 +180,8 @@ impl CGCDMAR { #[doc = "Possible values of the field `CGCERM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCERMR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCERMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -231,10 +225,8 @@ impl CGCERMR { #[doc = "Possible values of the field `CGCEIM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CGCEIMR { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCEIMR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -277,10 +269,8 @@ impl CGCEIMR { } #[doc = "Values that can be written to the field `CGCMSCM`"] pub enum CGCMSCMW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCMSCMW { #[allow(missing_docs)] @@ -335,10 +325,8 @@ impl<'a> _CGCMSCMW<'a> { } #[doc = "Values that can be written to the field `CGCMPU`"] pub enum CGCMPUW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCMPUW { #[allow(missing_docs)] @@ -393,10 +381,8 @@ impl<'a> _CGCMPUW<'a> { } #[doc = "Values that can be written to the field `CGCDMA`"] pub enum CGCDMAW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCDMAW { #[allow(missing_docs)] @@ -451,10 +437,8 @@ impl<'a> _CGCDMAW<'a> { } #[doc = "Values that can be written to the field `CGCERM`"] pub enum CGCERMW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCERMW { #[allow(missing_docs)] @@ -509,10 +493,8 @@ impl<'a> _CGCERMW<'a> { } #[doc = "Values that can be written to the field `CGCEIM`"] pub enum CGCEIMW { - #[doc = "Clock disabled"] - _0, - #[doc = "Clock enabled"] - _1, + #[doc = "Clock disabled"] _0, + #[doc = "Clock enabled"] _1, } impl CGCEIMW { #[allow(missing_docs)] diff --git a/src/sim/sdid/mod.rs b/src/sim/sdid/mod.rs index 61b9347..33e97c5 100644 --- a/src/sim/sdid/mod.rs +++ b/src/sim/sdid/mod.rs @@ -6,7 +6,9 @@ impl super::SDID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] @@ -23,20 +25,13 @@ impl FEATURESR { #[doc = "Possible values of the field `PACKAGE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PACKAGER { - #[doc = "48 LQFP"] - _0010, - #[doc = "64 LQFP"] - _0011, - #[doc = "100 LQFP"] - _0100, - #[doc = "144 LQFP"] - _0110, - #[doc = "176 LQFP"] - _0111, - #[doc = "100 MAP BGA"] - _1000, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "48 LQFP"] _0010, + #[doc = "64 LQFP"] _0011, + #[doc = "100 LQFP"] _0100, + #[doc = "144 LQFP"] _0110, + #[doc = "176 LQFP"] _0111, + #[doc = "100 MAP BGA"] _1000, + #[doc = r" Reserved"] _Reserved(u8), } impl PACKAGER { #[doc = r" Value of the field as raw bits"] @@ -111,18 +106,12 @@ impl REVIDR { #[doc = "Possible values of the field `RAMSIZE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RAMSIZER { - #[doc = "128 KB (S32K148), Reserved (others)"] - _0111, - #[doc = "160 KB (S32K148) , Reserved (others)"] - _1001, - #[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"] - _1011, - #[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"] - _1101, - #[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"] - _1111, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "128 KB (S32K148), Reserved (others)"] _0111, + #[doc = "160 KB (S32K148) , Reserved (others)"] _1001, + #[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"] _1011, + #[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"] _1101, + #[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"] _1111, + #[doc = r" Reserved"] _Reserved(u8), } impl RAMSIZER { #[doc = r" Value of the field as raw bits"] diff --git a/src/sim/uidh/mod.rs b/src/sim/uidh/mod.rs index efee92f..8b83ec9 100644 --- a/src/sim/uidh/mod.rs +++ b/src/sim/uidh/mod.rs @@ -6,7 +6,9 @@ impl super::UIDH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/sim/uidl/mod.rs b/src/sim/uidl/mod.rs index 1d59b5c..e44681a 100644 --- a/src/sim/uidl/mod.rs +++ b/src/sim/uidl/mod.rs @@ -6,7 +6,9 @@ impl super::UIDL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/sim/uidmh/mod.rs b/src/sim/uidmh/mod.rs index 591833b..30c554c 100644 --- a/src/sim/uidmh/mod.rs +++ b/src/sim/uidmh/mod.rs @@ -6,7 +6,9 @@ impl super::UIDMH { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/sim/uidml/mod.rs b/src/sim/uidml/mod.rs index 7b0a063..4fffe78 100644 --- a/src/sim/uidml/mod.rs +++ b/src/sim/uidml/mod.rs @@ -6,7 +6,9 @@ impl super::UIDML { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/smc/mod.rs b/src/smc/mod.rs index ec3c742..50a74d5 100644 --- a/src/smc/mod.rs +++ b/src/smc/mod.rs @@ -2,18 +2,12 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SMC Version ID Register"] - pub verid: VERID, - #[doc = "0x04 - SMC Parameter Register"] - pub param: PARAM, - #[doc = "0x08 - Power Mode Protection register"] - pub pmprot: PMPROT, - #[doc = "0x0c - Power Mode Control register"] - pub pmctrl: PMCTRL, - #[doc = "0x10 - Stop Control Register"] - pub stopctrl: STOPCTRL, - #[doc = "0x14 - Power Mode Status register"] - pub pmstat: PMSTAT, + #[doc = "0x00 - SMC Version ID Register"] pub verid: VERID, + #[doc = "0x04 - SMC Parameter Register"] pub param: PARAM, + #[doc = "0x08 - Power Mode Protection register"] pub pmprot: PMPROT, + #[doc = "0x0c - Power Mode Control register"] pub pmctrl: PMCTRL, + #[doc = "0x10 - Stop Control Register"] pub stopctrl: STOPCTRL, + #[doc = "0x14 - Power Mode Status register"] pub pmstat: PMSTAT, } #[doc = "SMC Version ID Register"] pub struct VERID { diff --git a/src/smc/param/mod.rs b/src/smc/param/mod.rs index 40b197a..bbd102b 100644 --- a/src/smc/param/mod.rs +++ b/src/smc/param/mod.rs @@ -6,16 +6,16 @@ impl super::PARAM { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `EHSRUN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EHSRUNR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EHSRUNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -59,10 +59,8 @@ impl EHSRUNR { #[doc = "Possible values of the field `ELLS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELLSR { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELLSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -106,10 +104,8 @@ impl ELLSR { #[doc = "Possible values of the field `ELLS2`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ELLS2R { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl ELLS2R { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -153,10 +149,8 @@ impl ELLS2R { #[doc = "Possible values of the field `EVLLS0`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EVLLS0R { - #[doc = "The feature is not available."] - _0, - #[doc = "The feature is available."] - _1, + #[doc = "The feature is not available."] _0, + #[doc = "The feature is available."] _1, } impl EVLLS0R { #[doc = r" Returns `true` if the bit is clear (0)"] diff --git a/src/smc/pmctrl/mod.rs b/src/smc/pmctrl/mod.rs index 2b55b8c..460432e 100644 --- a/src/smc/pmctrl/mod.rs +++ b/src/smc/pmctrl/mod.rs @@ -22,7 +22,9 @@ impl super::PMCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,14 +45,10 @@ impl super::PMCTRL { #[doc = "Possible values of the field `STOPM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STOPMR { - #[doc = "Normal Stop (STOP)"] - _000, - #[doc = "Very-Low-Power Stop (VLPS)"] - _010, - #[doc = "Reseved"] - _110, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Normal Stop (STOP)"] _000, + #[doc = "Very-Low-Power Stop (VLPS)"] _010, + #[doc = "Reseved"] _110, + #[doc = r" Reserved"] _Reserved(u8), } impl STOPMR { #[doc = r" Value of the field as raw bits"] @@ -93,10 +91,8 @@ impl STOPMR { #[doc = "Possible values of the field `VLPSA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum VLPSAR { - #[doc = "The previous stop mode entry was successful."] - _0, - #[doc = "The previous stop mode entry was aborted."] - _1, + #[doc = "The previous stop mode entry was successful."] _0, + #[doc = "The previous stop mode entry was aborted."] _1, } impl VLPSAR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -140,14 +136,10 @@ impl VLPSAR { #[doc = "Possible values of the field `RUNM`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RUNMR { - #[doc = "Normal Run mode (RUN)"] - _00, - #[doc = "Very-Low-Power Run mode (VLPR)"] - _10, - #[doc = "High Speed Run mode (HSRUN)"] - _11, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "Normal Run mode (RUN)"] _00, + #[doc = "Very-Low-Power Run mode (VLPR)"] _10, + #[doc = "High Speed Run mode (HSRUN)"] _11, + #[doc = r" Reserved"] _Reserved(u8), } impl RUNMR { #[doc = r" Value of the field as raw bits"] @@ -189,12 +181,9 @@ impl RUNMR { } #[doc = "Values that can be written to the field `STOPM`"] pub enum STOPMW { - #[doc = "Normal Stop (STOP)"] - _000, - #[doc = "Very-Low-Power Stop (VLPS)"] - _010, - #[doc = "Reseved"] - _110, + #[doc = "Normal Stop (STOP)"] _000, + #[doc = "Very-Low-Power Stop (VLPS)"] _010, + #[doc = "Reseved"] _110, } impl STOPMW { #[allow(missing_docs)] @@ -245,12 +234,9 @@ impl<'a> _STOPMW<'a> { } #[doc = "Values that can be written to the field `RUNM`"] pub enum RUNMW { - #[doc = "Normal Run mode (RUN)"] - _00, - #[doc = "Very-Low-Power Run mode (VLPR)"] - _10, - #[doc = "High Speed Run mode (HSRUN)"] - _11, + #[doc = "Normal Run mode (RUN)"] _00, + #[doc = "Very-Low-Power Run mode (VLPR)"] _10, + #[doc = "High Speed Run mode (HSRUN)"] _11, } impl RUNMW { #[allow(missing_docs)] diff --git a/src/smc/pmprot/mod.rs b/src/smc/pmprot/mod.rs index ba35619..51cced9 100644 --- a/src/smc/pmprot/mod.rs +++ b/src/smc/pmprot/mod.rs @@ -22,7 +22,9 @@ impl super::PMPROT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::PMPROT { #[doc = "Possible values of the field `AVLP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AVLPR { - #[doc = "VLPR and VLPS are not allowed."] - _0, - #[doc = "VLPR and VLPS are allowed."] - _1, + #[doc = "VLPR and VLPS are not allowed."] _0, + #[doc = "VLPR and VLPS are allowed."] _1, } impl AVLPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl AVLPR { #[doc = "Possible values of the field `AHSRUN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum AHSRUNR { - #[doc = "HSRUN is not allowed"] - _0, - #[doc = "HSRUN is allowed"] - _1, + #[doc = "HSRUN is not allowed"] _0, + #[doc = "HSRUN is allowed"] _1, } impl AHSRUNR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -136,10 +134,8 @@ impl AHSRUNR { } #[doc = "Values that can be written to the field `AVLP`"] pub enum AVLPW { - #[doc = "VLPR and VLPS are not allowed."] - _0, - #[doc = "VLPR and VLPS are allowed."] - _1, + #[doc = "VLPR and VLPS are not allowed."] _0, + #[doc = "VLPR and VLPS are allowed."] _1, } impl AVLPW { #[allow(missing_docs)] @@ -194,10 +190,8 @@ impl<'a> _AVLPW<'a> { } #[doc = "Values that can be written to the field `AHSRUN`"] pub enum AHSRUNW { - #[doc = "HSRUN is not allowed"] - _0, - #[doc = "HSRUN is allowed"] - _1, + #[doc = "HSRUN is not allowed"] _0, + #[doc = "HSRUN is allowed"] _1, } impl AHSRUNW { #[allow(missing_docs)] diff --git a/src/smc/pmstat/mod.rs b/src/smc/pmstat/mod.rs index e30a964..b19051d 100644 --- a/src/smc/pmstat/mod.rs +++ b/src/smc/pmstat/mod.rs @@ -6,7 +6,9 @@ impl super::PMSTAT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = r" Value of the field"] diff --git a/src/smc/stopctrl/mod.rs b/src/smc/stopctrl/mod.rs index 4d00fdc..21ceef3 100644 --- a/src/smc/stopctrl/mod.rs +++ b/src/smc/stopctrl/mod.rs @@ -22,7 +22,9 @@ impl super::STOPCTRL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,12 +45,9 @@ impl super::STOPCTRL { #[doc = "Possible values of the field `STOPO`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STOPOR { - #[doc = "STOP1 - Stop with both system and bus clocks disabled"] - _01, - #[doc = "STOP2 - Stop with system clock disabled and bus clock enabled"] - _10, - #[doc = r" Reserved"] - _Reserved(u8), + #[doc = "STOP1 - Stop with both system and bus clocks disabled"] _01, + #[doc = "STOP2 - Stop with system clock disabled and bus clock enabled"] _10, + #[doc = r" Reserved"] _Reserved(u8), } impl STOPOR { #[doc = r" Value of the field as raw bits"] @@ -83,10 +82,8 @@ impl STOPOR { } #[doc = "Values that can be written to the field `STOPO`"] pub enum STOPOW { - #[doc = "STOP1 - Stop with both system and bus clocks disabled"] - _01, - #[doc = "STOP2 - Stop with system clock disabled and bus clock enabled"] - _10, + #[doc = "STOP1 - Stop with both system and bus clocks disabled"] _01, + #[doc = "STOP2 - Stop with system clock disabled and bus clock enabled"] _10, } impl STOPOW { #[allow(missing_docs)] diff --git a/src/smc/verid/mod.rs b/src/smc/verid/mod.rs index 8b62309..572fbf0 100644 --- a/src/smc/verid/mod.rs +++ b/src/smc/verid/mod.rs @@ -6,16 +6,16 @@ impl super::VERID { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } } #[doc = "Possible values of the field `FEATURE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FEATURER { - #[doc = "Standard features implemented"] - _0, - #[doc = r" Reserved"] - _Reserved(u16), + #[doc = "Standard features implemented"] _0, + #[doc = r" Reserved"] _Reserved(u16), } impl FEATURER { #[doc = r" Value of the field as raw bits"] diff --git a/src/trgmux/mod.rs b/src/trgmux/mod.rs index e0599aa..56b3b06 100644 --- a/src/trgmux/mod.rs +++ b/src/trgmux/mod.rs @@ -2,58 +2,32 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - TRGMUX DMAMUX0 Register"] - pub trgmux_dmamux0: TRGMUX_DMAMUX0, - #[doc = "0x04 - TRGMUX EXTOUT0 Register"] - pub trgmux_extout0: TRGMUX_EXTOUT0, - #[doc = "0x08 - TRGMUX EXTOUT1 Register"] - pub trgmux_extout1: TRGMUX_EXTOUT1, - #[doc = "0x0c - TRGMUX ADC0 Register"] - pub trgmux_adc0: TRGMUX_ADC0, - #[doc = "0x10 - TRGMUX ADC1 Register"] - pub trgmux_adc1: TRGMUX_ADC1, - #[doc = "0x14 - TRGMUX Reserved Register 5"] - pub trgmuxdummy5: TRGMUXDUMMY5, - #[doc = "0x18 - TRGMUX Reserved Register 6"] - pub trgmuxdummy6: TRGMUXDUMMY6, - #[doc = "0x1c - TRGMUX CMP0 Register"] - pub trgmux_cmp0: TRGMUX_CMP0, - #[doc = "0x20 - TRGMUX Reserved Register 8"] - pub trgmuxdummy8: TRGMUXDUMMY8, - #[doc = "0x24 - TRGMUX Reserved Register 9"] - pub trgmuxdummy9: TRGMUXDUMMY9, - #[doc = "0x28 - TRGMUX FTM0 Register"] - pub trgmux_ftm0: TRGMUX_FTM0, - #[doc = "0x2c - TRGMUX FTM1 Register"] - pub trgmux_ftm1: TRGMUX_FTM1, - #[doc = "0x30 - TRGMUX FTM2 Register"] - pub trgmux_ftm2: TRGMUX_FTM2, - #[doc = "0x34 - TRGMUX FTM3 Register"] - pub trgmux_ftm3: TRGMUX_FTM3, - #[doc = "0x38 - TRGMUX PDB0 Register"] - pub trgmux_pdb0: TRGMUX_PDB0, - #[doc = "0x3c - TRGMUX PDB1 Register"] - pub trgmux_pdb1: TRGMUX_PDB1, - #[doc = "0x40 - TRGMUX Reserved Register 16"] - pub trgmuxdummy16: TRGMUXDUMMY16, - #[doc = "0x44 - TRGMUX FLEXIO Register"] - pub trgmux_flexio: TRGMUX_FLEXIO, - #[doc = "0x48 - TRGMUX LPIT0 Register"] - pub trgmux_lpit0: TRGMUX_LPIT0, - #[doc = "0x4c - TRGMUX LPUART0 Register"] - pub trgmux_lpuart0: TRGMUX_LPUART0, - #[doc = "0x50 - TRGMUX LPUART1 Register"] - pub trgmux_lpuart1: TRGMUX_LPUART1, - #[doc = "0x54 - TRGMUX LPI2C0 Register"] - pub trgmux_lpi2c0: TRGMUX_LPI2C0, - #[doc = "0x58 - TRGMUX Reserved Register 22"] - pub trgmuxdummy22: TRGMUXDUMMY22, - #[doc = "0x5c - TRGMUX LPSPI0 Register"] - pub trgmux_lpspi0: TRGMUX_LPSPI0, - #[doc = "0x60 - TRGMUX LPSPI1 Register"] - pub trgmux_lpspi1: TRGMUX_LPSPI1, - #[doc = "0x64 - TRGMUX LPTMR0 Register"] - pub trgmux_lptmr0: TRGMUX_LPTMR0, + #[doc = "0x00 - TRGMUX DMAMUX0 Register"] pub trgmux_dmamux0: TRGMUX_DMAMUX0, + #[doc = "0x04 - TRGMUX EXTOUT0 Register"] pub trgmux_extout0: TRGMUX_EXTOUT0, + #[doc = "0x08 - TRGMUX EXTOUT1 Register"] pub trgmux_extout1: TRGMUX_EXTOUT1, + #[doc = "0x0c - TRGMUX ADC0 Register"] pub trgmux_adc0: TRGMUX_ADC0, + #[doc = "0x10 - TRGMUX ADC1 Register"] pub trgmux_adc1: TRGMUX_ADC1, + #[doc = "0x14 - TRGMUX Reserved Register 5"] pub trgmuxdummy5: TRGMUXDUMMY5, + #[doc = "0x18 - TRGMUX Reserved Register 6"] pub trgmuxdummy6: TRGMUXDUMMY6, + #[doc = "0x1c - TRGMUX CMP0 Register"] pub trgmux_cmp0: TRGMUX_CMP0, + #[doc = "0x20 - TRGMUX Reserved Register 8"] pub trgmuxdummy8: TRGMUXDUMMY8, + #[doc = "0x24 - TRGMUX Reserved Register 9"] pub trgmuxdummy9: TRGMUXDUMMY9, + #[doc = "0x28 - TRGMUX FTM0 Register"] pub trgmux_ftm0: TRGMUX_FTM0, + #[doc = "0x2c - TRGMUX FTM1 Register"] pub trgmux_ftm1: TRGMUX_FTM1, + #[doc = "0x30 - TRGMUX FTM2 Register"] pub trgmux_ftm2: TRGMUX_FTM2, + #[doc = "0x34 - TRGMUX FTM3 Register"] pub trgmux_ftm3: TRGMUX_FTM3, + #[doc = "0x38 - TRGMUX PDB0 Register"] pub trgmux_pdb0: TRGMUX_PDB0, + #[doc = "0x3c - TRGMUX PDB1 Register"] pub trgmux_pdb1: TRGMUX_PDB1, + #[doc = "0x40 - TRGMUX Reserved Register 16"] pub trgmuxdummy16: TRGMUXDUMMY16, + #[doc = "0x44 - TRGMUX FLEXIO Register"] pub trgmux_flexio: TRGMUX_FLEXIO, + #[doc = "0x48 - TRGMUX LPIT0 Register"] pub trgmux_lpit0: TRGMUX_LPIT0, + #[doc = "0x4c - TRGMUX LPUART0 Register"] pub trgmux_lpuart0: TRGMUX_LPUART0, + #[doc = "0x50 - TRGMUX LPUART1 Register"] pub trgmux_lpuart1: TRGMUX_LPUART1, + #[doc = "0x54 - TRGMUX LPI2C0 Register"] pub trgmux_lpi2c0: TRGMUX_LPI2C0, + #[doc = "0x58 - TRGMUX Reserved Register 22"] pub trgmuxdummy22: TRGMUXDUMMY22, + #[doc = "0x5c - TRGMUX LPSPI0 Register"] pub trgmux_lpspi0: TRGMUX_LPSPI0, + #[doc = "0x60 - TRGMUX LPSPI1 Register"] pub trgmux_lpspi1: TRGMUX_LPSPI1, + #[doc = "0x64 - TRGMUX LPTMR0 Register"] pub trgmux_lptmr0: TRGMUX_LPTMR0, } #[doc = "TRGMUX DMAMUX0 Register"] pub struct TRGMUX_DMAMUX0 { diff --git a/src/trgmux/trgmux_adc0/mod.rs b/src/trgmux/trgmux_adc0/mod.rs index 3256417..976dc2c 100644 --- a/src/trgmux/trgmux_adc0/mod.rs +++ b/src/trgmux/trgmux_adc0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_ADC0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_adc1/mod.rs b/src/trgmux/trgmux_adc1/mod.rs index 11ba90d..9950e6b 100644 --- a/src/trgmux/trgmux_adc1/mod.rs +++ b/src/trgmux/trgmux_adc1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_ADC1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_cmp0/mod.rs b/src/trgmux/trgmux_cmp0/mod.rs index dbcd035..ace053c 100644 --- a/src/trgmux/trgmux_cmp0/mod.rs +++ b/src/trgmux/trgmux_cmp0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_CMP0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_dmamux0/mod.rs b/src/trgmux/trgmux_dmamux0/mod.rs index 061b5a9..dfb409c 100644 --- a/src/trgmux/trgmux_dmamux0/mod.rs +++ b/src/trgmux/trgmux_dmamux0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_DMAMUX0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_extout0/mod.rs b/src/trgmux/trgmux_extout0/mod.rs index 3da3f74..ac31411 100644 --- a/src/trgmux/trgmux_extout0/mod.rs +++ b/src/trgmux/trgmux_extout0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_EXTOUT0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_extout1/mod.rs b/src/trgmux/trgmux_extout1/mod.rs index 17a99df..62b15a2 100644 --- a/src/trgmux/trgmux_extout1/mod.rs +++ b/src/trgmux/trgmux_extout1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_EXTOUT1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_flexio/mod.rs b/src/trgmux/trgmux_flexio/mod.rs index 767e73a..7e5af7d 100644 --- a/src/trgmux/trgmux_flexio/mod.rs +++ b/src/trgmux/trgmux_flexio/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_FLEXIO { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_ftm0/mod.rs b/src/trgmux/trgmux_ftm0/mod.rs index 26eb2da..82d2288 100644 --- a/src/trgmux/trgmux_ftm0/mod.rs +++ b/src/trgmux/trgmux_ftm0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_FTM0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_ftm1/mod.rs b/src/trgmux/trgmux_ftm1/mod.rs index fd0c2fd..9a3cc76 100644 --- a/src/trgmux/trgmux_ftm1/mod.rs +++ b/src/trgmux/trgmux_ftm1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_FTM1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_ftm2/mod.rs b/src/trgmux/trgmux_ftm2/mod.rs index e48d10a..c5cc0ad 100644 --- a/src/trgmux/trgmux_ftm2/mod.rs +++ b/src/trgmux/trgmux_ftm2/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_FTM2 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_ftm3/mod.rs b/src/trgmux/trgmux_ftm3/mod.rs index 69a0640..5562c9b 100644 --- a/src/trgmux/trgmux_ftm3/mod.rs +++ b/src/trgmux/trgmux_ftm3/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_FTM3 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpi2c0/mod.rs b/src/trgmux/trgmux_lpi2c0/mod.rs index c700cc7..c593c3d 100644 --- a/src/trgmux/trgmux_lpi2c0/mod.rs +++ b/src/trgmux/trgmux_lpi2c0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPI2C0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpit0/mod.rs b/src/trgmux/trgmux_lpit0/mod.rs index fdb3e79..65e89aa 100644 --- a/src/trgmux/trgmux_lpit0/mod.rs +++ b/src/trgmux/trgmux_lpit0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPIT0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -87,10 +89,8 @@ impl SEL3R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -193,10 +193,8 @@ impl<'a> _SEL3W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpspi0/mod.rs b/src/trgmux/trgmux_lpspi0/mod.rs index bd15ddb..4a42da6 100644 --- a/src/trgmux/trgmux_lpspi0/mod.rs +++ b/src/trgmux/trgmux_lpspi0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPSPI0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpspi1/mod.rs b/src/trgmux/trgmux_lpspi1/mod.rs index 66e5c62..1b4c494 100644 --- a/src/trgmux/trgmux_lpspi1/mod.rs +++ b/src/trgmux/trgmux_lpspi1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPSPI1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lptmr0/mod.rs b/src/trgmux/trgmux_lptmr0/mod.rs index 177610d..948844d 100644 --- a/src/trgmux/trgmux_lptmr0/mod.rs +++ b/src/trgmux/trgmux_lptmr0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPTMR0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpuart0/mod.rs b/src/trgmux/trgmux_lpuart0/mod.rs index 8edbeb0..d3c58da 100644 --- a/src/trgmux/trgmux_lpuart0/mod.rs +++ b/src/trgmux/trgmux_lpuart0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPUART0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_lpuart1/mod.rs b/src/trgmux/trgmux_lpuart1/mod.rs index 8ddee21..37255cb 100644 --- a/src/trgmux/trgmux_lpuart1/mod.rs +++ b/src/trgmux/trgmux_lpuart1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_LPUART1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_pdb0/mod.rs b/src/trgmux/trgmux_pdb0/mod.rs index ed7a3b0..4085653 100644 --- a/src/trgmux/trgmux_pdb0/mod.rs +++ b/src/trgmux/trgmux_pdb0/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_PDB0 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmux_pdb1/mod.rs b/src/trgmux/trgmux_pdb1/mod.rs index ca54c0e..877134f 100644 --- a/src/trgmux/trgmux_pdb1/mod.rs +++ b/src/trgmux/trgmux_pdb1/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUX_PDB1 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -54,10 +56,8 @@ impl SEL0R { #[doc = "Possible values of the field `LK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LKR { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -115,10 +115,8 @@ impl<'a> _SEL0W<'a> { } #[doc = "Values that can be written to the field `LK`"] pub enum LKW { - #[doc = "Register can be written."] - _0, - #[doc = "Register cannot be written until the next system Reset."] - _1, + #[doc = "Register can be written."] _0, + #[doc = "Register cannot be written until the next system Reset."] _1, } impl LKW { #[allow(missing_docs)] diff --git a/src/trgmux/trgmuxdummy16/mod.rs b/src/trgmux/trgmuxdummy16/mod.rs index 29c2f1a..e1ee501 100644 --- a/src/trgmux/trgmuxdummy16/mod.rs +++ b/src/trgmux/trgmuxdummy16/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY16 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/trgmux/trgmuxdummy22/mod.rs b/src/trgmux/trgmuxdummy22/mod.rs index f36a6a3..50bb709 100644 --- a/src/trgmux/trgmuxdummy22/mod.rs +++ b/src/trgmux/trgmuxdummy22/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY22 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/trgmux/trgmuxdummy5/mod.rs b/src/trgmux/trgmuxdummy5/mod.rs index af16499..86337d4 100644 --- a/src/trgmux/trgmuxdummy5/mod.rs +++ b/src/trgmux/trgmuxdummy5/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY5 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/trgmux/trgmuxdummy6/mod.rs b/src/trgmux/trgmuxdummy6/mod.rs index 5ca0074..6bf0bfa 100644 --- a/src/trgmux/trgmuxdummy6/mod.rs +++ b/src/trgmux/trgmuxdummy6/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY6 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/trgmux/trgmuxdummy8/mod.rs b/src/trgmux/trgmuxdummy8/mod.rs index ceb55b2..573ba5c 100644 --- a/src/trgmux/trgmuxdummy8/mod.rs +++ b/src/trgmux/trgmuxdummy8/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY8 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/trgmux/trgmuxdummy9/mod.rs b/src/trgmux/trgmuxdummy9/mod.rs index 4753e52..768ffda 100644 --- a/src/trgmux/trgmuxdummy9/mod.rs +++ b/src/trgmux/trgmuxdummy9/mod.rs @@ -22,7 +22,9 @@ impl super::TRGMUXDUMMY9 { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/wdog/cnt/mod.rs b/src/wdog/cnt/mod.rs index 9d1d799..15e4451 100644 --- a/src/wdog/cnt/mod.rs +++ b/src/wdog/cnt/mod.rs @@ -22,7 +22,9 @@ impl super::CNT { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/wdog/cs/mod.rs b/src/wdog/cs/mod.rs index 1c481d7..883613b 100644 --- a/src/wdog/cs/mod.rs +++ b/src/wdog/cs/mod.rs @@ -22,7 +22,9 @@ impl super::CS { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] @@ -43,10 +45,8 @@ impl super::CS { #[doc = "Possible values of the field `STOP`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STOPR { - #[doc = "Watchdog disabled in chip stop mode."] - _0, - #[doc = "Watchdog enabled in chip stop mode."] - _1, + #[doc = "Watchdog disabled in chip stop mode."] _0, + #[doc = "Watchdog enabled in chip stop mode."] _1, } impl STOPR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -90,10 +90,8 @@ impl STOPR { #[doc = "Possible values of the field `WAIT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WAITR { - #[doc = "Watchdog disabled in chip wait mode."] - _0, - #[doc = "Watchdog enabled in chip wait mode."] - _1, + #[doc = "Watchdog disabled in chip wait mode."] _0, + #[doc = "Watchdog enabled in chip wait mode."] _1, } impl WAITR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -137,10 +135,8 @@ impl WAITR { #[doc = "Possible values of the field `DBG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DBGR { - #[doc = "Watchdog disabled in chip debug mode."] - _0, - #[doc = "Watchdog enabled in chip debug mode."] - _1, + #[doc = "Watchdog disabled in chip debug mode."] _0, + #[doc = "Watchdog enabled in chip debug mode."] _1, } impl DBGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -184,8 +180,7 @@ impl DBGR { #[doc = "Possible values of the field `TST`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TSTR { - #[doc = "Watchdog test mode disabled."] - _00, + #[doc = "Watchdog test mode disabled."] _00, #[doc = "Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode."] _01, #[doc = "Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]."] @@ -287,8 +282,7 @@ impl UPDATER { #[doc = "Possible values of the field `INT`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum INTR { - #[doc = "Watchdog interrupts are disabled. Watchdog resets are not delayed."] - _0, + #[doc = "Watchdog interrupts are disabled. Watchdog resets are not delayed."] _0, #[doc = "Watchdog interrupts are enabled. Watchdog resets are delayed by 8'd128 bus clocks from the interrupt vector fetch."] _1, } @@ -334,10 +328,8 @@ impl INTR { #[doc = "Possible values of the field `EN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ENR { - #[doc = "Watchdog disabled."] - _0, - #[doc = "Watchdog enabled."] - _1, + #[doc = "Watchdog disabled."] _0, + #[doc = "Watchdog enabled."] _1, } impl ENR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -381,14 +373,10 @@ impl ENR { #[doc = "Possible values of the field `CLK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKR { - #[doc = "Bus clock"] - _00, - #[doc = "LPO clock"] - _01, - #[doc = "INTCLK (internal clock)"] - _10, - #[doc = "ERCLK (external reference clock)"] - _11, + #[doc = "Bus clock"] _00, + #[doc = "LPO clock"] _01, + #[doc = "INTCLK (internal clock)"] _10, + #[doc = "ERCLK (external reference clock)"] _11, } impl CLKR { #[doc = r" Value of the field as raw bits"] @@ -437,10 +425,8 @@ impl CLKR { #[doc = "Possible values of the field `RCS`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum RCSR { - #[doc = "Reconfiguring WDOG."] - _0, - #[doc = "Reconfiguration is successful."] - _1, + #[doc = "Reconfiguring WDOG."] _0, + #[doc = "Reconfiguration is successful."] _1, } impl RCSR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -484,10 +470,8 @@ impl RCSR { #[doc = "Possible values of the field `ULK`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ULKR { - #[doc = "WDOG is locked."] - _0, - #[doc = "WDOG is unlocked."] - _1, + #[doc = "WDOG is locked."] _0, + #[doc = "WDOG is unlocked."] _1, } impl ULKR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -531,10 +515,8 @@ impl ULKR { #[doc = "Possible values of the field `PRES`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PRESR { - #[doc = "256 prescaler disabled."] - _0, - #[doc = "256 prescaler enabled."] - _1, + #[doc = "256 prescaler disabled."] _0, + #[doc = "256 prescaler enabled."] _1, } impl PRESR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -625,10 +607,8 @@ impl CMD32ENR { #[doc = "Possible values of the field `FLG`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FLGR { - #[doc = "No interrupt occurred."] - _0, - #[doc = "An interrupt occurred."] - _1, + #[doc = "No interrupt occurred."] _0, + #[doc = "An interrupt occurred."] _1, } impl FLGR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -672,10 +652,8 @@ impl FLGR { #[doc = "Possible values of the field `WIN`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WINR { - #[doc = "Window mode disabled."] - _0, - #[doc = "Window mode enabled."] - _1, + #[doc = "Window mode disabled."] _0, + #[doc = "Window mode enabled."] _1, } impl WINR { #[doc = r" Returns `true` if the bit is clear (0)"] @@ -718,10 +696,8 @@ impl WINR { } #[doc = "Values that can be written to the field `STOP`"] pub enum STOPW { - #[doc = "Watchdog disabled in chip stop mode."] - _0, - #[doc = "Watchdog enabled in chip stop mode."] - _1, + #[doc = "Watchdog disabled in chip stop mode."] _0, + #[doc = "Watchdog enabled in chip stop mode."] _1, } impl STOPW { #[allow(missing_docs)] @@ -776,10 +752,8 @@ impl<'a> _STOPW<'a> { } #[doc = "Values that can be written to the field `WAIT`"] pub enum WAITW { - #[doc = "Watchdog disabled in chip wait mode."] - _0, - #[doc = "Watchdog enabled in chip wait mode."] - _1, + #[doc = "Watchdog disabled in chip wait mode."] _0, + #[doc = "Watchdog enabled in chip wait mode."] _1, } impl WAITW { #[allow(missing_docs)] @@ -834,10 +808,8 @@ impl<'a> _WAITW<'a> { } #[doc = "Values that can be written to the field `DBG`"] pub enum DBGW { - #[doc = "Watchdog disabled in chip debug mode."] - _0, - #[doc = "Watchdog enabled in chip debug mode."] - _1, + #[doc = "Watchdog disabled in chip debug mode."] _0, + #[doc = "Watchdog enabled in chip debug mode."] _1, } impl DBGW { #[allow(missing_docs)] @@ -892,8 +864,7 @@ impl<'a> _DBGW<'a> { } #[doc = "Values that can be written to the field `TST`"] pub enum TSTW { - #[doc = "Watchdog test mode disabled."] - _00, + #[doc = "Watchdog test mode disabled."] _00, #[doc = "Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode."] _01, #[doc = "Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]."] @@ -1016,8 +987,7 @@ impl<'a> _UPDATEW<'a> { } #[doc = "Values that can be written to the field `INT`"] pub enum INTW { - #[doc = "Watchdog interrupts are disabled. Watchdog resets are not delayed."] - _0, + #[doc = "Watchdog interrupts are disabled. Watchdog resets are not delayed."] _0, #[doc = "Watchdog interrupts are enabled. Watchdog resets are delayed by 8'd128 bus clocks from the interrupt vector fetch."] _1, } @@ -1074,10 +1044,8 @@ impl<'a> _INTW<'a> { } #[doc = "Values that can be written to the field `EN`"] pub enum ENW { - #[doc = "Watchdog disabled."] - _0, - #[doc = "Watchdog enabled."] - _1, + #[doc = "Watchdog disabled."] _0, + #[doc = "Watchdog enabled."] _1, } impl ENW { #[allow(missing_docs)] @@ -1132,14 +1100,10 @@ impl<'a> _ENW<'a> { } #[doc = "Values that can be written to the field `CLK`"] pub enum CLKW { - #[doc = "Bus clock"] - _00, - #[doc = "LPO clock"] - _01, - #[doc = "INTCLK (internal clock)"] - _10, - #[doc = "ERCLK (external reference clock)"] - _11, + #[doc = "Bus clock"] _00, + #[doc = "LPO clock"] _01, + #[doc = "INTCLK (internal clock)"] _10, + #[doc = "ERCLK (external reference clock)"] _11, } impl CLKW { #[allow(missing_docs)] @@ -1198,10 +1162,8 @@ impl<'a> _CLKW<'a> { } #[doc = "Values that can be written to the field `PRES`"] pub enum PRESW { - #[doc = "256 prescaler disabled."] - _0, - #[doc = "256 prescaler enabled."] - _1, + #[doc = "256 prescaler disabled."] _0, + #[doc = "256 prescaler enabled."] _1, } impl PRESW { #[allow(missing_docs)] @@ -1314,10 +1276,8 @@ impl<'a> _CMD32ENW<'a> { } #[doc = "Values that can be written to the field `FLG`"] pub enum FLGW { - #[doc = "No interrupt occurred."] - _0, - #[doc = "An interrupt occurred."] - _1, + #[doc = "No interrupt occurred."] _0, + #[doc = "An interrupt occurred."] _1, } impl FLGW { #[allow(missing_docs)] @@ -1372,10 +1332,8 @@ impl<'a> _FLGW<'a> { } #[doc = "Values that can be written to the field `WIN`"] pub enum WINW { - #[doc = "Window mode disabled."] - _0, - #[doc = "Window mode enabled."] - _1, + #[doc = "Window mode disabled."] _0, + #[doc = "Window mode enabled."] _1, } impl WINW { #[allow(missing_docs)] diff --git a/src/wdog/mod.rs b/src/wdog/mod.rs index 5a5d838..5478caa 100644 --- a/src/wdog/mod.rs +++ b/src/wdog/mod.rs @@ -2,14 +2,10 @@ use vcell::VolatileCell; #[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - Watchdog Control and Status Register"] - pub cs: CS, - #[doc = "0x04 - Watchdog Counter Register"] - pub cnt: CNT, - #[doc = "0x08 - Watchdog Timeout Value Register"] - pub toval: TOVAL, - #[doc = "0x0c - Watchdog Window Register"] - pub win: WIN, + #[doc = "0x00 - Watchdog Control and Status Register"] pub cs: CS, + #[doc = "0x04 - Watchdog Counter Register"] pub cnt: CNT, + #[doc = "0x08 - Watchdog Timeout Value Register"] pub toval: TOVAL, + #[doc = "0x0c - Watchdog Window Register"] pub win: WIN, } #[doc = "Watchdog Control and Status Register"] pub struct CS { diff --git a/src/wdog/toval/mod.rs b/src/wdog/toval/mod.rs index 9460ea1..a8438c8 100644 --- a/src/wdog/toval/mod.rs +++ b/src/wdog/toval/mod.rs @@ -22,7 +22,9 @@ impl super::TOVAL { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline] diff --git a/src/wdog/win/mod.rs b/src/wdog/win/mod.rs index 3de9e32..96ccf6b 100644 --- a/src/wdog/win/mod.rs +++ b/src/wdog/win/mod.rs @@ -22,7 +22,9 @@ impl super::WIN { #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { - R { bits: self.register.get() } + R { + bits: self.register.get(), + } } #[doc = r" Writes to the register"] #[inline]