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Same as last commit just run through the form tool (splits up large lib.rs files)

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This commit is contained in:
Kjetil Kjeka 2017-09-23 20:09:53 +02:00
parent 63efe927e5
commit 7facea48b2
1680 changed files with 666069 additions and 667757 deletions
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103
src/adc0/base_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::BASE_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BA_OFSR {
bits: u8,
}
impl BA_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BA_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _BA_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&self) -> BA_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BA_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 64 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&mut self) -> _BA_OFSW {
_BA_OFSW { w: self }
}
}

482
src/adc0/cfg1/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADICLK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADICLKR {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADICLKR::_00 => 0,
ADICLKR::_01 => 1,
ADICLKR::_10 => 2,
ADICLKR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADICLKR {
match value {
0 => ADICLKR::_00,
1 => ADICLKR::_01,
2 => ADICLKR::_10,
3 => ADICLKR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADICLKR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADICLKR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADICLKR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADICLKR::_11
}
}
#[doc = "Possible values of the field `MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODER {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
MODER::_00 => 0,
MODER::_01 => 1,
MODER::_10 => 2,
MODER::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> MODER {
match value {
0 => MODER::_00,
1 => MODER::_01,
2 => MODER::_10,
i => MODER::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == MODER::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == MODER::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == MODER::_10
}
}
#[doc = "Possible values of the field `ADIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADIVR {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADIVR::_00 => 0,
ADIVR::_01 => 1,
ADIVR::_10 => 2,
ADIVR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADIVR {
match value {
0 => ADIVR::_00,
1 => ADIVR::_01,
2 => ADIVR::_10,
3 => ADIVR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADIVR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADIVR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADIVR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADIVR::_11
}
}
#[doc = "Values that can be written to the field `ADICLK`"]
pub enum ADICLKW {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADICLKW::_00 => 0,
ADICLKW::_01 => 1,
ADICLKW::_10 => 2,
ADICLKW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADICLKW<'a> {
w: &'a mut W,
}
impl<'a> _ADICLKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADICLKW::_00)
}
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADICLKW::_01)
}
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADICLKW::_10)
}
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADICLKW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
}
impl MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
MODEW::_00 => 0,
MODEW::_01 => 1,
MODEW::_10 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _MODEW<'a> {
w: &'a mut W,
}
impl<'a> _MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODEW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8-bit conversion."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(MODEW::_00)
}
#[doc = "12-bit conversion."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(MODEW::_01)
}
#[doc = "10-bit conversion."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(MODEW::_10)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADIV`"]
pub enum ADIVW {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADIVW::_00 => 0,
ADIVW::_01 => 1,
ADIVW::_10 => 2,
ADIVW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADIVW<'a> {
w: &'a mut W,
}
impl<'a> _ADIVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADIVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADIVW::_00)
}
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADIVW::_01)
}
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADIVW::_10)
}
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADIVW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLRLTRGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRLTRGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&self) -> ADICLKR {
ADICLKR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&self) -> ADIVR {
ADIVR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&mut self) -> _ADICLKW {
_ADICLKW { w: self }
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&mut self) -> _ADIVW {
_ADIVW { w: self }
}
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
#[inline]
pub fn clrltrg(&mut self) -> _CLRLTRGW {
_CLRLTRGW { w: self }
}
}

103
src/adc0/cfg2/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SMPLTSR {
bits: u8,
}
impl SMPLTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SMPLTSW<'a> {
w: &'a mut W,
}
impl<'a> _SMPLTSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&self) -> SMPLTSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SMPLTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 12 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&mut self) -> _SMPLTSW {
_SMPLTSW { w: self }
}
}

103
src/adc0/clp0/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0R {
bits: u8,
}
impl CLP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0W<'a> {
w: &'a mut W,
}
impl<'a> _CLP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&self) -> CLP0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&mut self) -> _CLP0W {
_CLP0W { w: self }
}
}

103
src/adc0/clp0_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0_OFSR {
bits: u8,
}
impl CLP0_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP0_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&self) -> CLP0_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
_CLP0_OFSW { w: self }
}
}

103
src/adc0/clp1/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1R {
bits: u16,
}
impl CLP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1W<'a> {
w: &'a mut W,
}
impl<'a> _CLP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&self) -> CLP1R {
let bits = {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 92 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&mut self) -> _CLP1W {
_CLP1W { w: self }
}
}

103
src/adc0/clp1_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1_OFSR {
bits: u8,
}
impl CLP1_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP1_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&self) -> CLP1_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP1_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
_CLP1_OFSW { w: self }
}
}

103
src/adc0/clp2/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2R {
bits: u16,
}
impl CLP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2W<'a> {
w: &'a mut W,
}
impl<'a> _CLP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&self) -> CLP2R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 184 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&mut self) -> _CLP2W {
_CLP2W { w: self }
}
}

103
src/adc0/clp2_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2_OFSR {
bits: u8,
}
impl CLP2_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP2_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&self) -> CLP2_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP2_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
_CLP2_OFSW { w: self }
}
}

103
src/adc0/clp3/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3R {
bits: u16,
}
impl CLP3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3W<'a> {
w: &'a mut W,
}
impl<'a> _CLP3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&self) -> CLP3R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 384 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&mut self) -> _CLP3W {
_CLP3W { w: self }
}
}

103
src/adc0/clp3_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3_OFSR {
bits: u8,
}
impl CLP3_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP3_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&self) -> CLP3_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP3_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
_CLP3_OFSW { w: self }
}
}

103
src/adc0/clp9/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9R {
bits: u8,
}
impl CLP9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9W<'a> {
w: &'a mut W,
}
impl<'a> _CLP9W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&self) -> CLP9R {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP9R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&mut self) -> _CLP9W {
_CLP9W { w: self }
}
}

103
src/adc0/clp9_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9_OFSR {
bits: u16,
}
impl CLP9_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP9_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&self) -> CLP9_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP9_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 576 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
_CLP9_OFSW { w: self }
}
}

103
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPSR {
bits: u8,
}
impl CLPSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&self) -> CLPSR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&mut self) -> _CLPSW {
_CLPSW { w: self }
}
}

103
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPS_OFSR {
bits: u8,
}
impl CLPS_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPS_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPS_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&self) -> CLPS_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPS_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
_CLPS_OFSW { w: self }
}
}

103
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPXR {
bits: u8,
}
impl CLPXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPXW<'a> {
w: &'a mut W,
}
impl<'a> _CLPXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&self) -> CLPXR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&mut self) -> _CLPXW {
_CLPXW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPX_OFSR {
bits: u16,
}
impl CLPX_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPX_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPX_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&self) -> CLPX_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLPX_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1088 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
_CLPX_OFSW { w: self }
}
}

103
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CVR {
bits: u16,
}
impl CVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CVW<'a> {
w: &'a mut W,
}
impl<'a> _CVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&self) -> CVR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&mut self) -> _CVW {
_CVW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::G {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GR {
bits: u16,
}
impl GR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GW<'a> {
w: &'a mut W,
}
impl<'a> _GW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&self) -> GR {
let bits = {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
GR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 752 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&mut self) -> _GW {
_GW { w: self }
}
}

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use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - ADC Status and Control Register 1"]
pub sc1a: SC1,
#[doc = "0x04 - ADC Status and Control Register 1"]
pub sc1b: SC1,
#[doc = "0x08 - ADC Status and Control Register 1"]
pub sc1c: SC1,
#[doc = "0x0c - ADC Status and Control Register 1"]
pub sc1d: SC1,
#[doc = "0x10 - ADC Status and Control Register 1"]
pub sc1e: SC1,
#[doc = "0x14 - ADC Status and Control Register 1"]
pub sc1f: SC1,
#[doc = "0x18 - ADC Status and Control Register 1"]
pub sc1g: SC1,
#[doc = "0x1c - ADC Status and Control Register 1"]
pub sc1h: SC1,
#[doc = "0x20 - ADC Status and Control Register 1"]
pub sc1i: SC1,
#[doc = "0x24 - ADC Status and Control Register 1"]
pub sc1j: SC1,
#[doc = "0x28 - ADC Status and Control Register 1"]
pub sc1k: SC1,
#[doc = "0x2c - ADC Status and Control Register 1"]
pub sc1l: SC1,
#[doc = "0x30 - ADC Status and Control Register 1"]
pub sc1m: SC1,
#[doc = "0x34 - ADC Status and Control Register 1"]
pub sc1n: SC1,
#[doc = "0x38 - ADC Status and Control Register 1"]
pub sc1o: SC1,
#[doc = "0x3c - ADC Status and Control Register 1"]
pub sc1p: SC1,
#[doc = "0x40 - ADC Configuration Register 1"]
pub cfg1: CFG1,
#[doc = "0x44 - ADC Configuration Register 2"]
pub cfg2: CFG2,
#[doc = "0x48 - ADC Data Result Registers"]
pub ra: R,
#[doc = "0x4c - ADC Data Result Registers"]
pub rb: R,
#[doc = "0x50 - ADC Data Result Registers"]
pub rc: R,
#[doc = "0x54 - ADC Data Result Registers"]
pub rd: R,
#[doc = "0x58 - ADC Data Result Registers"]
pub re: R,
#[doc = "0x5c - ADC Data Result Registers"]
pub rf: R,
#[doc = "0x60 - ADC Data Result Registers"]
pub rg: R,
#[doc = "0x64 - ADC Data Result Registers"]
pub rh: R,
#[doc = "0x68 - ADC Data Result Registers"]
pub ri: R,
#[doc = "0x6c - ADC Data Result Registers"]
pub rj: R,
#[doc = "0x70 - ADC Data Result Registers"]
pub rk: R,
#[doc = "0x74 - ADC Data Result Registers"]
pub rl: R,
#[doc = "0x78 - ADC Data Result Registers"]
pub rm: R,
#[doc = "0x7c - ADC Data Result Registers"]
pub rn: R,
#[doc = "0x80 - ADC Data Result Registers"]
pub ro: R,
#[doc = "0x84 - ADC Data Result Registers"]
pub rp: R,
#[doc = "0x88 - Compare Value Registers"]
pub cv1: CV,
#[doc = "0x8c - Compare Value Registers"]
pub cv2: CV,
#[doc = "0x90 - Status and Control Register 2"]
pub sc2: SC2,
#[doc = "0x94 - Status and Control Register 3"]
pub sc3: SC3,
#[doc = "0x98 - BASE Offset Register"]
pub base_ofs: BASE_OFS,
#[doc = "0x9c - ADC Offset Correction Register"]
pub ofs: OFS,
#[doc = "0xa0 - USER Offset Correction Register"]
pub usr_ofs: USR_OFS,
#[doc = "0xa4 - ADC X Offset Correction Register"]
pub xofs: XOFS,
#[doc = "0xa8 - ADC Y Offset Correction Register"]
pub yofs: YOFS,
#[doc = "0xac - ADC Gain Register"]
pub g: G,
#[doc = "0xb0 - ADC User Gain Register"]
pub ug: UG,
#[doc = "0xb4 - ADC General Calibration Value Register S"]
pub clps: CLPS,
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
pub clp3: CLP3,
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
pub clp2: CLP2,
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
pub clp1: CLP1,
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
pub clp0: CLP0,
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
pub clpx: CLPX,
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
pub clp9: CLP9,
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
pub clps_ofs: CLPS_OFS,
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
pub clp3_ofs: CLP3_OFS,
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
pub clp2_ofs: CLP2_OFS,
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
pub clp1_ofs: CLP1_OFS,
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
pub clp0_ofs: CLP0_OFS,
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
pub clpx_ofs: CLPX_OFS,
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
pub clp9_ofs: CLP9_OFS,
}
#[doc = "ADC Status and Control Register 1"]
pub struct SC1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Status and Control Register 1"]
pub mod sc1;
#[doc = "ADC Configuration Register 1"]
pub struct CFG1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 1"]
pub mod cfg1;
#[doc = "ADC Configuration Register 2"]
pub struct CFG2 {
register: VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 2"]
pub mod cfg2;
#[doc = "ADC Data Result Registers"]
pub struct R {
register: VolatileCell<u32>,
}
#[doc = "ADC Data Result Registers"]
pub mod r;
#[doc = "Compare Value Registers"]
pub struct CV {
register: VolatileCell<u32>,
}
#[doc = "Compare Value Registers"]
pub mod cv;
#[doc = "Status and Control Register 2"]
pub struct SC2 {
register: VolatileCell<u32>,
}
#[doc = "Status and Control Register 2"]
pub mod sc2;
#[doc = "Status and Control Register 3"]
pub struct SC3 {
register: VolatileCell<u32>,
}
#[doc = "Status and Control Register 3"]
pub mod sc3;
#[doc = "BASE Offset Register"]
pub struct BASE_OFS {
register: VolatileCell<u32>,
}
#[doc = "BASE Offset Register"]
pub mod base_ofs;
#[doc = "ADC Offset Correction Register"]
pub struct OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Offset Correction Register"]
pub mod ofs;
#[doc = "USER Offset Correction Register"]
pub struct USR_OFS {
register: VolatileCell<u32>,
}
#[doc = "USER Offset Correction Register"]
pub mod usr_ofs;
#[doc = "ADC X Offset Correction Register"]
pub struct XOFS {
register: VolatileCell<u32>,
}
#[doc = "ADC X Offset Correction Register"]
pub mod xofs;
#[doc = "ADC Y Offset Correction Register"]
pub struct YOFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Y Offset Correction Register"]
pub mod yofs;
#[doc = "ADC Gain Register"]
pub struct G {
register: VolatileCell<u32>,
}
#[doc = "ADC Gain Register"]
pub mod g;
#[doc = "ADC User Gain Register"]
pub struct UG {
register: VolatileCell<u32>,
}
#[doc = "ADC User Gain Register"]
pub mod ug;
#[doc = "ADC General Calibration Value Register S"]
pub struct CLPS {
register: VolatileCell<u32>,
}
#[doc = "ADC General Calibration Value Register S"]
pub mod clps;
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub struct CLP3 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub mod clp3;
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub struct CLP2 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub mod clp2;
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub struct CLP1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub mod clp1;
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub struct CLP0 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub mod clp0;
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub struct CLPX {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub mod clpx;
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub struct CLP9 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub mod clp9;
#[doc = "ADC General Calibration Offset Value Register S"]
pub struct CLPS_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC General Calibration Offset Value Register S"]
pub mod clps_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub struct CLP3_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub mod clp3_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub struct CLP2_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub mod clp2_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub struct CLP1_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub mod clp1_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub struct CLP0_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub mod clp0_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub struct CLPX_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub mod clpx_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub struct CLP9_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub mod clp9_ofs;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct OFSR {
bits: u16,
}
impl OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _OFSW<'a> {
w: &'a mut W,
}
impl<'a> _OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&self) -> OFSR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&mut self) -> _OFSW {
_OFSW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::R {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct DR {
bits: u16,
}
impl DR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Data result"]
#[inline]
pub fn d(&self) -> DR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DR { bits }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCHR {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11110,
#[doc = "Module is disabled"]
_11111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADCHR::_00000 => 0,
ADCHR::_00001 => 1,
ADCHR::_00010 => 2,
ADCHR::_00011 => 3,
ADCHR::_00100 => 4,
ADCHR::_00101 => 5,
ADCHR::_00110 => 6,
ADCHR::_00111 => 7,
ADCHR::_01000 => 8,
ADCHR::_01001 => 9,
ADCHR::_01010 => 10,
ADCHR::_01011 => 11,
ADCHR::_01100 => 12,
ADCHR::_01101 => 13,
ADCHR::_01110 => 14,
ADCHR::_01111 => 15,
ADCHR::_10010 => 18,
ADCHR::_10011 => 19,
ADCHR::_10101 => 21,
ADCHR::_10110 => 22,
ADCHR::_10111 => 23,
ADCHR::_11010 => 26,
ADCHR::_11011 => 27,
ADCHR::_11100 => 28,
ADCHR::_11101 => 29,
ADCHR::_11110 => 30,
ADCHR::_11111 => 31,
ADCHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADCHR {
match value {
0 => ADCHR::_00000,
1 => ADCHR::_00001,
2 => ADCHR::_00010,
3 => ADCHR::_00011,
4 => ADCHR::_00100,
5 => ADCHR::_00101,
6 => ADCHR::_00110,
7 => ADCHR::_00111,
8 => ADCHR::_01000,
9 => ADCHR::_01001,
10 => ADCHR::_01010,
11 => ADCHR::_01011,
12 => ADCHR::_01100,
13 => ADCHR::_01101,
14 => ADCHR::_01110,
15 => ADCHR::_01111,
18 => ADCHR::_10010,
19 => ADCHR::_10011,
21 => ADCHR::_10101,
22 => ADCHR::_10110,
23 => ADCHR::_10111,
26 => ADCHR::_11010,
27 => ADCHR::_11011,
28 => ADCHR::_11100,
29 => ADCHR::_11101,
30 => ADCHR::_11110,
31 => ADCHR::_11111,
i => ADCHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00000`"]
#[inline]
pub fn is_00000(&self) -> bool {
*self == ADCHR::_00000
}
#[doc = "Checks if the value of the field is `_00001`"]
#[inline]
pub fn is_00001(&self) -> bool {
*self == ADCHR::_00001
}
#[doc = "Checks if the value of the field is `_00010`"]
#[inline]
pub fn is_00010(&self) -> bool {
*self == ADCHR::_00010
}
#[doc = "Checks if the value of the field is `_00011`"]
#[inline]
pub fn is_00011(&self) -> bool {
*self == ADCHR::_00011
}
#[doc = "Checks if the value of the field is `_00100`"]
#[inline]
pub fn is_00100(&self) -> bool {
*self == ADCHR::_00100
}
#[doc = "Checks if the value of the field is `_00101`"]
#[inline]
pub fn is_00101(&self) -> bool {
*self == ADCHR::_00101
}
#[doc = "Checks if the value of the field is `_00110`"]
#[inline]
pub fn is_00110(&self) -> bool {
*self == ADCHR::_00110
}
#[doc = "Checks if the value of the field is `_00111`"]
#[inline]
pub fn is_00111(&self) -> bool {
*self == ADCHR::_00111
}
#[doc = "Checks if the value of the field is `_01000`"]
#[inline]
pub fn is_01000(&self) -> bool {
*self == ADCHR::_01000
}
#[doc = "Checks if the value of the field is `_01001`"]
#[inline]
pub fn is_01001(&self) -> bool {
*self == ADCHR::_01001
}
#[doc = "Checks if the value of the field is `_01010`"]
#[inline]
pub fn is_01010(&self) -> bool {
*self == ADCHR::_01010
}
#[doc = "Checks if the value of the field is `_01011`"]
#[inline]
pub fn is_01011(&self) -> bool {
*self == ADCHR::_01011
}
#[doc = "Checks if the value of the field is `_01100`"]
#[inline]
pub fn is_01100(&self) -> bool {
*self == ADCHR::_01100
}
#[doc = "Checks if the value of the field is `_01101`"]
#[inline]
pub fn is_01101(&self) -> bool {
*self == ADCHR::_01101
}
#[doc = "Checks if the value of the field is `_01110`"]
#[inline]
pub fn is_01110(&self) -> bool {
*self == ADCHR::_01110
}
#[doc = "Checks if the value of the field is `_01111`"]
#[inline]
pub fn is_01111(&self) -> bool {
*self == ADCHR::_01111
}
#[doc = "Checks if the value of the field is `_10010`"]
#[inline]
pub fn is_10010(&self) -> bool {
*self == ADCHR::_10010
}
#[doc = "Checks if the value of the field is `_10011`"]
#[inline]
pub fn is_10011(&self) -> bool {
*self == ADCHR::_10011
}
#[doc = "Checks if the value of the field is `_10101`"]
#[inline]
pub fn is_10101(&self) -> bool {
*self == ADCHR::_10101
}
#[doc = "Checks if the value of the field is `_10110`"]
#[inline]
pub fn is_10110(&self) -> bool {
*self == ADCHR::_10110
}
#[doc = "Checks if the value of the field is `_10111`"]
#[inline]
pub fn is_10111(&self) -> bool {
*self == ADCHR::_10111
}
#[doc = "Checks if the value of the field is `_11010`"]
#[inline]
pub fn is_11010(&self) -> bool {
*self == ADCHR::_11010
}
#[doc = "Checks if the value of the field is `_11011`"]
#[inline]
pub fn is_11011(&self) -> bool {
*self == ADCHR::_11011
}
#[doc = "Checks if the value of the field is `_11100`"]
#[inline]
pub fn is_11100(&self) -> bool {
*self == ADCHR::_11100
}
#[doc = "Checks if the value of the field is `_11101`"]
#[inline]
pub fn is_11101(&self) -> bool {
*self == ADCHR::_11101
}
#[doc = "Checks if the value of the field is `_11110`"]
#[inline]
pub fn is_11110(&self) -> bool {
*self == ADCHR::_11110
}
#[doc = "Checks if the value of the field is `_11111`"]
#[inline]
pub fn is_11111(&self) -> bool {
*self == ADCHR::_11111
}
}
#[doc = "Possible values of the field `AIEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AIENR {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AIENR::_0 => false,
AIENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AIENR {
match value {
false => AIENR::_0,
true => AIENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AIENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AIENR::_1
}
}
#[doc = "Possible values of the field `COCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COCOR {
#[doc = "Conversion is not completed."]
_0,
#[doc = "Conversion is completed."]
_1,
}
impl COCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
COCOR::_0 => false,
COCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> COCOR {
match value {
false => COCOR::_0,
true => COCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == COCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == COCOR::_1
}
}
#[doc = "Values that can be written to the field `ADCH`"]
pub enum ADCHW {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11110,
#[doc = "Module is disabled"]
_11111,
}
impl ADCHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADCHW::_00000 => 0,
ADCHW::_00001 => 1,
ADCHW::_00010 => 2,
ADCHW::_00011 => 3,
ADCHW::_00100 => 4,
ADCHW::_00101 => 5,
ADCHW::_00110 => 6,
ADCHW::_00111 => 7,
ADCHW::_01000 => 8,
ADCHW::_01001 => 9,
ADCHW::_01010 => 10,
ADCHW::_01011 => 11,
ADCHW::_01100 => 12,
ADCHW::_01101 => 13,
ADCHW::_01110 => 14,
ADCHW::_01111 => 15,
ADCHW::_10010 => 18,
ADCHW::_10011 => 19,
ADCHW::_10101 => 21,
ADCHW::_10110 => 22,
ADCHW::_10111 => 23,
ADCHW::_11010 => 26,
ADCHW::_11011 => 27,
ADCHW::_11100 => 28,
ADCHW::_11101 => 29,
ADCHW::_11110 => 30,
ADCHW::_11111 => 31,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCHW<'a> {
w: &'a mut W,
}
impl<'a> _ADCHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Exernal channel 0 is selected as input."]
#[inline]
pub fn _00000(self) -> &'a mut W {
self.variant(ADCHW::_00000)
}
#[doc = "Exernal channel 1 is selected as input."]
#[inline]
pub fn _00001(self) -> &'a mut W {
self.variant(ADCHW::_00001)
}
#[doc = "Exernal channel 2 is selected as input."]
#[inline]
pub fn _00010(self) -> &'a mut W {
self.variant(ADCHW::_00010)
}
#[doc = "Exernal channel 3 is selected as input."]
#[inline]
pub fn _00011(self) -> &'a mut W {
self.variant(ADCHW::_00011)
}
#[doc = "Exernal channel 4 is selected as input."]
#[inline]
pub fn _00100(self) -> &'a mut W {
self.variant(ADCHW::_00100)
}
#[doc = "Exernal channel 5 is selected as input."]
#[inline]
pub fn _00101(self) -> &'a mut W {
self.variant(ADCHW::_00101)
}
#[doc = "Exernal channel 6 is selected as input."]
#[inline]
pub fn _00110(self) -> &'a mut W {
self.variant(ADCHW::_00110)
}
#[doc = "Exernal channel 7 is selected as input."]
#[inline]
pub fn _00111(self) -> &'a mut W {
self.variant(ADCHW::_00111)
}
#[doc = "Exernal channel 8 is selected as input."]
#[inline]
pub fn _01000(self) -> &'a mut W {
self.variant(ADCHW::_01000)
}
#[doc = "Exernal channel 9 is selected as input."]
#[inline]
pub fn _01001(self) -> &'a mut W {
self.variant(ADCHW::_01001)
}
#[doc = "Exernal channel 10 is selected as input."]
#[inline]
pub fn _01010(self) -> &'a mut W {
self.variant(ADCHW::_01010)
}
#[doc = "Exernal channel 11 is selected as input."]
#[inline]
pub fn _01011(self) -> &'a mut W {
self.variant(ADCHW::_01011)
}
#[doc = "Exernal channel 12 is selected as input."]
#[inline]
pub fn _01100(self) -> &'a mut W {
self.variant(ADCHW::_01100)
}
#[doc = "Exernal channel 13 is selected as input."]
#[inline]
pub fn _01101(self) -> &'a mut W {
self.variant(ADCHW::_01101)
}
#[doc = "Exernal channel 14 is selected as input."]
#[inline]
pub fn _01110(self) -> &'a mut W {
self.variant(ADCHW::_01110)
}
#[doc = "Exernal channel 15 is selected as input."]
#[inline]
pub fn _01111(self) -> &'a mut W {
self.variant(ADCHW::_01111)
}
#[doc = "Exernal channel 18 is selected as input."]
#[inline]
pub fn _10010(self) -> &'a mut W {
self.variant(ADCHW::_10010)
}
#[doc = "Exernal channel 19 is selected as input."]
#[inline]
pub fn _10011(self) -> &'a mut W {
self.variant(ADCHW::_10011)
}
#[doc = "Internal channel 0 is selected as input."]
#[inline]
pub fn _10101(self) -> &'a mut W {
self.variant(ADCHW::_10101)
}
#[doc = "Internal channel 1 is selected as input."]
#[inline]
pub fn _10110(self) -> &'a mut W {
self.variant(ADCHW::_10110)
}
#[doc = "Internal channel 2 is selected as input."]
#[inline]
pub fn _10111(self) -> &'a mut W {
self.variant(ADCHW::_10111)
}
#[doc = "Temp Sensor"]
#[inline]
pub fn _11010(self) -> &'a mut W {
self.variant(ADCHW::_11010)
}
#[doc = "Band Gap"]
#[inline]
pub fn _11011(self) -> &'a mut W {
self.variant(ADCHW::_11011)
}
#[doc = "Internal channel 3 is selected as input."]
#[inline]
pub fn _11100(self) -> &'a mut W {
self.variant(ADCHW::_11100)
}
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
#[inline]
pub fn _11101(self) -> &'a mut W {
self.variant(ADCHW::_11101)
}
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
#[inline]
pub fn _11110(self) -> &'a mut W {
self.variant(ADCHW::_11110)
}
#[doc = "Module is disabled"]
#[inline]
pub fn _11111(self) -> &'a mut W {
self.variant(ADCHW::_11111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AIEN`"]
pub enum AIENW {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AIENW::_0 => false,
AIENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AIENW<'a> {
w: &'a mut W,
}
impl<'a> _AIENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AIENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Conversion complete interrupt is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AIENW::_0)
}
#[doc = "Conversion complete interrupt is enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AIENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&self) -> ADCHR {
ADCHR::_from({
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&self) -> AIENR {
AIENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Complete Flag"]
#[inline]
pub fn coco(&self) -> COCOR {
COCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 31 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&mut self) -> _ADCHW {
_ADCHW { w: self }
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&mut self) -> _AIENW {
_AIENW { w: self }
}
}

817
src/adc0/sc2/mod.rs Normal file
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@ -0,0 +1,817 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `REFSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REFSELR {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl REFSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
REFSELR::_00 => 0,
REFSELR::_01 => 1,
REFSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> REFSELR {
match value {
0 => REFSELR::_00,
1 => REFSELR::_01,
i => REFSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == REFSELR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == REFSELR::_01
}
}
#[doc = "Possible values of the field `DMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAENR {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
_1,
}
impl DMAENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMAENR::_0 => false,
DMAENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMAENR {
match value {
false => DMAENR::_0,
true => DMAENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == DMAENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == DMAENR::_1
}
}
#[doc = r" Value of the field"]
pub struct ACRENR {
bits: bool,
}
impl ACRENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ACFGTR {
bits: bool,
}
impl ACFGTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `ACFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACFER {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ACFER::_0 => false,
ACFER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ACFER {
match value {
false => ACFER::_0,
true => ACFER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ACFER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ACFER::_1
}
}
#[doc = "Possible values of the field `ADTRG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADTRGR {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADTRGR::_0 => false,
ADTRGR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADTRGR {
match value {
false => ADTRGR::_0,
true => ADTRGR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADTRGR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADTRGR::_1
}
}
#[doc = "Possible values of the field `ADACT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADACTR {
#[doc = "Conversion not in progress."]
_0,
#[doc = "Conversion in progress."]
_1,
}
impl ADACTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADACTR::_0 => false,
ADACTR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADACTR {
match value {
false => ADACTR::_0,
true => ADACTR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADACTR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADACTR::_1
}
}
#[doc = r" Value of the field"]
pub struct TRGPRNUMR {
bits: u8,
}
impl TRGPRNUMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `TRGSTLAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTLATR {
#[doc = "No trigger request has been latched"]
_0,
#[doc = "A trigger request has been latched"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTLATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTLATR::_0 => 0,
TRGSTLATR::_1 => 1,
TRGSTLATR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTLATR {
match value {
0 => TRGSTLATR::_0,
1 => TRGSTLATR::_1,
i => TRGSTLATR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTLATR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTLATR::_1
}
}
#[doc = "Possible values of the field `TRGSTERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTERRR {
#[doc = "No error has occurred"]
_0,
#[doc = "An error has occurred"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTERRR::_0 => 0,
TRGSTERRR::_1 => 1,
TRGSTERRR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTERRR {
match value {
0 => TRGSTERRR::_0,
1 => TRGSTERRR::_1,
i => TRGSTERRR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTERRR::_1
}
}
#[doc = "Values that can be written to the field `REFSEL`"]
pub enum REFSELW {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
}
impl REFSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
REFSELW::_00 => 0,
REFSELW::_01 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _REFSELW<'a> {
w: &'a mut W,
}
impl<'a> _REFSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: REFSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(REFSELW::_00)
}
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(REFSELW::_01)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMAEN`"]
pub enum DMAENW {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
_1,
}
impl DMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMAENW::_0 => false,
DMAENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMAENW<'a> {
w: &'a mut W,
}
impl<'a> _DMAENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(DMAENW::_0)
}
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(DMAENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACRENW<'a> {
w: &'a mut W,
}
impl<'a> _ACRENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACFGTW<'a> {
w: &'a mut W,
}
impl<'a> _ACFGTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ACFE`"]
pub enum ACFEW {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ACFEW::_0 => false,
ACFEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ACFEW<'a> {
w: &'a mut W,
}
impl<'a> _ACFEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ACFEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Compare function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ACFEW::_0)
}
#[doc = "Compare function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ACFEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADTRG`"]
pub enum ADTRGW {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADTRGW::_0 => false,
ADTRGW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADTRGW<'a> {
w: &'a mut W,
}
impl<'a> _ADTRGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADTRGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Software trigger selected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADTRGW::_0)
}
#[doc = "Hardware trigger selected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADTRGW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&self) -> REFSELR {
REFSELR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&self) -> DMAENR {
DMAENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&self) -> ACRENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACRENR { bits }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&self) -> ACFGTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACFGTR { bits }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&self) -> ACFER {
ACFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&self) -> ADTRGR {
ADTRGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Active"]
#[inline]
pub fn adact(&self) -> ADACTR {
ADACTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 13:14 - Trigger Process Number"]
#[inline]
pub fn trgprnum(&self) -> TRGPRNUMR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TRGPRNUMR { bits }
}
#[doc = "Bits 16:19 - Trigger Status"]
#[inline]
pub fn trgstlat(&self) -> TRGSTLATR {
TRGSTLATR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
#[inline]
pub fn trgsterr(&self) -> TRGSTERRR {
TRGSTERRR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&mut self) -> _REFSELW {
_REFSELW { w: self }
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&mut self) -> _DMAENW {
_DMAENW { w: self }
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&mut self) -> _ACRENW {
_ACRENW { w: self }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&mut self) -> _ACFGTW {
_ACFGTW { w: self }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&mut self) -> _ACFEW {
_ACFEW { w: self }
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&mut self) -> _ADTRGW {
_ADTRGW { w: self }
}
}

495
src/adc0/sc3/mod.rs Normal file
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@ -0,0 +1,495 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `AVGS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGSR {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
AVGSR::_00 => 0,
AVGSR::_01 => 1,
AVGSR::_10 => 2,
AVGSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> AVGSR {
match value {
0 => AVGSR::_00,
1 => AVGSR::_01,
2 => AVGSR::_10,
3 => AVGSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == AVGSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == AVGSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == AVGSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == AVGSR::_11
}
}
#[doc = "Possible values of the field `AVGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGER {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AVGER::_0 => false,
AVGER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AVGER {
match value {
false => AVGER::_0,
true => AVGER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AVGER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AVGER::_1
}
}
#[doc = "Possible values of the field `ADCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCOR {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADCOR::_0 => false,
ADCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADCOR {
match value {
false => ADCOR::_0,
true => ADCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADCOR::_1
}
}
#[doc = r" Value of the field"]
pub struct CALR {
bits: bool,
}
impl CALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `AVGS`"]
pub enum AVGSW {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
AVGSW::_00 => 0,
AVGSW::_01 => 1,
AVGSW::_10 => 2,
AVGSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGSW<'a> {
w: &'a mut W,
}
impl<'a> _AVGSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "4 samples averaged."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(AVGSW::_00)
}
#[doc = "8 samples averaged."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(AVGSW::_01)
}
#[doc = "16 samples averaged."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(AVGSW::_10)
}
#[doc = "32 samples averaged."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(AVGSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AVGE`"]
pub enum AVGEW {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AVGEW::_0 => false,
AVGEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGEW<'a> {
w: &'a mut W,
}
impl<'a> _AVGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Hardware average function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AVGEW::_0)
}
#[doc = "Hardware average function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AVGEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADCO`"]
pub enum ADCOW {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADCOW::_0 => false,
ADCOW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCOW<'a> {
w: &'a mut W,
}
impl<'a> _ADCOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADCOW::_0)
}
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADCOW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CALW<'a> {
w: &'a mut W,
}
impl<'a> _CALW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&self) -> AVGSR {
AVGSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&self) -> AVGER {
AVGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&self) -> ADCOR {
ADCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&self) -> CALR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&mut self) -> _AVGSW {
_AVGSW { w: self }
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&mut self) -> _AVGEW {
_AVGEW { w: self }
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&mut self) -> _ADCOW {
_ADCOW { w: self }
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&mut self) -> _CALW {
_CALW { w: self }
}
}

103
src/adc0/ug/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::UG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct UGR {
bits: u16,
}
impl UGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _UGW<'a> {
w: &'a mut W,
}
impl<'a> _UGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&self) -> UGR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
UGR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&mut self) -> _UGW {
_UGW { w: self }
}
}

103
src/adc0/usr_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USR_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct USR_OFSR {
bits: u8,
}
impl USR_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _USR_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _USR_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&self) -> USR_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
USR_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&mut self) -> _USR_OFSW {
_USR_OFSW { w: self }
}
}

103
src/adc0/xofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::XOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct XOFSR {
bits: u8,
}
impl XOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _XOFSW<'a> {
w: &'a mut W,
}
impl<'a> _XOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&self) -> XOFSR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
XOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 48 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&mut self) -> _XOFSW {
_XOFSW { w: self }
}
}

103
src/adc0/yofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::YOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct YOFSR {
bits: u8,
}
impl YOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YOFSW<'a> {
w: &'a mut W,
}
impl<'a> _YOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&self) -> YOFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
YOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 55 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&mut self) -> _YOFSW {
_YOFSW { w: self }
}
}

103
src/adc1/base_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::BASE_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BA_OFSR {
bits: u8,
}
impl BA_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BA_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _BA_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&self) -> BA_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BA_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 64 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&mut self) -> _BA_OFSW {
_BA_OFSW { w: self }
}
}

482
src/adc1/cfg1/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADICLK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADICLKR {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADICLKR::_00 => 0,
ADICLKR::_01 => 1,
ADICLKR::_10 => 2,
ADICLKR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADICLKR {
match value {
0 => ADICLKR::_00,
1 => ADICLKR::_01,
2 => ADICLKR::_10,
3 => ADICLKR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADICLKR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADICLKR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADICLKR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADICLKR::_11
}
}
#[doc = "Possible values of the field `MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODER {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
MODER::_00 => 0,
MODER::_01 => 1,
MODER::_10 => 2,
MODER::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> MODER {
match value {
0 => MODER::_00,
1 => MODER::_01,
2 => MODER::_10,
i => MODER::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == MODER::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == MODER::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == MODER::_10
}
}
#[doc = "Possible values of the field `ADIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADIVR {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADIVR::_00 => 0,
ADIVR::_01 => 1,
ADIVR::_10 => 2,
ADIVR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADIVR {
match value {
0 => ADIVR::_00,
1 => ADIVR::_01,
2 => ADIVR::_10,
3 => ADIVR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADIVR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADIVR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADIVR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADIVR::_11
}
}
#[doc = "Values that can be written to the field `ADICLK`"]
pub enum ADICLKW {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADICLKW::_00 => 0,
ADICLKW::_01 => 1,
ADICLKW::_10 => 2,
ADICLKW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADICLKW<'a> {
w: &'a mut W,
}
impl<'a> _ADICLKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADICLKW::_00)
}
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADICLKW::_01)
}
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADICLKW::_10)
}
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADICLKW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
}
impl MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
MODEW::_00 => 0,
MODEW::_01 => 1,
MODEW::_10 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _MODEW<'a> {
w: &'a mut W,
}
impl<'a> _MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODEW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8-bit conversion."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(MODEW::_00)
}
#[doc = "12-bit conversion."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(MODEW::_01)
}
#[doc = "10-bit conversion."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(MODEW::_10)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADIV`"]
pub enum ADIVW {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADIVW::_00 => 0,
ADIVW::_01 => 1,
ADIVW::_10 => 2,
ADIVW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADIVW<'a> {
w: &'a mut W,
}
impl<'a> _ADIVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADIVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADIVW::_00)
}
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADIVW::_01)
}
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADIVW::_10)
}
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADIVW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLRLTRGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRLTRGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&self) -> ADICLKR {
ADICLKR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&self) -> ADIVR {
ADIVR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&mut self) -> _ADICLKW {
_ADICLKW { w: self }
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&mut self) -> _ADIVW {
_ADIVW { w: self }
}
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
#[inline]
pub fn clrltrg(&mut self) -> _CLRLTRGW {
_CLRLTRGW { w: self }
}
}

103
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SMPLTSR {
bits: u8,
}
impl SMPLTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SMPLTSW<'a> {
w: &'a mut W,
}
impl<'a> _SMPLTSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&self) -> SMPLTSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SMPLTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 12 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&mut self) -> _SMPLTSW {
_SMPLTSW { w: self }
}
}

103
src/adc1/clp0/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0R {
bits: u8,
}
impl CLP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0W<'a> {
w: &'a mut W,
}
impl<'a> _CLP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&self) -> CLP0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&mut self) -> _CLP0W {
_CLP0W { w: self }
}
}

103
src/adc1/clp0_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0_OFSR {
bits: u8,
}
impl CLP0_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP0_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&self) -> CLP0_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
_CLP0_OFSW { w: self }
}
}

103
src/adc1/clp1/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1R {
bits: u16,
}
impl CLP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1W<'a> {
w: &'a mut W,
}
impl<'a> _CLP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&self) -> CLP1R {
let bits = {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 92 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&mut self) -> _CLP1W {
_CLP1W { w: self }
}
}

103
src/adc1/clp1_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1_OFSR {
bits: u8,
}
impl CLP1_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP1_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&self) -> CLP1_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP1_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
_CLP1_OFSW { w: self }
}
}

103
src/adc1/clp2/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2R {
bits: u16,
}
impl CLP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2W<'a> {
w: &'a mut W,
}
impl<'a> _CLP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&self) -> CLP2R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 184 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&mut self) -> _CLP2W {
_CLP2W { w: self }
}
}

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src/adc1/clp2_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2_OFSR {
bits: u8,
}
impl CLP2_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP2_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&self) -> CLP2_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP2_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
_CLP2_OFSW { w: self }
}
}

103
src/adc1/clp3/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3R {
bits: u16,
}
impl CLP3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3W<'a> {
w: &'a mut W,
}
impl<'a> _CLP3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&self) -> CLP3R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 384 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&mut self) -> _CLP3W {
_CLP3W { w: self }
}
}

103
src/adc1/clp3_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3_OFSR {
bits: u8,
}
impl CLP3_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP3_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&self) -> CLP3_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP3_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
_CLP3_OFSW { w: self }
}
}

103
src/adc1/clp9/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9R {
bits: u8,
}
impl CLP9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9W<'a> {
w: &'a mut W,
}
impl<'a> _CLP9W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&self) -> CLP9R {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP9R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&mut self) -> _CLP9W {
_CLP9W { w: self }
}
}

103
src/adc1/clp9_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9_OFSR {
bits: u16,
}
impl CLP9_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP9_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&self) -> CLP9_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP9_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 576 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
_CLP9_OFSW { w: self }
}
}

103
src/adc1/clps/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPSR {
bits: u8,
}
impl CLPSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&self) -> CLPSR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&mut self) -> _CLPSW {
_CLPSW { w: self }
}
}

103
src/adc1/clps_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPS_OFSR {
bits: u8,
}
impl CLPS_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPS_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPS_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&self) -> CLPS_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPS_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
_CLPS_OFSW { w: self }
}
}

103
src/adc1/clpx/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPXR {
bits: u8,
}
impl CLPXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPXW<'a> {
w: &'a mut W,
}
impl<'a> _CLPXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&self) -> CLPXR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&mut self) -> _CLPXW {
_CLPXW { w: self }
}
}

103
src/adc1/clpx_ofs/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPX_OFSR {
bits: u16,
}
impl CLPX_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPX_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPX_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&self) -> CLPX_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLPX_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1088 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
_CLPX_OFSW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CVR {
bits: u16,
}
impl CVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CVW<'a> {
w: &'a mut W,
}
impl<'a> _CVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&self) -> CVR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&mut self) -> _CVW {
_CVW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::G {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GR {
bits: u16,
}
impl GR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GW<'a> {
w: &'a mut W,
}
impl<'a> _GW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&self) -> GR {
let bits = {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
GR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 752 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&mut self) -> _GW {
_GW { w: self }
}
}

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use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - ADC Status and Control Register 1"]
pub sc1a: SC1,
#[doc = "0x04 - ADC Status and Control Register 1"]
pub sc1b: SC1,
#[doc = "0x08 - ADC Status and Control Register 1"]
pub sc1c: SC1,
#[doc = "0x0c - ADC Status and Control Register 1"]
pub sc1d: SC1,
#[doc = "0x10 - ADC Status and Control Register 1"]
pub sc1e: SC1,
#[doc = "0x14 - ADC Status and Control Register 1"]
pub sc1f: SC1,
#[doc = "0x18 - ADC Status and Control Register 1"]
pub sc1g: SC1,
#[doc = "0x1c - ADC Status and Control Register 1"]
pub sc1h: SC1,
#[doc = "0x20 - ADC Status and Control Register 1"]
pub sc1i: SC1,
#[doc = "0x24 - ADC Status and Control Register 1"]
pub sc1j: SC1,
#[doc = "0x28 - ADC Status and Control Register 1"]
pub sc1k: SC1,
#[doc = "0x2c - ADC Status and Control Register 1"]
pub sc1l: SC1,
#[doc = "0x30 - ADC Status and Control Register 1"]
pub sc1m: SC1,
#[doc = "0x34 - ADC Status and Control Register 1"]
pub sc1n: SC1,
#[doc = "0x38 - ADC Status and Control Register 1"]
pub sc1o: SC1,
#[doc = "0x3c - ADC Status and Control Register 1"]
pub sc1p: SC1,
#[doc = "0x40 - ADC Configuration Register 1"]
pub cfg1: CFG1,
#[doc = "0x44 - ADC Configuration Register 2"]
pub cfg2: CFG2,
#[doc = "0x48 - ADC Data Result Registers"]
pub ra: R,
#[doc = "0x4c - ADC Data Result Registers"]
pub rb: R,
#[doc = "0x50 - ADC Data Result Registers"]
pub rc: R,
#[doc = "0x54 - ADC Data Result Registers"]
pub rd: R,
#[doc = "0x58 - ADC Data Result Registers"]
pub re: R,
#[doc = "0x5c - ADC Data Result Registers"]
pub rf: R,
#[doc = "0x60 - ADC Data Result Registers"]
pub rg: R,
#[doc = "0x64 - ADC Data Result Registers"]
pub rh: R,
#[doc = "0x68 - ADC Data Result Registers"]
pub ri: R,
#[doc = "0x6c - ADC Data Result Registers"]
pub rj: R,
#[doc = "0x70 - ADC Data Result Registers"]
pub rk: R,
#[doc = "0x74 - ADC Data Result Registers"]
pub rl: R,
#[doc = "0x78 - ADC Data Result Registers"]
pub rm: R,
#[doc = "0x7c - ADC Data Result Registers"]
pub rn: R,
#[doc = "0x80 - ADC Data Result Registers"]
pub ro: R,
#[doc = "0x84 - ADC Data Result Registers"]
pub rp: R,
#[doc = "0x88 - Compare Value Registers"]
pub cv1: CV,
#[doc = "0x8c - Compare Value Registers"]
pub cv2: CV,
#[doc = "0x90 - Status and Control Register 2"]
pub sc2: SC2,
#[doc = "0x94 - Status and Control Register 3"]
pub sc3: SC3,
#[doc = "0x98 - BASE Offset Register"]
pub base_ofs: BASE_OFS,
#[doc = "0x9c - ADC Offset Correction Register"]
pub ofs: OFS,
#[doc = "0xa0 - USER Offset Correction Register"]
pub usr_ofs: USR_OFS,
#[doc = "0xa4 - ADC X Offset Correction Register"]
pub xofs: XOFS,
#[doc = "0xa8 - ADC Y Offset Correction Register"]
pub yofs: YOFS,
#[doc = "0xac - ADC Gain Register"]
pub g: G,
#[doc = "0xb0 - ADC User Gain Register"]
pub ug: UG,
#[doc = "0xb4 - ADC General Calibration Value Register S"]
pub clps: CLPS,
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
pub clp3: CLP3,
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
pub clp2: CLP2,
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
pub clp1: CLP1,
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
pub clp0: CLP0,
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
pub clpx: CLPX,
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
pub clp9: CLP9,
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
pub clps_ofs: CLPS_OFS,
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
pub clp3_ofs: CLP3_OFS,
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
pub clp2_ofs: CLP2_OFS,
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
pub clp1_ofs: CLP1_OFS,
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
pub clp0_ofs: CLP0_OFS,
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
pub clpx_ofs: CLPX_OFS,
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
pub clp9_ofs: CLP9_OFS,
}
#[doc = "ADC Status and Control Register 1"]
pub struct SC1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Status and Control Register 1"]
pub mod sc1;
#[doc = "ADC Configuration Register 1"]
pub struct CFG1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 1"]
pub mod cfg1;
#[doc = "ADC Configuration Register 2"]
pub struct CFG2 {
register: VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 2"]
pub mod cfg2;
#[doc = "ADC Data Result Registers"]
pub struct R {
register: VolatileCell<u32>,
}
#[doc = "ADC Data Result Registers"]
pub mod r;
#[doc = "Compare Value Registers"]
pub struct CV {
register: VolatileCell<u32>,
}
#[doc = "Compare Value Registers"]
pub mod cv;
#[doc = "Status and Control Register 2"]
pub struct SC2 {
register: VolatileCell<u32>,
}
#[doc = "Status and Control Register 2"]
pub mod sc2;
#[doc = "Status and Control Register 3"]
pub struct SC3 {
register: VolatileCell<u32>,
}
#[doc = "Status and Control Register 3"]
pub mod sc3;
#[doc = "BASE Offset Register"]
pub struct BASE_OFS {
register: VolatileCell<u32>,
}
#[doc = "BASE Offset Register"]
pub mod base_ofs;
#[doc = "ADC Offset Correction Register"]
pub struct OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Offset Correction Register"]
pub mod ofs;
#[doc = "USER Offset Correction Register"]
pub struct USR_OFS {
register: VolatileCell<u32>,
}
#[doc = "USER Offset Correction Register"]
pub mod usr_ofs;
#[doc = "ADC X Offset Correction Register"]
pub struct XOFS {
register: VolatileCell<u32>,
}
#[doc = "ADC X Offset Correction Register"]
pub mod xofs;
#[doc = "ADC Y Offset Correction Register"]
pub struct YOFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Y Offset Correction Register"]
pub mod yofs;
#[doc = "ADC Gain Register"]
pub struct G {
register: VolatileCell<u32>,
}
#[doc = "ADC Gain Register"]
pub mod g;
#[doc = "ADC User Gain Register"]
pub struct UG {
register: VolatileCell<u32>,
}
#[doc = "ADC User Gain Register"]
pub mod ug;
#[doc = "ADC General Calibration Value Register S"]
pub struct CLPS {
register: VolatileCell<u32>,
}
#[doc = "ADC General Calibration Value Register S"]
pub mod clps;
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub struct CLP3 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub mod clp3;
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub struct CLP2 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub mod clp2;
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub struct CLP1 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub mod clp1;
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub struct CLP0 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub mod clp0;
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub struct CLPX {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub mod clpx;
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub struct CLP9 {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub mod clp9;
#[doc = "ADC General Calibration Offset Value Register S"]
pub struct CLPS_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC General Calibration Offset Value Register S"]
pub mod clps_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub struct CLP3_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub mod clp3_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub struct CLP2_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub mod clp2_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub struct CLP1_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub mod clp1_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub struct CLP0_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub mod clp0_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub struct CLPX_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub mod clpx_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub struct CLP9_OFS {
register: VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub mod clp9_ofs;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct OFSR {
bits: u16,
}
impl OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _OFSW<'a> {
w: &'a mut W,
}
impl<'a> _OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&self) -> OFSR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&mut self) -> _OFSW {
_OFSW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::R {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct DR {
bits: u16,
}
impl DR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Data result"]
#[inline]
pub fn d(&self) -> DR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DR { bits }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCHR {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11110,
#[doc = "Module is disabled"]
_11111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADCHR::_00000 => 0,
ADCHR::_00001 => 1,
ADCHR::_00010 => 2,
ADCHR::_00011 => 3,
ADCHR::_00100 => 4,
ADCHR::_00101 => 5,
ADCHR::_00110 => 6,
ADCHR::_00111 => 7,
ADCHR::_01000 => 8,
ADCHR::_01001 => 9,
ADCHR::_01010 => 10,
ADCHR::_01011 => 11,
ADCHR::_01100 => 12,
ADCHR::_01101 => 13,
ADCHR::_01110 => 14,
ADCHR::_01111 => 15,
ADCHR::_10010 => 18,
ADCHR::_10011 => 19,
ADCHR::_10101 => 21,
ADCHR::_10110 => 22,
ADCHR::_10111 => 23,
ADCHR::_11010 => 26,
ADCHR::_11011 => 27,
ADCHR::_11100 => 28,
ADCHR::_11101 => 29,
ADCHR::_11110 => 30,
ADCHR::_11111 => 31,
ADCHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADCHR {
match value {
0 => ADCHR::_00000,
1 => ADCHR::_00001,
2 => ADCHR::_00010,
3 => ADCHR::_00011,
4 => ADCHR::_00100,
5 => ADCHR::_00101,
6 => ADCHR::_00110,
7 => ADCHR::_00111,
8 => ADCHR::_01000,
9 => ADCHR::_01001,
10 => ADCHR::_01010,
11 => ADCHR::_01011,
12 => ADCHR::_01100,
13 => ADCHR::_01101,
14 => ADCHR::_01110,
15 => ADCHR::_01111,
18 => ADCHR::_10010,
19 => ADCHR::_10011,
21 => ADCHR::_10101,
22 => ADCHR::_10110,
23 => ADCHR::_10111,
26 => ADCHR::_11010,
27 => ADCHR::_11011,
28 => ADCHR::_11100,
29 => ADCHR::_11101,
30 => ADCHR::_11110,
31 => ADCHR::_11111,
i => ADCHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00000`"]
#[inline]
pub fn is_00000(&self) -> bool {
*self == ADCHR::_00000
}
#[doc = "Checks if the value of the field is `_00001`"]
#[inline]
pub fn is_00001(&self) -> bool {
*self == ADCHR::_00001
}
#[doc = "Checks if the value of the field is `_00010`"]
#[inline]
pub fn is_00010(&self) -> bool {
*self == ADCHR::_00010
}
#[doc = "Checks if the value of the field is `_00011`"]
#[inline]
pub fn is_00011(&self) -> bool {
*self == ADCHR::_00011
}
#[doc = "Checks if the value of the field is `_00100`"]
#[inline]
pub fn is_00100(&self) -> bool {
*self == ADCHR::_00100
}
#[doc = "Checks if the value of the field is `_00101`"]
#[inline]
pub fn is_00101(&self) -> bool {
*self == ADCHR::_00101
}
#[doc = "Checks if the value of the field is `_00110`"]
#[inline]
pub fn is_00110(&self) -> bool {
*self == ADCHR::_00110
}
#[doc = "Checks if the value of the field is `_00111`"]
#[inline]
pub fn is_00111(&self) -> bool {
*self == ADCHR::_00111
}
#[doc = "Checks if the value of the field is `_01000`"]
#[inline]
pub fn is_01000(&self) -> bool {
*self == ADCHR::_01000
}
#[doc = "Checks if the value of the field is `_01001`"]
#[inline]
pub fn is_01001(&self) -> bool {
*self == ADCHR::_01001
}
#[doc = "Checks if the value of the field is `_01010`"]
#[inline]
pub fn is_01010(&self) -> bool {
*self == ADCHR::_01010
}
#[doc = "Checks if the value of the field is `_01011`"]
#[inline]
pub fn is_01011(&self) -> bool {
*self == ADCHR::_01011
}
#[doc = "Checks if the value of the field is `_01100`"]
#[inline]
pub fn is_01100(&self) -> bool {
*self == ADCHR::_01100
}
#[doc = "Checks if the value of the field is `_01101`"]
#[inline]
pub fn is_01101(&self) -> bool {
*self == ADCHR::_01101
}
#[doc = "Checks if the value of the field is `_01110`"]
#[inline]
pub fn is_01110(&self) -> bool {
*self == ADCHR::_01110
}
#[doc = "Checks if the value of the field is `_01111`"]
#[inline]
pub fn is_01111(&self) -> bool {
*self == ADCHR::_01111
}
#[doc = "Checks if the value of the field is `_10010`"]
#[inline]
pub fn is_10010(&self) -> bool {
*self == ADCHR::_10010
}
#[doc = "Checks if the value of the field is `_10011`"]
#[inline]
pub fn is_10011(&self) -> bool {
*self == ADCHR::_10011
}
#[doc = "Checks if the value of the field is `_10101`"]
#[inline]
pub fn is_10101(&self) -> bool {
*self == ADCHR::_10101
}
#[doc = "Checks if the value of the field is `_10110`"]
#[inline]
pub fn is_10110(&self) -> bool {
*self == ADCHR::_10110
}
#[doc = "Checks if the value of the field is `_10111`"]
#[inline]
pub fn is_10111(&self) -> bool {
*self == ADCHR::_10111
}
#[doc = "Checks if the value of the field is `_11010`"]
#[inline]
pub fn is_11010(&self) -> bool {
*self == ADCHR::_11010
}
#[doc = "Checks if the value of the field is `_11011`"]
#[inline]
pub fn is_11011(&self) -> bool {
*self == ADCHR::_11011
}
#[doc = "Checks if the value of the field is `_11100`"]
#[inline]
pub fn is_11100(&self) -> bool {
*self == ADCHR::_11100
}
#[doc = "Checks if the value of the field is `_11101`"]
#[inline]
pub fn is_11101(&self) -> bool {
*self == ADCHR::_11101
}
#[doc = "Checks if the value of the field is `_11110`"]
#[inline]
pub fn is_11110(&self) -> bool {
*self == ADCHR::_11110
}
#[doc = "Checks if the value of the field is `_11111`"]
#[inline]
pub fn is_11111(&self) -> bool {
*self == ADCHR::_11111
}
}
#[doc = "Possible values of the field `AIEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AIENR {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AIENR::_0 => false,
AIENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AIENR {
match value {
false => AIENR::_0,
true => AIENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AIENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AIENR::_1
}
}
#[doc = "Possible values of the field `COCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COCOR {
#[doc = "Conversion is not completed."]
_0,
#[doc = "Conversion is completed."]
_1,
}
impl COCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
COCOR::_0 => false,
COCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> COCOR {
match value {
false => COCOR::_0,
true => COCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == COCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == COCOR::_1
}
}
#[doc = "Values that can be written to the field `ADCH`"]
pub enum ADCHW {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
_11110,
#[doc = "Module is disabled"]
_11111,
}
impl ADCHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADCHW::_00000 => 0,
ADCHW::_00001 => 1,
ADCHW::_00010 => 2,
ADCHW::_00011 => 3,
ADCHW::_00100 => 4,
ADCHW::_00101 => 5,
ADCHW::_00110 => 6,
ADCHW::_00111 => 7,
ADCHW::_01000 => 8,
ADCHW::_01001 => 9,
ADCHW::_01010 => 10,
ADCHW::_01011 => 11,
ADCHW::_01100 => 12,
ADCHW::_01101 => 13,
ADCHW::_01110 => 14,
ADCHW::_01111 => 15,
ADCHW::_10010 => 18,
ADCHW::_10011 => 19,
ADCHW::_10101 => 21,
ADCHW::_10110 => 22,
ADCHW::_10111 => 23,
ADCHW::_11010 => 26,
ADCHW::_11011 => 27,
ADCHW::_11100 => 28,
ADCHW::_11101 => 29,
ADCHW::_11110 => 30,
ADCHW::_11111 => 31,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCHW<'a> {
w: &'a mut W,
}
impl<'a> _ADCHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Exernal channel 0 is selected as input."]
#[inline]
pub fn _00000(self) -> &'a mut W {
self.variant(ADCHW::_00000)
}
#[doc = "Exernal channel 1 is selected as input."]
#[inline]
pub fn _00001(self) -> &'a mut W {
self.variant(ADCHW::_00001)
}
#[doc = "Exernal channel 2 is selected as input."]
#[inline]
pub fn _00010(self) -> &'a mut W {
self.variant(ADCHW::_00010)
}
#[doc = "Exernal channel 3 is selected as input."]
#[inline]
pub fn _00011(self) -> &'a mut W {
self.variant(ADCHW::_00011)
}
#[doc = "Exernal channel 4 is selected as input."]
#[inline]
pub fn _00100(self) -> &'a mut W {
self.variant(ADCHW::_00100)
}
#[doc = "Exernal channel 5 is selected as input."]
#[inline]
pub fn _00101(self) -> &'a mut W {
self.variant(ADCHW::_00101)
}
#[doc = "Exernal channel 6 is selected as input."]
#[inline]
pub fn _00110(self) -> &'a mut W {
self.variant(ADCHW::_00110)
}
#[doc = "Exernal channel 7 is selected as input."]
#[inline]
pub fn _00111(self) -> &'a mut W {
self.variant(ADCHW::_00111)
}
#[doc = "Exernal channel 8 is selected as input."]
#[inline]
pub fn _01000(self) -> &'a mut W {
self.variant(ADCHW::_01000)
}
#[doc = "Exernal channel 9 is selected as input."]
#[inline]
pub fn _01001(self) -> &'a mut W {
self.variant(ADCHW::_01001)
}
#[doc = "Exernal channel 10 is selected as input."]
#[inline]
pub fn _01010(self) -> &'a mut W {
self.variant(ADCHW::_01010)
}
#[doc = "Exernal channel 11 is selected as input."]
#[inline]
pub fn _01011(self) -> &'a mut W {
self.variant(ADCHW::_01011)
}
#[doc = "Exernal channel 12 is selected as input."]
#[inline]
pub fn _01100(self) -> &'a mut W {
self.variant(ADCHW::_01100)
}
#[doc = "Exernal channel 13 is selected as input."]
#[inline]
pub fn _01101(self) -> &'a mut W {
self.variant(ADCHW::_01101)
}
#[doc = "Exernal channel 14 is selected as input."]
#[inline]
pub fn _01110(self) -> &'a mut W {
self.variant(ADCHW::_01110)
}
#[doc = "Exernal channel 15 is selected as input."]
#[inline]
pub fn _01111(self) -> &'a mut W {
self.variant(ADCHW::_01111)
}
#[doc = "Exernal channel 18 is selected as input."]
#[inline]
pub fn _10010(self) -> &'a mut W {
self.variant(ADCHW::_10010)
}
#[doc = "Exernal channel 19 is selected as input."]
#[inline]
pub fn _10011(self) -> &'a mut W {
self.variant(ADCHW::_10011)
}
#[doc = "Internal channel 0 is selected as input."]
#[inline]
pub fn _10101(self) -> &'a mut W {
self.variant(ADCHW::_10101)
}
#[doc = "Internal channel 1 is selected as input."]
#[inline]
pub fn _10110(self) -> &'a mut W {
self.variant(ADCHW::_10110)
}
#[doc = "Internal channel 2 is selected as input."]
#[inline]
pub fn _10111(self) -> &'a mut W {
self.variant(ADCHW::_10111)
}
#[doc = "Temp Sensor"]
#[inline]
pub fn _11010(self) -> &'a mut W {
self.variant(ADCHW::_11010)
}
#[doc = "Band Gap"]
#[inline]
pub fn _11011(self) -> &'a mut W {
self.variant(ADCHW::_11011)
}
#[doc = "Internal channel 3 is selected as input."]
#[inline]
pub fn _11100(self) -> &'a mut W {
self.variant(ADCHW::_11100)
}
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
#[inline]
pub fn _11101(self) -> &'a mut W {
self.variant(ADCHW::_11101)
}
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
#[inline]
pub fn _11110(self) -> &'a mut W {
self.variant(ADCHW::_11110)
}
#[doc = "Module is disabled"]
#[inline]
pub fn _11111(self) -> &'a mut W {
self.variant(ADCHW::_11111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AIEN`"]
pub enum AIENW {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AIENW::_0 => false,
AIENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AIENW<'a> {
w: &'a mut W,
}
impl<'a> _AIENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AIENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Conversion complete interrupt is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AIENW::_0)
}
#[doc = "Conversion complete interrupt is enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AIENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&self) -> ADCHR {
ADCHR::_from({
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&self) -> AIENR {
AIENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Complete Flag"]
#[inline]
pub fn coco(&self) -> COCOR {
COCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 31 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&mut self) -> _ADCHW {
_ADCHW { w: self }
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&mut self) -> _AIENW {
_AIENW { w: self }
}
}

817
src/adc1/sc2/mod.rs Normal file
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@ -0,0 +1,817 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `REFSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REFSELR {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl REFSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
REFSELR::_00 => 0,
REFSELR::_01 => 1,
REFSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> REFSELR {
match value {
0 => REFSELR::_00,
1 => REFSELR::_01,
i => REFSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == REFSELR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == REFSELR::_01
}
}
#[doc = "Possible values of the field `DMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAENR {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
_1,
}
impl DMAENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMAENR::_0 => false,
DMAENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMAENR {
match value {
false => DMAENR::_0,
true => DMAENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == DMAENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == DMAENR::_1
}
}
#[doc = r" Value of the field"]
pub struct ACRENR {
bits: bool,
}
impl ACRENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ACFGTR {
bits: bool,
}
impl ACFGTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `ACFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACFER {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ACFER::_0 => false,
ACFER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ACFER {
match value {
false => ACFER::_0,
true => ACFER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ACFER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ACFER::_1
}
}
#[doc = "Possible values of the field `ADTRG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADTRGR {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADTRGR::_0 => false,
ADTRGR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADTRGR {
match value {
false => ADTRGR::_0,
true => ADTRGR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADTRGR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADTRGR::_1
}
}
#[doc = "Possible values of the field `ADACT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADACTR {
#[doc = "Conversion not in progress."]
_0,
#[doc = "Conversion in progress."]
_1,
}
impl ADACTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADACTR::_0 => false,
ADACTR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADACTR {
match value {
false => ADACTR::_0,
true => ADACTR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADACTR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADACTR::_1
}
}
#[doc = r" Value of the field"]
pub struct TRGPRNUMR {
bits: u8,
}
impl TRGPRNUMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `TRGSTLAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTLATR {
#[doc = "No trigger request has been latched"]
_0,
#[doc = "A trigger request has been latched"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTLATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTLATR::_0 => 0,
TRGSTLATR::_1 => 1,
TRGSTLATR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTLATR {
match value {
0 => TRGSTLATR::_0,
1 => TRGSTLATR::_1,
i => TRGSTLATR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTLATR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTLATR::_1
}
}
#[doc = "Possible values of the field `TRGSTERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTERRR {
#[doc = "No error has occurred"]
_0,
#[doc = "An error has occurred"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTERRR::_0 => 0,
TRGSTERRR::_1 => 1,
TRGSTERRR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTERRR {
match value {
0 => TRGSTERRR::_0,
1 => TRGSTERRR::_1,
i => TRGSTERRR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTERRR::_1
}
}
#[doc = "Values that can be written to the field `REFSEL`"]
pub enum REFSELW {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
}
impl REFSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
REFSELW::_00 => 0,
REFSELW::_01 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _REFSELW<'a> {
w: &'a mut W,
}
impl<'a> _REFSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: REFSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(REFSELW::_00)
}
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(REFSELW::_01)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMAEN`"]
pub enum DMAENW {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
_1,
}
impl DMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMAENW::_0 => false,
DMAENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMAENW<'a> {
w: &'a mut W,
}
impl<'a> _DMAENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(DMAENW::_0)
}
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(DMAENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACRENW<'a> {
w: &'a mut W,
}
impl<'a> _ACRENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACFGTW<'a> {
w: &'a mut W,
}
impl<'a> _ACFGTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ACFE`"]
pub enum ACFEW {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ACFEW::_0 => false,
ACFEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ACFEW<'a> {
w: &'a mut W,
}
impl<'a> _ACFEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ACFEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Compare function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ACFEW::_0)
}
#[doc = "Compare function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ACFEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADTRG`"]
pub enum ADTRGW {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADTRGW::_0 => false,
ADTRGW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADTRGW<'a> {
w: &'a mut W,
}
impl<'a> _ADTRGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADTRGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Software trigger selected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADTRGW::_0)
}
#[doc = "Hardware trigger selected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADTRGW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&self) -> REFSELR {
REFSELR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&self) -> DMAENR {
DMAENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&self) -> ACRENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACRENR { bits }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&self) -> ACFGTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACFGTR { bits }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&self) -> ACFER {
ACFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&self) -> ADTRGR {
ADTRGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Active"]
#[inline]
pub fn adact(&self) -> ADACTR {
ADACTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 13:14 - Trigger Process Number"]
#[inline]
pub fn trgprnum(&self) -> TRGPRNUMR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TRGPRNUMR { bits }
}
#[doc = "Bits 16:19 - Trigger Status"]
#[inline]
pub fn trgstlat(&self) -> TRGSTLATR {
TRGSTLATR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
#[inline]
pub fn trgsterr(&self) -> TRGSTERRR {
TRGSTERRR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&mut self) -> _REFSELW {
_REFSELW { w: self }
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&mut self) -> _DMAENW {
_DMAENW { w: self }
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&mut self) -> _ACRENW {
_ACRENW { w: self }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&mut self) -> _ACFGTW {
_ACFGTW { w: self }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&mut self) -> _ACFEW {
_ACFEW { w: self }
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&mut self) -> _ADTRGW {
_ADTRGW { w: self }
}
}

495
src/adc1/sc3/mod.rs Normal file
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@ -0,0 +1,495 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `AVGS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGSR {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
AVGSR::_00 => 0,
AVGSR::_01 => 1,
AVGSR::_10 => 2,
AVGSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> AVGSR {
match value {
0 => AVGSR::_00,
1 => AVGSR::_01,
2 => AVGSR::_10,
3 => AVGSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == AVGSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == AVGSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == AVGSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == AVGSR::_11
}
}
#[doc = "Possible values of the field `AVGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGER {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AVGER::_0 => false,
AVGER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AVGER {
match value {
false => AVGER::_0,
true => AVGER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AVGER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AVGER::_1
}
}
#[doc = "Possible values of the field `ADCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCOR {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADCOR::_0 => false,
ADCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADCOR {
match value {
false => ADCOR::_0,
true => ADCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADCOR::_1
}
}
#[doc = r" Value of the field"]
pub struct CALR {
bits: bool,
}
impl CALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `AVGS`"]
pub enum AVGSW {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
AVGSW::_00 => 0,
AVGSW::_01 => 1,
AVGSW::_10 => 2,
AVGSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGSW<'a> {
w: &'a mut W,
}
impl<'a> _AVGSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "4 samples averaged."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(AVGSW::_00)
}
#[doc = "8 samples averaged."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(AVGSW::_01)
}
#[doc = "16 samples averaged."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(AVGSW::_10)
}
#[doc = "32 samples averaged."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(AVGSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AVGE`"]
pub enum AVGEW {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AVGEW::_0 => false,
AVGEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGEW<'a> {
w: &'a mut W,
}
impl<'a> _AVGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Hardware average function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AVGEW::_0)
}
#[doc = "Hardware average function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AVGEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADCO`"]
pub enum ADCOW {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADCOW::_0 => false,
ADCOW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCOW<'a> {
w: &'a mut W,
}
impl<'a> _ADCOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADCOW::_0)
}
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADCOW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CALW<'a> {
w: &'a mut W,
}
impl<'a> _CALW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&self) -> AVGSR {
AVGSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&self) -> AVGER {
AVGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&self) -> ADCOR {
ADCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&self) -> CALR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&mut self) -> _AVGSW {
_AVGSW { w: self }
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&mut self) -> _AVGEW {
_AVGEW { w: self }
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&mut self) -> _ADCOW {
_ADCOW { w: self }
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&mut self) -> _CALW {
_CALW { w: self }
}
}

103
src/adc1/ug/mod.rs Normal file
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@ -0,0 +1,103 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::UG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct UGR {
bits: u16,
}
impl UGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _UGW<'a> {
w: &'a mut W,
}
impl<'a> _UGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&self) -> UGR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
UGR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&mut self) -> _UGW {
_UGW { w: self }
}
}

103
src/adc1/usr_ofs/mod.rs Normal file
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@ -0,0 +1,103 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USR_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct USR_OFSR {
bits: u8,
}
impl USR_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _USR_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _USR_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&self) -> USR_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
USR_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&mut self) -> _USR_OFSW {
_USR_OFSW { w: self }
}
}

103
src/adc1/xofs/mod.rs Normal file
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@ -0,0 +1,103 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::XOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct XOFSR {
bits: u8,
}
impl XOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _XOFSW<'a> {
w: &'a mut W,
}
impl<'a> _XOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&self) -> XOFSR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
XOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 48 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&mut self) -> _XOFSW {
_XOFSW { w: self }
}
}

103
src/adc1/yofs/mod.rs Normal file
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@ -0,0 +1,103 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::YOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct YOFSR {
bits: u8,
}
impl YOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YOFSW<'a> {
w: &'a mut W,
}
impl<'a> _YOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&self) -> YOFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
YOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 55 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&mut self) -> _YOFSW {
_YOFSW { w: self }
}
}

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use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Master Privilege Register A"]
pub mpra: MPRA,
_reserved0: [u8; 28usize],
#[doc = "0x20 - Peripheral Access Control Register"]
pub pacra: PACRA,
#[doc = "0x24 - Peripheral Access Control Register"]
pub pacrb: PACRB,
#[doc = "0x28 - Peripheral Access Control Register"]
pub pacrc: PACRC,
#[doc = "0x2c - Peripheral Access Control Register"]
pub pacrd: PACRD,
_reserved1: [u8; 16usize],
#[doc = "0x40 - Off-Platform Peripheral Access Control Register"]
pub opacra: OPACRA,
#[doc = "0x44 - Off-Platform Peripheral Access Control Register"]
pub opacrb: OPACRB,
#[doc = "0x48 - Off-Platform Peripheral Access Control Register"]
pub opacrc: OPACRC,
#[doc = "0x4c - Off-Platform Peripheral Access Control Register"]
pub opacrd: OPACRD,
#[doc = "0x50 - Off-Platform Peripheral Access Control Register"]
pub opacre: OPACRE,
#[doc = "0x54 - Off-Platform Peripheral Access Control Register"]
pub opacrf: OPACRF,
#[doc = "0x58 - Off-Platform Peripheral Access Control Register"]
pub opacrg: OPACRG,
#[doc = "0x5c - Off-Platform Peripheral Access Control Register"]
pub opacrh: OPACRH,
#[doc = "0x60 - Off-Platform Peripheral Access Control Register"]
pub opacri: OPACRI,
#[doc = "0x64 - Off-Platform Peripheral Access Control Register"]
pub opacrj: OPACRJ,
#[doc = "0x68 - Off-Platform Peripheral Access Control Register"]
pub opacrk: OPACRK,
#[doc = "0x6c - Off-Platform Peripheral Access Control Register"]
pub opacrl: OPACRL,
}
#[doc = "Master Privilege Register A"]
pub struct MPRA {
register: VolatileCell<u32>,
}
#[doc = "Master Privilege Register A"]
pub mod mpra;
#[doc = "Peripheral Access Control Register"]
pub struct PACRA {
register: VolatileCell<u32>,
}
#[doc = "Peripheral Access Control Register"]
pub mod pacra;
#[doc = "Peripheral Access Control Register"]
pub struct PACRB {
register: VolatileCell<u32>,
}
#[doc = "Peripheral Access Control Register"]
pub mod pacrb;
#[doc = "Peripheral Access Control Register"]
pub struct PACRC {
register: VolatileCell<u32>,
}
#[doc = "Peripheral Access Control Register"]
pub mod pacrc;
#[doc = "Peripheral Access Control Register"]
pub struct PACRD {
register: VolatileCell<u32>,
}
#[doc = "Peripheral Access Control Register"]
pub mod pacrd;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRA {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacra;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRB {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrb;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRC {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrc;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRD {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrd;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRE {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacre;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRF {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrf;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRG {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrg;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRH {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrh;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRI {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacri;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRJ {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrj;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRK {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrk;
#[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRL {
register: VolatileCell<u32>,
}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrl;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OPACRE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP6R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP6R::_0 => false,
TP6R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP6R {
match value {
false => TP6R::_0,
true => TP6R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP6R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP6R::_1
}
}
#[doc = "Possible values of the field `WP6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP6R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP6R::_0 => false,
WP6R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP6R {
match value {
false => WP6R::_0,
true => WP6R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP6R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP6R::_1
}
}
#[doc = "Possible values of the field `SP6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP6R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP6R::_0 => false,
SP6R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP6R {
match value {
false => SP6R::_0,
true => SP6R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP6R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP6R::_1
}
}
#[doc = "Possible values of the field `TP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP0R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP0R::_0 => false,
TP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP0R {
match value {
false => TP0R::_0,
true => TP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP0R::_1
}
}
#[doc = "Possible values of the field `WP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP0R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP0R::_0 => false,
WP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP0R {
match value {
false => WP0R::_0,
true => WP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP0R::_1
}
}
#[doc = "Possible values of the field `SP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP0R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP0R::_0 => false,
SP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP0R {
match value {
false => SP0R::_0,
true => SP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP0R::_1
}
}
#[doc = "Values that can be written to the field `TP6`"]
pub enum TP6W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP6W::_0 => false,
TP6W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP6W<'a> {
w: &'a mut W,
}
impl<'a> _TP6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP6W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP6W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP6`"]
pub enum WP6W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP6W::_0 => false,
WP6W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP6W<'a> {
w: &'a mut W,
}
impl<'a> _WP6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP6W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP6W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP6`"]
pub enum SP6W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP6W::_0 => false,
SP6W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP6W<'a> {
w: &'a mut W,
}
impl<'a> _SP6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP6W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP6W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TP0`"]
pub enum TP0W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP0W::_0 => false,
TP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP0W<'a> {
w: &'a mut W,
}
impl<'a> _TP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP0W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP0`"]
pub enum WP0W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP0W::_0 => false,
WP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP0W<'a> {
w: &'a mut W,
}
impl<'a> _WP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP0W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP0`"]
pub enum SP0W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP0W::_0 => false,
SP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP0W<'a> {
w: &'a mut W,
}
impl<'a> _SP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP0W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 4 - Trusted Protect"]
#[inline]
pub fn tp6(&self) -> TP6R {
TP6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Write Protect"]
#[inline]
pub fn wp6(&self) -> WP6R {
WP6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Supervisor Protect"]
#[inline]
pub fn sp6(&self) -> SP6R {
SP6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&self) -> TP0R {
TP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&self) -> WP0R {
WP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&self) -> SP0R {
SP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1073741888 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 4 - Trusted Protect"]
#[inline]
pub fn tp6(&mut self) -> _TP6W {
_TP6W { w: self }
}
#[doc = "Bit 5 - Write Protect"]
#[inline]
pub fn wp6(&mut self) -> _WP6W {
_WP6W { w: self }
}
#[doc = "Bit 6 - Supervisor Protect"]
#[inline]
pub fn sp6(&mut self) -> _SP6W {
_SP6W { w: self }
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&mut self) -> _TP0W {
_TP0W { w: self }
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&mut self) -> _WP0W {
_WP0W { w: self }
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&mut self) -> _SP0W {
_SP0W { w: self }
}
}

2204
src/aips/opacrf/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OPACRG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP2R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP2R::_0 => false,
TP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP2R {
match value {
false => TP2R::_0,
true => TP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP2R::_1
}
}
#[doc = "Possible values of the field `WP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP2R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP2R::_0 => false,
WP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP2R {
match value {
false => WP2R::_0,
true => WP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP2R::_1
}
}
#[doc = "Possible values of the field `SP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP2R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP2R::_0 => false,
SP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP2R {
match value {
false => SP2R::_0,
true => SP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP2R::_1
}
}
#[doc = "Values that can be written to the field `TP2`"]
pub enum TP2W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP2W::_0 => false,
TP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP2W<'a> {
w: &'a mut W,
}
impl<'a> _TP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP2W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP2`"]
pub enum WP2W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP2W::_0 => false,
WP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP2W<'a> {
w: &'a mut W,
}
impl<'a> _WP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP2W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP2`"]
pub enum SP2W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP2W::_0 => false,
SP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP2W<'a> {
w: &'a mut W,
}
impl<'a> _SP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP2W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&self) -> TP2R {
TP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&self) -> WP2R {
WP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&self) -> SP2R {
SP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4194304 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&mut self) -> _TP2W {
_TP2W { w: self }
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&mut self) -> _WP2W {
_WP2W { w: self }
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&mut self) -> _SP2W {
_SP2W { w: self }
}
}

419
src/aips/opacrh/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OPACRH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP2R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP2R::_0 => false,
TP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP2R {
match value {
false => TP2R::_0,
true => TP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP2R::_1
}
}
#[doc = "Possible values of the field `WP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP2R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP2R::_0 => false,
WP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP2R {
match value {
false => WP2R::_0,
true => WP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP2R::_1
}
}
#[doc = "Possible values of the field `SP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP2R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP2R::_0 => false,
SP2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP2R {
match value {
false => SP2R::_0,
true => SP2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP2R::_1
}
}
#[doc = "Values that can be written to the field `TP2`"]
pub enum TP2W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP2W::_0 => false,
TP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP2W<'a> {
w: &'a mut W,
}
impl<'a> _TP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP2W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP2`"]
pub enum WP2W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP2W::_0 => false,
WP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP2W<'a> {
w: &'a mut W,
}
impl<'a> _WP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP2W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP2`"]
pub enum SP2W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP2W::_0 => false,
SP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP2W<'a> {
w: &'a mut W,
}
impl<'a> _SP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP2W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&self) -> TP2R {
TP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&self) -> WP2R {
WP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&self) -> SP2R {
SP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4194304 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&mut self) -> _TP2W {
_TP2W { w: self }
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&mut self) -> _WP2W {
_WP2W { w: self }
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&mut self) -> _SP2W {
_SP2W { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OPACRK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP3R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP3R::_0 => false,
TP3R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP3R {
match value {
false => TP3R::_0,
true => TP3R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP3R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP3R::_1
}
}
#[doc = "Possible values of the field `WP3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP3R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP3R::_0 => false,
WP3R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP3R {
match value {
false => WP3R::_0,
true => WP3R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP3R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP3R::_1
}
}
#[doc = "Possible values of the field `SP3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP3R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP3R::_0 => false,
SP3R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP3R {
match value {
false => SP3R::_0,
true => SP3R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP3R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP3R::_1
}
}
#[doc = "Values that can be written to the field `TP3`"]
pub enum TP3W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP3W::_0 => false,
TP3W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP3W<'a> {
w: &'a mut W,
}
impl<'a> _TP3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP3W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP3`"]
pub enum WP3W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP3W::_0 => false,
WP3W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP3W<'a> {
w: &'a mut W,
}
impl<'a> _WP3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP3W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP3`"]
pub enum SP3W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP3W::_0 => false,
SP3W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP3W<'a> {
w: &'a mut W,
}
impl<'a> _SP3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP3W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 16 - Trusted Protect"]
#[inline]
pub fn tp3(&self) -> TP3R {
TP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Write Protect"]
#[inline]
pub fn wp3(&self) -> WP3R {
WP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Supervisor Protect"]
#[inline]
pub fn sp3(&self) -> SP3R {
SP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 262144 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 16 - Trusted Protect"]
#[inline]
pub fn tp3(&mut self) -> _TP3W {
_TP3W { w: self }
}
#[doc = "Bit 17 - Write Protect"]
#[inline]
pub fn wp3(&mut self) -> _WP3W {
_WP3W { w: self }
}
#[doc = "Bit 18 - Supervisor Protect"]
#[inline]
pub fn sp3(&mut self) -> _SP3W {
_SP3W { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PACRA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP1R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP1R::_0 => false,
TP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP1R {
match value {
false => TP1R::_0,
true => TP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP1R::_1
}
}
#[doc = "Possible values of the field `WP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP1R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP1R::_0 => false,
WP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP1R {
match value {
false => WP1R::_0,
true => WP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP1R::_1
}
}
#[doc = "Possible values of the field `SP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP1R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP1R::_0 => false,
SP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP1R {
match value {
false => SP1R::_0,
true => SP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP1R::_1
}
}
#[doc = "Possible values of the field `TP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP0R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP0R::_0 => false,
TP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP0R {
match value {
false => TP0R::_0,
true => TP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP0R::_1
}
}
#[doc = "Possible values of the field `WP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP0R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP0R::_0 => false,
WP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP0R {
match value {
false => WP0R::_0,
true => WP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP0R::_1
}
}
#[doc = "Possible values of the field `SP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP0R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP0R::_0 => false,
SP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP0R {
match value {
false => SP0R::_0,
true => SP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP0R::_1
}
}
#[doc = "Values that can be written to the field `TP1`"]
pub enum TP1W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP1W::_0 => false,
TP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP1W<'a> {
w: &'a mut W,
}
impl<'a> _TP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP1W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP1`"]
pub enum WP1W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP1W::_0 => false,
WP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP1W<'a> {
w: &'a mut W,
}
impl<'a> _WP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP1W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP1`"]
pub enum SP1W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP1W::_0 => false,
SP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP1W<'a> {
w: &'a mut W,
}
impl<'a> _SP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP1W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TP0`"]
pub enum TP0W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP0W::_0 => false,
TP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP0W<'a> {
w: &'a mut W,
}
impl<'a> _TP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP0W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP0`"]
pub enum WP0W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP0W::_0 => false,
WP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP0W<'a> {
w: &'a mut W,
}
impl<'a> _WP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP0W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP0`"]
pub enum SP0W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP0W::_0 => false,
SP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP0W<'a> {
w: &'a mut W,
}
impl<'a> _SP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP0W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 24 - Trusted Protect"]
#[inline]
pub fn tp1(&self) -> TP1R {
TP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Write Protect"]
#[inline]
pub fn wp1(&self) -> WP1R {
WP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Supervisor Protect"]
#[inline]
pub fn sp1(&self) -> SP1R {
SP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&self) -> TP0R {
TP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&self) -> WP0R {
WP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&self) -> SP0R {
SP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1409286144 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 24 - Trusted Protect"]
#[inline]
pub fn tp1(&mut self) -> _TP1W {
_TP1W { w: self }
}
#[doc = "Bit 25 - Write Protect"]
#[inline]
pub fn wp1(&mut self) -> _WP1W {
_WP1W { w: self }
}
#[doc = "Bit 26 - Supervisor Protect"]
#[inline]
pub fn sp1(&mut self) -> _SP1W {
_SP1W { w: self }
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&mut self) -> _TP0W {
_TP0W { w: self }
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&mut self) -> _WP0W {
_WP0W { w: self }
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&mut self) -> _SP0W {
_SP0W { w: self }
}
}

1133
src/aips/pacrb/mod.rs Normal file
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18
src/aips/pacrc/mod.rs Normal file
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@ -0,0 +1,18 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::PACRC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}

776
src/aips/pacrd/mod.rs Normal file
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@ -0,0 +1,776 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PACRD {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP1R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP1R::_0 => false,
TP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP1R {
match value {
false => TP1R::_0,
true => TP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP1R::_1
}
}
#[doc = "Possible values of the field `WP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP1R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP1R::_0 => false,
WP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP1R {
match value {
false => WP1R::_0,
true => WP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP1R::_1
}
}
#[doc = "Possible values of the field `SP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP1R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP1R::_0 => false,
SP1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP1R {
match value {
false => SP1R::_0,
true => SP1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP1R::_1
}
}
#[doc = "Possible values of the field `TP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TP0R {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TP0R::_0 => false,
TP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TP0R {
match value {
false => TP0R::_0,
true => TP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TP0R::_1
}
}
#[doc = "Possible values of the field `WP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WP0R {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WP0R::_0 => false,
WP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WP0R {
match value {
false => WP0R::_0,
true => WP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WP0R::_1
}
}
#[doc = "Possible values of the field `SP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SP0R {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SP0R::_0 => false,
SP0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SP0R {
match value {
false => SP0R::_0,
true => SP0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SP0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SP0R::_1
}
}
#[doc = "Values that can be written to the field `TP1`"]
pub enum TP1W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP1W::_0 => false,
TP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP1W<'a> {
w: &'a mut W,
}
impl<'a> _TP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP1W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP1`"]
pub enum WP1W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP1W::_0 => false,
WP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP1W<'a> {
w: &'a mut W,
}
impl<'a> _WP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP1W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP1`"]
pub enum SP1W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP1W::_0 => false,
SP1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP1W<'a> {
w: &'a mut W,
}
impl<'a> _SP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP1W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TP0`"]
pub enum TP0W {
#[doc = "Accesses from an untrusted master are allowed."]
_0,
#[doc = "Accesses from an untrusted master are not allowed."]
_1,
}
impl TP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TP0W::_0 => false,
TP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TP0W<'a> {
w: &'a mut W,
}
impl<'a> _TP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accesses from an untrusted master are allowed."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TP0W::_0)
}
#[doc = "Accesses from an untrusted master are not allowed."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WP0`"]
pub enum WP0W {
#[doc = "This peripheral allows write accesses."]
_0,
#[doc = "This peripheral is write protected."]
_1,
}
impl WP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WP0W::_0 => false,
WP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WP0W<'a> {
w: &'a mut W,
}
impl<'a> _WP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP0W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP0`"]
pub enum SP0W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP0W::_0 => false,
SP0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP0W<'a> {
w: &'a mut W,
}
impl<'a> _SP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP0W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 24 - Trusted Protect"]
#[inline]
pub fn tp1(&self) -> TP1R {
TP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Write Protect"]
#[inline]
pub fn wp1(&self) -> WP1R {
WP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Supervisor Protect"]
#[inline]
pub fn sp1(&self) -> SP1R {
SP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&self) -> TP0R {
TP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&self) -> WP0R {
WP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&self) -> SP0R {
SP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1140850688 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 24 - Trusted Protect"]
#[inline]
pub fn tp1(&mut self) -> _TP1W {
_TP1W { w: self }
}
#[doc = "Bit 25 - Write Protect"]
#[inline]
pub fn wp1(&mut self) -> _WP1W {
_WP1W { w: self }
}
#[doc = "Bit 26 - Supervisor Protect"]
#[inline]
pub fn sp1(&mut self) -> _SP1W {
_SP1W { w: self }
}
#[doc = "Bit 28 - Trusted Protect"]
#[inline]
pub fn tp0(&mut self) -> _TP0W {
_TP0W { w: self }
}
#[doc = "Bit 29 - Write Protect"]
#[inline]
pub fn wp0(&mut self) -> _WP0W {
_WP0W { w: self }
}
#[doc = "Bit 30 - Supervisor Protect"]
#[inline]
pub fn sp0(&mut self) -> _SP0W {
_SP0W { w: self }
}
}

386
src/can0/cbt/mod.rs Normal file
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@ -0,0 +1,386 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CBT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EPSEG2R {
bits: u8,
}
impl EPSEG2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct EPSEG1R {
bits: u8,
}
impl EPSEG1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct EPROPSEGR {
bits: u8,
}
impl EPROPSEGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct ERJWR {
bits: u8,
}
impl ERJWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct EPRESDIVR {
bits: u16,
}
impl EPRESDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Possible values of the field `BTF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BTFR {
#[doc = "Extended bit time definitions disabled."]
_0,
#[doc = "Extended bit time definitions enabled."]
_1,
}
impl BTFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BTFR::_0 => false,
BTFR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BTFR {
match value {
false => BTFR::_0,
true => BTFR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BTFR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BTFR::_1
}
}
#[doc = r" Proxy"]
pub struct _EPSEG2W<'a> {
w: &'a mut W,
}
impl<'a> _EPSEG2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSEG1W<'a> {
w: &'a mut W,
}
impl<'a> _EPSEG1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPROPSEGW<'a> {
w: &'a mut W,
}
impl<'a> _EPROPSEGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 63;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERJWW<'a> {
w: &'a mut W,
}
impl<'a> _ERJWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRESDIVW<'a> {
w: &'a mut W,
}
impl<'a> _EPRESDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BTF`"]
pub enum BTFW {
#[doc = "Extended bit time definitions disabled."]
_0,
#[doc = "Extended bit time definitions enabled."]
_1,
}
impl BTFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BTFW::_0 => false,
BTFW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BTFW<'a> {
w: &'a mut W,
}
impl<'a> _BTFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BTFW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Extended bit time definitions disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BTFW::_0)
}
#[doc = "Extended bit time definitions enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BTFW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Extended Phase Segment 2"]
#[inline]
pub fn epseg2(&self) -> EPSEG2R {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPSEG2R { bits }
}
#[doc = "Bits 5:9 - Extended Phase Segment 1"]
#[inline]
pub fn epseg1(&self) -> EPSEG1R {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPSEG1R { bits }
}
#[doc = "Bits 10:15 - Extended Propagation Segment"]
#[inline]
pub fn epropseg(&self) -> EPROPSEGR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPROPSEGR { bits }
}
#[doc = "Bits 16:20 - Extended Resync Jump Width"]
#[inline]
pub fn erjw(&self) -> ERJWR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ERJWR { bits }
}
#[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
#[inline]
pub fn epresdiv(&self) -> EPRESDIVR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) as u16
};
EPRESDIVR { bits }
}
#[doc = "Bit 31 - Bit Timing Format Enable"]
#[inline]
pub fn btf(&self) -> BTFR {
BTFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Extended Phase Segment 2"]
#[inline]
pub fn epseg2(&mut self) -> _EPSEG2W {
_EPSEG2W { w: self }
}
#[doc = "Bits 5:9 - Extended Phase Segment 1"]
#[inline]
pub fn epseg1(&mut self) -> _EPSEG1W {
_EPSEG1W { w: self }
}
#[doc = "Bits 10:15 - Extended Propagation Segment"]
#[inline]
pub fn epropseg(&mut self) -> _EPROPSEGW {
_EPROPSEGW { w: self }
}
#[doc = "Bits 16:20 - Extended Resync Jump Width"]
#[inline]
pub fn erjw(&mut self) -> _ERJWW {
_ERJWW { w: self }
}
#[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
#[inline]
pub fn epresdiv(&mut self) -> _EPRESDIVW {
_EPRESDIVW { w: self }
}
#[doc = "Bit 31 - Bit Timing Format Enable"]
#[inline]
pub fn btf(&mut self) -> _BTFW {
_BTFW { w: self }
}
}

60
src/can0/crcr/mod.rs Normal file
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@ -0,0 +1,60 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CRCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct TXCRCR {
bits: u16,
}
impl TXCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MBCRCR {
bits: u8,
}
impl MBCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:14 - Transmitted CRC value"]
#[inline]
pub fn txcrc(&self) -> TXCRCR {
let bits = {
const MASK: u16 = 32767;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TXCRCR { bits }
}
#[doc = "Bits 16:22 - CRC Mailbox"]
#[inline]
pub fn mbcrc(&self) -> MBCRCR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MBCRCR { bits }
}
}

1576
src/can0/ctrl1/mod.rs Normal file
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828
src/can0/ctrl1_pn/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTRL1_PN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FCSR {
#[doc = "Message ID filtering only"]
_00,
#[doc = "Message ID filtering and payload filtering"]
_01,
#[doc = "Message ID filtering occurring a specified number of times."]
_10,
#[doc = "Message ID filtering and payload filtering a specified number of times"]
_11,
}
impl FCSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
FCSR::_00 => 0,
FCSR::_01 => 1,
FCSR::_10 => 2,
FCSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> FCSR {
match value {
0 => FCSR::_00,
1 => FCSR::_01,
2 => FCSR::_10,
3 => FCSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == FCSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == FCSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == FCSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == FCSR::_11
}
}
#[doc = "Possible values of the field `IDFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDFSR {
#[doc = "Match upon a ID contents against an exact target value"]
_00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
impl IDFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
IDFSR::_00 => 0,
IDFSR::_01 => 1,
IDFSR::_10 => 2,
IDFSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> IDFSR {
match value {
0 => IDFSR::_00,
1 => IDFSR::_01,
2 => IDFSR::_10,
3 => IDFSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == IDFSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == IDFSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == IDFSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == IDFSR::_11
}
}
#[doc = "Possible values of the field `PLFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLFSR {
#[doc = "Match upon a payload contents against an exact target value"]
_00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
impl PLFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PLFSR::_00 => 0,
PLFSR::_01 => 1,
PLFSR::_10 => 2,
PLFSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PLFSR {
match value {
0 => PLFSR::_00,
1 => PLFSR::_01,
2 => PLFSR::_10,
3 => PLFSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == PLFSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == PLFSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == PLFSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == PLFSR::_11
}
}
#[doc = "Possible values of the field `NMATCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NMATCHR {
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL once before generating a wake up event."]
_00000001,
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wake up event."]
_00000010,
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."]
_11111111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl NMATCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
NMATCHR::_00000001 => 1,
NMATCHR::_00000010 => 2,
NMATCHR::_11111111 => 255,
NMATCHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> NMATCHR {
match value {
1 => NMATCHR::_00000001,
2 => NMATCHR::_00000010,
255 => NMATCHR::_11111111,
i => NMATCHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00000001`"]
#[inline]
pub fn is_00000001(&self) -> bool {
*self == NMATCHR::_00000001
}
#[doc = "Checks if the value of the field is `_00000010`"]
#[inline]
pub fn is_00000010(&self) -> bool {
*self == NMATCHR::_00000010
}
#[doc = "Checks if the value of the field is `_11111111`"]
#[inline]
pub fn is_11111111(&self) -> bool {
*self == NMATCHR::_11111111
}
}
#[doc = "Possible values of the field `WUMF_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WUMF_MSKR {
#[doc = "Wake up match event is disabled"]
_0,
#[doc = "Wake up match event is enabled"]
_1,
}
impl WUMF_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WUMF_MSKR::_0 => false,
WUMF_MSKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WUMF_MSKR {
match value {
false => WUMF_MSKR::_0,
true => WUMF_MSKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WUMF_MSKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WUMF_MSKR::_1
}
}
#[doc = "Possible values of the field `WTOF_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WTOF_MSKR {
#[doc = "Timeout wake up event is disabled"]
_0,
#[doc = "Timeout wake up event is enabled"]
_1,
}
impl WTOF_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WTOF_MSKR::_0 => false,
WTOF_MSKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WTOF_MSKR {
match value {
false => WTOF_MSKR::_0,
true => WTOF_MSKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == WTOF_MSKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == WTOF_MSKR::_1
}
}
#[doc = "Values that can be written to the field `FCS`"]
pub enum FCSW {
#[doc = "Message ID filtering only"]
_00,
#[doc = "Message ID filtering and payload filtering"]
_01,
#[doc = "Message ID filtering occurring a specified number of times."]
_10,
#[doc = "Message ID filtering and payload filtering a specified number of times"]
_11,
}
impl FCSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
FCSW::_00 => 0,
FCSW::_01 => 1,
FCSW::_10 => 2,
FCSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _FCSW<'a> {
w: &'a mut W,
}
impl<'a> _FCSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FCSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Message ID filtering only"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(FCSW::_00)
}
#[doc = "Message ID filtering and payload filtering"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(FCSW::_01)
}
#[doc = "Message ID filtering occurring a specified number of times."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(FCSW::_10)
}
#[doc = "Message ID filtering and payload filtering a specified number of times"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(FCSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `IDFS`"]
pub enum IDFSW {
#[doc = "Match upon a ID contents against an exact target value"]
_00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
impl IDFSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
IDFSW::_00 => 0,
IDFSW::_01 => 1,
IDFSW::_10 => 2,
IDFSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _IDFSW<'a> {
w: &'a mut W,
}
impl<'a> _IDFSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: IDFSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Match upon a ID contents against an exact target value"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(IDFSW::_00)
}
#[doc = "Match upon a ID value greater than or equal to a specified target value"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(IDFSW::_01)
}
#[doc = "Match upon a ID value smaller than or equal to a specified target value"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(IDFSW::_10)
}
#[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(IDFSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PLFS`"]
pub enum PLFSW {
#[doc = "Match upon a payload contents against an exact target value"]
_00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
impl PLFSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PLFSW::_00 => 0,
PLFSW::_01 => 1,
PLFSW::_10 => 2,
PLFSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PLFSW<'a> {
w: &'a mut W,
}
impl<'a> _PLFSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PLFSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Match upon a payload contents against an exact target value"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(PLFSW::_00)
}
#[doc = "Match upon a payload value greater than or equal to a specified target value"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(PLFSW::_01)
}
#[doc = "Match upon a payload value smaller than or equal to a specified target value"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(PLFSW::_10)
}
#[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(PLFSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `NMATCH`"]
pub enum NMATCHW {
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL once before generating a wake up event."]
_00000001,
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wake up event."]
_00000010,
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."]
_11111111,
}
impl NMATCHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
NMATCHW::_00000001 => 1,
NMATCHW::_00000010 => 2,
NMATCHW::_11111111 => 255,
}
}
}
#[doc = r" Proxy"]
pub struct _NMATCHW<'a> {
w: &'a mut W,
}
impl<'a> _NMATCHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: NMATCHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL once before generating a wake up event."]
#[inline]
pub fn _00000001(self) -> &'a mut W {
self.variant(NMATCHW::_00000001)
}
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wake up event."]
#[inline]
pub fn _00000010(self) -> &'a mut W {
self.variant(NMATCHW::_00000010)
}
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."]
#[inline]
pub fn _11111111(self) -> &'a mut W {
self.variant(NMATCHW::_11111111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WUMF_MSK`"]
pub enum WUMF_MSKW {
#[doc = "Wake up match event is disabled"]
_0,
#[doc = "Wake up match event is enabled"]
_1,
}
impl WUMF_MSKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WUMF_MSKW::_0 => false,
WUMF_MSKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WUMF_MSKW<'a> {
w: &'a mut W,
}
impl<'a> _WUMF_MSKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WUMF_MSKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Wake up match event is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WUMF_MSKW::_0)
}
#[doc = "Wake up match event is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WUMF_MSKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WTOF_MSK`"]
pub enum WTOF_MSKW {
#[doc = "Timeout wake up event is disabled"]
_0,
#[doc = "Timeout wake up event is enabled"]
_1,
}
impl WTOF_MSKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WTOF_MSKW::_0 => false,
WTOF_MSKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WTOF_MSKW<'a> {
w: &'a mut W,
}
impl<'a> _WTOF_MSKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WTOF_MSKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Timeout wake up event is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WTOF_MSKW::_0)
}
#[doc = "Timeout wake up event is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WTOF_MSKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Filtering Combination Selection"]
#[inline]
pub fn fcs(&self) -> FCSR {
FCSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - ID Filtering Selection"]
#[inline]
pub fn idfs(&self) -> IDFSR {
IDFSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Payload Filtering Selection"]
#[inline]
pub fn plfs(&self) -> PLFSR {
PLFSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"]
#[inline]
pub fn nmatch(&self) -> NMATCHR {
NMATCHR::_from({
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 16 - Wake Up by Match Flag Mask Bit"]
#[inline]
pub fn wumf_msk(&self) -> WUMF_MSKR {
WUMF_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Wake Up by Timeout Flag Mask Bit"]
#[inline]
pub fn wtof_msk(&self) -> WTOF_MSKR {
WTOF_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 256 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Filtering Combination Selection"]
#[inline]
pub fn fcs(&mut self) -> _FCSW {
_FCSW { w: self }
}
#[doc = "Bits 2:3 - ID Filtering Selection"]
#[inline]
pub fn idfs(&mut self) -> _IDFSW {
_IDFSW { w: self }
}
#[doc = "Bits 4:5 - Payload Filtering Selection"]
#[inline]
pub fn plfs(&mut self) -> _PLFSW {
_PLFSW { w: self }
}
#[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"]
#[inline]
pub fn nmatch(&mut self) -> _NMATCHW {
_NMATCHW { w: self }
}
#[doc = "Bit 16 - Wake Up by Match Flag Mask Bit"]
#[inline]
pub fn wumf_msk(&mut self) -> _WUMF_MSKW {
_WUMF_MSKW { w: self }
}
#[doc = "Bit 17 - Wake Up by Timeout Flag Mask Bit"]
#[inline]
pub fn wtof_msk(&mut self) -> _WTOF_MSKW {
_WTOF_MSKW { w: self }
}
}

1215
src/can0/ctrl2/mod.rs Normal file
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103
src/can0/ctrl2_pn/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTRL2_PN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MATCHTOR {
bits: u16,
}
impl MATCHTOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MATCHTOW<'a> {
w: &'a mut W,
}
impl<'a> _MATCHTOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
#[inline]
pub fn matchto(&self) -> MATCHTOR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MATCHTOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
#[inline]
pub fn matchto(&mut self) -> _MATCHTOW {
_MATCHTOW { w: self }
}
}

226
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ECR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXERRCNTR {
bits: u8,
}
impl TXERRCNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RXERRCNTR {
bits: u8,
}
impl RXERRCNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TXERRCNT_FASTR {
bits: u8,
}
impl TXERRCNT_FASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RXERRCNT_FASTR {
bits: u8,
}
impl RXERRCNT_FASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TXERRCNTW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRCNTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRCNTW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRCNTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXERRCNT_FASTW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRCNT_FASTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRCNT_FASTW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRCNT_FASTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline]
pub fn txerrcnt(&self) -> TXERRCNTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TXERRCNTR { bits }
}
#[doc = "Bits 8:15 - Receive Error Counter"]
#[inline]
pub fn rxerrcnt(&self) -> RXERRCNTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXERRCNTR { bits }
}
#[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
#[inline]
pub fn txerrcnt_fast(&self) -> TXERRCNT_FASTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TXERRCNT_FASTR { bits }
}
#[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
#[inline]
pub fn rxerrcnt_fast(&self) -> RXERRCNT_FASTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXERRCNT_FASTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline]
pub fn txerrcnt(&mut self) -> _TXERRCNTW {
_TXERRCNTW { w: self }
}
#[doc = "Bits 8:15 - Receive Error Counter"]
#[inline]
pub fn rxerrcnt(&mut self) -> _RXERRCNTW {
_RXERRCNTW { w: self }
}
#[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
#[inline]
pub fn txerrcnt_fast(&mut self) -> _TXERRCNT_FASTW {
_TXERRCNT_FASTW { w: self }
}
#[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
#[inline]
pub fn rxerrcnt_fast(&mut self) -> _RXERRCNT_FASTW {
_RXERRCNT_FASTW { w: self }
}
}

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src/can0/embedded_ram/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EMBEDDEDRAM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_3R {
bits: u8,
}
impl DATA_BYTE_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_2R {
bits: u8,
}
impl DATA_BYTE_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_1R {
bits: u8,
}
impl DATA_BYTE_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_0R {
bits: u8,
}
impl DATA_BYTE_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_0W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data byte 3 of Rx/Tx frame."]
#[inline]
pub fn data_byte_3(&self) -> DATA_BYTE_3R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_3R { bits }
}
#[doc = "Bits 8:15 - Data byte 2 of Rx/Tx frame."]
#[inline]
pub fn data_byte_2(&self) -> DATA_BYTE_2R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_2R { bits }
}
#[doc = "Bits 16:23 - Data byte 1 of Rx/Tx frame."]
#[inline]
pub fn data_byte_1(&self) -> DATA_BYTE_1R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_1R { bits }
}
#[doc = "Bits 24:31 - Data byte 0 of Rx/Tx frame."]
#[inline]
pub fn data_byte_0(&self) -> DATA_BYTE_0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data byte 3 of Rx/Tx frame."]
#[inline]
pub fn data_byte_3(&mut self) -> _DATA_BYTE_3W {
_DATA_BYTE_3W { w: self }
}
#[doc = "Bits 8:15 - Data byte 2 of Rx/Tx frame."]
#[inline]
pub fn data_byte_2(&mut self) -> _DATA_BYTE_2W {
_DATA_BYTE_2W { w: self }
}
#[doc = "Bits 16:23 - Data byte 1 of Rx/Tx frame."]
#[inline]
pub fn data_byte_1(&mut self) -> _DATA_BYTE_1W {
_DATA_BYTE_1W { w: self }
}
#[doc = "Bits 24:31 - Data byte 0 of Rx/Tx frame."]
#[inline]
pub fn data_byte_0(&mut self) -> _DATA_BYTE_0W {
_DATA_BYTE_0W { w: self }
}
}

1906
src/can0/esr1/mod.rs Normal file
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src/can0/esr2/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::ESR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `IMB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMBR {
#[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."]
_0,
#[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
_1,
}
impl IMBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMBR::_0 => false,
IMBR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMBR {
match value {
false => IMBR::_0,
true => IMBR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == IMBR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == IMBR::_1
}
}
#[doc = "Possible values of the field `VPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum VPSR {
#[doc = "Contents of IMB and LPTM are invalid."]
_0,
#[doc = "Contents of IMB and LPTM are valid."]
_1,
}
impl VPSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
VPSR::_0 => false,
VPSR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> VPSR {
match value {
false => VPSR::_0,
true => VPSR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == VPSR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == VPSR::_1
}
}
#[doc = r" Value of the field"]
pub struct LPTMR {
bits: u8,
}
impl LPTMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 13 - Inactive Mailbox"]
#[inline]
pub fn imb(&self) -> IMBR {
IMBR::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Valid Priority Status"]
#[inline]
pub fn vps(&self) -> VPSR {
VPSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 16:22 - Lowest Priority Tx Mailbox"]
#[inline]
pub fn lptm(&self) -> LPTMR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
LPTMR { bits }
}
}

267
src/can0/fdcbt/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FDCBT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FPSEG2R {
bits: u8,
}
impl FPSEG2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FPSEG1R {
bits: u8,
}
impl FPSEG1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FPROPSEGR {
bits: u8,
}
impl FPROPSEGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FRJWR {
bits: u8,
}
impl FRJWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FPRESDIVR {
bits: u16,
}
impl FPRESDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _FPSEG2W<'a> {
w: &'a mut W,
}
impl<'a> _FPSEG2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FPSEG1W<'a> {
w: &'a mut W,
}
impl<'a> _FPSEG1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FPROPSEGW<'a> {
w: &'a mut W,
}
impl<'a> _FPROPSEGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FRJWW<'a> {
w: &'a mut W,
}
impl<'a> _FRJWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FPRESDIVW<'a> {
w: &'a mut W,
}
impl<'a> _FPRESDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Fast Phase Segment 2"]
#[inline]
pub fn fpseg2(&self) -> FPSEG2R {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPSEG2R { bits }
}
#[doc = "Bits 5:7 - Fast Phase Segment 1"]
#[inline]
pub fn fpseg1(&self) -> FPSEG1R {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPSEG1R { bits }
}
#[doc = "Bits 10:14 - Fast Propagation Segment"]
#[inline]
pub fn fpropseg(&self) -> FPROPSEGR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPROPSEGR { bits }
}
#[doc = "Bits 16:18 - Fast Resync Jump Width"]
#[inline]
pub fn frjw(&self) -> FRJWR {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FRJWR { bits }
}
#[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
#[inline]
pub fn fpresdiv(&self) -> FPRESDIVR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u16
};
FPRESDIVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Fast Phase Segment 2"]
#[inline]
pub fn fpseg2(&mut self) -> _FPSEG2W {
_FPSEG2W { w: self }
}
#[doc = "Bits 5:7 - Fast Phase Segment 1"]
#[inline]
pub fn fpseg1(&mut self) -> _FPSEG1W {
_FPSEG1W { w: self }
}
#[doc = "Bits 10:14 - Fast Propagation Segment"]
#[inline]
pub fn fpropseg(&mut self) -> _FPROPSEGW {
_FPROPSEGW { w: self }
}
#[doc = "Bits 16:18 - Fast Resync Jump Width"]
#[inline]
pub fn frjw(&mut self) -> _FRJWW {
_FRJWW { w: self }
}
#[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
#[inline]
pub fn fpresdiv(&mut self) -> _FPRESDIVW {
_FPRESDIVW { w: self }
}
}

60
src/can0/fdcrc/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::FDCRC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct FD_TXCRCR {
bits: u32,
}
impl FD_TXCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FD_MBCRCR {
bits: u8,
}
impl FD_MBCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:20 - Extended Transmitted CRC value"]
#[inline]
pub fn fd_txcrc(&self) -> FD_TXCRCR {
let bits = {
const MASK: u32 = 2097151;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FD_TXCRCR { bits }
}
#[doc = "Bits 24:30 - CRC Mailbox Number for FD_TXCRC"]
#[inline]
pub fn fd_mbcrc(&self) -> FD_MBCRCR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FD_MBCRCR { bits }
}
}

617
src/can0/fdctrl/mod.rs Normal file
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@ -0,0 +1,617 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FDCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TDCVALR {
bits: u8,
}
impl TDCVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TDCOFFR {
bits: u8,
}
impl TDCOFFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `TDCFAIL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDCFAILR {
#[doc = "Measured loop delay is in range."]
_0,
#[doc = "Measured loop delay is out of range."]
_1,
}
impl TDCFAILR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TDCFAILR::_0 => false,
TDCFAILR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TDCFAILR {
match value {
false => TDCFAILR::_0,
true => TDCFAILR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TDCFAILR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TDCFAILR::_1
}
}
#[doc = "Possible values of the field `TDCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDCENR {
#[doc = "TDC is disabled"]
_0,
#[doc = "TDC is enabled"]
_1,
}
impl TDCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TDCENR::_0 => false,
TDCENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TDCENR {
match value {
false => TDCENR::_0,
true => TDCENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TDCENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TDCENR::_1
}
}
#[doc = "Possible values of the field `MBDSR0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MBDSR0R {
#[doc = "Selects 8 bytes per Message Buffer."]
_00,
#[doc = "Selects 16 bytes per Message Buffer."]
_01,
#[doc = "Selects 32 bytes per Message Buffer."]
_10,
#[doc = "Selects 64 bytes per Message Buffer."]
_11,
}
impl MBDSR0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
MBDSR0R::_00 => 0,
MBDSR0R::_01 => 1,
MBDSR0R::_10 => 2,
MBDSR0R::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> MBDSR0R {
match value {
0 => MBDSR0R::_00,
1 => MBDSR0R::_01,
2 => MBDSR0R::_10,
3 => MBDSR0R::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == MBDSR0R::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == MBDSR0R::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == MBDSR0R::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == MBDSR0R::_11
}
}
#[doc = "Possible values of the field `FDRATE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FDRATER {
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
_0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
_1,
}
impl FDRATER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FDRATER::_0 => false,
FDRATER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FDRATER {
match value {
false => FDRATER::_0,
true => FDRATER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FDRATER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FDRATER::_1
}
}
#[doc = r" Proxy"]
pub struct _TDCOFFW<'a> {
w: &'a mut W,
}
impl<'a> _TDCOFFW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TDCFAIL`"]
pub enum TDCFAILW {
#[doc = "Measured loop delay is in range."]
_0,
#[doc = "Measured loop delay is out of range."]
_1,
}
impl TDCFAILW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TDCFAILW::_0 => false,
TDCFAILW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TDCFAILW<'a> {
w: &'a mut W,
}
impl<'a> _TDCFAILW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TDCFAILW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Measured loop delay is in range."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TDCFAILW::_0)
}
#[doc = "Measured loop delay is out of range."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TDCFAILW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TDCEN`"]
pub enum TDCENW {
#[doc = "TDC is disabled"]
_0,
#[doc = "TDC is enabled"]
_1,
}
impl TDCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TDCENW::_0 => false,
TDCENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TDCENW<'a> {
w: &'a mut W,
}
impl<'a> _TDCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TDCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TDC is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(TDCENW::_0)
}
#[doc = "TDC is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(TDCENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MBDSR0`"]
pub enum MBDSR0W {
#[doc = "Selects 8 bytes per Message Buffer."]
_00,
#[doc = "Selects 16 bytes per Message Buffer."]
_01,
#[doc = "Selects 32 bytes per Message Buffer."]
_10,
#[doc = "Selects 64 bytes per Message Buffer."]
_11,
}
impl MBDSR0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
MBDSR0W::_00 => 0,
MBDSR0W::_01 => 1,
MBDSR0W::_10 => 2,
MBDSR0W::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _MBDSR0W<'a> {
w: &'a mut W,
}
impl<'a> _MBDSR0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MBDSR0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Selects 8 bytes per Message Buffer."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(MBDSR0W::_00)
}
#[doc = "Selects 16 bytes per Message Buffer."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(MBDSR0W::_01)
}
#[doc = "Selects 32 bytes per Message Buffer."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(MBDSR0W::_10)
}
#[doc = "Selects 64 bytes per Message Buffer."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(MBDSR0W::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FDRATE`"]
pub enum FDRATEW {
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
_0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
_1,
}
impl FDRATEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FDRATEW::_0 => false,
FDRATEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FDRATEW<'a> {
w: &'a mut W,
}
impl<'a> _FDRATEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FDRATEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FDRATEW::_0)
}
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FDRATEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Transceiver Delay Compensation Value"]
#[inline]
pub fn tdcval(&self) -> TDCVALR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TDCVALR { bits }
}
#[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
#[inline]
pub fn tdcoff(&self) -> TDCOFFR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TDCOFFR { bits }
}
#[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
#[inline]
pub fn tdcfail(&self) -> TDCFAILR {
TDCFAILR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
#[inline]
pub fn tdcen(&self) -> TDCENR {
TDCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
#[inline]
pub fn mbdsr0(&self) -> MBDSR0R {
MBDSR0R::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 31 - Bit Rate Switch Enable"]
#[inline]
pub fn fdrate(&self) -> FDRATER {
FDRATER::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 2147483904 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
#[inline]
pub fn tdcoff(&mut self) -> _TDCOFFW {
_TDCOFFW { w: self }
}
#[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
#[inline]
pub fn tdcfail(&mut self) -> _TDCFAILW {
_TDCFAILW { w: self }
}
#[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
#[inline]
pub fn tdcen(&mut self) -> _TDCENW {
_TDCENW { w: self }
}
#[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
#[inline]
pub fn mbdsr0(&mut self) -> _MBDSR0W {
_MBDSR0W { w: self }
}
#[doc = "Bit 31 - Bit Rate Switch Enable"]
#[inline]
pub fn fdrate(&mut self) -> _FDRATEW {
_FDRATEW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FLT_DLC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FLT_DLC_HIR {
bits: u8,
}
impl FLT_DLC_HIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FLT_DLC_LOR {
bits: u8,
}
impl FLT_DLC_LOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _FLT_DLC_HIW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_DLC_HIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FLT_DLC_LOW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_DLC_LOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_hi(&self) -> FLT_DLC_HIR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FLT_DLC_HIR { bits }
}
#[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_lo(&self) -> FLT_DLC_LOR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FLT_DLC_LOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 8 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_hi(&mut self) -> _FLT_DLC_HIW {
_FLT_DLC_HIW { w: self }
}
#[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_lo(&mut self) -> _FLT_DLC_LOW {
_FLT_DLC_LOW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FLT_ID1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FLT_ID1R {
bits: u32,
}
impl FLT_ID1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = "Possible values of the field `FLT_RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT_RTRR {
#[doc = "Reject remote frame (accept data frame)"]
_0,
#[doc = "Accept remote frame"]
_1,
}
impl FLT_RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FLT_RTRR::_0 => false,
FLT_RTRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FLT_RTRR {
match value {
false => FLT_RTRR::_0,
true => FLT_RTRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FLT_RTRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FLT_RTRR::_1
}
}
#[doc = "Possible values of the field `FLT_IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT_IDER {
#[doc = "Accept standard frame format"]
_0,
#[doc = "Accept extended frame format"]
_1,
}
impl FLT_IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FLT_IDER::_0 => false,
FLT_IDER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FLT_IDER {
match value {
false => FLT_IDER::_0,
true => FLT_IDER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FLT_IDER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FLT_IDER::_1
}
}
#[doc = r" Proxy"]
pub struct _FLT_ID1W<'a> {
w: &'a mut W,
}
impl<'a> _FLT_ID1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FLT_RTR`"]
pub enum FLT_RTRW {
#[doc = "Reject remote frame (accept data frame)"]
_0,
#[doc = "Accept remote frame"]
_1,
}
impl FLT_RTRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FLT_RTRW::_0 => false,
FLT_RTRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FLT_RTRW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_RTRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FLT_RTRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Reject remote frame (accept data frame)"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FLT_RTRW::_0)
}
#[doc = "Accept remote frame"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FLT_RTRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FLT_IDE`"]
pub enum FLT_IDEW {
#[doc = "Accept standard frame format"]
_0,
#[doc = "Accept extended frame format"]
_1,
}
impl FLT_IDEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FLT_IDEW::_0 => false,
FLT_IDEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FLT_IDEW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_IDEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FLT_IDEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accept standard frame format"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FLT_IDEW::_0)
}
#[doc = "Accept extended frame format"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FLT_IDEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
#[inline]
pub fn flt_id1(&self) -> FLT_ID1R {
let bits = {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FLT_ID1R { bits }
}
#[doc = "Bit 29 - Remote Transmission Request Filter"]
#[inline]
pub fn flt_rtr(&self) -> FLT_RTRR {
FLT_RTRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - ID Extended Filter"]
#[inline]
pub fn flt_ide(&self) -> FLT_IDER {
FLT_IDER::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
#[inline]
pub fn flt_id1(&mut self) -> _FLT_ID1W {
_FLT_ID1W { w: self }
}
#[doc = "Bit 29 - Remote Transmission Request Filter"]
#[inline]
pub fn flt_rtr(&mut self) -> _FLT_RTRW {
_FLT_RTRW { w: self }
}
#[doc = "Bit 30 - ID Extended Filter"]
#[inline]
pub fn flt_ide(&mut self) -> _FLT_IDEW {
_FLT_IDEW { w: self }
}
}

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src/can0/flt_id2_idmask/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FLT_ID2_IDMASK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FLT_ID2_IDMASKR {
bits: u32,
}
impl FLT_ID2_IDMASKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = "Possible values of the field `RTR_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTR_MSKR {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
}
impl RTR_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RTR_MSKR::_0 => false,
RTR_MSKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RTR_MSKR {
match value {
false => RTR_MSKR::_0,
true => RTR_MSKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == RTR_MSKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == RTR_MSKR::_1
}
}
#[doc = "Possible values of the field `IDE_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDE_MSKR {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
}
impl IDE_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IDE_MSKR::_0 => false,
IDE_MSKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IDE_MSKR {
match value {
false => IDE_MSKR::_0,
true => IDE_MSKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == IDE_MSKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == IDE_MSKR::_1
}
}
#[doc = r" Proxy"]
pub struct _FLT_ID2_IDMASKW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_ID2_IDMASKW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RTR_MSK`"]
pub enum RTR_MSKW {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
}
impl RTR_MSKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RTR_MSKW::_0 => false,
RTR_MSKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RTR_MSKW<'a> {
w: &'a mut W,
}
impl<'a> _RTR_MSKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RTR_MSKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The corresponding bit in the filter is \"don't care\""]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(RTR_MSKW::_0)
}
#[doc = "The corresponding bit in the filter is checked"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(RTR_MSKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `IDE_MSK`"]
pub enum IDE_MSKW {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
}
impl IDE_MSKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
IDE_MSKW::_0 => false,
IDE_MSKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _IDE_MSKW<'a> {
w: &'a mut W,
}
impl<'a> _IDE_MSKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: IDE_MSKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The corresponding bit in the filter is \"don't care\""]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(IDE_MSKW::_0)
}
#[doc = "The corresponding bit in the filter is checked"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(IDE_MSKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
#[inline]
pub fn flt_id2_idmask(&self) -> FLT_ID2_IDMASKR {
let bits = {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FLT_ID2_IDMASKR { bits }
}
#[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
#[inline]
pub fn rtr_msk(&self) -> RTR_MSKR {
RTR_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - ID Extended Mask Bit"]
#[inline]
pub fn ide_msk(&self) -> IDE_MSKR {
IDE_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
#[inline]
pub fn flt_id2_idmask(&mut self) -> _FLT_ID2_IDMASKW {
_FLT_ID2_IDMASKW { w: self }
}
#[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
#[inline]
pub fn rtr_msk(&mut self) -> _RTR_MSKW {
_RTR_MSKW { w: self }
}
#[doc = "Bit 30 - ID Extended Mask Bit"]
#[inline]
pub fn ide_msk(&mut self) -> _IDE_MSKW {
_IDE_MSKW { w: self }
}
}

620
src/can0/iflag1/mod.rs Normal file
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@ -0,0 +1,620 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IFLAG1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `BUF0I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF0IR {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
_0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
_1,
}
impl BUF0IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF0IR::_0 => false,
BUF0IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF0IR {
match value {
false => BUF0IR::_0,
true => BUF0IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF0IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF0IR::_1
}
}
#[doc = r" Value of the field"]
pub struct BUF4TO1IR {
bits: u8,
}
impl BUF4TO1IR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `BUF5I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF5IR {
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
_0,
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
_1,
}
impl BUF5IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF5IR::_0 => false,
BUF5IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF5IR {
match value {
false => BUF5IR::_0,
true => BUF5IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF5IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF5IR::_1
}
}
#[doc = "Possible values of the field `BUF6I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF6IR {
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
_0,
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
_1,
}
impl BUF6IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF6IR::_0 => false,
BUF6IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF6IR {
match value {
false => BUF6IR::_0,
true => BUF6IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF6IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF6IR::_1
}
}
#[doc = "Possible values of the field `BUF7I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF7IR {
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
_0,
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
_1,
}
impl BUF7IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF7IR::_0 => false,
BUF7IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF7IR {
match value {
false => BUF7IR::_0,
true => BUF7IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF7IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF7IR::_1
}
}
#[doc = r" Value of the field"]
pub struct BUF31TO8IR {
bits: u32,
}
impl BUF31TO8IR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = "Values that can be written to the field `BUF0I`"]
pub enum BUF0IW {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
_0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
_1,
}
impl BUF0IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BUF0IW::_0 => false,
BUF0IW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BUF0IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF0IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BUF0IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF0IW::_0)
}
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF0IW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BUF4TO1IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF4TO1IW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BUF5I`"]
pub enum BUF5IW {
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
_0,
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
_1,
}
impl BUF5IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BUF5IW::_0 => false,
BUF5IW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BUF5IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF5IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BUF5IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF5IW::_0)
}
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF5IW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BUF6I`"]
pub enum BUF6IW {
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
_0,
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
_1,
}
impl BUF6IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BUF6IW::_0 => false,
BUF6IW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BUF6IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF6IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BUF6IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF6IW::_0)
}
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF6IW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BUF7I`"]
pub enum BUF7IW {
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
_0,
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
_1,
}
impl BUF7IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BUF7IW::_0 => false,
BUF7IW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BUF7IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF7IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BUF7IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF7IW::_0)
}
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF7IW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BUF31TO8IW<'a> {
w: &'a mut W,
}
impl<'a> _BUF31TO8IW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 16777215;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"]
#[inline]
pub fn buf0i(&self) -> BUF0IR {
BUF0IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""]
#[inline]
pub fn buf4to1i(&self) -> BUF4TO1IR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BUF4TO1IR { bits }
}
#[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""]
#[inline]
pub fn buf5i(&self) -> BUF5IR {
BUF5IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""]
#[inline]
pub fn buf6i(&self) -> BUF6IR {
BUF6IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""]
#[inline]
pub fn buf7i(&self) -> BUF7IR {
BUF7IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 8:31 - Buffer MBi Interrupt"]
#[inline]
pub fn buf31to8i(&self) -> BUF31TO8IR {
let bits = {
const MASK: u32 = 16777215;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u32
};
BUF31TO8IR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"]
#[inline]
pub fn buf0i(&mut self) -> _BUF0IW {
_BUF0IW { w: self }
}
#[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""]
#[inline]
pub fn buf4to1i(&mut self) -> _BUF4TO1IW {
_BUF4TO1IW { w: self }
}
#[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""]
#[inline]
pub fn buf5i(&mut self) -> _BUF5IW {
_BUF5IW { w: self }
}
#[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""]
#[inline]
pub fn buf6i(&mut self) -> _BUF6IW {
_BUF6IW { w: self }
}
#[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""]
#[inline]
pub fn buf7i(&mut self) -> _BUF7IW {
_BUF7IW { w: self }
}
#[doc = "Bits 8:31 - Buffer MBi Interrupt"]
#[inline]
pub fn buf31to8i(&mut self) -> _BUF31TO8IW {
_BUF31TO8IW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IMASK1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BUF31TO0MR {
bits: u32,
}
impl BUF31TO0MR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BUF31TO0MW<'a> {
w: &'a mut W,
}
impl<'a> _BUF31TO0MW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Buffer MB i Mask"]
#[inline]
pub fn buf31to0m(&self) -> BUF31TO0MR {
let bits = {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
BUF31TO0MR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Buffer MB i Mask"]
#[inline]
pub fn buf31to0m(&mut self) -> _BUF31TO0MW {
_BUF31TO0MW { w: self }
}
}

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use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Module Configuration Register"]
pub mcr: MCR,
#[doc = "0x04 - Control 1 register"]
pub ctrl1: CTRL1,
#[doc = "0x08 - Free Running Timer"]
pub timer: TIMER,
_reserved0: [u8; 4usize],
#[doc = "0x10 - Rx Mailboxes Global Mask Register"]
pub rxmgmask: RXMGMASK,
#[doc = "0x14 - Rx 14 Mask register"]
pub rx14mask: RX14MASK,
#[doc = "0x18 - Rx 15 Mask register"]
pub rx15mask: RX15MASK,
#[doc = "0x1c - Error Counter"]
pub ecr: ECR,
#[doc = "0x20 - Error and Status 1 register"]
pub esr1: ESR1,
_reserved1: [u8; 4usize],
#[doc = "0x28 - Interrupt Masks 1 register"]
pub imask1: IMASK1,
_reserved2: [u8; 4usize],
#[doc = "0x30 - Interrupt Flags 1 register"]
pub iflag1: IFLAG1,
#[doc = "0x34 - Control 2 register"]
pub ctrl2: CTRL2,
#[doc = "0x38 - Error and Status 2 register"]
pub esr2: ESR2,
_reserved3: [u8; 8usize],
#[doc = "0x44 - CRC Register"]
pub crcr: CRCR,
#[doc = "0x48 - Rx FIFO Global Mask register"]
pub rxfgmask: RXFGMASK,
#[doc = "0x4c - Rx FIFO Information Register"]
pub rxfir: RXFIR,
#[doc = "0x50 - CAN Bit Timing Register"]
pub cbt: CBT,
_reserved4: [u8; 44usize],
#[doc = "0x80 - Embedded RAM"]
pub embedded_ram: [EMBEDDEDRAM; 128],
_reserved5: [u8; 1536usize],
#[doc = "0x880 - Rx Individual Mask Registers"]
pub rximr0: RXIMR0,
#[doc = "0x884 - Rx Individual Mask Registers"]
pub rximr1: RXIMR1,
#[doc = "0x888 - Rx Individual Mask Registers"]
pub rximr2: RXIMR2,
#[doc = "0x88c - Rx Individual Mask Registers"]
pub rximr3: RXIMR3,
#[doc = "0x890 - Rx Individual Mask Registers"]
pub rximr4: RXIMR4,
#[doc = "0x894 - Rx Individual Mask Registers"]
pub rximr5: RXIMR5,
#[doc = "0x898 - Rx Individual Mask Registers"]
pub rximr6: RXIMR6,
#[doc = "0x89c - Rx Individual Mask Registers"]
pub rximr7: RXIMR7,
#[doc = "0x8a0 - Rx Individual Mask Registers"]
pub rximr8: RXIMR8,
#[doc = "0x8a4 - Rx Individual Mask Registers"]
pub rximr9: RXIMR9,
#[doc = "0x8a8 - Rx Individual Mask Registers"]
pub rximr10: RXIMR10,
#[doc = "0x8ac - Rx Individual Mask Registers"]
pub rximr11: RXIMR11,
#[doc = "0x8b0 - Rx Individual Mask Registers"]
pub rximr12: RXIMR12,
#[doc = "0x8b4 - Rx Individual Mask Registers"]
pub rximr13: RXIMR13,
#[doc = "0x8b8 - Rx Individual Mask Registers"]
pub rximr14: RXIMR14,
#[doc = "0x8bc - Rx Individual Mask Registers"]
pub rximr15: RXIMR15,
_reserved6: [u8; 576usize],
#[doc = "0xb00 - Pretended Networking Control 1 Register"]
pub ctrl1_pn: CTRL1_PN,
#[doc = "0xb04 - Pretended Networking Control 2 Register"]
pub ctrl2_pn: CTRL2_PN,
#[doc = "0xb08 - Pretended Networking Wake Up Match Register"]
pub wu_mtc: WU_MTC,
#[doc = "0xb0c - Pretended Networking ID Filter 1 Register"]
pub flt_id1: FLT_ID1,
#[doc = "0xb10 - Pretended Networking DLC Filter Register"]
pub flt_dlc: FLT_DLC,
#[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"]
pub pl1_lo: PL1_LO,
#[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"]
pub pl1_hi: PL1_HI,
#[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub flt_id2_idmask: FLT_ID2_IDMASK,
#[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub pl2_plmask_lo: PL2_PLMASK_LO,
#[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub pl2_plmask_hi: PL2_PLMASK_HI,
_reserved7: [u8; 24usize],
#[doc = "0xb40 - Wake Up Message Buffer Register for C/S"]
pub wmb0_cs: WMB0_CS,
#[doc = "0xb44 - Wake Up Message Buffer Register for ID"]
pub wmb0_id: WMB0_ID,
#[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb0_d03: WMB0_D03,
#[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"]
pub wmb0_d47: WMB0_D47,
#[doc = "0xb50 - Wake Up Message Buffer Register for C/S"]
pub wmb1_cs: WMB1_CS,
#[doc = "0xb54 - Wake Up Message Buffer Register for ID"]
pub wmb1_id: WMB1_ID,
#[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb1_d03: WMB1_D03,
#[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"]
pub wmb1_d47: WMB1_D47,
#[doc = "0xb60 - Wake Up Message Buffer Register for C/S"]
pub wmb2_cs: WMB2_CS,
#[doc = "0xb64 - Wake Up Message Buffer Register for ID"]
pub wmb2_id: WMB2_ID,
#[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb2_d03: WMB2_D03,
#[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"]
pub wmb2_d47: WMB2_D47,
#[doc = "0xb70 - Wake Up Message Buffer Register for C/S"]
pub wmb3_cs: WMB3_CS,
#[doc = "0xb74 - Wake Up Message Buffer Register for ID"]
pub wmb3_id: WMB3_ID,
#[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb3_d03: WMB3_D03,
#[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"]
pub wmb3_d47: WMB3_D47,
_reserved8: [u8; 128usize],
#[doc = "0xc00 - CAN FD Control Register"]
pub fdctrl: FDCTRL,
#[doc = "0xc04 - CAN FD Bit Timing Register"]
pub fdcbt: FDCBT,
#[doc = "0xc08 - CAN FD CRC Register"]
pub fdcrc: FDCRC,
}
#[doc = "Module Configuration Register"]
pub struct MCR {
register: VolatileCell<u32>,
}
#[doc = "Module Configuration Register"]
pub mod mcr;
#[doc = "Control 1 register"]
pub struct CTRL1 {
register: VolatileCell<u32>,
}
#[doc = "Control 1 register"]
pub mod ctrl1;
#[doc = "Free Running Timer"]
pub struct TIMER {
register: VolatileCell<u32>,
}
#[doc = "Free Running Timer"]
pub mod timer;
#[doc = "Rx Mailboxes Global Mask Register"]
pub struct RXMGMASK {
register: VolatileCell<u32>,
}
#[doc = "Rx Mailboxes Global Mask Register"]
pub mod rxmgmask;
#[doc = "Rx 14 Mask register"]
pub struct RX14MASK {
register: VolatileCell<u32>,
}
#[doc = "Rx 14 Mask register"]
pub mod rx14mask;
#[doc = "Rx 15 Mask register"]
pub struct RX15MASK {
register: VolatileCell<u32>,
}
#[doc = "Rx 15 Mask register"]
pub mod rx15mask;
#[doc = "Error Counter"]
pub struct ECR {
register: VolatileCell<u32>,
}
#[doc = "Error Counter"]
pub mod ecr;
#[doc = "Error and Status 1 register"]
pub struct ESR1 {
register: VolatileCell<u32>,
}
#[doc = "Error and Status 1 register"]
pub mod esr1;
#[doc = "Interrupt Masks 1 register"]
pub struct IMASK1 {
register: VolatileCell<u32>,
}
#[doc = "Interrupt Masks 1 register"]
pub mod imask1;
#[doc = "Interrupt Flags 1 register"]
pub struct IFLAG1 {
register: VolatileCell<u32>,
}
#[doc = "Interrupt Flags 1 register"]
pub mod iflag1;
#[doc = "Control 2 register"]
pub struct CTRL2 {
register: VolatileCell<u32>,
}
#[doc = "Control 2 register"]
pub mod ctrl2;
#[doc = "Error and Status 2 register"]
pub struct ESR2 {
register: VolatileCell<u32>,
}
#[doc = "Error and Status 2 register"]
pub mod esr2;
#[doc = "CRC Register"]
pub struct CRCR {
register: VolatileCell<u32>,
}
#[doc = "CRC Register"]
pub mod crcr;
#[doc = "Rx FIFO Global Mask register"]
pub struct RXFGMASK {
register: VolatileCell<u32>,
}
#[doc = "Rx FIFO Global Mask register"]
pub mod rxfgmask;
#[doc = "Rx FIFO Information Register"]
pub struct RXFIR {
register: VolatileCell<u32>,
}
#[doc = "Rx FIFO Information Register"]
pub mod rxfir;
#[doc = "CAN Bit Timing Register"]
pub struct CBT {
register: VolatileCell<u32>,
}
#[doc = "CAN Bit Timing Register"]
pub mod cbt;
#[doc = "Embedded RAM"]
pub struct EMBEDDEDRAM {
register: VolatileCell<u32>,
}
#[doc = "Embedded RAM"]
pub mod embedded_ram;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR0 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr0;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR1 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr1;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR2 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr2;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR3 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr3;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR4 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr4;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR5 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr5;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR6 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr6;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR7 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr7;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR8 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr8;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR9 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr9;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR10 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr10;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR11 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr11;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR12 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr12;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR13 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr13;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR14 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr14;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR15 {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr15;
#[doc = "Pretended Networking Control 1 Register"]
pub struct CTRL1_PN {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Control 1 Register"]
pub mod ctrl1_pn;
#[doc = "Pretended Networking Control 2 Register"]
pub struct CTRL2_PN {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Control 2 Register"]
pub mod ctrl2_pn;
#[doc = "Pretended Networking Wake Up Match Register"]
pub struct WU_MTC {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Wake Up Match Register"]
pub mod wu_mtc;
#[doc = "Pretended Networking ID Filter 1 Register"]
pub struct FLT_ID1 {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking ID Filter 1 Register"]
pub mod flt_id1;
#[doc = "Pretended Networking DLC Filter Register"]
pub struct FLT_DLC {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking DLC Filter Register"]
pub mod flt_dlc;
#[doc = "Pretended Networking Payload Low Filter 1 Register"]
pub struct PL1_LO {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload Low Filter 1 Register"]
pub mod pl1_lo;
#[doc = "Pretended Networking Payload High Filter 1 Register"]
pub struct PL1_HI {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload High Filter 1 Register"]
pub mod pl1_hi;
#[doc = "Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub struct FLT_ID2_IDMASK {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub mod flt_id2_idmask;
#[doc = "Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub struct PL2_PLMASK_LO {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub mod pl2_plmask_lo;
#[doc = "Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub struct PL2_PLMASK_HI {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub mod pl2_plmask_hi;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB0_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb0_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB0_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb0_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB0_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb0_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB0_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb0_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB1_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb1_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB1_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb1_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB1_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb1_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB1_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb1_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB2_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb2_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB2_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb2_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB2_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb2_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB2_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb2_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB3_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb3_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB3_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb3_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB3_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb3_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB3_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb3_d47;
#[doc = "CAN FD Control Register"]
pub struct FDCTRL {
register: VolatileCell<u32>,
}
#[doc = "CAN FD Control Register"]
pub mod fdctrl;
#[doc = "CAN FD Bit Timing Register"]
pub struct FDCBT {
register: VolatileCell<u32>,
}
#[doc = "CAN FD Bit Timing Register"]
pub mod fdcbt;
#[doc = "CAN FD CRC Register"]
pub struct FDCRC {
register: VolatileCell<u32>,
}
#[doc = "CAN FD CRC Register"]
pub mod fdcrc;

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PL1_HI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_7R {
bits: u8,
}
impl DATA_BYTE_7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_6R {
bits: u8,
}
impl DATA_BYTE_6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_5R {
bits: u8,
}
impl DATA_BYTE_5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_4R {
bits: u8,
}
impl DATA_BYTE_4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_7W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_7W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_6W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_6W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_5W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_4W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&self) -> DATA_BYTE_7R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_7R { bits }
}
#[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&self) -> DATA_BYTE_6R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_6R { bits }
}
#[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&self) -> DATA_BYTE_5R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_5R { bits }
}
#[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&self) -> DATA_BYTE_4R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_4R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&mut self) -> _DATA_BYTE_7W {
_DATA_BYTE_7W { w: self }
}
#[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&mut self) -> _DATA_BYTE_6W {
_DATA_BYTE_6W { w: self }
}
#[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&mut self) -> _DATA_BYTE_5W {
_DATA_BYTE_5W { w: self }
}
#[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&mut self) -> _DATA_BYTE_4W {
_DATA_BYTE_4W { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PL1_LO {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_3R {
bits: u8,
}
impl DATA_BYTE_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_2R {
bits: u8,
}
impl DATA_BYTE_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_1R {
bits: u8,
}
impl DATA_BYTE_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_0R {
bits: u8,
}
impl DATA_BYTE_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_0W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3."]
#[inline]
pub fn data_byte_3(&self) -> DATA_BYTE_3R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_3R { bits }
}
#[doc = "Bits 8:15 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2."]
#[inline]
pub fn data_byte_2(&self) -> DATA_BYTE_2R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_2R { bits }
}
#[doc = "Bits 16:23 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1."]
#[inline]
pub fn data_byte_1(&self) -> DATA_BYTE_1R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_1R { bits }
}
#[doc = "Bits 24:31 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0."]
#[inline]
pub fn data_byte_0(&self) -> DATA_BYTE_0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3."]
#[inline]
pub fn data_byte_3(&mut self) -> _DATA_BYTE_3W {
_DATA_BYTE_3W { w: self }
}
#[doc = "Bits 8:15 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2."]
#[inline]
pub fn data_byte_2(&mut self) -> _DATA_BYTE_2W {
_DATA_BYTE_2W { w: self }
}
#[doc = "Bits 16:23 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1."]
#[inline]
pub fn data_byte_1(&mut self) -> _DATA_BYTE_1W {
_DATA_BYTE_1W { w: self }
}
#[doc = "Bits 24:31 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0."]
#[inline]
pub fn data_byte_0(&mut self) -> _DATA_BYTE_0W {
_DATA_BYTE_0W { w: self }
}
}

226
src/can0/pl2_plmask_hi/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PL2_PLMASK_HI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_7R {
bits: u8,
}
impl DATA_BYTE_7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_6R {
bits: u8,
}
impl DATA_BYTE_6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_5R {
bits: u8,
}
impl DATA_BYTE_5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_4R {
bits: u8,
}
impl DATA_BYTE_4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_7W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_7W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_6W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_6W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_5W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_4W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&self) -> DATA_BYTE_7R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_7R { bits }
}
#[doc = "Bits 8:15 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&self) -> DATA_BYTE_6R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_6R { bits }
}
#[doc = "Bits 16:23 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&self) -> DATA_BYTE_5R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_5R { bits }
}
#[doc = "Bits 24:31 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&self) -> DATA_BYTE_4R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_4R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&mut self) -> _DATA_BYTE_7W {
_DATA_BYTE_7W { w: self }
}
#[doc = "Bits 8:15 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&mut self) -> _DATA_BYTE_6W {
_DATA_BYTE_6W { w: self }
}
#[doc = "Bits 16:23 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&mut self) -> _DATA_BYTE_5W {
_DATA_BYTE_5W { w: self }
}
#[doc = "Bits 24:31 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&mut self) -> _DATA_BYTE_4W {
_DATA_BYTE_4W { w: self }
}
}

226
src/can0/pl2_plmask_lo/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PL2_PLMASK_LO {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_3R {
bits: u8,
}
impl DATA_BYTE_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_2R {
bits: u8,
}
impl DATA_BYTE_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_1R {
bits: u8,
}
impl DATA_BYTE_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_0R {
bits: u8,
}
impl DATA_BYTE_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_0W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3."]
#[inline]
pub fn data_byte_3(&self) -> DATA_BYTE_3R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_3R { bits }
}
#[doc = "Bits 8:15 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2."]
#[inline]
pub fn data_byte_2(&self) -> DATA_BYTE_2R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_2R { bits }
}
#[doc = "Bits 16:23 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1."]
#[inline]
pub fn data_byte_1(&self) -> DATA_BYTE_1R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_1R { bits }
}
#[doc = "Bits 24:31 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0."]
#[inline]
pub fn data_byte_0(&self) -> DATA_BYTE_0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3."]
#[inline]
pub fn data_byte_3(&mut self) -> _DATA_BYTE_3W {
_DATA_BYTE_3W { w: self }
}
#[doc = "Bits 8:15 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2."]
#[inline]
pub fn data_byte_2(&mut self) -> _DATA_BYTE_2W {
_DATA_BYTE_2W { w: self }
}
#[doc = "Bits 16:23 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1."]
#[inline]
pub fn data_byte_1(&mut self) -> _DATA_BYTE_1W {
_DATA_BYTE_1W { w: self }
}
#[doc = "Bits 24:31 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0."]
#[inline]
pub fn data_byte_0(&mut self) -> _DATA_BYTE_0W {
_DATA_BYTE_0W { w: self }
}
}

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