Commit Graph

19 Commits

Author SHA1 Message Date
b09333f023 hw: add spi and new vexriscv to foboot
This is the beginning of having SPI.

Also add a new two-stage pipeline.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 11:25:09 +08:00
c7632ae8bd deps: litex: sync with latest version
This pulls in several fixes, including custom vexriscv modules.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-17 17:33:31 +01:00
4aa3861c03 hw: deps: update to first feature-complete valentyusb
This is the first version of `valentyusb` that successfully enumerates
without any errors.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-11 11:52:03 +08:00
5bcd6c44fb deps: update valentyusb to working rev
This revision works, although more tuning needs to be done.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:43:28 +08:00
2d7c7794f5 hw: foboot-bitstream: remove debug pins, use epfifo
Remove the debug pins to let timing close.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:06:37 +08:00
0c6e444789 hw: foboot-bitstream: add -relut and friends to nextpnr
Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:51 +08:00
8aed600cd6 hw: foboot-bitstream: specify additional clock domain constraints
Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:12 +08:00
6638801886 hw: foboot-bitstream: remove clk48_in signal
It's unused.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:04:19 +08:00
8fb6b5977b hw: foboot-bitstream: remove unused clk48 net
We only use the raw and usb48 nets.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:58 +08:00
13360015db Merge branch 'master' of github.com:xobs/foboot 2019-03-08 20:49:13 +08:00
d603113b6f foboot-bitstream: send clk48 through shifter, then through pll
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-08 20:47:42 +08:00
44ee19c8b4 valentyusb: use latest fix for metastable transmissions
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-06 14:06:17 +08:00
f34601df98 hw: lxbuildenv: fix uninitialized repo issue
We would get stuck in a loop.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 22:08:11 +08:00
3df59a866d metastable fix: wip
Trying to figure out what's causing this problem.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 20:28:54 +08:00
73176b65de hw: lxbuildenv: fix detection of .git directory
It was giving an incorrect path, which would cause it to refresh
submodules during every build.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 13:20:54 +08:00
350497924e README: add simple readme file
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:17:20 +08:00
74ec6be245 hw: remove gitignore
It's stored in the root now

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:52 +08:00
1c8634e954 gitmodules: add hw deps
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:36 +08:00
8fe27d9371 Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
git-subtree-dir: hw
git-subtree-mainline: e4af98b4aa
git-subtree-split: d812378c4d
2019-03-05 09:05:50 +08:00