History

Sean Cross b09333f023 hw: add spi and new vexriscv to foboot

This is the beginning of having SPI.

Also add a new two-stage pipeline.

Signed-off-by: Sean Cross <sean@xobs.io>

2019-03-20 11:25:09 +08:00

2019-03-05 09:05:50 +08:00

2019-03-17 17:33:31 +01:00

crc5-test.c

metastable fix: wip

2019-03-05 20:28:54 +08:00

csr-test.py

2019-03-05 09:05:50 +08:00

foboot-bitstream.py

2019-03-20 11:25:09 +08:00

lxbuildenv.py

2019-03-05 22:08:11 +08:00

README.md

2019-03-05 09:17:20 +08:00

vexriscv-2-stage-with-debug.v

2019-03-20 11:25:09 +08:00

Foboot Firmware Component

Usage

To build:

python3 .\foboot-bitstream.py

This will ensure you have the required dependencies, and check out all submodules.

You can run tests by using the unittest command:

python .\lxbuildenv.py -r -m unittest -v valentyusb.usbcore.cpu.epfifo_test.TestPerEndpointFifoInterface