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Sean Cross b09333f023 hw: add spi and new vexriscv to foboot 
This is the beginning of having SPI.

Also add a new two-stage pipeline.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 11:25:09 +08:00
..
bin Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458' 2019-03-05 09:05:50 +08:00
deps deps: litex: sync with latest version 2019-03-17 17:33:31 +01:00
crc5-test.c metastable fix: wip 2019-03-05 20:28:54 +08:00
csr-test.py Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458' 2019-03-05 09:05:50 +08:00
foboot-bitstream.py hw: add spi and new vexriscv to foboot 2019-03-20 11:25:09 +08:00
lxbuildenv.py hw: lxbuildenv: fix uninitialized repo issue 2019-03-05 22:08:11 +08:00
README.md README: add simple readme file 2019-03-05 09:17:20 +08:00
vexriscv-2-stage-with-debug.v hw: add spi and new vexriscv to foboot 2019-03-20 11:25:09 +08:00

README.md

Foboot Firmware Component

Usage

To build:

python3 .\foboot-bitstream.py

This will ensure you have the required dependencies, and check out all submodules.

Tests

You can run tests by using the unittest command:

python .\lxbuildenv.py -r -m unittest -v valentyusb.usbcore.cpu.epfifo_test.TestPerEndpointFifoInterface