History

Sean Cross 8aed600cd6 hw: foboot-bitstream: specify additional clock domain constraints

Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>

2019-03-10 21:05:12 +08:00

bin

Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'

2019-03-05 09:05:50 +08:00

deps

valentyusb: use latest fix for metastable transmissions

2019-03-06 14:06:17 +08:00

crc5-test.c

metastable fix: wip

2019-03-05 20:28:54 +08:00

csr-test.py

Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'

2019-03-05 09:05:50 +08:00

foboot-bitstream.py

hw: foboot-bitstream: specify additional clock domain constraints

2019-03-10 21:05:12 +08:00

lxbuildenv.py

hw: lxbuildenv: fix uninitialized repo issue

2019-03-05 22:08:11 +08:00

README.md

README: add simple readme file

2019-03-05 09:17:20 +08:00

README.md

Foboot Firmware Component

Usage

To build:

python3 .\foboot-bitstream.py

This will ensure you have the required dependencies, and check out all submodules.

Tests

You can run tests by using the unittest command:

python .\lxbuildenv.py -r -m unittest -v valentyusb.usbcore.cpu.epfifo_test.TestPerEndpointFifoInterface