6435aec3db
foboot-bitstream: add hacker revision
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Untested commit -- this should add support for the Hacker version of the
PCB.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-05 18:58:19 +08:00
db65ccc199
hw: document warmboot some more
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Realized that there are 5 images and not 4. With this, everything
works as it should.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-05 17:34:10 +08:00
4c3f0f2402
valentyusb: use experimental shorter pipeline
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This helps to improve timing.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-03 22:11:02 +08:00
1660681d38
hw: add 2-stage-1024-cache
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-03 21:57:53 +08:00
c33d86adb9
foboot-bitstream: fix warmboot and add rgb block
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-02 18:11:58 +08:00
8599ec7007
hw: bitstream: simplify command line argument parsing
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-02 13:03:47 +08:00
0e720d5acc
README: add information about sw and hw and building
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-01 10:10:13 +08:00
2fd01b8303
foboot-bitstream: more help description, add dvt support
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-01 10:09:20 +08:00
6595eb1ef1
valentyusb: increase incoming buffer to 128 bytes
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-28 11:12:32 +08:00
7191c12490
wip: just need to get WARMBOOT working
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-28 11:11:36 +08:00
3d6acaf51e
sw: wip commit -- getting dfu working
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Now that we have SPI and USB both working, we can start to close the
loop and get DFU working.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-25 17:39:06 +08:00
23b9962067
hw: foboot-bitstream: remove pmod debug comments
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 13:12:53 +08:00
fa690d63ed
hw: foboot-bitstream: clean up debug generation
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 13:12:29 +08:00
4f0507fc77
hw: foboot-bitstream: remove "generating firmware" message
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 13:12:08 +08:00
f3d779787b
hw: foboot-bitstream: add reset to usb_48
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This is required to meet timing.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 13:11:45 +08:00
b09333f023
hw: add spi and new vexriscv to foboot
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This is the beginning of having SPI.
Also add a new two-stage pipeline.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 11:25:09 +08:00
c7632ae8bd
deps: litex: sync with latest version
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This pulls in several fixes, including custom vexriscv modules.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-17 17:33:31 +01:00
4aa3861c03
hw: deps: update to first feature-complete valentyusb
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This is the first version of `valentyusb` that successfully enumerates
without any errors.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-11 11:52:03 +08:00
5bcd6c44fb
deps: update valentyusb to working rev
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This revision works, although more tuning needs to be done.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 22:43:28 +08:00
2d7c7794f5
hw: foboot-bitstream: remove debug pins, use epfifo
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Remove the debug pins to let timing close.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:06:37 +08:00
0c6e444789
hw: foboot-bitstream: add -relut and friends to nextpnr
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Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:51 +08:00
8aed600cd6
hw: foboot-bitstream: specify additional clock domain constraints
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Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:12 +08:00
6638801886
hw: foboot-bitstream: remove clk48_in signal
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It's unused.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:04:19 +08:00
8fb6b5977b
hw: foboot-bitstream: remove unused clk48 net
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We only use the raw and usb48 nets.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:58 +08:00
13360015db
Merge branch 'master' of github.com:xobs/foboot
2019-03-08 20:49:13 +08:00
d603113b6f
foboot-bitstream: send clk48 through shifter, then through pll
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-08 20:47:42 +08:00
44ee19c8b4
valentyusb: use latest fix for metastable transmissions
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-06 14:06:17 +08:00
f34601df98
hw: lxbuildenv: fix uninitialized repo issue
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We would get stuck in a loop.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 22:08:11 +08:00
3df59a866d
metastable fix: wip
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Trying to figure out what's causing this problem.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 20:28:54 +08:00
73176b65de
hw: lxbuildenv: fix detection of .git directory
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It was giving an incorrect path, which would cause it to refresh
submodules during every build.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 13:20:54 +08:00
350497924e
README: add simple readme file
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:17:20 +08:00
74ec6be245
hw: remove gitignore
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It's stored in the root now
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:52 +08:00
1c8634e954
gitmodules: add hw deps
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 09:16:36 +08:00
8fe27d9371
Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
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git-subtree-dir: hw
git-subtree-mainline: e4af98b4aad812378c4d
2019-03-05 09:05:50 +08:00
