foboot-bitstream: more help description, add dvt support
Signed-off-by: Sean Cross <sean@xobs.io>
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@ -34,7 +34,7 @@ from lxsocsupport import up5kspram, spi_flash
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import argparse
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_io = [
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_io_evt = [
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("serial", 0,
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Subsignal("rx", Pins("21")),
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Subsignal("tx", Pins("13"), Misc("PULLUP")),
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@ -73,11 +73,38 @@ _io = [
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),
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("clk48", 0, Pins("44"), IOStandard("LVCMOS33"))
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]
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_io_dvt = [
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("serial", 0,
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Subsignal("rx", Pins("C3")),
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Subsignal("tx", Pins("B3"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("A1")),
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Subsignal("d_n", Pins("A2")),
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Subsignal("pullup", Pins("A4")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("E1"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("F1"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("F2"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("B1"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("E1 F1 F2 B1"), IOStandard("LVCMOS33")),
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),
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("clk48", 0, Pins("F4"), IOStandard("LVCMOS33"))
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]
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_connectors = []
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class _CRG(Module):
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def __init__(self, platform, use_pll=False):
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def __init__(self, platform, use_pll):
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if use_pll:
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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@ -250,28 +277,30 @@ class Platform(LatticePlatform):
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gateware_size = 0x20000
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def __init__(self, toolchain="icestorm"):
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
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def __init__(self, revision=None, toolchain="icestorm"):
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if revision == "evt":
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io_evt, _connectors, toolchain="icestorm")
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elif revision == "dvt":
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LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io_dvt, _connectors, toolchain="icestorm")
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else:
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raise ValueError("Unrecognized reivsion: {}. Known values: evt, dvt".format(revision))
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def create_programmer(self):
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raise ValueError("programming is not supported")
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# def do_finalize(self, fragment):
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# LatticePlatform.do_finalize(self, fragment)
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class SBWarmBoot(Module, AutoCSR):
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def __init__(self):
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self.ctrl = CSRStorage(size=8)
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do_reset = Signal()
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self.comb += [
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# "Reset Key" is 0xac
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do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
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& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
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]
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self.ctrl = CSRStorage(size=3)
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# do_reset = Signal()
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# self.comb += [
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# # "Reset Key" is 0xac
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# do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
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# & self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
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# ]
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self.specials += Instance("SB_WARMBOOT",
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i_BOOT=do_reset,
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i_S0 = self.ctrl.storage[0],
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i_S1 = self.ctrl.storage[1]
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i_S0 = self.ctrl.storage[0],
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i_S1 = self.ctrl.storage[1],
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i_BOOT = self.ctrl.storage[2] & self.ctrl.re,
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)
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@ -396,16 +425,18 @@ class BaseSoC(SoCCore):
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self.integrated_sram_size = 0
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clk_freq = int(12e6)
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self.submodules.crg = _CRG(platform, use_pll)
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self.submodules.crg = _CRG(platform, use_pll=use_pll)
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SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs)
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if debug:
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from litex.soc.cores.uart import UARTWishboneBridge
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self.cpu.use_external_variant("2-stage-1024-cache-debug.v")
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from litex.soc.cores.uart import UARTWishboneBridge
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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else:
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self.cpu.use_external_variant("2-stage-1024-cache.v")
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# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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# free up scarce block RAM.
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@ -510,15 +541,15 @@ def make_multiboot_header(filename, boot_offsets=[128]):
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output.write(bytes([0]))
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def main():
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# make_multiboot_header("multiboot", [128, 262144, 524288, 524288*2])
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# import sys
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# sys.exit(0)
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platform = Platform()
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parser = argparse.ArgumentParser(
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description="Build Fomu Main Gateware")
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parser.add_argument(
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"--boot-source", choices=["spi", "rand", "bios"], default="rand"
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"--boot-source", choices=["spi", "rand", "bios"], default="rand",
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help="where to have the CPU obtain its executable code from"
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)
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parser.add_argument(
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"--revision", choices=["dvt", "evt"], required=True,
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help="build foboot for a particular hardware revision"
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)
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parser.add_argument(
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"--bios", help="use specified file as a BIOS, rather than building one"
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@ -575,9 +606,10 @@ def main():
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cpu_variant = "debug"
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debug = True
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platform = Platform(revision=args.revision)
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soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant,
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debug=debug, boot_source=boot_source,
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bios_file=bios_file, use_pll=not args.no_pll)
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bios_file=bios_file, use_pll=args.no_pll)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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vns = builder.build()
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soc.do_exit(vns)
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