Sean Cross 9e6faf4456 sch: mark VCCPLL regulator as DNP, use filter circuit ... The VCCPLL line is extraordinarily sensitive to voltage rise times, and appears to cause the FPGA to go into latchup very very easily. As a result, the VCCPLL regulator burns all 250 mA of its budget constantly, as the FPGA shunts VCCPLL to GND. This would be ideal during an ESD event, but not ideal during normal operations. Indicate the VCCPLL Regulator approach is DNP, and that the VCCPLL Filter Network is preferred. Mostly because the regulator doesn't work at all. Signed-off-by: Sean Cross <sean@xobs.io>		2018-11-23 15:56:35 +08:00
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pcb	sch: mark VCCPLL regulator as DNP, use filter circuit	2018-11-23 15:56:35 +08:00
releases/evt1	hardware: misc kicad-related commits	2018-11-10 12:25:48 +08:00
CHANGES.md	hardware: add some misc notes about evt	2018-11-20 22:53:13 +08:00
EVT1a.md	hardware: evt1a: work-in-progress charactarization	2018-11-23 11:40:31 +08:00