hardware: add some misc notes about evt

Signed-off-by: Sean Cross <sean@xobs.io>

hardware/CHANGES.md

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+## EVT1a -> EVT1b Changes
+
+ECO001: XTAL pin 1 is not NC
+
+Description: The first pin of most XTALs needs to be floating (NC).  This is in contrast to the MEMS oscillator which requires pin 1 be connected to pin 4.
+
+Action: Modify the schematic so that pin 1 of the crystal oscillator is NC.
+
+---
+
+ECO002: SPI flash footprint is incorrectly sized
+
+Description: The footprint for the SPI flash is sized according to the lead lengths, but is not wide enough.  As a result, this part cannot be assembled.
+
+Action: Increase the width of the pads in the footprint.
+
+---
+
+ECO003: USB footprint is slightly too narrow
+
+Description: The USB footprint is slightly too narrow.  As a result, it slides back and forth in the USB slot.
+
+Action: Widen up the USB pad by 0.1mm
+
+---
+
+ECO004: USB board edge has too much clearance.
+
+Description: Because of the clearance on the edge of the PCB, it can rock back and forth.  This, in combination with ECO003, means the PCB does not sit firmly in a USB slot.
+
+Action: Extend the edge of the PCB towards the USB slot by 0.2mm.
+
+---
+
+ECO005: XTAL footprint is backwards
+
+Description: The XTAL footprint has pin 1 in the upper-right-corner.  However, the picture in the datasheet is mirrored, so pin 1 should actually be in the lower-left corner with numbering proceeding anti-clockwise (as opposed to the picture, which has pin 1 in the upper-right corner with numbering proceeding clockwise).
+
+Action: Fix the footprint and redo wiring.

hardware/EVT1a.md

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+Subsystem | Quick Test | In-Depth Test
+----------+------------+--------------+
+1.2V Reg     | Pass
+2.5V Reg     | Pass
+3.3V Reg     | Pass
+VCCPLL Reg   | Pass
+Xtal Oscillator | FAIL (Wrong footprint)
+SPI Flash       | FAIL (Wrong footprint)
+USB Pullup
+USB Pad Polarity
+Captouch Pads
+Capacitance
+Reset Button
+User buttons
+
+For Raspberry Pi as clock source, use PLLD with I=28,F=1675 or PLLC with I=56,F=3351.
+
+GPIO pinouts:
+
+17 (11): C_DONE
+27 (13): C_RESET
+24 (18): SPI_IO2/WP
+-- (19): SPI_MOSI
+-- (21): SPI_MISO
+25 (22): SPI_IO3/HOLD
+(23): SPI_CLK
+(24): SPI_CS
+
+# Put the SPI flash in "HOLD" mode, so it ignores us.
+gpio -g mode 25 out
+gpio -g write 25 0
+
+# Enable SPI flash "WP" mode
+gpio -g mode 24 out
+gpio -g write 24 1
+
+# Put FPGA into reset
+gpio -g mode 27 out
+gpio -g write 27 0
+
+# Monitor the C_DONE pin
+gpio -g mode 17 in
+gpio -g read 17 # Goes 1 when programming is done