Commit Graph

120 Commits

Author SHA1 Message Date
d5b7701bc7 hardware: releases: re-release dvt1a
This adds a keepout area around the ground plane underneath the IC, to
try and prevent it from migrating during reflow.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:52:35 +08:00
1af0d1c06e hardware: pcb: increase under-fpga keepout area size
Increase the size of the keepout area in order to remove some extra
copper that was appearing around one of the ground pads.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:51:40 +08:00
4da7854799 dvt1a: tag release
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:48:26 +08:00
a3621766c5 hardware: cache: commit kicad's line-ending changes
I really don't know why it keeps doing this...

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:47:27 +08:00
5d90502947 pcb: fix up assembly notes layers
Resize the assembly note layers so that it's usable (in theory).

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:46:44 +08:00
7a4497b0c9 hardware: pcb: connect usb esd diodes inline first
Move the USB ESD diodes so they connect first.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 17:58:54 +08:00
3e72bd1086 hardware: sch: add column for "DNP"
After discussing with one factory, this is their preferred method of
indicating a part is "Do-Not-Populate".

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 15:19:17 +08:00
28aae5e4a8 hardware: footprints: 8-uson: redo footprint from pdf
Redo the footprint for the SPI flash chip from a recommended footprint
provided by one of the vendors.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 15:18:25 +08:00
64020199e8 hardware: cache: commit kicad's line-ending change
Why does it do this?  No one can say.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:45:25 +08:00
5a074ea4e1 hardware: pcb: finish routing with esd diodes
Finish routing the PCB with the esd diodes in place.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:44:49 +08:00
6344d45c1b hardware: sch: define spi part numbers for dvt board
This part is smaller.  Define both the part number and an alternative
part number.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:44:12 +08:00
8b7adafd9d hardware: pcb: finish first draft of esd routing
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:52 +08:00
42b7a235c6 reference: add esd, and security pdf
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:43 +08:00
f7cd16496c hardware: footprint: add footprint for esd diode
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:17 +08:00
dcc33ac81b hardware: pcb: partial routing of new esd diodes
There's still a bit more to go...

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:49:25 +08:00
9ec87cb483 hardware: sch: add esd diodes
These will be placed on the USB lines as well as the captouch lines.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:49:05 +08:00
d0bd902112 hardware: lib: update cache file
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:48:37 +08:00
9abd177b38 hardware: sch: remove "-rescue" and "-tomu-fpga"
Somehow, KiCad added these strings to the parts libraries, which
resulted in referencing a file that didn't exist.

Remove them.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 10:25:05 +08:00
cc19668309 hardware: pcb: reduce the number of capacitors
This is an initial commit removing the excess capacitors.

We will eventually add ESD protection ICs in the space that has been
freed up.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:24:55 +08:00
a98cd5727e hardware: sch: remove excess decoupling caps
We probably don't need 10nF, because this won't do any very-high-speed
(>100 MHz) operations.  We can think about putting them back in later,
space permitting.

Additionally, remove an extra bank of caps for one of the IO pads.
We'll double-up on capacitors there, which should be alright given the
close proximity and the fact that the only thing on that IO bank is
captouch.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:23:05 +08:00
23106ab57d hardware: pcb: reduce ground fill, loosen up routing
Reduce the ground fill under the IC, to prevent it from sliding around.
This gives less copper, but it should be fine for the currents we're
drawing.

Loosen up the routing of the 5V plane, which involves moving some
components around.  This increases the amount of copper that goes to the
various regulators.

Finally, reorder the caps so that the larger ones are further from the
IC.  This is done because they have a slower response time, and so can
be further away.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:14:24 +08:00
22aa8c8aca hardware: pcb: hide usb footprint silk
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:49:14 +08:00
b151d005f2 hardware: pcb: update PCB to use local copies of 3D files
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:46:54 +08:00
06be1fdb35 hardware: footprint: add models for regulator, BGA
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:46:23 +08:00
ccb5f49d19 reference: dvt1: re-render images
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 18:23:35 +08:00
571646f5c1 hardware: pcb: more tuning of traces and pours
Open up some more pours, and move some vias to make pours larger.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 18:21:39 +08:00
bdf8b8558d hardware: pcb: remove text leftover from EFM32
This was used to select which ARM MCU to use.  It is no longer relevant.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 16:45:06 +08:00
77d47db980 hardware: sch: add some spice models to passives
Identify passives and implement the various spice models.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-08 21:43:32 +08:00
294ecfe782 hardware: pcb: add more copper to 1.2V line
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-08 19:11:24 +08:00
8050e796ab hardware: pcb: clean up traces, widen up pours
Rework the traces somewhat to widen up the pours and remove some of the
bifurcation that's going on.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-08 19:07:56 +08:00
9813a20efb reference: add screenshot and schematic for dvt1
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:47:57 +08:00
c2566ea16d hardware: pcb: add version and update silkscreen
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:47:16 +08:00
e87a882f84 hardware: footprints: add local copies of 3D models
Because these files keep moving, add local copies of all of these files.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:39:38 +08:00
66584765ff hardware: footprints: add new SON50
This has more copper, which might make hand-soldering easier.  Though
this PCB isn't going to be hand-soldered.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:21:21 +08:00
db938e5557 hardware: pcb: first full routing of pcb
This passes DRC and has no unconnected nets.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:20:53 +08:00
d2b73fbc5e hardware: schematic: rewire fpga as necessary for routing
FPGAs are great, because if there's an alternate method that's easier to
route -- go for it!  This modifies some of the connections to ease
routing constraints.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-07 21:20:05 +08:00
cdcbe4dece hardware: footprints: add new footprints
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-06 19:45:14 +08:00
ba64beee64 reference: add gd25q16c SPI ROM
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-06 19:44:50 +08:00
140717e3c6 hardware: pcb: first unrouted layout of dvt1
This is just a placement test, to see if it can be laid out.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-06 19:44:12 +08:00
596c686249 hardware: sch: complete schematic layout of DVT1
This is the first cut of a schematic layout of DVT1.

It includes all the decoupling caps still.  We'll need to see if they're
kept around.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-06 19:43:31 +08:00
a6fa6cf3e9 hardware: footprints: cleanup ice40 footprints
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-06 19:42:01 +08:00
bbc18d2a90 hardware: sch: work-in-progress to go from QFN to WLCSP
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-05 13:03:36 +08:00
f9205b7027 hardware: pcb: replace pcb with usb-tomu version
We'll use this as a starting point, to maintain the same shape and size.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-05 13:03:07 +08:00
d518357f76 hardware: footprints: add testpoint footprint
This is from Tomu, so it's verified to be the correct size.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-05 13:02:28 +08:00
75c15fdb98 hardware: footprints: initial commit of WLCSP models
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-05 08:45:58 +08:00
34f74fbf51 hardware: sch: first draft of dvt1
This removes much of the support debugging stuff from evt1.  Still to
do:

- Assign footprints
- Figure out which PU resistor to include (if any)
- Figure out if we need to keep the USB buffering
- Remove extra decoupling caps

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-04 22:00:23 +08:00
0bda71a0c8 hardware: footprints: add power regulator footprint
Add a footprint from KiCad for the power regulator we'll use.

It refers to a 3D file that doesn't exist, so we'll need to find that
first.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-04 21:57:55 +08:00
9639d75a11 releases: remove evt1 and evt2, and rename evt3 -> evt1
evt1 and evt2 were never produced.  They also would never have worked,
because the USB connector was drawn mirrored.

Remove these and replace them with a single `evt1` that was actually
produced.

This reflects the fact that the `evt1` boards actually say "EVT1" on
them.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-04 21:00:16 +08:00
49d2924c26 hardware: pcb: redo timestamps, because kicad
kicad decided to redo all the timestamps.  There are no other changes to
this commit.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-03 11:50:44 +08:00
57f68c4a26 release: evt3: add bom files
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-03 10:38:20 +08:00