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df5889e4dd
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img: add evt1-rework
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-07-29 22:33:09 +08:00 |
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a60cc8ef40
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add note about software/crystal
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-23 08:59:02 -07:00 |
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36a11f69ea
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index: add page on spi id
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-22 22:43:33 -07:00 |
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700a9b86d2
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minor rewording of riscv-section
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-22 17:46:19 -07:00 |
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86f806f80b
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footer: add software link
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-21 10:05:44 -07:00 |
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a9e9643143
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add opening graphic
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-21 09:53:37 -07:00 |
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edc98a5289
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nearly feature-complete
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-20 11:24:00 -07:00 |
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ddee9849ca
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feature-complete-ish
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-19 19:36:17 -07:00 |
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c84d5d9e50
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index: finish up to the end of risc-v
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-18 20:04:33 -07:00 |
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03aab024d6
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verilog: use a wider example and include an img
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-18 16:06:09 -07:00 |
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9901b83844
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add initial python section
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-18 15:56:54 -07:00 |
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4f50750b32
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index: add dfu-util section
Rough
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-18 10:50:48 -07:00 |
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47565196c6
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index: more rough outline
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-18 10:11:09 -07:00 |
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e1424c4534
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starting to fill in talk
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-16 10:48:01 -07:00 |
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81fe77c179
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outline: add more stuff
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-16 10:15:06 -07:00 |
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4beca5ea3f
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initial commit
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-06-16 08:39:06 -07:00 |
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