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verilog: use a wider example and include an img

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-06-18 16:06:09 -07:00
parent 9901b83844
commit 03aab024d6
2 changed files with 12 additions and 11 deletions
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index.html
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@ -155,15 +155,16 @@
<section>
<h2>What is an FPGA?</h2>
<pre><code class="verilog" data-trim>
module DFF (output reg Q, input C, D, R);
always @(posedge C)
if (~R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
endmodule
</code></pre>
module example (output reg [0:5] Q, input C);
reg [0:8] counter;
always @(posedge C)
begin
counter <= counter + 1'b1;
Q = counter[7] ^ counter[5] | counter<<2;
end
endmodule
</code></pre>
<img class="fragment" data-src="img/verilog-synthesis.png" alt="Verilog Synthesis">
</section>
<section>
@ -172,10 +173,10 @@
<li>5280 4-input LUTs (LC)</li>
<li>16 kilobytes BRAM</li>
<li class="fragment highlight-blue">128 kilobytes "SPRAM"</li>
<li>Current-limited 3-channel LED</li>
<li>Current-limited 3-channel LED driver</li>
<li>2x I2C and 2x SPI</li>
<li>8 16-bit DSP units</li>
<li>Warmboot capability</li>
<li class="fragment highlight-blue">Warmboot capability</li>
</ol>
</section>