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feature-complete-ish 

Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross 2019-06-19 19:36:17 -07:00
parent c84d5d9e50
commit ddee9849ca
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* League theme for reveal.js.
*
* This was the default theme pre-3.0.0.
*
* Copyright (C) 2011-2012 Hakim El Hattab, http://hakim.se
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<meta name="viewport" content="width=device-width, initial-scale=1.0, maximum-scale=1.0, user-scalable=no">
<link rel="stylesheet" href="css/reveal.css">
<link rel="stylesheet" href="css/theme/solarized.css" id="theme">
<link rel="stylesheet" href="css/theme/teardown19.css" id="theme">
<!-- Theme used for syntax highlighting of code -->
<link rel="stylesheet" href="lib/css/zenburn.css">
@ -106,9 +106,9 @@
<p>
Fomu aims to be accessable on three levels:
<ol>
<li>Python / Interpreted</li>
<li>RISC-V</li>
<li>Verilog / FPGA</li>
<li>Python / Interpreter</li>
<li>RISC-V / C</li>
<li>FPGA / HDL</li>
</ol>
</p>
</section>
@ -118,8 +118,7 @@
<ol>
<li>What do I need to get started?</li>
<li>What is an FPGA, and what is Fomu?</li>
<li>What makes Fomu special?</li>
<li>What can I do with Fomu?</li>
<li>Working with Fomu using Python, RISC-V, and HDL</li>
</ol>
</section>
@ -150,7 +149,127 @@
FPGAs are measured in resources called LUTs or LCs.
</p>
-->
</section>
</section>
<section>
<h2>What is an FPGA?</h2>
<table style="transform: scale(.80) translate(-15%)">
<tr>
<th></th>
<th>0</th>
<th>1</th>
<th>2</th>
<th>3</th>
<th>4</th>
<th>5</th>
<th>6</th>
<th>7</th>
<th>8</th>
<th>9</th>
<th>10</th>
<th>11</th>
<th>12</th>
<th>13</th>
<th>14</th>
<th>15</th>
</tr>
<tr>
<td>IO0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>IO1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>IO2</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>IO3</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>O</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
<td>?</td>
</tr>
</table>
</section>
<section>
<h2>What is an FPGA?</h2>
@ -177,6 +296,7 @@
<li>2x I2C and 2x SPI</li>
<li>8 16-bit DSP units</li>
<li class="fragment highlight-blue">Warmboot capability</li>
<li class="fragment highlight-blue">Open toolchain</li>
</ol>
</section>
@ -184,7 +304,7 @@
<h2>What is Fomu?</h2>
<ul>
<li>ICE40UP5K</li>
<li>2MB flash memory</li>
<li>2MB QSPI flash memory</li>
<li>Four edge-plated pads</li>
<li>ESD protection</li>
<li>USB implemented in HDL</li>
@ -198,6 +318,11 @@
</section>
<section>
<h2>Fomu Block Design Diagram</h2>
<img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram">
</section>
<section>
<h2>What is this PCB?</h2>
<img data-src="img/tomu-fpga-evt-1-small.jpg" alt="Fomu EVT1">
<h3>Fomu EVT1</h3>
@ -234,11 +359,6 @@
</ul>
</section>
<section>
<h2>Fomu Block Design Diagram</h2>
<img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram">
</section>
<section>
<h2>Fomu SPI Flash Layout</h2>
<img data-src="img/fomu-memory-layout.png" alt="Fomu memory layout">
@ -255,10 +375,23 @@
<section>
<section>
<h2>Working with Fomu</h2>
</section>
</section>
<section>
<h2>FAT Bootloader</h2>
<ul>
<li>Presents itself as a USB disk</li>
<li>Drag and drop files to program</li>
<li>Multiple interpreter support</li>
</ul>
<div>
<img data-src="img/under-construction.gif" class="fragment">
</div>
</section>
<section>
<h2>"fail safe" bootloader</h2>
Using dfu
Device Firmware Update - <strong>DFU</strong>
</section>
<section>
<h2>Updating Fomu</h2>
@ -301,7 +434,7 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
<h2>Connecting via serial</h2>
<pre class="fragment"><code>screen /dev/cu.usbserial*</code></pre>
<pre class="fragment"><code>screen /dev/ttyACM*</code></pre>
<pre class="fragment"><code>Teraterm</code></pre>
<pre class="fragment"><code>Tera Term</code></pre>
<pre class="fragment"><code>MicroPython v1.10-296-g0a5a77a on 2019-06-18; fomu with vexriscv
>>></code></pre>
</section>
@ -322,18 +455,21 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
<pre class="fragment"><code class="python" data-trim>>>> rgb.write_raw(0b0001, 255)
>>> rgb.write_raw(0b1010, 14)
>>> rgb.write_raw(0b1011, 1)
>>>
</code></pre>
>>> </code></pre>
</section>
<section>
<h2>Future Work</h2>
CircuitPython, etc.
<ul>
<li>CircuitPython</li>
<li>eLua</li>
<li>Espurino?</li>
</ul>
</section>
</section>
<section>
<section>
<h2>RISC-V code</h2>
<h2>RISC-V</h2>
</section>
<section>
@ -346,17 +482,33 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
<img data-src="img/wishbone-usb-debug-bridge.png" alt="Wishbone bridge">
</section>
<section>
<h2>CPU is Optional</h2>
<ul>
<li>Multiple CPUs available</li>
<li>
<ul>
<li>VexRiscv</li>
<li>picorv32</li>
<li>lm32</li>
<li>...</li>
</ul>
</li>
<li>Also works just fine with no CPU</li>
</ul>
</section>
<section>
<h2>CSR Access</h2>
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000L
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MAJOR_SIZE 1
#define CSR_VERSION_MINOR_ADDR 0xe0007004L
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_MINOR_SIZE 1
#define CSR_VERSION_REVISION_ADDR 0xe0007008L
#define CSR_VERSION_REVISION_ADDR 0xe0007008
#define CSR_VERSION_REVISION_SIZE 1
#define CSR_VERSION_GITREV_ADDR 0xe000700cL
#define CSR_VERSION_GITREV_ADDR 0xe000700c
#define CSR_VERSION_GITREV_SIZE 4
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
#define CSR_VERSION_GITEXTRA_SIZE 2
</code></pre>
Excerpt from <code>csr.h</code>
@ -383,7 +535,35 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
<section>
<h2>Writing RISC-V Code</h2>
<pre><code>$ make
CC ./src/main.c main.o
CC ./src/rgb.c rgb.o
CC ./src/time.c time.o
AS ./src/crt0-vexriscv.S crt0-vexriscv.o
LD riscv-blink.elf
OBJCOPY riscv-blink.bin
IHEX riscv-blink.ihex
$ </code></pre>
</section>
<section>
<h2>Modifying RISC-V Code</h2>
<pre><code class="diff">--- a/riscv-blink/src/main.c
+++ b/riscv-blink/src/main.c
@@ -38,6 +38,7 @@ void isr(void) {
void main(void) {
rgb_init();
irq_setie(0);
+ rgb_write((100000/64000)-1, LEDDBR);
int i = 0;
while (1) {
i++;</code></pre>
</section>
<section>
<h2>Other RISC-V Programs</h2>
riscv-usb-cdcacm: echo characters back after adding 1
</section>
</section>
<section>
@ -392,18 +572,85 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
</section>
<section>
<h2>Yosys and NextPNR</h2>
<h2>Yosys and NextPNR</h2>
<ul>
<li>Timing Driven!</li>
</ul>
<pre><code>Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)</code></pre>
</section>
<section>
<h2>Blinking an LED</h2>
<h2>Blinking an LED</h2>
<pre><code>$ make FOMU_REV=evt
...
20 warnings, 0 errors
PACK blink.bin
Built 'blink' for Fomu evt1
$ dfu-util -D blink.bin</code></pre>
</section>
<section>
<h2>LiteX and MiGen</h2>
<h2>LiteX and MiGen</h2>
<ol>
<li>Define hardware in Python</li>
<li>Evaluate Python to produce netlist</li>
<li>Synthesize netlist to FPGA</li>
</ol>
</section>
<section>
<section>
<h2>lxbuildenv.py</h2>
<ol>
<li>Python environment using native interpreter</li>
<li>Very stable, good for hardware projects</li>
<li>Should work with system Python</li>
<li>Runs on Linux, Windows, Raspberry Pi</li>
</ol>
</section>
<section>
<h2>Why do we need a CPU?</h2>
<img data-src="img/litex-design.png" alt="LiteX Design">
</section>
<section>
<h2>What if we remove the CPU?</h2>
<ul>
<li>Workshop project has no CPU</li>
<li>DummyUsb module automatically enumerates</li>
<li>Wishbone Debug Bridge still accessible</li>
</ul>
</section>
<section>
<h2>Build Workshop Module</h2>
<pre><code>$ python3 workshop.py --placer heap
...
5 warnings, 0 errors
$ </code></pre>
</section>
<section>
<h2>Load onto Fomu</h2>
<pre><code>$ dfu-util -D build/gateware/top.bin
Download [=========================] 100% 104090 bytes
Download done.
$ </code></pre>
</section>
<section>
<h2>Write a value to RAM</h2>
<pre><code>$ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 0baf801e
$ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
$ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 12345678
$ </code></pre>
</section>
<section>
<h2>VexRiscv</h2>
</section>
</section>