messy commit

Signed-off-by: Sean Cross <sean@xobs.io>

memtest/-p

@@ -0,0 +1,28 @@
+
+ /----------------------------------------------------------------------------\
+ |                                                                            |
+ |  yosys -- Yosys Open SYnthesis Suite                                       |
+ |                                                                            |
+ |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |
+ |                                                                            |
+ |  Permission to use, copy, modify, and/or distribute this software for any  |
+ |  purpose with or without fee is hereby granted, provided that the above    |
+ |  copyright notice and this permission notice appear in all copies.         |
+ |                                                                            |
+ |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
+ |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
+ |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
+ |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
+ |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
+ |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
+ |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
+ |                                                                            |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
+
+
+-- Parsing `synth_ice40 -top memtest -json .build/memtest.json' using frontend `json' --
+
+1. Executing JSON frontend.
+ERROR: Can't open input file `synth_ice40 -top memtest -json .build/memtest.json' for reading: No such file or directory

memtest/Makefile

@@ -0,0 +1,71 @@
+PACKAGE   ?= $(notdir $(realpath .))
+TOP       ?= $(PACKAGE)
+
+GIT_VERSION := $(shell git describe --tags)
+
+# Default programs
+NEXTPNR   ?= nextpnr-ice40
+YOSYS     ?= yosys -q -l top.rpt
+ICEPACK   ?= icepack
+
+PCF_PATH ?= .
+
+# Add Windows and Unix support
+RM         = rm -rf
+COPY       = cp -a
+PATH_SEP   = /
+ifeq ($(OS),Windows_NT)
+COPY       = copy
+RM         = del
+PATH_SEP   = \\
+endif
+
+FOMU_REV  ?= evt3
+ifeq ($(FOMU_REV),evt3)
+PCF       ?= $(PCF_PATH)/fomu-evt3.pcf
+PKG       ?= sg48
+PNRFLAGS  ?= --up5k --package $(PKG)
+else
+ifeq ($(FOMU_REV),evt2)
+PCF       ?= $(PCF_PATH)/fomu-evt2.pcf
+PKG       ?= sg48
+PNRFLAGS  ?= --up5k --package $(PKG)
+else
+$(error Unrecognized FOMU_REV value. must be "evt2" or "evt3")
+endif
+endif
+
+BUILD_DIR  = .build
+VSOURCES   = $(wildcard *.v)
+QUIET      = @
+
+ALL        = all
+TARGET     = $(PACKAGE).bin
+CLEAN      = clean
+
+$(ALL): $(TARGET)
+
+$(BUILD_DIR)/$(PACKAGE).json: $(VSOURCES) | $(BUILD_DIR)
+	$(QUIET) echo " SYNTH    $@"
+	$(QUIET) $(YOSYS) -p 'synth_ice40 -top $(TOP) -json $@' $(PACKAGE).v
+
+$(BUILD_DIR)/$(PACKAGE).asc: $(BUILD_DIR)/$(PACKAGE).json $(PCF)
+	$(QUIET) echo " PNR      $@"
+	$(QUIET) $(NEXTPNR) $(PNRFLAGS) --json $(BUILD_DIR)/$(PACKAGE).json --pcf $(PCF) --asc $@
+
+$(TARGET): $(BUILD_DIR)/$(PACKAGE).asc
+	$(QUIET) echo " PACK     $@"
+	$(QUIET) $(ICEPACK) $(BUILD_DIR)/$(PACKAGE).asc $@
+
+$(BUILD_DIR):
+	$(QUIET) mkdir $(BUILD_DIR)
+
+.PHONY: clean
+
+clean:
+	$(QUIET) echo "  RM      $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.json))"
+	-$(QUIET) $(RM) $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.json))
+	$(QUIET) echo "  RM      $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.asc))"
+	-$(QUIET) $(RM) $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.asc))
+	$(QUIET) echo "  RM      $(TARGET) $(PACKAGE).bin"
+	-$(QUIET) $(RM) $(TARGET) $(PACKAGE).bin

memtest/fomu-evt3.pcf

@@ -0,0 +1,41 @@
+set_io led_r 39
+set_io led_b 40
+set_io led_g 41
+set_io pmod_1 28
+set_io pmod_2 27
+set_io pmod_3 26
+set_io pmod_4 23
+set_io pmoda_1 28
+set_io pmoda_2 27
+set_io pmoda_3 26
+set_io pmoda_4 23
+set_io clki_alt 20
+set_io clki 44
+set_io user_1 48
+set_io user_2 47
+set_io user_3 46
+set_io user_4 45
+set_io user_5 42
+set_io user_6 38
+set_io pmodb_1 48
+set_io pmodb_2 47
+set_io pmodb_3 46
+set_io pmodb_4 45
+set_io spi_mosi 14
+set_io spi_miso 17
+set_io spi_clk 15
+set_io spi_io2 18
+set_io spi_io3 19
+set_io spi_cs 16
+set_io uart_tx 21
+set_io uart_rx 13
+set_io usb_dn 37
+set_io usb_dp 34
+set_io usb_dp_pu 35
+set_io usb_dn_pu 36
+set_io dbg_1 20
+set_io dbg_2 12
+set_io dbg_3 11
+set_io dbg_4 25
+set_io dbg_5 10
+set_io dbg_6 9

memtest/memtest.v

@@ -0,0 +1,67 @@
+module memtest (
+    output led_r,
+    output led_g,
+    output led_b,
+    output pmod_1,
+    output pmod_2,
+    output pmod_3,
+    output pmod_4,
+    input user_5,
+    input user_6,
+    input clki
+);
+
+    reg [31:0] mem[0:2047];
+    reg [10:0] memadr;
+    assign random_rom_dat_r = mem[memadr];
+
+    wire clkosc;
+    SB_GB clk_gb (
+        .USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
+        .GLOBAL_BUFFER_OUTPUT(clkosc)
+    );
+    assign clk = clkosc;
+
+    initial begin
+        $readmemh("empty.init", mem);
+    end
+
+    always @(posedge clk) begin
+        memadr <= memadr + 1;
+        led_r <= 
+            mem[memadr][0] ^
+            mem[memadr][1] ^
+            mem[memadr][2] ^
+            mem[memadr][3] ^
+            mem[memadr][4] ^
+            mem[memadr][5] ^
+            mem[memadr][6] ^
+            mem[memadr][7] ^
+            mem[memadr][8] ^
+            mem[memadr][9] ^
+            mem[memadr][10] ^
+            mem[memadr][11] ^
+            mem[memadr][12] ^
+            mem[memadr][13] ^
+            mem[memadr][14] ^
+            mem[memadr][15] ^
+            mem[memadr][16] ^
+            mem[memadr][17] ^
+            mem[memadr][18] ^
+            mem[memadr][19] ^
+            mem[memadr][20] ^
+            mem[memadr][21] ^
+            mem[memadr][22] ^
+            mem[memadr][23] ^
+            mem[memadr][24] ^
+            mem[memadr][25] ^
+            mem[memadr][26] ^
+            mem[memadr][27] ^
+            mem[memadr][28] ^
+            mem[memadr][29] ^
+            mem[memadr][30] ^
+            mem[memadr][31];
+    end
+
+
+endmodule