1729 lines
176 KiB
Plaintext
1729 lines
176 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
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-- Parsing `memtest.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `memtest.v' to AST representation.
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Generating RTLIL representation for module `\memtest'.
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Warning: wire '\led_r' is assigned in a block at memtest.v:63.
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memtest.v:16: Warning: Identifier `\random_rom_dat_r' is implicitly declared.
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memtest.v:23: Warning: Identifier `\clk' is implicitly declared.
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Successfully finished Verilog frontend.
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-- Running command `synth_ice40 -top memtest -json .build/memtest.json' --
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2. Executing SYNTH_ICE40 pass.
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2.1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\SB_IO'.
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Generating RTLIL representation for module `\SB_GB_IO'.
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Generating RTLIL representation for module `\SB_GB'.
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Generating RTLIL representation for module `\SB_LUT4'.
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Generating RTLIL representation for module `\SB_CARRY'.
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Generating RTLIL representation for module `\SB_DFF'.
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Generating RTLIL representation for module `\SB_DFFE'.
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Generating RTLIL representation for module `\SB_DFFSR'.
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Generating RTLIL representation for module `\SB_DFFR'.
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Generating RTLIL representation for module `\SB_DFFSS'.
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Generating RTLIL representation for module `\SB_DFFS'.
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Generating RTLIL representation for module `\SB_DFFESR'.
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Generating RTLIL representation for module `\SB_DFFER'.
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Generating RTLIL representation for module `\SB_DFFESS'.
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Generating RTLIL representation for module `\SB_DFFES'.
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Generating RTLIL representation for module `\SB_DFFN'.
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Generating RTLIL representation for module `\SB_DFFNE'.
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Generating RTLIL representation for module `\SB_DFFNSR'.
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Generating RTLIL representation for module `\SB_DFFNR'.
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Generating RTLIL representation for module `\SB_DFFNSS'.
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Generating RTLIL representation for module `\SB_DFFNS'.
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Generating RTLIL representation for module `\SB_DFFNESR'.
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Generating RTLIL representation for module `\SB_DFFNER'.
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Generating RTLIL representation for module `\SB_DFFNESS'.
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Generating RTLIL representation for module `\SB_DFFNES'.
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Generating RTLIL representation for module `\SB_RAM40_4K'.
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Generating RTLIL representation for module `\SB_RAM40_4KNR'.
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Generating RTLIL representation for module `\SB_RAM40_4KNW'.
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Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
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Generating RTLIL representation for module `\ICESTORM_LC'.
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Generating RTLIL representation for module `\SB_PLL40_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
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Generating RTLIL representation for module `\SB_WARMBOOT'.
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Generating RTLIL representation for module `\SB_MAC16'.
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Generating RTLIL representation for module `\SB_SPRAM256KA'.
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Generating RTLIL representation for module `\SB_HFOSC'.
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Generating RTLIL representation for module `\SB_LFOSC'.
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Generating RTLIL representation for module `\SB_RGBA_DRV'.
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Generating RTLIL representation for module `\SB_I2C'.
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Generating RTLIL representation for module `\SB_SPI'.
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Generating RTLIL representation for module `\SB_LEDDA_IP'.
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Generating RTLIL representation for module `\SB_FILTER_50NS'.
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Generating RTLIL representation for module `\SB_IO_I3C'.
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Generating RTLIL representation for module `\SB_IO_OD'.
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Successfully finished Verilog frontend.
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2.2. Executing HIERARCHY pass (managing design hierarchy).
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2.2.1. Analyzing design hierarchy..
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Top module: \memtest
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2.2.2. Analyzing design hierarchy..
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Top module: \memtest
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Removed 0 unused modules.
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2.3. Executing PROC pass (convert processes to netlists).
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2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:25$132'.
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Cleaned up 0 empty switches.
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2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.3.3. Executing PROC_INIT pass (extract init attributes).
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2.3.4. Executing PROC_ARST pass (detect async resets in processes).
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2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\memtest.$proc$memtest.v:29$34'.
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1/34: $0\led_r[0:0]
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2/34: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66
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3/34: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65
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4/34: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64
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5/34: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63
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6/34: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62
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7/34: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61
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8/34: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60
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9/34: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59
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10/34: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58
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11/34: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57
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12/34: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56
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13/34: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55
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14/34: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54
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15/34: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53
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16/34: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52
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17/34: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51
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18/34: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50
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19/34: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49
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20/34: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48
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21/34: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47
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22/34: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46
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23/34: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45
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24/34: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44
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25/34: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43
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26/34: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42
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27/34: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41
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28/34: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40
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29/34: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39
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30/34: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38
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31/34: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37
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32/34: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36
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33/34: $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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34/34: $0\memadr[10:0]
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2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\memtest.\led_r' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$133' with positive edge clock.
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Creating register for signal `\memtest.\memadr' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$134' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:32$1' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$135' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:33$2' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$136' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:34$3' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$137' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:35$4' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$138' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:36$5' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$139' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:37$6' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$140' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:38$7' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$141' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:39$8' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$142' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:40$9' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$143' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:41$10' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$144' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:42$11' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$145' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:43$12' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$146' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:44$13' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$147' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:45$14' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$148' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:46$15' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$149' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:47$16' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$150' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:48$17' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$151' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:49$18' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$152' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:50$19' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$153' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:51$20' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$154' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:52$21' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$155' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:53$22' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$156' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:54$23' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$157' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:55$24' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$158' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:56$25' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$159' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:57$26' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$160' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:58$27' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$161' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:59$28' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$162' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:60$29' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$163' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:61$30' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$164' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:62$31' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$165' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:63$32' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$166' with positive edge clock.
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2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:29$34'.
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Cleaned up 0 empty switches.
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2.4. Executing FLATTEN pass (flatten design).
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No more expansions possible.
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2.5. Executing TRIBUF pass.
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2.6. Executing DEMINOUT pass (demote inout ports to input or output).
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2.7. Executing SYNTH pass.
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2.7.1. Executing PROC pass (convert processes to netlists).
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2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.7.1.3. Executing PROC_INIT pass (extract init attributes).
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2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).
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2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
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2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.2. Executing OPT_EXPR pass (perform const folding).
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2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \memtest..
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removing unused `$memrd' cell `$memrd$\mem$memtest.v:16$33'.
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removing unused `$dff' cell `$procdff$135'.
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removing unused `$dff' cell `$procdff$136'.
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removing unused `$dff' cell `$procdff$137'.
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removing unused `$dff' cell `$procdff$138'.
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removing unused `$dff' cell `$procdff$139'.
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removing unused `$dff' cell `$procdff$140'.
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removing unused `$dff' cell `$procdff$141'.
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removing unused `$dff' cell `$procdff$142'.
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removing unused `$dff' cell `$procdff$143'.
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removing unused `$dff' cell `$procdff$144'.
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removing unused `$dff' cell `$procdff$145'.
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removing unused `$dff' cell `$procdff$146'.
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removing unused `$dff' cell `$procdff$147'.
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removing unused `$dff' cell `$procdff$148'.
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removing unused `$dff' cell `$procdff$149'.
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removing unused `$dff' cell `$procdff$150'.
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removing unused `$dff' cell `$procdff$151'.
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removing unused `$dff' cell `$procdff$152'.
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removing unused `$dff' cell `$procdff$153'.
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removing unused `$dff' cell `$procdff$154'.
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removing unused `$dff' cell `$procdff$155'.
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removing unused `$dff' cell `$procdff$156'.
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removing unused `$dff' cell `$procdff$157'.
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removing unused `$dff' cell `$procdff$158'.
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removing unused `$dff' cell `$procdff$159'.
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removing unused `$dff' cell `$procdff$160'.
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removing unused `$dff' cell `$procdff$161'.
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removing unused `$dff' cell `$procdff$162'.
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removing unused `$dff' cell `$procdff$163'.
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removing unused `$dff' cell `$procdff$164'.
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removing unused `$dff' cell `$procdff$165'.
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removing unused `$dff' cell `$procdff$166'.
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removing unused non-port wire \random_rom_dat_r.
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removed 67 unused temporary wires.
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Removed 33 unused cells and 67 unused wires.
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2.7.4. Executing CHECK pass (checking for obvious problems).
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checking module memtest..
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Warning: Wire memtest.\pmod_4 is used but has no driver.
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Warning: Wire memtest.\pmod_3 is used but has no driver.
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Warning: Wire memtest.\pmod_2 is used but has no driver.
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Warning: Wire memtest.\pmod_1 is used but has no driver.
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Warning: Wire memtest.\led_g is used but has no driver.
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Warning: Wire memtest.\led_b is used but has no driver.
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found and reported 6 problems.
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2.7.5. Executing OPT pass (performing simple optimizations).
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2.7.5.1. Executing OPT_EXPR pass (perform const folding).
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2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\memtest'.
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Cell `$memrd$\mem$memtest.v:33$69' is identical to cell `$memrd$\mem$memtest.v:32$68'.
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Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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Removing $memrd cell `$memrd$\mem$memtest.v:33$69' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:34$70' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:34$70' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:35$71' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:35$71' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:36$72' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:36$72' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:37$73' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:37$73' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:38$74' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:38$74' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:39$75' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:39$75' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:40$76' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:40$76' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:41$77' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:41$77' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:42$78' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:42$78' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:43$79' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:43$79' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:44$80' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:44$80' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:45$81' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:45$81' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:46$82' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:46$82' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:47$83' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:47$83' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:48$84' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:48$84' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:49$85' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:49$85' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:50$86' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:50$86' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:51$87' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:51$87' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:52$88' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:52$88' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:53$89' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:53$89' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:54$90' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:54$90' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:55$91' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:55$91' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:56$92' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:56$92' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:57$93' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:57$93' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:58$94' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:58$94' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:59$95' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:59$95' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:60$96' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:60$96' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:61$97' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:61$97' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:62$98' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:62$98' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:63$99' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:63$99' from module `\memtest'.
|
|
Removed a total of 31 cells.
|
|
|
|
2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 31 unused temporary wires.
|
|
Removed 33 unused cells and 98 unused wires.
|
|
|
|
2.7.5.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.5.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.6. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 21 address bits (of 32) from memory init port memtest.$meminit$\mem$memtest.v:26$131 (mem).
|
|
Removed top 31 bits (of 32) from port B of cell memtest.$add$memtest.v:30$67 ($add).
|
|
Removed top 21 bits (of 32) from port Y of cell memtest.$add$memtest.v:30$67 ($add).
|
|
|
|
2.7.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.7.7.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.7.8. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module memtest:
|
|
creating $macc model for $add$memtest.v:30$67 ($add).
|
|
creating $alu model for $macc $add$memtest.v:30$67.
|
|
creating $alu cell for $add$memtest.v:30$67: $auto$alumacc.cc:474:replace_alu$167
|
|
created 1 $alu and 0 $macc cells.
|
|
|
|
2.7.9. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.7.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.10.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 1 unused temporary wires.
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.10.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.11. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.7.11.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
2.7.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
2.7.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
2.7.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
2.7.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
2.7.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.12.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.12.5. Finished fast OPT passes.
|
|
|
|
2.7.13. Executing MEMORY pass.
|
|
|
|
2.7.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$memrd$\mem$memtest.v:32$68' in module `\memtest': merged address $dff to cell.
|
|
|
|
2.7.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\memtest':
|
|
$meminit$\mem$memtest.v:26$131 ($meminit)
|
|
$memrd$\mem$memtest.v:32$68 ($memrd)
|
|
|
|
2.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing memtest.mem:
|
|
Properties: ports=1 bits=65536 rports=1 wports=0 dbits=32 abits=11 words=2048
|
|
Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Bram geometry: abits=8 dbits=16 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Bram geometry: abits=9 dbits=8 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Bram geometry: abits=10 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Bram geometry: abits=11 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Selecting best of 4 rules:
|
|
Efficiency for rule 2.3: efficiency=100, cells=16, acells=1
|
|
Efficiency for rule 2.2: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 2.1: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 1.1: efficiency=100, cells=16, acells=8
|
|
Selected rule 2.3 with efficiency 100.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: mem.0.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: mem.1.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: mem.2.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: mem.3.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <4 0 0>: mem.4.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <5 0 0>: mem.5.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <6 0 0>: mem.6.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <7 0 0>: mem.7.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <8 0 0>: mem.8.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <9 0 0>: mem.9.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <10 0 0>: mem.10.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <11 0 0>: mem.11.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <12 0 0>: mem.12.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <13 0 0>: mem.13.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <14 0 0>: mem.14.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <15 0 0>: mem.15.0.0
|
|
|
|
2.9. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.9.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Generating RTLIL representation for module `$paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.3. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.0.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.1.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.2.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.3.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.4.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.5.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.6.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011
|
|
Generating RTLIL representation for module `$paramod$214e7d8d8d18244b8a4e8f431eec90e369896474\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.5. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.15.0.0 using $paramod$214e7d8d8d18244b8a4e8f431eec90e369896474\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.14.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.13.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.12.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.11.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.10.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.9.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.8.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
Mapping memtest.mem.7.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Generating RTLIL representation for module `$paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K'.
|
|
|
|
2.9.7. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.0.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.1.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.2.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.3.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.4.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.5.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.6.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
|
|
2.9.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Generating RTLIL representation for module `$paramod$6b65790f63d533af747fa735f04ceab83c6a4652\$__ICE40_RAM4K'.
|
|
|
|
2.9.9. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.15.0.0 using $paramod$6b65790f63d533af747fa735f04ceab83c6a4652\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.14.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.13.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.12.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.11.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.10.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.9.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.8.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
Mapping memtest.mem.7.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K.
|
|
No more expansions possible.
|
|
|
|
2.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
Setting undriven signal in memtest to undef: $techmap223\mem.7.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap222\mem.8.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap221\mem.9.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap220\mem.10.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap219\mem.11.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap218\mem.12.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap217\mem.13.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap216\mem.14.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap215\mem.15.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap214\mem.6.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap213\mem.5.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap212\mem.4.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap211\mem.3.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap210\mem.2.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap209\mem.1.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap208\mem.0.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [8]
|
|
Setting undriven signal in memtest to undef: \pmod_1
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [14:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [10]
|
|
Setting undriven signal in memtest to undef: \led_b
|
|
Setting undriven signal in memtest to undef: \led_g
|
|
Setting undriven signal in memtest to undef: \pmod_2
|
|
Setting undriven signal in memtest to undef: \pmod_4
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [1]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [4]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [0]
|
|
Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [7:4]
|
|
Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [0]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [2:1]
|
|
Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [10:8]
|
|
Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [12]
|
|
Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [15:13]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [4]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [10:5]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [6]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: \pmod_3
|
|
Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [2]
|
|
Replacing $reduce_or cell `$techmap$techmap194\mem.3.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap194\mem.3.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap193\mem.2.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap193\mem.2.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap192\mem.1.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap192\mem.1.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap191\mem.0.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap191\mem.0.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap196\mem.5.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap196\mem.5.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap195\mem.4.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap195\mem.4.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap197\mem.6.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap197\mem.6.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap199\mem.15.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$198' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap199\mem.15.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$198_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap200\mem.14.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap200\mem.14.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap201\mem.13.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap201\mem.13.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap202\mem.12.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap202\mem.12.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap203\mem.11.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap203\mem.11.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap204\mem.10.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap204\mem.10.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap205\mem.9.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap205\mem.9.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap206\mem.8.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap206\mem.8.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap207\mem.7.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap207\mem.7.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
|
|
2.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.10.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 384 unused temporary wires.
|
|
Removed 33 unused cells and 483 unused wires.
|
|
|
|
2.10.5. Finished fast OPT passes.
|
|
|
|
2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
|
|
|
|
2.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 483 unused wires.
|
|
|
|
2.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.13.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.2. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ice40_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'.
|
|
Parameter \A_SIGNED = 0
|
|
Parameter \B_SIGNED = 0
|
|
Parameter \A_WIDTH = 1
|
|
Parameter \B_WIDTH = 11
|
|
Parameter \Y_WIDTH = 11
|
|
Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11'.
|
|
|
|
2.13.4. Continuing TECHMAP pass.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11.
|
|
Mapping memtest.$xor$memtest.v:33$100 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:34$101 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:35$102 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:36$103 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:37$104 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:38$105 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:39$106 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:40$107 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:41$108 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:42$109 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:43$110 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:44$111 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:45$112 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:46$113 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:47$114 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:48$115 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:49$116 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:50$117 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:51$118 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:52$119 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:53$120 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:54$121 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:55$122 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:56$123 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:57$124 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:58$125 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:59$126 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:60$127 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:61$128 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:62$129 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:63$130 ($xor) with simplemap.
|
|
Mapping memtest.$procdff$133 ($dff) with simplemap.
|
|
Mapping memtest.$procdff$134 ($dff) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.A_conv ($pos) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.B_conv ($pos) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$not$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$271 ($not) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272 ($mux) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273 ($xor) with simplemap.
|
|
No more expansions possible.
|
|
|
|
2.14. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.14.1. Running ICE40 specific optimizations.
|
|
|
|
2.14.2. Executing OPT_EXPR pass (perform const folding).
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$332' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [4] = \memadr [4]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$343' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [4] = \memadr [4]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$338' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [10] = \memadr [10]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$328' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [0] = \memadr [0]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$329' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [1] = \memadr [1]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$340' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [1] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$330' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [2] = \memadr [2]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$341' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [2] = \memadr [2]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$331' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [3] = \memadr [3]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$342' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [3] = \memadr [3]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$336' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [8] = \memadr [8]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$334' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [6] = \memadr [6]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$349' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [10] = \memadr [10]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$337' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [9] = \memadr [9]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$348' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [9] = \memadr [9]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$333' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [5] = \memadr [5]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$344' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [5] = \memadr [5]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$347' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [8] = \memadr [8]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$335' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [7] = \memadr [7]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$346' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [7] = \memadr [7]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$345' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [6] = \memadr [6]'.
|
|
|
|
2.14.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$317'.
|
|
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$339'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$319'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$324'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$320'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$323'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$327'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$322'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$326'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$321'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$325'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$318'.
|
|
removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[10].carry'.
|
|
removed 17 unused temporary wires.
|
|
Removed 46 unused cells and 500 unused wires.
|
|
|
|
2.14.6. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.7. Running ICE40 specific optimizations.
|
|
Optimized away SB_CARRY cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[0].carry: CO=\memadr [0]
|
|
Mapping SB_LUT4 cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[1].adder back to logic.
|
|
|
|
2.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$352' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$351' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$360' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$353' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [2] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$354' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [3] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$361' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$365' (01?) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [0] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$356' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [5] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$355' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [4] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$362' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [2] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$357' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [6] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$358' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [7] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$363' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [3] = 1'0'.
|
|
|
|
2.14.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.10. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 3 unused temporary wires.
|
|
Removed 46 unused cells and 503 unused wires.
|
|
|
|
2.14.12. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.13. Running ICE40 specific optimizations.
|
|
|
|
2.14.14. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.14.15. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.16. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 46 unused cells and 503 unused wires.
|
|
|
|
2.14.18. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
|
|
|
|
2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
|
|
Selected cell types for direct conversion:
|
|
$_DFF_PP1_ -> $__DFFE_PP1
|
|
$_DFF_PP0_ -> $__DFFE_PP0
|
|
$_DFF_PN1_ -> $__DFFE_PN1
|
|
$_DFF_PN0_ -> $__DFFE_PN0
|
|
$_DFF_NP1_ -> $__DFFE_NP1
|
|
$_DFF_NP0_ -> $__DFFE_NP0
|
|
$_DFF_NN1_ -> $__DFFE_NN1
|
|
$_DFF_NN0_ -> $__DFFE_NN0
|
|
$_DFF_N_ -> $_DFFE_NP_
|
|
$_DFF_P_ -> $_DFFE_PP_
|
|
Transforming FF to FF+Enable cells in module memtest:
|
|
|
|
2.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.17.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Successfully finished Verilog frontend.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$306 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$311 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$307 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$316 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$310 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$315 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$314 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$309 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$313 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$308 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$312 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$305 using \$_DFF_P_.
|
|
No more expansions possible.
|
|
|
|
2.18. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.20. Executing ICE40_FFINIT pass (implement FF init values).
|
|
Handling FF init values in memtest.
|
|
|
|
2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
|
|
Merging set/reset $_MUX_ cells into SB_FFs in memtest.
|
|
|
|
2.22. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.22.1. Running ICE40 specific optimizations.
|
|
|
|
2.22.2. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.22.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.22.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 36 unused temporary wires.
|
|
Removed 46 unused cells and 539 unused wires.
|
|
|
|
2.22.6. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.23.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.24. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.24.1. Extracting gate netlist of module `\memtest' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 33 gates and 67 wires to a netlist network with 34 inputs and 2 outputs.
|
|
|
|
2.24.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + lutpack -S 1
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.24.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 26
|
|
ABC RESULTS: internal signals: 31
|
|
ABC RESULTS: input signals: 34
|
|
ABC RESULTS: output signals: 2
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 67 unused wires.
|
|
|
|
2.25. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.25.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 2
|
|
Parameter \LUT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0110'.
|
|
|
|
2.25.3. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$395 using $paramod\$lut\WIDTH=2\LUT=4'0110.
|
|
|
|
2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10010110'.
|
|
|
|
2.25.5. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$407 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$406 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
|
|
2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0110100110010110'.
|
|
|
|
2.25.7. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$402 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
|
|
2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1001011001101001'.
|
|
|
|
2.25.9. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$403 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
|
|
2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'01101001'.
|
|
|
|
2.25.11. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$401 using $paramod\$lut\WIDTH=3\LUT=8'01101001.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$405 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$404 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$398 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$399 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$400 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$397 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$396 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
No more expansions possible.
|
|
Removed 0 unused cells and 26 unused wires.
|
|
|
|
2.26. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.26.1. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
|
|
2.26.2. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
Removed 0 unused modules.
|
|
|
|
2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0110'.
|
|
|
|
2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'01101001'.
|
|
|
|
2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Generating RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.28. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.29. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.30. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.31. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.32. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.33. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Generating RTLIL representation for module `$paramod$334b97d74ac2fc34e989b7abd0f6e0033972d758\SB_RAM40_4K'.
|
|
|
|
2.26.34. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.35. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.36. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.37. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.38. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.39. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.40. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.26.41. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
|
Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'.
|
|
|
|
2.27. Printing statistics.
|
|
|
|
=== memtest ===
|
|
|
|
Number of wires: 44
|
|
Number of wire bits: 345
|
|
Number of public wires: 13
|
|
Number of public wire bits: 23
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 61
|
|
SB_CARRY 9
|
|
SB_DFF 12
|
|
SB_GB 1
|
|
SB_LUT4 23
|
|
SB_RAM40_4K 16
|
|
|
|
2.28. Executing CHECK pass (checking for obvious problems).
|
|
checking module memtest..
|
|
found and reported 0 problems.
|
|
|
|
2.29. Executing JSON backend.
|
|
|
|
Warnings: 9 unique messages, 9 total
|
|
End of script. Logfile hash: af174dade3
|
|
Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
|
|
Time spent: 2% 14x opt_expr (0 sec), 2% 14x opt_clean (0 sec), ...
|