commit 418a26a060e78af19ca8283f6f0670a449a79520 Author: Sean Cross Date: Thu Feb 21 21:20:55 2019 +0800 messy commit Signed-off-by: Sean Cross diff --git a/memtest/-p b/memtest/-p new file mode 100644 index 0000000..cb1fd45 --- /dev/null +++ b/memtest/-p @@ -0,0 +1,28 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2018 Clifford Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG) + + +-- Parsing `synth_ice40 -top memtest -json .build/memtest.json' using frontend `json' -- + +1. Executing JSON frontend. +ERROR: Can't open input file `synth_ice40 -top memtest -json .build/memtest.json' for reading: No such file or directory diff --git a/memtest/.build/memtest.asc b/memtest/.build/memtest.asc new file mode 100644 index 0000000..38315ad --- /dev/null +++ b/memtest/.build/memtest.asc @@ -0,0 +1,16608 @@ +.comment from next-pnr +.device 5k +.io_tile 1 0 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 + +.io_tile 2 0 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 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$0\memadr[10:0][7] +.sym 25498 $0\memadr[10:0][4] +.sym 25499 $PACKER_GND_NET +.sym 25500 $0\memadr[10:0][2] +.sym 25501 $0\memadr[10:0][1] +.sym 25502 $0\memadr[10:0][3] +.sym 25503 $0\memadr[10:0][5] +.sym 25596 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[4] +.sym 25606 $0\memadr[10:0][1] +.sym 25610 $0\memadr[10:0][0] +.sym 25612 $0\memadr[10:0][8] +.sym 25622 $0\memadr[10:0][10] +.sym 25719 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 25735 $PACKER_GND_NET +.sym 25737 $PACKER_VCC_NET +.sym 25842 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[16] +.sym 25991 $PACKER_GND_NET +.sym 25996 $PACKER_GND_NET +.sym 26352 $PACKER_GND_NET +.sym 26484 $PACKER_GND_NET +.sym 26498 $PACKER_GND_NET +.sym 26507 $PACKER_GND_NET +.sym 26527 clki +.sym 26549 clki +.sym 27539 $PACKER_VCC_NET +.sym 27542 $PACKER_VCC_NET +.sym 27544 $PACKER_VCC_NET +.sym 27659 $0\memadr[10:0][9] +.sym 27663 $0\memadr[10:0][8] +.sym 27669 $0\memadr[10:0][5] +.sym 27670 $0\memadr[10:0][4] +.sym 27671 $0\memadr[10:0][7] +.sym 27672 $0\memadr[10:0][0] +.sym 27675 $0\memadr[10:0][1] +.sym 27677 $0\memadr[10:0][2] +.sym 27678 $0\memadr[10:0][3] +.sym 27679 $0\memadr[10:0][6] +.sym 27680 $PACKER_VCC_NET +.sym 27681 $0\memadr[10:0][10] +.sym 27682 $PACKER_VCC_NET +.sym 27701 $0\memadr[10:0][0] +.sym 27702 $0\memadr[10:0][1] +.sym 27703 $0\memadr[10:0][10] +.sym 27704 $0\memadr[10:0][2] +.sym 27705 $0\memadr[10:0][3] +.sym 27706 $0\memadr[10:0][4] +.sym 27707 $0\memadr[10:0][5] +.sym 27708 $0\memadr[10:0][6] +.sym 27709 $0\memadr[10:0][7] +.sym 27710 $0\memadr[10:0][8] +.sym 27711 $0\memadr[10:0][9] +.sym 27712 clk +.sym 27713 $PACKER_VCC_NET +.sym 27714 $PACKER_VCC_NET +.sym 27737 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 27739 $0\memadr[10:0][9] +.sym 27757 $PACKER_GND_NET +.sym 27768 $PACKER_VCC_NET +.sym 27814 $PACKER_GND_NET_$glb_clk +.sym 27815 $PACKER_GND_NET +.sym 27824 $PACKER_VCC_NET +.sym 27846 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[22] +.sym 27859 $0\memadr[10:0][1] +.sym 27862 $0\memadr[10:0][4] +.sym 27864 $0\memadr[10:0][6] +.sym 27865 $0\memadr[10:0][2] +.sym 27866 $0\memadr[10:0][5] +.sym 27867 $0\memadr[10:0][8] +.sym 27868 $0\memadr[10:0][7] +.sym 27869 $0\memadr[10:0][10] +.sym 27872 $0\memadr[10:0][3] +.sym 27877 $0\memadr[10:0][9] +.sym 27881 $0\memadr[10:0][0] +.sym 27884 $PACKER_VCC_NET +.sym 27886 $PACKER_VCC_NET +.sym 27905 $0\memadr[10:0][0] +.sym 27906 $0\memadr[10:0][1] +.sym 27907 $0\memadr[10:0][10] +.sym 27908 $0\memadr[10:0][2] +.sym 27909 $0\memadr[10:0][3] +.sym 27910 $0\memadr[10:0][4] +.sym 27911 $0\memadr[10:0][5] +.sym 27912 $0\memadr[10:0][6] +.sym 27913 $0\memadr[10:0][7] +.sym 27914 $0\memadr[10:0][8] +.sym 27915 $0\memadr[10:0][9] +.sym 27916 clk +.sym 27917 $PACKER_VCC_NET +.sym 27918 $PACKER_VCC_NET +.sym 27932 $0\memadr[10:0][5] +.sym 27933 $0\memadr[10:0][1] +.sym 27934 $0\memadr[10:0][7] +.sym 27935 $PACKER_GND_NET +.sym 27938 $0\memadr[10:0][4] +.sym 27940 $0\memadr[10:0][6] +.sym 27941 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 27942 $0\memadr[10:0][3] +.sym 27947 $PACKER_VCC_NET +.sym 27950 $PACKER_VCC_NET +.sym 27952 $PACKER_VCC_NET +.sym 27972 $PACKER_VCC_NET +.sym 27977 $PACKER_GND_NET +.sym 28018 $PACKER_GND_NET_$glb_clk +.sym 28019 $PACKER_GND_NET +.sym 28028 $PACKER_VCC_NET +.sym 28042 $0\memadr[10:0][8] +.sym 28049 $PACKER_VCC_NET +.sym 28050 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[28] +.sym 28056 $PACKER_VCC_NET +.sym 28071 $0\memadr[10:0][8] +.sym 28074 $0\memadr[10:0][7] +.sym 28077 $0\memadr[10:0][5] +.sym 28078 $0\memadr[10:0][2] +.sym 28079 $0\memadr[10:0][1] +.sym 28081 $0\memadr[10:0][9] +.sym 28082 $0\memadr[10:0][4] +.sym 28083 $0\memadr[10:0][3] +.sym 28085 $0\memadr[10:0][0] +.sym 28087 $0\memadr[10:0][6] +.sym 28088 $PACKER_VCC_NET +.sym 28089 $0\memadr[10:0][10] +.sym 28090 $PACKER_VCC_NET +.sym 28109 $0\memadr[10:0][0] +.sym 28110 $0\memadr[10:0][1] +.sym 28111 $0\memadr[10:0][10] +.sym 28112 $0\memadr[10:0][2] +.sym 28113 $0\memadr[10:0][3] +.sym 28114 $0\memadr[10:0][4] +.sym 28115 $0\memadr[10:0][5] +.sym 28116 $0\memadr[10:0][6] +.sym 28117 $0\memadr[10:0][7] +.sym 28118 $0\memadr[10:0][8] +.sym 28119 $0\memadr[10:0][9] +.sym 28120 clk +.sym 28121 $PACKER_VCC_NET +.sym 28122 $PACKER_VCC_NET +.sym 28145 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 28147 $0\memadr[10:0][9] +.sym 28151 $PACKER_VCC_NET +.sym 28154 $0\memadr[10:0][9] +.sym 28155 $0\memadr[10:0][8] +.sym 28165 $PACKER_GND_NET +.sym 28176 $PACKER_VCC_NET +.sym 28198 $abc$394$n41_1 +.sym 28222 $PACKER_GND_NET_$glb_clk +.sym 28223 $PACKER_GND_NET +.sym 28232 $PACKER_VCC_NET +.sym 28254 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[22] +.sym 28266 $0\memadr[10:0][2] +.sym 28267 $0\memadr[10:0][1] +.sym 28270 $0\memadr[10:0][4] +.sym 28271 $0\memadr[10:0][3] +.sym 28272 $0\memadr[10:0][6] +.sym 28273 $0\memadr[10:0][0] +.sym 28276 $0\memadr[10:0][5] +.sym 28277 $0\memadr[10:0][10] +.sym 28278 $PACKER_VCC_NET +.sym 28280 $0\memadr[10:0][7] +.sym 28283 $PACKER_VCC_NET +.sym 28292 $0\memadr[10:0][9] +.sym 28293 $0\memadr[10:0][8] +.sym 28313 $0\memadr[10:0][0] +.sym 28314 $0\memadr[10:0][1] +.sym 28315 $0\memadr[10:0][10] +.sym 28316 $0\memadr[10:0][2] +.sym 28317 $0\memadr[10:0][3] +.sym 28318 $0\memadr[10:0][4] +.sym 28319 $0\memadr[10:0][5] +.sym 28320 $0\memadr[10:0][6] +.sym 28321 $0\memadr[10:0][7] +.sym 28322 $0\memadr[10:0][8] +.sym 28323 $0\memadr[10:0][9] +.sym 28324 clk +.sym 28325 $PACKER_VCC_NET +.sym 28326 $PACKER_VCC_NET +.sym 28339 $0\memadr[10:0][0] +.sym 28340 $0\memadr[10:0][2] +.sym 28341 $0\memadr[10:0][1] +.sym 28342 $0\memadr[10:0][7] +.sym 28343 $PACKER_GND_NET +.sym 28344 $0\memadr[10:0][5] +.sym 28345 $0\memadr[10:0][2] +.sym 28346 $0\memadr[10:0][4] +.sym 28347 $0\memadr[10:0][3] +.sym 28348 $0\memadr[10:0][7] +.sym 28350 $0\memadr[10:0][6] +.sym 28351 $PACKER_VCC_NET +.sym 28356 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[9] +.sym 28358 $PACKER_VCC_NET +.sym 28361 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[12] +.sym 28380 $PACKER_VCC_NET +.sym 28385 $PACKER_GND_NET +.sym 28404 $abc$394$n45_1 +.sym 28426 $PACKER_GND_NET_$glb_clk +.sym 28427 $PACKER_GND_NET +.sym 28436 $PACKER_VCC_NET +.sym 28447 $0\memadr[10:0][10] +.sym 28458 $0\memadr[10:0][6] +.sym 28461 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[21] +.sym 28471 $0\memadr[10:0][9] +.sym 28473 $0\memadr[10:0][7] +.sym 28474 $0\memadr[10:0][6] +.sym 28476 $0\memadr[10:0][10] +.sym 28477 $0\memadr[10:0][8] +.sym 28480 $0\memadr[10:0][5] +.sym 28481 $0\memadr[10:0][0] +.sym 28483 $0\memadr[10:0][4] +.sym 28484 $0\memadr[10:0][1] +.sym 28489 $PACKER_VCC_NET +.sym 28491 $0\memadr[10:0][3] +.sym 28495 $0\memadr[10:0][2] +.sym 28496 $PACKER_VCC_NET +.sym 28517 $0\memadr[10:0][0] +.sym 28518 $0\memadr[10:0][1] +.sym 28519 $0\memadr[10:0][10] +.sym 28520 $0\memadr[10:0][2] +.sym 28521 $0\memadr[10:0][3] +.sym 28522 $0\memadr[10:0][4] +.sym 28523 $0\memadr[10:0][5] +.sym 28524 $0\memadr[10:0][6] +.sym 28525 $0\memadr[10:0][7] +.sym 28526 $0\memadr[10:0][8] +.sym 28527 $0\memadr[10:0][9] +.sym 28528 clk +.sym 28529 $PACKER_VCC_NET +.sym 28530 $PACKER_VCC_NET +.sym 28546 $0\memadr[10:0][5] +.sym 28549 $0\memadr[10:0][10] +.sym 28555 $0\memadr[10:0][9] +.sym 28558 $0\memadr[10:0][8] +.sym 28561 $0\memadr[10:0][9] +.sym 28562 $PACKER_VCC_NET +.sym 28564 $PACKER_VCC_NET +.sym 28582 $PACKER_GND_NET +.sym 28584 $PACKER_VCC_NET +.sym 28630 $PACKER_GND_NET_$glb_clk +.sym 28631 $PACKER_GND_NET +.sym 28640 $PACKER_VCC_NET +.sym 28645 $0\memadr[10:0][9] +.sym 28646 $0\memadr[10:0][2] +.sym 28652 $0\memadr[10:0][4] +.sym 28653 $0\memadr[10:0][7] +.sym 28654 $0\memadr[10:0][3] +.sym 28655 $0\memadr[10:0][6] +.sym 28656 $0\memadr[10:0][5] +.sym 28674 $0\memadr[10:0][10] +.sym 28676 $0\memadr[10:0][4] +.sym 28677 $0\memadr[10:0][1] +.sym 28679 $0\memadr[10:0][3] +.sym 28681 $0\memadr[10:0][0] +.sym 28683 $0\memadr[10:0][2] +.sym 28684 $0\memadr[10:0][5] +.sym 28685 $0\memadr[10:0][6] +.sym 28686 $0\memadr[10:0][7] +.sym 28693 $0\memadr[10:0][9] +.sym 28696 $0\memadr[10:0][8] +.sym 28700 $PACKER_VCC_NET +.sym 28702 $PACKER_VCC_NET +.sym 28721 $0\memadr[10:0][0] +.sym 28722 $0\memadr[10:0][1] +.sym 28723 $0\memadr[10:0][10] +.sym 28724 $0\memadr[10:0][2] +.sym 28725 $0\memadr[10:0][3] +.sym 28726 $0\memadr[10:0][4] +.sym 28727 $0\memadr[10:0][5] +.sym 28728 $0\memadr[10:0][6] +.sym 28729 $0\memadr[10:0][7] +.sym 28730 $0\memadr[10:0][8] +.sym 28731 $0\memadr[10:0][9] +.sym 28732 clk +.sym 28733 $PACKER_VCC_NET +.sym 28734 $PACKER_VCC_NET +.sym 28752 $0\memadr[10:0][1] +.sym 28753 $0\memadr[10:0][4] +.sym 28754 $0\memadr[10:0][7] +.sym 28756 $PACKER_GND_NET +.sym 28757 $0\memadr[10:0][3] +.sym 28758 $0\memadr[10:0][6] +.sym 28766 $PACKER_VCC_NET +.sym 28767 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[4] +.sym 28768 $PACKER_VCC_NET +.sym 28793 $PACKER_GND_NET +.sym 28795 $PACKER_VCC_NET +.sym 28809 $abc$394$n46 +.sym 28834 $PACKER_GND_NET_$glb_clk +.sym 28835 $PACKER_GND_NET +.sym 28844 $PACKER_VCC_NET +.sym 28872 $PACKER_VCC_NET +.sym 28878 $0\memadr[10:0][0] +.sym 28879 $0\memadr[10:0][3] +.sym 28880 $0\memadr[10:0][8] +.sym 28882 $0\memadr[10:0][6] +.sym 28883 $0\memadr[10:0][5] +.sym 28887 $0\memadr[10:0][10] +.sym 28888 $0\memadr[10:0][7] +.sym 28889 $0\memadr[10:0][2] +.sym 28890 $0\memadr[10:0][9] +.sym 28891 $0\memadr[10:0][4] +.sym 28892 $0\memadr[10:0][1] +.sym 28904 $PACKER_VCC_NET +.sym 28906 $PACKER_VCC_NET +.sym 28925 $0\memadr[10:0][0] +.sym 28926 $0\memadr[10:0][1] +.sym 28927 $0\memadr[10:0][10] +.sym 28928 $0\memadr[10:0][2] +.sym 28929 $0\memadr[10:0][3] +.sym 28930 $0\memadr[10:0][4] +.sym 28931 $0\memadr[10:0][5] +.sym 28932 $0\memadr[10:0][6] +.sym 28933 $0\memadr[10:0][7] +.sym 28934 $0\memadr[10:0][8] +.sym 28935 $0\memadr[10:0][9] +.sym 28936 clk +.sym 28937 $PACKER_VCC_NET +.sym 28938 $PACKER_VCC_NET +.sym 28963 $PACKER_VCC_NET +.sym 28966 $0\memadr[10:0][8] +.sym 28967 $PACKER_VCC_NET +.sym 28971 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[16] +.sym 28974 $0\memadr[10:0][9] +.sym 28990 $PACKER_GND_NET +.sym 28992 $PACKER_VCC_NET +.sym 29038 $PACKER_GND_NET_$glb_clk +.sym 29039 $PACKER_GND_NET +.sym 29048 $PACKER_VCC_NET +.sym 29081 $0\memadr[10:0][3] +.sym 29084 $0\memadr[10:0][6] +.sym 29089 $0\memadr[10:0][0] +.sym 29090 $0\memadr[10:0][1] +.sym 29091 $0\memadr[10:0][10] +.sym 29092 $0\memadr[10:0][5] +.sym 29093 $0\memadr[10:0][4] +.sym 29094 $0\memadr[10:0][7] +.sym 29095 $0\memadr[10:0][2] +.sym 29099 $PACKER_VCC_NET +.sym 29101 $PACKER_VCC_NET +.sym 29104 $0\memadr[10:0][8] +.sym 29112 $0\memadr[10:0][9] +.sym 29129 $0\memadr[10:0][0] +.sym 29130 $0\memadr[10:0][1] +.sym 29131 $0\memadr[10:0][10] +.sym 29132 $0\memadr[10:0][2] +.sym 29133 $0\memadr[10:0][3] +.sym 29134 $0\memadr[10:0][4] +.sym 29135 $0\memadr[10:0][5] +.sym 29136 $0\memadr[10:0][6] +.sym 29137 $0\memadr[10:0][7] +.sym 29138 $0\memadr[10:0][8] +.sym 29139 $0\memadr[10:0][9] +.sym 29140 clk +.sym 29141 $PACKER_VCC_NET +.sym 29142 $PACKER_VCC_NET +.sym 29157 $PACKER_GND_NET +.sym 29164 $PACKER_GND_NET +.sym 29165 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 29196 $PACKER_VCC_NET +.sym 29201 $PACKER_GND_NET +.sym 29242 $PACKER_GND_NET_$glb_clk +.sym 29243 $PACKER_GND_NET +.sym 29252 $PACKER_VCC_NET +.sym 29698 $PACKER_GND_NET +.sym 29709 $PACKER_GND_NET +.sym 31287 $PACKER_VCC_NET +.sym 31289 $PACKER_VCC_NET +.sym 31290 $PACKER_VCC_NET +.sym 31296 $0\memadr[10:0][0] +.sym 31549 $0\memadr[10:0][0] +.sym 31766 $0\memadr[10:0][0] +.sym 31774 $PACKER_VCC_NET +.sym 31779 $PACKER_VCC_NET +.sym 31782 $PACKER_VCC_NET +.sym 31787 $0\memadr[10:0][0] +.sym 31807 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[28] +.sym 31823 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[8] +.sym 31831 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[6] +.sym 31833 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[12] +.sym 31854 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[6] +.sym 31855 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[8] +.sym 31856 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[12] +.sym 31857 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[28] +.sym 31903 $0\memadr[10:0][6] +.sym 31904 $PACKER_VCC_NET +.sym 31912 $abc$394$n41_1 +.sym 32021 $0\memadr[10:0][9] +.sym 32024 $PACKER_VCC_NET +.sym 32026 $0\memadr[10:0][8] +.sym 32027 $PACKER_VCC_NET +.sym 32030 $0\memadr[10:0][8] +.sym 32050 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[9] +.sym 32053 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[22] +.sym 32061 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[13] +.sym 32074 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[21] +.sym 32112 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[9] +.sym 32113 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[21] +.sym 32114 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[13] +.sym 32115 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[22] +.sym 32145 $abc$394$n45_1 +.sym 32274 $PACKER_VCC_NET +.sym 32276 $PACKER_VCC_NET +.sym 32282 $abc$394$n46 +.sym 32391 $PACKER_VCC_NET +.sym 32513 $PACKER_VCC_NET +.sym 32515 $PACKER_VCC_NET +.sym 32522 $0\memadr[10:0][8] +.sym 32545 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[5] +.sym 32553 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[4] +.sym 32561 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[16] +.sym 32569 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[20] +.sym 32586 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[5] +.sym 32587 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[20] +.sym 32588 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[16] +.sym 32589 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[4] +.sym 35617 $0\memadr[10:0][0] +.sym 35634 $PACKER_VCC_NET +.sym 35651 memadr[0] +.sym 35691 $PACKER_VCC_NET +.sym 35694 memadr[0] +.sym 35738 $0\memadr[10:0][0] +.sym 35869 $PACKER_GND_NET +.sym 35981 $abc$394$n46 +.sym 36101 $abc$394$n41_1 +.sym 36113 $0\memadr[10:0][1] +.sym 36114 $0\memadr[10:0][0] +.sym 36361 $PACKER_GND_NET +.sym 36849 $PACKER_GND_NET +.sym 36966 led_r +.sym 38826 $0\memadr[10:0][9] +.sym 38830 $0\memadr[10:0][8] +.sym 39075 $0\memadr[10:0][3] +.sym 39204 $0\memadr[10:0][3] +.sym 39205 $PACKER_GND_NET +.sym 39313 $0\memadr[10:0][7] +.sym 39316 $0\memadr[10:0][8] +.sym 39565 memadr[0] +.sym 39568 $PACKER_GND_NET +.sym 39696 $0\memadr[10:0][3] +.sym 39697 $PACKER_GND_NET +.sym 39698 $0\memadr[10:0][7] +.sym 39702 $0\memadr[10:0][6] +.sym 39704 $0\memadr[10:0][4] +.sym 39705 $0\memadr[10:0][1] +.sym 39805 $0\memadr[10:0][4] +.sym 39808 $0\memadr[10:0][1] +.sym 39809 $0\memadr[10:0][10] +.sym 39811 $0\memadr[10:0][6] +.sym 39812 $0\memadr[10:0][8] +.sym 39813 $0\memadr[10:0][7] +.sym 39814 $0\memadr[10:0][9] +.sym 39934 $PACKER_VCC_NET +.sym 39936 $PACKER_GND_NET +.sym 40189 $PACKER_GND_NET +.sym 40197 $PACKER_GND_NET +.sym 40305 $0\memadr[10:0][8] +.sym 40428 $PACKER_GND_NET +.sym 40430 $PACKER_VCC_NET +.sym 42662 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 42904 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 43030 $0\memadr[10:0][8] +.sym 43150 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 43391 $0\memadr[10:0][2] +.sym 43392 $0\memadr[10:0][1] +.sym 43393 $0\memadr[10:0][7] +.sym 43394 $PACKER_GND_NET +.sym 43395 $0\memadr[10:0][3] +.sym 43397 $0\memadr[10:0][4] +.sym 43399 $0\memadr[10:0][5] +.sym 43401 $0\memadr[10:0][6] +.sym 43514 $0\memadr[10:0][10] +.sym 43641 $0\memadr[10:0][5] +.sym 43646 $0\memadr[10:0][10] +.sym 43657 $0\memadr[10:0][8] +.sym 43761 $0\memadr[10:0][7] +.sym 43765 $0\memadr[10:0][9] +.sym 43766 $0\memadr[10:0][2] +.sym 43767 $0\memadr[10:0][5] +.sym 43768 $0\memadr[10:0][3] +.sym 43769 $0\memadr[10:0][6] +.sym 43770 $0\memadr[10:0][4] +.sym 44380 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 45273 $PACKER_GND_NET +.sym 45395 $PACKER_GND_NET +.sym 45887 $PACKER_GND_NET +.sym 46379 $PACKER_GND_NET +.sym 46611 $PACKER_VCC_NET +.sym 46617 $PACKER_VCC_NET +.sym 46875 $PACKER_GND_NET +.sym 47086 memadr[5] +.sym 47087 $0\memadr[10:0][1] +.sym 47091 $PACKER_GND_NET +.sym 47092 memadr[1] +.sym 47098 $PACKER_VCC_NET +.sym 47106 $PACKER_VCC_NET +.sym 47113 $PACKER_GND_NET +.sym 47225 $0\memadr[10:0][5] +.sym 47227 $0\memadr[10:0][6] +.sym 47228 $PACKER_VCC_NET +.sym 47230 $0\memadr[10:0][1] +.sym 47346 $0\memadr[10:0][9] +.sym 47348 $PACKER_VCC_NET +.sym 47354 $0\memadr[10:0][8] +.sym 47469 $abc$394$n45_1 +.sym 47590 $PACKER_VCC_NET +.sym 47595 $PACKER_VCC_NET +.sym 47715 $PACKER_VCC_NET +.sym 47837 $PACKER_VCC_NET +.sym 47846 $PACKER_VCC_NET +.sym 48094 led_r +.sym 48882 $PACKER_GND_NET +.sym 48906 $PACKER_GND_NET +.sym 50449 $0\memadr[10:0][8] +.sym 50451 $0\memadr[10:0][9] +.sym 50562 $PACKER_GND_NET +.sym 50697 $0\memadr[10:0][1] +.sym 50702 $0\memadr[10:0][3] +.sym 50794 memadr[4] +.sym 50799 memadr[7] +.sym 50919 $0\memadr[10:0][2] +.sym 50920 $0\memadr[10:0][3] +.sym 50921 $0\memadr[10:0][4] +.sym 50922 $0\memadr[10:0][5] +.sym 50923 $0\memadr[10:0][6] +.sym 50924 $0\memadr[10:0][7] +.sym 50942 $0\memadr[10:0][4] +.sym 50943 $PACKER_GND_NET +.sym 50945 $0\memadr[10:0][8] +.sym 50946 $0\memadr[10:0][6] +.sym 50947 $0\memadr[10:0][9] +.sym 50948 $0\memadr[10:0][7] +.sym 50949 $0\memadr[10:0][10] +.sym 50951 $0\memadr[10:0][1] +.sym 50959 $0\memadr[10:0][1] +.sym 50979 $0\memadr[10:0][5] +.sym 50983 memadr[0] +.sym 50988 memadr[1] +.sym 50992 $0\memadr[10:0][5] +.sym 50999 memadr[1] +.sym 51000 memadr[0] +.sym 51028 $0\memadr[10:0][1] +.sym 51038 clk +.sym 51040 $0\memadr[10:0][8] +.sym 51041 $0\memadr[10:0][9] +.sym 51042 $0\memadr[10:0][10] +.sym 51043 memadr[8] +.sym 51045 memadr[9] +.sym 51046 memadr[10] +.sym 51047 memadr[3] +.sym 51053 $0\memadr[10:0][6] +.sym 51054 $PACKER_GND_NET +.sym 51055 $0\memadr[10:0][3] +.sym 51056 $0\memadr[10:0][1] +.sym 51057 $0\memadr[10:0][7] +.sym 51062 $0\memadr[10:0][0] +.sym 51063 $0\memadr[10:0][2] +.sym 51071 $PACKER_GND_NET +.sym 51182 $0\memadr[10:0][8] +.sym 51184 $0\memadr[10:0][9] +.sym 51186 $0\memadr[10:0][10] +.sym 51302 $PACKER_GND_NET +.sym 51305 $abc$394$n46 +.sym 51425 $abc$394$n41_1 +.sym 51433 $0\memadr[10:0][8] +.sym 51563 $PACKER_GND_NET +.sym 51565 $PACKER_VCC_NET +.sym 51791 led_r +.sym 54146 $0\memadr[10:0][8] +.sym 54155 $0\memadr[10:0][9] +.sym 54284 $0\memadr[10:0][6] +.sym 54287 $0\memadr[10:0][5] +.sym 54288 $0\memadr[10:0][4] +.sym 54290 $0\memadr[10:0][10] +.sym 54401 $0\memadr[10:0][1] +.sym 54530 $0\memadr[10:0][2] +.sym 54532 $0\memadr[10:0][3] +.sym 54534 $0\memadr[10:0][4] +.sym 54536 $0\memadr[10:0][5] +.sym 54644 $0\memadr[10:0][4] +.sym 54649 $0\memadr[10:0][8] +.sym 54678 $0\memadr[10:0][4] +.sym 54681 $0\memadr[10:0][7] +.sym 54702 $0\memadr[10:0][4] +.sym 54732 $0\memadr[10:0][7] +.sym 54746 clk +.sym 54750 memadr[6] +.sym 54752 memadr[2] +.sym 54772 $0\memadr[10:0][4] +.sym 54774 $0\memadr[10:0][5] +.sym 54776 $0\memadr[10:0][6] +.sym 54777 $0\memadr[10:0][8] +.sym 54778 $0\memadr[10:0][7] +.sym 54779 $0\memadr[10:0][9] +.sym 54781 $0\memadr[10:0][10] +.sym 54789 memadr[4] +.sym 54793 memadr[0] +.sym 54794 memadr[7] +.sym 54797 memadr[5] +.sym 54803 memadr[1] +.sym 54804 memadr[3] +.sym 54815 memadr[6] +.sym 54817 memadr[2] +.sym 54821 $nextpnr_ICESTORM_LC_0$O +.sym 54824 memadr[0] +.sym 54827 $auto$alumacc.cc:474:replace_alu$167.C[2] +.sym 54830 memadr[1] +.sym 54833 $auto$alumacc.cc:474:replace_alu$167.C[3] +.sym 54835 memadr[2] +.sym 54837 $auto$alumacc.cc:474:replace_alu$167.C[2] +.sym 54839 $auto$alumacc.cc:474:replace_alu$167.C[4] +.sym 54841 memadr[3] +.sym 54843 $auto$alumacc.cc:474:replace_alu$167.C[3] +.sym 54845 $auto$alumacc.cc:474:replace_alu$167.C[5] +.sym 54848 memadr[4] +.sym 54849 $auto$alumacc.cc:474:replace_alu$167.C[4] +.sym 54851 $auto$alumacc.cc:474:replace_alu$167.C[6] +.sym 54854 memadr[5] +.sym 54855 $auto$alumacc.cc:474:replace_alu$167.C[5] +.sym 54857 $auto$alumacc.cc:474:replace_alu$167.C[7] +.sym 54859 memadr[6] +.sym 54861 $auto$alumacc.cc:474:replace_alu$167.C[6] +.sym 54863 $auto$alumacc.cc:474:replace_alu$167.C[8] +.sym 54866 memadr[7] +.sym 54867 $auto$alumacc.cc:474:replace_alu$167.C[7] +.sym 54885 $0\memadr[10:0][5] +.sym 54889 memadr[0] +.sym 54891 $0\memadr[10:0][3] +.sym 54893 $0\memadr[10:0][4] +.sym 54896 $0\memadr[10:0][2] +.sym 54898 $0\memadr[10:0][3] +.sym 54900 $0\memadr[10:0][4] +.sym 54902 $0\memadr[10:0][5] +.sym 54904 $0\memadr[10:0][6] +.sym 54905 $0\memadr[10:0][9] +.sym 54906 $0\memadr[10:0][7] +.sym 54907 $auto$alumacc.cc:474:replace_alu$167.C[8] +.sym 54918 memadr[10] +.sym 54920 $0\memadr[10:0][8] +.sym 54923 $0\memadr[10:0][3] +.sym 54930 $0\memadr[10:0][10] +.sym 54931 memadr[8] +.sym 54933 memadr[9] +.sym 54937 $0\memadr[10:0][9] +.sym 54944 $auto$alumacc.cc:474:replace_alu$167.C[9] +.sym 54946 memadr[8] +.sym 54948 $auto$alumacc.cc:474:replace_alu$167.C[8] +.sym 54950 $auto$alumacc.cc:474:replace_alu$167.C[10] +.sym 54953 memadr[9] +.sym 54954 $auto$alumacc.cc:474:replace_alu$167.C[9] +.sym 54959 memadr[10] +.sym 54960 $auto$alumacc.cc:474:replace_alu$167.C[10] +.sym 54965 $0\memadr[10:0][8] +.sym 54978 $0\memadr[10:0][9] +.sym 54983 $0\memadr[10:0][10] +.sym 54990 $0\memadr[10:0][3] +.sym 54992 clk +.sym 54998 $abc$394$n44 +.sym 55019 $0\memadr[10:0][10] +.sym 55134 $PACKER_GND_NET +.sym 55262 $PACKER_VCC_NET +.sym 57978 $0\memadr[10:0][10] +.sym 57979 $0\memadr[10:0][4] +.sym 57982 $0\memadr[10:0][6] +.sym 57983 $0\memadr[10:0][5] +.sym 57985 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 58221 $0\memadr[10:0][3] +.sym 58223 $0\memadr[10:0][2] +.sym 58224 $0\memadr[10:0][5] +.sym 58225 $0\memadr[10:0][4] +.sym 58227 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 58235 $PACKER_VCC_NET +.sym 58362 $0\memadr[10:0][1] +.sym 58467 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 58468 $0\memadr[10:0][10] +.sym 58473 $0\memadr[10:0][8] +.sym 58474 $0\memadr[10:0][6] +.sym 58475 $0\memadr[10:0][9] +.sym 58476 $0\memadr[10:0][7] +.sym 58477 $0\memadr[10:0][5] +.sym 58629 $0\memadr[10:0][2] +.sym 58633 $0\memadr[10:0][6] +.sym 58665 $0\memadr[10:0][6] +.sym 58677 $0\memadr[10:0][2] +.sym 58699 clk +.sym 58725 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 58726 $PACKER_VCC_NET +.sym 58852 $PACKER_VCC_NET +.sym 58885 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 58886 $abc$394$n46 +.sym 58888 $abc$394$n45_1 +.sym 58922 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 58923 $abc$394$n46 +.sym 58925 $abc$394$n45_1 +.sym 58947 $PACKER_VCC_NET +.sym 58959 $0\memadr[10:0][9] +.sym 58960 $0\memadr[10:0][7] +.sym 58961 $0\memadr[10:0][8] +.sym 58963 $0\memadr[10:0][10] +.sym 58966 $0\memadr[10:0][6] +.sym 58967 $0\memadr[10:0][9] +.sym 58968 $0\memadr[10:0][4] +.sym 58969 $abc$394$n44 +.sym 58970 $0\memadr[10:0][5] +.sym 58980 $PACKER_VCC_NET +.sym 59089 $PACKER_VCC_NET +.sym 59213 $0\memadr[10:0][10] +.sym 59697 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 62051 $0\memadr[10:0][1] +.sym 62063 $PACKER_VCC_NET +.sym 62190 $0\memadr[10:0][3] +.sym 62192 $0\memadr[10:0][6] +.sym 62194 $0\memadr[10:0][7] +.sym 62195 $0\memadr[10:0][0] +.sym 62309 $0\memadr[10:0][9] +.sym 62311 $0\memadr[10:0][10] +.sym 62319 $0\memadr[10:0][8] +.sym 62420 $PACKER_VCC_NET +.sym 62427 $PACKER_VCC_NET +.sym 62545 $0\memadr[10:0][1] +.sym 62547 $0\memadr[10:0][5] +.sym 62555 $PACKER_VCC_NET +.sym 62684 $0\memadr[10:0][1] +.sym 62809 $PACKER_VCC_NET +.sym 62912 $PACKER_VCC_NET +.sym 62922 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 62933 led_r +.sym 63038 $PACKER_VCC_NET +.sym 63162 $PACKER_VCC_NET +.sym 65760 $PACKER_VCC_NET +.sym 65767 $PACKER_VCC_NET +.sym 65886 $0\memadr[10:0][7] +.sym 65889 $0\memadr[10:0][3] +.sym 65890 $PACKER_GND_NET +.sym 65891 $0\memadr[10:0][6] +.sym 65892 $0\memadr[10:0][0] +.sym 66006 $0\memadr[10:0][9] +.sym 66008 $0\memadr[10:0][8] +.sym 66015 $0\memadr[10:0][10] +.sym 66252 $PACKER_VCC_NET +.sym 66259 $PACKER_VCC_NET +.sym 66374 $0\memadr[10:0][2] +.sym 66375 $PACKER_GND_NET +.sym 66376 $0\memadr[10:0][1] +.sym 66377 $0\memadr[10:0][0] +.sym 66378 $0\memadr[10:0][3] +.sym 66379 $0\memadr[10:0][7] +.sym 66380 $0\memadr[10:0][0] +.sym 66381 $0\memadr[10:0][2] +.sym 66382 $PACKER_GND_NET +.sym 66384 $0\memadr[10:0][0] +.sym 66385 $0\memadr[10:0][6] +.sym 66497 $0\memadr[10:0][10] +.sym 66499 $0\memadr[10:0][9] +.sym 66504 $0\memadr[10:0][8] +.sym 66506 $0\memadr[10:0][9] +.sym 66507 $0\memadr[10:0][8] +.sym 66508 $PACKER_VCC_NET +.sym 66518 $0\memadr[10:0][4] +.sym 66520 $0\memadr[10:0][5] +.sym 66622 $PACKER_GND_NET +.sym 66630 led_r +.sym 66744 $PACKER_VCC_NET +.sym 66747 $abc$394$n41_1 +.sym 66764 $PACKER_GND_NET +.sym 66875 $0\memadr[10:0][1] +.sym 66994 $PACKER_VCC_NET +.sym 67001 $0\memadr[10:0][5] +.sym 67010 $0\memadr[10:0][4] +.sym 67257 $PACKER_GND_NET +.sym 67745 $PACKER_GND_NET +.sym 69473 $0\memadr[10:0][8] +.sym 69477 $0\memadr[10:0][9] +.sym 69583 $abc$394$n48 +.sym 69605 $abc$394$n48 +.sym 69608 $0\memadr[10:0][7] +.sym 69611 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 69723 $0\memadr[10:0][1] +.sym 69825 $abc$394$n47_1 +.sym 69966 $0\memadr[10:0][4] +.sym 70097 $abc$394$n47_1 +.sym 70207 $0\memadr[10:0][5] +.sym 70208 $0\memadr[10:0][4] +.sym 70216 $0\memadr[10:0][3] +.sym 70316 led_r +.sym 70452 $abc$394$n40 +.sym 70586 $0\memadr[10:0][7] +.sym 70588 $0\memadr[10:0][8] +.sym 70589 $0\memadr[10:0][10] +.sym 70590 $0\memadr[10:0][6] +.sym 70592 $0\memadr[10:0][4] +.sym 70593 $abc$394$n49_1 +.sym 70594 $0\memadr[10:0][5] +.sym 70596 $0\memadr[10:0][9] +.sym 70699 $0\memadr[10:0][5] +.sym 70701 $0\memadr[10:0][4] +.sym 70811 $abc$394$n49_1 +.sym 70813 $abc$394$n50 +.sym 70833 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 70839 $0\memadr[10:0][10] +.sym 71198 $0\memadr[10:0][5] +.sym 71199 $0\memadr[10:0][4] +.sym 71837 $PACKER_GND_NET +.sym 71861 $PACKER_GND_NET +.sym 71863 $PACKER_GND_NET +.sym 73167 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[1] +.sym 73188 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[1] +.sym 73194 $0\memadr[10:0][1] +.sym 73290 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[0] +.sym 73300 $0\memadr[10:0][4] +.sym 73301 $0\memadr[10:0][10] +.sym 73307 $0\memadr[10:0][7] +.sym 73308 $0\memadr[10:0][6] +.sym 73309 $0\memadr[10:0][5] +.sym 73413 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[19] +.sym 73437 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[0] +.sym 73458 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[1] +.sym 73462 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 73466 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 73470 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[19] +.sym 73513 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[1] +.sym 73514 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[19] +.sym 73515 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 73516 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[23] +.sym 73536 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[18] +.sym 73546 $0\memadr[10:0][4] +.sym 73548 $0\memadr[10:0][5] +.sym 73549 $0\memadr[10:0][3] +.sym 73550 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[29] +.sym 73552 $0\memadr[10:0][2] +.sym 73557 $PACKER_VCC_NET +.sym 73560 $PACKER_VCC_NET +.sym 73563 $PACKER_VCC_NET +.sym 73564 $PACKER_VCC_NET +.sym 73659 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[11] +.sym 73684 $0\memadr[10:0][1] +.sym 73696 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 73706 $abc$394$n48 +.sym 73709 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[0] +.sym 73724 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[11] +.sym 73735 $abc$394$n48 +.sym 73736 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 73737 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[11] +.sym 73738 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[0] +.sym 73782 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[10] +.sym 73790 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[7] +.sym 73791 $0\memadr[10:0][6] +.sym 73794 $abc$394$n47_1 +.sym 73795 $0\memadr[10:0][7] +.sym 73796 $0\memadr[10:0][10] +.sym 73798 $0\memadr[10:0][9] +.sym 73799 $0\memadr[10:0][8] +.sym 73800 $0\memadr[10:0][5] +.sym 73905 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[3] +.sym 74028 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[2] +.sym 74049 $PACKER_VCC_NET +.sym 74055 $PACKER_VCC_NET +.sym 74151 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[25] +.sym 74177 $0\memadr[10:0][5] +.sym 74182 $0\memadr[10:0][1] +.sym 74188 $abc$394$n44 +.sym 74190 $abc$394$n47_1 +.sym 74191 $abc$394$n49_1 +.sym 74200 $abc$394$n40 +.sym 74221 $abc$394$n47_1 +.sym 74222 $abc$394$n49_1 +.sym 74223 $abc$394$n44 +.sym 74224 $abc$394$n40 +.sym 74268 clk +.sym 74274 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 74285 $abc$394$n49_1 +.sym 74286 $0\memadr[10:0][10] +.sym 74287 $0\memadr[10:0][9] +.sym 74289 $0\memadr[10:0][6] +.sym 74290 $0\memadr[10:0][8] +.sym 74291 $0\memadr[10:0][4] +.sym 74292 $abc$394$n44 +.sym 74293 $0\memadr[10:0][7] +.sym 74397 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[31] +.sym 74415 $PACKER_VCC_NET +.sym 74418 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[31] +.sym 74520 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[30] +.sym 74536 $0\memadr[10:0][10] +.sym 74541 $PACKER_VCC_NET +.sym 74544 $PACKER_VCC_NET +.sym 74643 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[15] +.sym 74672 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[27] +.sym 74688 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[31] +.sym 74693 $abc$394$n50 +.sym 74696 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[27] +.sym 74704 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 74708 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[15] +.sym 74709 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[26] +.sym 74731 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[31] +.sym 74732 $abc$394$n50 +.sym 74734 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[26] +.sym 74743 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[17] +.sym 74744 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[27] +.sym 74745 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[15] +.sym 74766 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[14] +.sym 74775 $0\memadr[10:0][7] +.sym 74777 $0\memadr[10:0][6] +.sym 74778 $0\memadr[10:0][10] +.sym 74779 $0\memadr[10:0][5] +.sym 74781 $0\memadr[10:0][9] +.sym 74783 $0\memadr[10:0][4] +.sym 74785 $0\memadr[10:0][8] +.sym 74792 $PACKER_VCC_NET +.sym 74795 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[26] +.sym 74889 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[27] +.sym 75012 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[26] +.sym 75028 $0\memadr[10:0][10] +.sym 75036 $PACKER_VCC_NET +.sym 75668 $PACKER_GND_NET +.sym 75671 $PACKER_GND_NET +.sym 75682 $PACKER_GND_NET +.sym 75690 $PACKER_GND_NET +.sym 76705 $PACKER_VCC_NET +.sym 76712 $PACKER_VCC_NET +.sym 76807 $0\memadr[10:0][2] +.sym 76814 $PACKER_GND_NET +.sym 76816 $0\memadr[10:0][0] +.sym 76817 $0\memadr[10:0][3] +.sym 76823 $0\memadr[10:0][3] +.sym 76824 $0\memadr[10:0][2] +.sym 76825 $0\memadr[10:0][7] +.sym 76826 $0\memadr[10:0][0] +.sym 76827 $0\memadr[10:0][5] +.sym 76828 $0\memadr[10:0][6] +.sym 76830 $0\memadr[10:0][4] +.sym 76837 $0\memadr[10:0][10] +.sym 76839 $0\memadr[10:0][9] +.sym 76843 $PACKER_VCC_NET +.sym 76845 $0\memadr[10:0][1] +.sym 76850 $PACKER_VCC_NET +.sym 76851 $0\memadr[10:0][8] +.sym 76871 $0\memadr[10:0][0] +.sym 76872 $0\memadr[10:0][1] +.sym 76873 $0\memadr[10:0][10] +.sym 76874 $0\memadr[10:0][2] +.sym 76875 $0\memadr[10:0][3] +.sym 76876 $0\memadr[10:0][4] +.sym 76877 $0\memadr[10:0][5] +.sym 76878 $0\memadr[10:0][6] +.sym 76879 $0\memadr[10:0][7] +.sym 76880 $0\memadr[10:0][8] +.sym 76881 $0\memadr[10:0][9] +.sym 76882 clk +.sym 76883 $PACKER_VCC_NET +.sym 76884 $PACKER_VCC_NET +.sym 76909 $0\memadr[10:0][9] +.sym 76912 $0\memadr[10:0][10] +.sym 76919 $0\memadr[10:0][8] +.sym 76945 $PACKER_VCC_NET +.sym 76952 $PACKER_GND_NET +.sym 76984 $PACKER_GND_NET_$glb_clk +.sym 76985 $PACKER_GND_NET +.sym 76994 $PACKER_VCC_NET +.sym 77030 $0\memadr[10:0][2] +.sym 77033 $0\memadr[10:0][3] +.sym 77034 $0\memadr[10:0][4] +.sym 77042 $0\memadr[10:0][5] +.sym 77043 $0\memadr[10:0][1] +.sym 77047 $0\memadr[10:0][9] +.sym 77048 $0\memadr[10:0][0] +.sym 77050 $0\memadr[10:0][10] +.sym 77053 $0\memadr[10:0][6] +.sym 77054 $PACKER_VCC_NET +.sym 77056 $PACKER_VCC_NET +.sym 77057 $0\memadr[10:0][8] +.sym 77058 $0\memadr[10:0][7] +.sym 77075 $0\memadr[10:0][0] +.sym 77076 $0\memadr[10:0][1] +.sym 77077 $0\memadr[10:0][10] +.sym 77078 $0\memadr[10:0][2] +.sym 77079 $0\memadr[10:0][3] +.sym 77080 $0\memadr[10:0][4] +.sym 77081 $0\memadr[10:0][5] +.sym 77082 $0\memadr[10:0][6] +.sym 77083 $0\memadr[10:0][7] +.sym 77084 $0\memadr[10:0][8] +.sym 77085 $0\memadr[10:0][9] +.sym 77086 clk +.sym 77087 $PACKER_VCC_NET +.sym 77088 $PACKER_VCC_NET +.sym 77113 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[18] +.sym 77120 $PACKER_VCC_NET +.sym 77156 $PACKER_GND_NET +.sym 77158 $PACKER_VCC_NET +.sym 77188 $PACKER_GND_NET_$glb_clk +.sym 77189 $PACKER_GND_NET +.sym 77198 $PACKER_VCC_NET +.sym 77219 $0\memadr[10:0][2] +.sym 77222 $PACKER_GND_NET +.sym 77224 $0\memadr[10:0][3] +.sym 77225 $0\memadr[10:0][0] +.sym 77232 $0\memadr[10:0][10] +.sym 77235 $PACKER_VCC_NET +.sym 77236 $0\memadr[10:0][2] +.sym 77237 $0\memadr[10:0][7] +.sym 77241 $0\memadr[10:0][8] +.sym 77242 $0\memadr[10:0][9] +.sym 77243 $0\memadr[10:0][6] +.sym 77244 $0\memadr[10:0][5] +.sym 77247 $0\memadr[10:0][3] +.sym 77250 $0\memadr[10:0][0] +.sym 77251 $0\memadr[10:0][1] +.sym 77252 $0\memadr[10:0][4] +.sym 77258 $PACKER_VCC_NET +.sym 77279 $0\memadr[10:0][0] +.sym 77280 $0\memadr[10:0][1] +.sym 77281 $0\memadr[10:0][10] +.sym 77282 $0\memadr[10:0][2] +.sym 77283 $0\memadr[10:0][3] +.sym 77284 $0\memadr[10:0][4] +.sym 77285 $0\memadr[10:0][5] +.sym 77286 $0\memadr[10:0][6] +.sym 77287 $0\memadr[10:0][7] +.sym 77288 $0\memadr[10:0][8] +.sym 77289 $0\memadr[10:0][9] +.sym 77290 clk +.sym 77291 $PACKER_VCC_NET +.sym 77292 $PACKER_VCC_NET +.sym 77317 $0\memadr[10:0][9] +.sym 77318 $0\memadr[10:0][10] +.sym 77320 $0\memadr[10:0][8] +.sym 77353 $PACKER_VCC_NET +.sym 77360 $PACKER_GND_NET +.sym 77369 $abc$394$n42 +.sym 77392 $PACKER_GND_NET_$glb_clk +.sym 77393 $PACKER_GND_NET +.sym 77402 $PACKER_VCC_NET +.sym 77420 $abc$394$n42 +.sym 77453 $0\memadr[10:0][5] +.sym 77454 $0\memadr[10:0][4] +.sym 77455 $0\memadr[10:0][9] +.sym 77456 $0\memadr[10:0][10] +.sym 77457 $0\memadr[10:0][7] +.sym 77458 $0\memadr[10:0][8] +.sym 77459 $0\memadr[10:0][2] +.sym 77460 $0\memadr[10:0][3] +.sym 77462 $PACKER_VCC_NET +.sym 77463 $0\memadr[10:0][6] +.sym 77464 $PACKER_VCC_NET +.sym 77465 $0\memadr[10:0][0] +.sym 77466 $0\memadr[10:0][1] +.sym 77483 $0\memadr[10:0][0] +.sym 77484 $0\memadr[10:0][1] +.sym 77485 $0\memadr[10:0][10] +.sym 77486 $0\memadr[10:0][2] +.sym 77487 $0\memadr[10:0][3] +.sym 77488 $0\memadr[10:0][4] +.sym 77489 $0\memadr[10:0][5] +.sym 77490 $0\memadr[10:0][6] +.sym 77491 $0\memadr[10:0][7] +.sym 77492 $0\memadr[10:0][8] +.sym 77493 $0\memadr[10:0][9] +.sym 77494 clk +.sym 77495 $PACKER_VCC_NET +.sym 77496 $PACKER_VCC_NET +.sym 77524 $abc$394$n41_1 +.sym 77526 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[18] +.sym 77529 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[14] +.sym 77557 $PACKER_VCC_NET +.sym 77564 $PACKER_GND_NET +.sym 77571 $abc$394$n40 +.sym 77576 $abc$394$n43_1 +.sym 77596 $PACKER_GND_NET_$glb_clk +.sym 77597 $PACKER_GND_NET +.sym 77606 $PACKER_VCC_NET +.sym 77623 $0\memadr[10:0][0] +.sym 77624 $0\memadr[10:0][2] +.sym 77625 $0\memadr[10:0][1] +.sym 77626 $0\memadr[10:0][6] +.sym 77629 $0\memadr[10:0][3] +.sym 77630 $PACKER_GND_NET +.sym 77631 $0\memadr[10:0][0] +.sym 77632 $0\memadr[10:0][7] +.sym 77634 $0\memadr[10:0][2] +.sym 77640 $0\memadr[10:0][2] +.sym 77642 $0\memadr[10:0][8] +.sym 77643 $0\memadr[10:0][7] +.sym 77645 $0\memadr[10:0][9] +.sym 77646 $0\memadr[10:0][10] +.sym 77647 $0\memadr[10:0][6] +.sym 77649 $0\memadr[10:0][4] +.sym 77650 $PACKER_VCC_NET +.sym 77652 $PACKER_VCC_NET +.sym 77654 $0\memadr[10:0][3] +.sym 77656 $0\memadr[10:0][0] +.sym 77657 $0\memadr[10:0][1] +.sym 77670 $0\memadr[10:0][5] +.sym 77687 $0\memadr[10:0][0] +.sym 77688 $0\memadr[10:0][1] +.sym 77689 $0\memadr[10:0][10] +.sym 77690 $0\memadr[10:0][2] +.sym 77691 $0\memadr[10:0][3] +.sym 77692 $0\memadr[10:0][4] +.sym 77693 $0\memadr[10:0][5] +.sym 77694 $0\memadr[10:0][6] +.sym 77695 $0\memadr[10:0][7] +.sym 77696 $0\memadr[10:0][8] +.sym 77697 $0\memadr[10:0][9] +.sym 77698 clk +.sym 77699 $PACKER_VCC_NET +.sym 77700 $PACKER_VCC_NET +.sym 77725 $0\memadr[10:0][8] +.sym 77729 $0\memadr[10:0][8] +.sym 77733 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[30] +.sym 77736 $0\memadr[10:0][9] +.sym 77754 $PACKER_VCC_NET +.sym 77768 $PACKER_GND_NET +.sym 77800 $PACKER_GND_NET_$glb_clk +.sym 77801 $PACKER_GND_NET +.sym 77810 $PACKER_VCC_NET +.sym 77825 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[24] +.sym 77829 $PACKER_GND_NET +.sym 77845 $PACKER_VCC_NET +.sym 77846 $0\memadr[10:0][10] +.sym 77851 $0\memadr[10:0][2] +.sym 77853 $0\memadr[10:0][6] +.sym 77854 $0\memadr[10:0][1] +.sym 77858 $0\memadr[10:0][3] +.sym 77859 $0\memadr[10:0][7] +.sym 77860 $0\memadr[10:0][0] +.sym 77861 $0\memadr[10:0][5] +.sym 77867 $0\memadr[10:0][8] +.sym 77869 $0\memadr[10:0][4] +.sym 77872 $PACKER_VCC_NET +.sym 77874 $0\memadr[10:0][9] +.sym 77891 $0\memadr[10:0][0] +.sym 77892 $0\memadr[10:0][1] +.sym 77893 $0\memadr[10:0][10] +.sym 77894 $0\memadr[10:0][2] +.sym 77895 $0\memadr[10:0][3] +.sym 77896 $0\memadr[10:0][4] +.sym 77897 $0\memadr[10:0][5] +.sym 77898 $0\memadr[10:0][6] +.sym 77899 $0\memadr[10:0][7] +.sym 77900 $0\memadr[10:0][8] +.sym 77901 $0\memadr[10:0][9] +.sym 77902 clk +.sym 77903 $PACKER_VCC_NET +.sym 77904 $PACKER_VCC_NET +.sym 77921 $PACKER_VCC_NET +.sym 77936 $PACKER_VCC_NET +.sym 77937 $0$mem2bits$\mem$memtest.v:32$1[31:0]$35[14] +.sym 77972 $PACKER_GND_NET +.sym 77974 $PACKER_VCC_NET +.sym 78004 $PACKER_GND_NET_$glb_clk +.sym 78005 $PACKER_GND_NET +.sym 78014 $PACKER_VCC_NET +.sym 78031 $0\memadr[10:0][2] +.sym 78032 $0\memadr[10:0][2] +.sym 78033 $0\memadr[10:0][3] +.sym 78034 $0\memadr[10:0][6] +.sym 78036 $0\memadr[10:0][0] +.sym 78037 $0\memadr[10:0][1] +.sym 78038 $PACKER_GND_NET +.sym 78039 $0\memadr[10:0][0] +.sym 78040 $0\memadr[10:0][7] +.sym 78047 $0\memadr[10:0][9] +.sym 78048 $0\memadr[10:0][2] +.sym 78051 $0\memadr[10:0][7] +.sym 78053 $0\memadr[10:0][5] +.sym 78054 $0\memadr[10:0][10] +.sym 78057 $0\memadr[10:0][4] +.sym 78058 $0\memadr[10:0][3] +.sym 78059 $0\memadr[10:0][8] +.sym 78060 $PACKER_VCC_NET +.sym 78061 $0\memadr[10:0][6] +.sym 78062 $0\memadr[10:0][1] +.sym 78064 $0\memadr[10:0][0] +.sym 78074 $PACKER_VCC_NET +.sym 78095 $0\memadr[10:0][0] +.sym 78096 $0\memadr[10:0][1] +.sym 78097 $0\memadr[10:0][10] +.sym 78098 $0\memadr[10:0][2] +.sym 78099 $0\memadr[10:0][3] +.sym 78100 $0\memadr[10:0][4] +.sym 78101 $0\memadr[10:0][5] +.sym 78102 $0\memadr[10:0][6] +.sym 78103 $0\memadr[10:0][7] +.sym 78104 $0\memadr[10:0][8] +.sym 78105 $0\memadr[10:0][9] +.sym 78106 clk +.sym 78107 $PACKER_VCC_NET +.sym 78108 $PACKER_VCC_NET +.sym 78140 $0\memadr[10:0][9] +.sym 78141 $0\memadr[10:0][8] +.sym 78142 $PACKER_VCC_NET +.sym 78162 $PACKER_VCC_NET +.sym 78176 $PACKER_GND_NET +.sym 78208 $PACKER_GND_NET_$glb_clk +.sym 78209 $PACKER_GND_NET +.sym 78218 $PACKER_VCC_NET +.sym 78242 $PACKER_GND_NET +.sym 78253 $PACKER_VCC_NET +.sym 78254 $0\memadr[10:0][10] +.sym 78259 $0\memadr[10:0][2] +.sym 78261 $0\memadr[10:0][6] +.sym 78262 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+FOMU_REV ?= evt3 +ifeq ($(FOMU_REV),evt3) +PCF ?= $(PCF_PATH)/fomu-evt3.pcf +PKG ?= sg48 +PNRFLAGS ?= --up5k --package $(PKG) +else +ifeq ($(FOMU_REV),evt2) +PCF ?= $(PCF_PATH)/fomu-evt2.pcf +PKG ?= sg48 +PNRFLAGS ?= --up5k --package $(PKG) +else +$(error Unrecognized FOMU_REV value. must be "evt2" or "evt3") +endif +endif + +BUILD_DIR = .build +VSOURCES = $(wildcard *.v) +QUIET = @ + +ALL = all +TARGET = $(PACKAGE).bin +CLEAN = clean + +$(ALL): $(TARGET) + +$(BUILD_DIR)/$(PACKAGE).json: $(VSOURCES) | $(BUILD_DIR) + $(QUIET) echo " SYNTH $@" + $(QUIET) $(YOSYS) -p 'synth_ice40 -top $(TOP) -json $@' $(PACKAGE).v + +$(BUILD_DIR)/$(PACKAGE).asc: $(BUILD_DIR)/$(PACKAGE).json $(PCF) + $(QUIET) echo " PNR $@" + $(QUIET) $(NEXTPNR) $(PNRFLAGS) --json $(BUILD_DIR)/$(PACKAGE).json --pcf $(PCF) --asc $@ + +$(TARGET): $(BUILD_DIR)/$(PACKAGE).asc + $(QUIET) echo " PACK $@" + $(QUIET) $(ICEPACK) $(BUILD_DIR)/$(PACKAGE).asc $@ + +$(BUILD_DIR): + $(QUIET) mkdir $(BUILD_DIR) + +.PHONY: clean + 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+00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/memtest/fomu-evt3.pcf b/memtest/fomu-evt3.pcf new file mode 100644 index 0000000..be1b1a7 --- /dev/null +++ b/memtest/fomu-evt3.pcf @@ -0,0 +1,41 @@ +set_io led_r 39 +set_io led_b 40 +set_io led_g 41 +set_io pmod_1 28 +set_io pmod_2 27 +set_io pmod_3 26 +set_io pmod_4 23 +set_io pmoda_1 28 +set_io pmoda_2 27 +set_io pmoda_3 26 +set_io pmoda_4 23 +set_io clki_alt 20 +set_io clki 44 +set_io user_1 48 +set_io user_2 47 +set_io user_3 46 +set_io user_4 45 +set_io user_5 42 +set_io user_6 38 +set_io pmodb_1 48 +set_io pmodb_2 47 +set_io pmodb_3 46 +set_io pmodb_4 45 +set_io spi_mosi 14 +set_io spi_miso 17 +set_io spi_clk 15 +set_io spi_io2 18 +set_io spi_io3 19 +set_io spi_cs 16 +set_io uart_tx 21 +set_io uart_rx 13 +set_io usb_dn 37 +set_io usb_dp 34 +set_io usb_dp_pu 35 +set_io usb_dn_pu 36 +set_io dbg_1 20 +set_io dbg_2 12 +set_io dbg_3 11 +set_io dbg_4 25 +set_io dbg_5 10 +set_io dbg_6 9 diff --git a/memtest/mem.init b/memtest/mem.init new file mode 100644 index 0000000..82fec4e --- /dev/null +++ b/memtest/mem.init @@ -0,0 +1,2048 @@ +9823b6e +4fc5ac4c +1e48e7cc +42e1ed90 +c1bbe5a2 +5f497e20 +96bba0ba +aaf605cc +628c0df0 +35a509d4 +99864d5e +bb3cac2 +e64c89b4 +413a11c0 +1d847294 +746355c6 +6f5738f4 +a8675c86 +a2fb2462 +f995dd22 +9324d654 +3faf6814 +4747602e +1f7be838 +9872b782 +fba90b48 +f95accdc +6729e6a6 +ea1c042e +b2114f30 +e4396d98 +f9141e44 +24ee4480 +d169f766 +aa2d15a4 +109a7d78 +dd572dc6 +83feecec +5f2f72fe +d80ecdd0 +121249fa +609f520e +5944414c +95622b7e +1863f998 +5aeef480 +ec85cebc +8d76ba5e +14d26bbe +a3a93eda +dd2c3ff6 +8cceb13a +ffacca7c +13140a5e +7711c28 +9b80a93a +b068b1f8 +4fc85dc8 +e99e636c +1266d774 +df8560de +89e2ab4e +71c604ec +333c422a +c5914254 +c7c016c8 +9db579fa +b3629010 +e594d27e +5c75d6a6 +5d855f64 +7c52c336 +8a0364d8 +637a50e2 +c9f127e4 +a784b03e +239da172 +2967e354 +7dc3dcb6 +e9161054 +8641d8ae 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output pmod_1, + output pmod_2, + output pmod_3, + output pmod_4, + input user_5, + input user_6, + input clki +); + + reg [31:0] mem[0:2047]; + reg [10:0] memadr; + assign random_rom_dat_r = mem[memadr]; + + wire clkosc; + SB_GB clk_gb ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(clki), + .GLOBAL_BUFFER_OUTPUT(clkosc) + ); + assign clk = clkosc; + + initial begin + $readmemh("empty.init", mem); + end + + always @(posedge clk) begin + memadr <= memadr + 1; + led_r <= + mem[memadr][0] ^ + mem[memadr][1] ^ + mem[memadr][2] ^ + mem[memadr][3] ^ + mem[memadr][4] ^ + mem[memadr][5] ^ + mem[memadr][6] ^ + mem[memadr][7] ^ + mem[memadr][8] ^ + mem[memadr][9] ^ + mem[memadr][10] ^ + mem[memadr][11] ^ + mem[memadr][12] ^ + mem[memadr][13] ^ + mem[memadr][14] ^ + mem[memadr][15] ^ + mem[memadr][16] ^ + mem[memadr][17] ^ + mem[memadr][18] ^ + mem[memadr][19] ^ + mem[memadr][20] ^ + mem[memadr][21] ^ + mem[memadr][22] ^ + mem[memadr][23] ^ + mem[memadr][24] ^ + mem[memadr][25] ^ + mem[memadr][26] ^ + mem[memadr][27] ^ + mem[memadr][28] ^ + mem[memadr][29] ^ + mem[memadr][30] ^ + mem[memadr][31]; + end + + +endmodule \ No newline at end of file diff --git a/memtest/top.rpt b/memtest/top.rpt new file mode 100644 index 0000000..2d5e125 --- /dev/null +++ b/memtest/top.rpt @@ -0,0 +1,1728 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2018 Clifford Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG) + + +-- Parsing `memtest.v' using frontend `verilog' -- + +1. Executing Verilog-2005 frontend. +Parsing Verilog input from `memtest.v' to AST representation. +Generating RTLIL representation for module `\memtest'. +Warning: wire '\led_r' is assigned in a block at memtest.v:63. +memtest.v:16: Warning: Identifier `\random_rom_dat_r' is implicitly declared. +memtest.v:23: Warning: Identifier `\clk' is implicitly declared. +Successfully finished Verilog frontend. + +-- Running command `synth_ice40 -top memtest -json .build/memtest.json' -- + +2. Executing SYNTH_ICE40 pass. + +2.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\SB_IO'. +Generating RTLIL representation for module `\SB_GB_IO'. +Generating RTLIL representation for module `\SB_GB'. +Generating RTLIL representation for module `\SB_LUT4'. +Generating RTLIL representation for module `\SB_CARRY'. +Generating RTLIL representation for module `\SB_DFF'. +Generating RTLIL representation for module `\SB_DFFE'. +Generating RTLIL representation for module `\SB_DFFSR'. +Generating RTLIL representation for module `\SB_DFFR'. +Generating RTLIL representation for module `\SB_DFFSS'. +Generating RTLIL representation for module `\SB_DFFS'. +Generating RTLIL representation for module `\SB_DFFESR'. +Generating RTLIL representation for module `\SB_DFFER'. +Generating RTLIL representation for module `\SB_DFFESS'. +Generating RTLIL representation for module `\SB_DFFES'. +Generating RTLIL representation for module `\SB_DFFN'. +Generating RTLIL representation for module `\SB_DFFNE'. +Generating RTLIL representation for module `\SB_DFFNSR'. +Generating RTLIL representation for module `\SB_DFFNR'. +Generating RTLIL representation for module `\SB_DFFNSS'. +Generating RTLIL representation for module `\SB_DFFNS'. +Generating RTLIL representation for module `\SB_DFFNESR'. +Generating RTLIL representation for module `\SB_DFFNER'. +Generating RTLIL representation for module `\SB_DFFNESS'. +Generating RTLIL representation for module `\SB_DFFNES'. +Generating RTLIL representation for module `\SB_RAM40_4K'. +Generating RTLIL representation for module `\SB_RAM40_4KNR'. +Generating RTLIL representation for module `\SB_RAM40_4KNW'. +Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. +Generating RTLIL representation for module `\ICESTORM_LC'. +Generating RTLIL representation for module `\SB_PLL40_CORE'. +Generating RTLIL representation for module `\SB_PLL40_PAD'. +Generating RTLIL representation for module `\SB_PLL40_2_PAD'. +Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. +Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. +Generating RTLIL representation for module `\SB_WARMBOOT'. +Generating RTLIL representation for module `\SB_MAC16'. +Generating RTLIL representation for module `\SB_SPRAM256KA'. +Generating RTLIL representation for module `\SB_HFOSC'. +Generating RTLIL representation for module `\SB_LFOSC'. +Generating RTLIL representation for module `\SB_RGBA_DRV'. +Generating RTLIL representation for module `\SB_I2C'. +Generating RTLIL representation for module `\SB_SPI'. +Generating RTLIL representation for module `\SB_LEDDA_IP'. +Generating RTLIL representation for module `\SB_FILTER_50NS'. +Generating RTLIL representation for module `\SB_IO_I3C'. +Generating RTLIL representation for module `\SB_IO_OD'. +Successfully finished Verilog frontend. + +2.2. Executing HIERARCHY pass (managing design hierarchy). + +2.2.1. Analyzing design hierarchy.. +Top module: \memtest + +2.2.2. Analyzing design hierarchy.. +Top module: \memtest +Removed 0 unused modules. + +2.3. Executing PROC pass (convert processes to netlists). + +2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `memtest.$proc$memtest.v:25$132'. +Cleaned up 0 empty switches. + +2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +2.3.3. Executing PROC_INIT pass (extract init attributes). + +2.3.4. Executing PROC_ARST pass (detect async resets in processes). + +2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\memtest.$proc$memtest.v:29$34'. + 1/34: $0\led_r[0:0] + 2/34: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66 + 3/34: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65 + 4/34: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64 + 5/34: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63 + 6/34: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62 + 7/34: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61 + 8/34: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60 + 9/34: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59 + 10/34: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58 + 11/34: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57 + 12/34: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56 + 13/34: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55 + 14/34: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54 + 15/34: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53 + 16/34: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52 + 17/34: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51 + 18/34: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50 + 19/34: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49 + 20/34: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48 + 21/34: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47 + 22/34: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46 + 23/34: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45 + 24/34: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44 + 25/34: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43 + 26/34: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42 + 27/34: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41 + 28/34: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40 + 29/34: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39 + 30/34: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38 + 31/34: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37 + 32/34: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36 + 33/34: $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + 34/34: $0\memadr[10:0] + +2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\memtest.\led_r' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$133' with positive edge clock. +Creating register for signal `\memtest.\memadr' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$134' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:32$1' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$135' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:33$2' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$136' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:34$3' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$137' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:35$4' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$138' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:36$5' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$139' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:37$6' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$140' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:38$7' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$141' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:39$8' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$142' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:40$9' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$143' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:41$10' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$144' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:42$11' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$145' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:43$12' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$146' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:44$13' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$147' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:45$14' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$148' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:46$15' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$149' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:47$16' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$150' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:48$17' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$151' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:49$18' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$152' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:50$19' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$153' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:51$20' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$154' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:52$21' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$155' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:53$22' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$156' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:54$23' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$157' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:55$24' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$158' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:56$25' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$159' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:57$26' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$160' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:58$27' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$161' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:59$28' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$162' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:60$29' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$163' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:61$30' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$164' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:62$31' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$165' with positive edge clock. +Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:63$32' using process `\memtest.$proc$memtest.v:29$34'. + created $dff cell `$procdff$166' with positive edge clock. + +2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `memtest.$proc$memtest.v:29$34'. +Cleaned up 0 empty switches. + +2.4. Executing FLATTEN pass (flatten design). +No more expansions possible. + +2.5. Executing TRIBUF pass. + +2.6. Executing DEMINOUT pass (demote inout ports to input or output). + +2.7. Executing SYNTH pass. + +2.7.1. Executing PROC pass (convert processes to netlists). + +2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +2.7.1.3. Executing PROC_INIT pass (extract init attributes). + +2.7.1.4. Executing PROC_ARST pass (detect async resets in processes). + +2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers). + +2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs). + +2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.7.2. Executing OPT_EXPR pass (perform const folding). + +2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removing unused `$memrd' cell `$memrd$\mem$memtest.v:16$33'. + removing unused `$dff' cell `$procdff$135'. + removing unused `$dff' cell `$procdff$136'. + removing unused `$dff' cell `$procdff$137'. + removing unused `$dff' cell `$procdff$138'. + removing unused `$dff' cell `$procdff$139'. + removing unused `$dff' cell `$procdff$140'. + removing unused `$dff' cell `$procdff$141'. + removing unused `$dff' cell `$procdff$142'. + removing unused `$dff' cell `$procdff$143'. + removing unused `$dff' cell `$procdff$144'. + removing unused `$dff' cell `$procdff$145'. + removing unused `$dff' cell `$procdff$146'. + removing unused `$dff' cell `$procdff$147'. + removing unused `$dff' cell `$procdff$148'. + removing unused `$dff' cell `$procdff$149'. + removing unused `$dff' cell `$procdff$150'. + removing unused `$dff' cell `$procdff$151'. + removing unused `$dff' cell `$procdff$152'. + removing unused `$dff' cell `$procdff$153'. + removing unused `$dff' cell `$procdff$154'. + removing unused `$dff' cell `$procdff$155'. + removing unused `$dff' cell `$procdff$156'. + removing unused `$dff' cell `$procdff$157'. + removing unused `$dff' cell `$procdff$158'. + removing unused `$dff' cell `$procdff$159'. + removing unused `$dff' cell `$procdff$160'. + removing unused `$dff' cell `$procdff$161'. + removing unused `$dff' cell `$procdff$162'. + removing unused `$dff' cell `$procdff$163'. + removing unused `$dff' cell `$procdff$164'. + removing unused `$dff' cell `$procdff$165'. + removing unused `$dff' cell `$procdff$166'. + removing unused non-port wire \random_rom_dat_r. + removed 67 unused temporary wires. +Removed 33 unused cells and 67 unused wires. + +2.7.4. Executing CHECK pass (checking for obvious problems). +checking module memtest.. +Warning: Wire memtest.\pmod_4 is used but has no driver. +Warning: Wire memtest.\pmod_3 is used but has no driver. +Warning: Wire memtest.\pmod_2 is used but has no driver. +Warning: Wire memtest.\pmod_1 is used but has no driver. +Warning: Wire memtest.\led_g is used but has no driver. +Warning: Wire memtest.\led_b is used but has no driver. +found and reported 6 problems. + +2.7.5. Executing OPT pass (performing simple optimizations). + +2.7.5.1. Executing OPT_EXPR pass (perform const folding). + +2.7.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. + Cell `$memrd$\mem$memtest.v:33$69' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:33$69' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:34$70' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:34$70' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:35$71' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:35$71' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:36$72' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:36$72' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:37$73' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:37$73' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:38$74' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:38$74' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:39$75' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:39$75' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:40$76' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:40$76' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:41$77' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:41$77' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:42$78' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:42$78' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:43$79' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:43$79' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:44$80' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:44$80' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:45$81' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:45$81' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:46$82' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:46$82' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:47$83' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:47$83' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:48$84' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:48$84' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:49$85' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:49$85' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:50$86' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:50$86' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:51$87' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:51$87' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:52$88' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:52$88' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:53$89' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:53$89' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:54$90' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:54$90' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:55$91' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:55$91' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:56$92' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:56$92' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:57$93' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:57$93' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:58$94' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:58$94' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:59$95' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:59$95' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:60$96' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:60$96' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:61$97' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:61$97' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:62$98' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:62$98' from module `\memtest'. + Cell `$memrd$\mem$memtest.v:63$99' is identical to cell `$memrd$\mem$memtest.v:32$68'. + Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35 + Removing $memrd cell `$memrd$\mem$memtest.v:63$99' from module `\memtest'. +Removed a total of 31 cells. + +2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest. +Performed a total of 0 changes. + +2.7.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values). + +2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removed 31 unused temporary wires. +Removed 33 unused cells and 98 unused wires. + +2.7.5.8. Executing OPT_EXPR pass (perform const folding). + +2.7.5.9. Finished OPT passes. (There is nothing left to do.) + +2.7.6. Executing WREDUCE pass (reducing word size of cells). +Removed top 21 address bits (of 32) from memory init port memtest.$meminit$\mem$memtest.v:26$131 (mem). +Removed top 31 bits (of 32) from port B of cell memtest.$add$memtest.v:30$67 ($add). +Removed top 21 bits (of 32) from port Y of cell memtest.$add$memtest.v:30$67 ($add). + +2.7.7. Executing TECHMAP pass (map to technology primitives). + +2.7.7.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. +No more expansions possible. + +2.7.8. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module memtest: + creating $macc model for $add$memtest.v:30$67 ($add). + creating $alu model for $macc $add$memtest.v:30$67. + creating $alu cell for $add$memtest.v:30$67: $auto$alumacc.cc:474:replace_alu$167 + created 1 $alu and 0 $macc cells. + +2.7.9. Executing SHARE pass (SAT-based resource sharing). + +2.7.10. Executing OPT pass (performing simple optimizations). + +2.7.10.1. Executing OPT_EXPR pass (perform const folding). + +2.7.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.7.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.7.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest. +Performed a total of 0 changes. + +2.7.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.7.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +2.7.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removed 1 unused temporary wires. +Removed 33 unused cells and 99 unused wires. + +2.7.10.8. Executing OPT_EXPR pass (perform const folding). + +2.7.10.9. Finished OPT passes. (There is nothing left to do.) + +2.7.11. Executing FSM pass (extract and optimize FSM). + +2.7.11.1. Executing FSM_DETECT pass (finding FSMs in design). + +2.7.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +2.7.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 99 unused wires. + +2.7.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.7.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +2.7.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +2.7.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +2.7.12. Executing OPT pass (performing simple optimizations). + +2.7.12.1. Executing OPT_EXPR pass (perform const folding). + +2.7.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.7.12.3. Executing OPT_RMDFF pass (remove dff with constant values). + +2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 99 unused wires. + +2.7.12.5. Finished fast OPT passes. + +2.7.13. Executing MEMORY pass. + +2.7.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memrd$\mem$memtest.v:32$68' in module `\memtest': merged address $dff to cell. + +2.7.13.2. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 99 unused wires. + +2.7.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 99 unused wires. + +2.7.13.5. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\memtest': + $meminit$\mem$memtest.v:26$131 ($meminit) + $memrd$\mem$memtest.v:32$68 ($memrd) + +2.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 99 unused wires. + +2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing memtest.mem: + Properties: ports=1 bits=65536 rports=1 wports=0 dbits=32 abits=11 words=2048 + Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): + Bram geometry: abits=8 dbits=16 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. + Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): + Bram geometry: abits=9 dbits=8 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. + Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): + Bram geometry: abits=10 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. + Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): + Bram geometry: abits=11 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. + Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Selecting best of 4 rules: + Efficiency for rule 2.3: efficiency=100, cells=16, acells=1 + Efficiency for rule 2.2: efficiency=100, cells=16, acells=2 + Efficiency for rule 2.1: efficiency=100, cells=16, acells=4 + Efficiency for rule 1.1: efficiency=100, cells=16, acells=8 + Selected rule 2.3 with efficiency 100. + Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: mem.0.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: mem.1.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: mem.2.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: mem.3.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <4 0 0>: mem.4.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <5 0 0>: mem.5.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <6 0 0>: mem.6.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <7 0 0>: mem.7.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <8 0 0>: mem.8.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <9 0 0>: mem.9.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <10 0 0>: mem.10.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <11 0 0>: mem.11.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <12 0 0>: mem.12.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <13 0 0>: mem.13.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <14 0 0>: mem.14.0.0 + Creating $__ICE40_RAM4K_M123 cell at grid position <15 0 0>: mem.15.0.0 + +2.9. Executing TECHMAP pass (map to technology primitives). + +2.9.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ICE40_RAM4K'. +Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. +Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. +Successfully finished Verilog frontend. + +2.9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'. +Parameter \CFG_ABITS = 11 +Parameter \CFG_DBITS = 2 +Parameter \CLKPOL2 = 1 +Parameter \INIT = 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Generating RTLIL representation for module `$paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123'. + +2.9.3. Continuing TECHMAP pass. +Mapping memtest.mem.0.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.1.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.2.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.3.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.4.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.5.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.6.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. + +2.9.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'. +Parameter \CFG_ABITS = 11 +Parameter \CFG_DBITS = 2 +Parameter \CLKPOL2 = 1 +Parameter \INIT = 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +Generating RTLIL representation for module `$paramod$214e7d8d8d18244b8a4e8f431eec90e369896474\$__ICE40_RAM4K_M123'. + +2.9.5. Continuing TECHMAP pass. +Mapping memtest.mem.15.0.0 using $paramod$214e7d8d8d18244b8a4e8f431eec90e369896474\$__ICE40_RAM4K_M123. +Mapping memtest.mem.14.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.13.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.12.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.11.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.10.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.9.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.8.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. +Mapping memtest.mem.7.0.0 using $paramod$7b81346494518e454acabe0976121af63a9de2c6\$__ICE40_RAM4K_M123. + +2.9.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'. +Parameter \READ_MODE = 3 +Parameter \WRITE_MODE = 3 +Parameter \NEGCLK_R = 1'0 +Parameter \NEGCLK_W = 1'0 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Generating RTLIL representation for module `$paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K'. + +2.9.7. Continuing TECHMAP pass. +Mapping memtest.mem.0.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.1.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.2.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.3.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.4.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.5.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.6.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. + +2.9.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'. +Parameter \READ_MODE = 3 +Parameter \WRITE_MODE = 3 +Parameter \NEGCLK_R = 1'0 +Parameter \NEGCLK_W = 1'0 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Generating RTLIL representation for module `$paramod$6b65790f63d533af747fa735f04ceab83c6a4652\$__ICE40_RAM4K'. + +2.9.9. Continuing TECHMAP pass. +Mapping memtest.mem.15.0.0 using $paramod$6b65790f63d533af747fa735f04ceab83c6a4652\$__ICE40_RAM4K. +Mapping memtest.mem.14.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.13.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.12.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.11.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.10.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.9.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.8.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +Mapping memtest.mem.7.0.0 using $paramod$4ccb0d48d9d6e7f5f9abc633f56014afb4bede02\$__ICE40_RAM4K. +No more expansions possible. + +2.10. Executing OPT pass (performing simple optimizations). + +2.10.1. Executing OPT_EXPR pass (perform const folding). +Setting undriven signal in memtest to undef: $techmap223\mem.7.0.0.MASK +Setting undriven signal in memtest to undef: $techmap222\mem.8.0.0.MASK +Setting undriven signal in memtest to undef: $techmap221\mem.9.0.0.MASK +Setting undriven signal in memtest to undef: $techmap220\mem.10.0.0.MASK +Setting undriven signal in memtest to undef: $techmap219\mem.11.0.0.MASK +Setting undriven signal in memtest to undef: $techmap218\mem.12.0.0.MASK +Setting undriven signal in memtest to undef: $techmap217\mem.13.0.0.MASK +Setting undriven signal in memtest to undef: $techmap216\mem.14.0.0.MASK +Setting undriven signal in memtest to undef: $techmap215\mem.15.0.0.MASK +Setting undriven signal in memtest to undef: $techmap214\mem.6.0.0.MASK +Setting undriven signal in memtest to undef: $techmap213\mem.5.0.0.MASK +Setting undriven signal in memtest to undef: $techmap212\mem.4.0.0.MASK +Setting undriven signal in memtest to undef: $techmap211\mem.3.0.0.MASK +Setting undriven signal in memtest to undef: $techmap210\mem.2.0.0.MASK +Setting undriven signal in memtest to undef: $techmap209\mem.1.0.0.MASK +Setting undriven signal in memtest to undef: $techmap208\mem.0.0.0.MASK +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [15] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [8] +Setting undriven signal in memtest to undef: \pmod_1 +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [14:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [10] +Setting undriven signal in memtest to undef: \led_b +Setting undriven signal in memtest to undef: \led_g +Setting undriven signal in memtest to undef: \pmod_2 +Setting undriven signal in memtest to undef: \pmod_4 +Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap207\mem.7.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap195\mem.4.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap206\mem.8.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [1] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [4] +Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap205\mem.9.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [0] +Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap204\mem.10.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [7:4] +Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [0] +Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap203\mem.11.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [2:1] +Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap194\mem.3.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [5] +Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap202\mem.12.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap201\mem.13.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [10:8] +Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [12] +Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap200\mem.14.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap192\mem.1.0.0.B1DATA_16 [15:13] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [7] +Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [4] +Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap199\mem.15.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [9] +Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [10:5] +Setting undriven signal in memtest to undef: $techmap193\mem.2.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [6] +Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap197\mem.6.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: \pmod_3 +Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [2:0] +Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [10:4] +Setting undriven signal in memtest to undef: $techmap196\mem.5.0.0.B1DATA_16 [15:12] +Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [2] +Replacing $reduce_or cell `$techmap$techmap194\mem.3.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap194\mem.3.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap193\mem.2.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap193\mem.2.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap192\mem.1.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap192\mem.1.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap191\mem.0.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap191\mem.0.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap196\mem.5.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap196\mem.5.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap195\mem.4.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap195\mem.4.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap197\mem.6.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap197\mem.6.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap199\mem.15.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$198' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap199\mem.15.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$198_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap200\mem.14.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap200\mem.14.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap201\mem.13.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap201\mem.13.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap202\mem.12.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap202\mem.12.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap203\mem.11.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap203\mem.11.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap204\mem.10.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap204\mem.10.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap205\mem.9.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap205\mem.9.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap206\mem.8.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap206\mem.8.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. +Replacing $reduce_or cell `$techmap$techmap207\mem.7.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap207\mem.7.0.0.$reduce_or$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'. + +2.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.10.3. Executing OPT_RMDFF pass (remove dff with constant values). + +2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removed 384 unused temporary wires. +Removed 33 unused cells and 483 unused wires. + +2.10.5. Finished fast OPT passes. + +2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). + +2.12. Executing OPT pass (performing simple optimizations). + +2.12.1. Executing OPT_EXPR pass (perform const folding). + +2.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest. +Performed a total of 0 changes. + +2.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.12.6. Executing OPT_RMDFF pass (remove dff with constant values). + +2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 33 unused cells and 483 unused wires. + +2.12.8. Executing OPT_EXPR pass (perform const folding). + +2.12.9. Finished OPT passes. (There is nothing left to do.) + +2.13. Executing TECHMAP pass (map to technology primitives). + +2.13.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +2.13.2. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ice40_alu'. +Successfully finished Verilog frontend. + +2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. +Parameter \A_SIGNED = 0 +Parameter \B_SIGNED = 0 +Parameter \A_WIDTH = 1 +Parameter \B_WIDTH = 11 +Parameter \Y_WIDTH = 11 +Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11'. + +2.13.4. Continuing TECHMAP pass. +Mapping memtest.$auto$alumacc.cc:474:replace_alu$167 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11. +Mapping memtest.$xor$memtest.v:33$100 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:34$101 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:35$102 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:36$103 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:37$104 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:38$105 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:39$106 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:40$107 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:41$108 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:42$109 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:43$110 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:44$111 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:45$112 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:46$113 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:47$114 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:48$115 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:49$116 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:50$117 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:51$118 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:52$119 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:53$120 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:54$121 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:55$122 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:56$123 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:57$124 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:58$125 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:59$126 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:60$127 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:61$128 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:62$129 ($xor) with simplemap. +Mapping memtest.$xor$memtest.v:63$130 ($xor) with simplemap. +Mapping memtest.$procdff$133 ($dff) with simplemap. +Mapping memtest.$procdff$134 ($dff) with simplemap. +Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.A_conv ($pos) with simplemap. +Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.B_conv ($pos) with simplemap. +Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$not$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$271 ($not) with simplemap. +Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272 ($mux) with simplemap. +Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273 ($xor) with simplemap. +No more expansions possible. + +2.14. Executing ICE40_OPT pass (performing simple optimizations). + +2.14.1. Running ICE40 specific optimizations. + +2.14.2. Executing OPT_EXPR pass (perform const folding). +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$332' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [4] = \memadr [4]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$343' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [4] = \memadr [4]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$338' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [10] = \memadr [10]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$328' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [0] = \memadr [0]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$329' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [1] = \memadr [1]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$340' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [1] = \memadr [1]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$330' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [2] = \memadr [2]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$341' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [2] = \memadr [2]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$331' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [3] = \memadr [3]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$342' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [3] = \memadr [3]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$336' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [8] = \memadr [8]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$334' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [6] = \memadr [6]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$349' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [10] = \memadr [10]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$337' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [9] = \memadr [9]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$348' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [9] = \memadr [9]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$333' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [5] = \memadr [5]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$344' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [5] = \memadr [5]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$347' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [8] = \memadr [8]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$335' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:42$272_Y [7] = \memadr [7]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$346' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [7] = \memadr [7]'. +Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$345' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/arith_map.v:68$273_Y [6] = \memadr [6]'. + +2.14.3. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.14.4. Executing OPT_RMDFF pass (remove dff with constant values). + +2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$317'. + removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$339'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$319'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$324'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$320'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$323'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$327'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$322'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$326'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$321'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$325'. + removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$318'. + removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[10].carry'. + removed 17 unused temporary wires. +Removed 46 unused cells and 500 unused wires. + +2.14.6. Rerunning OPT passes. (Removed registers in this run.) + +2.14.7. Running ICE40 specific optimizations. +Optimized away SB_CARRY cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[0].carry: CO=\memadr [0] +Mapping SB_LUT4 cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[1].adder back to logic. + +2.14.8. Executing OPT_EXPR pass (perform const folding). +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$352' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [1] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$351' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [0] = 1'0'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$360' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [0] = 1'0'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$353' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [2] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$354' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [3] = 1'0'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$361' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [1] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$365' (01?) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [0] = \memadr [1]'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$356' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [5] = 1'0'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$355' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [4] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$362' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [2] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$357' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [6] = 1'0'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$358' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$350 [7] = 1'1'. +Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$363' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$359 [3] = 1'0'. + +2.14.9. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.14.10. Executing OPT_RMDFF pass (remove dff with constant values). + +2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removed 3 unused temporary wires. +Removed 46 unused cells and 503 unused wires. + +2.14.12. Rerunning OPT passes. (Removed registers in this run.) + +2.14.13. Running ICE40 specific optimizations. + +2.14.14. Executing OPT_EXPR pass (perform const folding). + +2.14.15. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.14.16. Executing OPT_RMDFF pass (remove dff with constant values). + +2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. +Removed 46 unused cells and 503 unused wires. + +2.14.18. Finished OPT passes. (There is nothing left to do.) + +2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). + +2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). +Selected cell types for direct conversion: + $_DFF_PP1_ -> $__DFFE_PP1 + $_DFF_PP0_ -> $__DFFE_PP0 + $_DFF_PN1_ -> $__DFFE_PN1 + $_DFF_PN0_ -> $__DFFE_PN0 + $_DFF_NP1_ -> $__DFFE_NP1 + $_DFF_NP0_ -> $__DFFE_NP0 + $_DFF_NN1_ -> $__DFFE_NN1 + $_DFF_NN0_ -> $__DFFE_NN0 + $_DFF_N_ -> $_DFFE_NP_ + $_DFF_P_ -> $_DFFE_PP_ +Transforming FF to FF+Enable cells in module memtest: + +2.17. Executing TECHMAP pass (map to technology primitives). + +2.17.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$__DFFE_NN0'. +Generating RTLIL representation for module `\$__DFFE_NN1'. +Generating RTLIL representation for module `\$__DFFE_PN0'. +Generating RTLIL representation for module `\$__DFFE_PN1'. +Generating RTLIL representation for module `\$__DFFE_NP0'. +Generating RTLIL representation for module `\$__DFFE_NP1'. +Generating RTLIL representation for module `\$__DFFE_PP0'. +Generating RTLIL representation for module `\$__DFFE_PP1'. +Successfully finished Verilog frontend. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$306 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$311 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$307 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$316 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$310 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$315 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$314 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$309 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$313 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$308 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$312 using \$_DFF_P_. +Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$305 using \$_DFF_P_. +No more expansions possible. + +2.18. Executing OPT_EXPR pass (perform const folding). + +2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.20. Executing ICE40_FFINIT pass (implement FF init values). +Handling FF init values in memtest. + +2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). +Merging set/reset $_MUX_ cells into SB_FFs in memtest. + +2.22. Executing ICE40_OPT pass (performing simple optimizations). + +2.22.1. Running ICE40 specific optimizations. + +2.22.2. Executing OPT_EXPR pass (perform const folding). + +2.22.3. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest'. +Removed a total of 0 cells. + +2.22.4. Executing OPT_RMDFF pass (remove dff with constant values). + +2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest.. + removed 36 unused temporary wires. +Removed 46 unused cells and 539 unused wires. + +2.22.6. Finished OPT passes. (There is nothing left to do.) + +2.23. Executing TECHMAP pass (map to technology primitives). + +2.23.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. +No more expansions possible. + +2.24. Executing ABC pass (technology mapping using ABC). + +2.24.1. Extracting gate netlist of module `\memtest' to `/input.blif'.. +Extracted 33 gates and 67 wires to a netlist network with 34 inputs and 2 outputs. + +2.24.1.1. Executing ABC. +Running ABC command: /yosys-abc -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lut /lutdefs.txt +ABC: + strash +ABC: + ifraig +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + dch -f +ABC: + if +ABC: + mfs2 +ABC: + lutpack -S 1 +ABC: + write_blif /output.blif + +2.24.1.2. Re-integrating ABC results. +ABC RESULTS: $lut cells: 26 +ABC RESULTS: internal signals: 31 +ABC RESULTS: input signals: 34 +ABC RESULTS: output signals: 2 +Removing temp directory. +Removed 0 unused cells and 67 unused wires. + +2.25. Executing TECHMAP pass (map to technology primitives). + +2.25.1. Executing Verilog-2005 frontend. +Parsing Verilog input from `C:\PROGRA~3\icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$__DFFE_NN0'. +Generating RTLIL representation for module `\$__DFFE_NN1'. +Generating RTLIL representation for module `\$__DFFE_PN0'. +Generating RTLIL representation for module `\$__DFFE_PN1'. +Generating RTLIL representation for module `\$__DFFE_NP0'. +Generating RTLIL representation for module `\$__DFFE_NP1'. +Generating RTLIL representation for module `\$__DFFE_PP0'. +Generating RTLIL representation for module `\$__DFFE_PP1'. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. +Parameter \WIDTH = 2 +Parameter \LUT = 4'0110 +Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0110'. + +2.25.3. Continuing TECHMAP pass. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$395 using $paramod\$lut\WIDTH=2\LUT=4'0110. + +2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. +Parameter \WIDTH = 3 +Parameter \LUT = 8'10010110 +Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10010110'. + +2.25.5. Continuing TECHMAP pass. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$407 using $paramod\$lut\WIDTH=3\LUT=8'10010110. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$406 using $paramod\$lut\WIDTH=3\LUT=8'10010110. + +2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. +Parameter \WIDTH = 4 +Parameter \LUT = 16'0110100110010110 +Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0110100110010110'. + +2.25.7. Continuing TECHMAP pass. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$402 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110. + +2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. +Parameter \WIDTH = 4 +Parameter \LUT = 16'1001011001101001 +Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1001011001101001'. + +2.25.9. Continuing TECHMAP pass. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$403 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001. + +2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. +Parameter \WIDTH = 3 +Parameter \LUT = 8'01101001 +Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'01101001'. + +2.25.11. Continuing TECHMAP pass. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$401 using $paramod\$lut\WIDTH=3\LUT=8'01101001. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$405 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$404 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$398 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$399 using $paramod\$lut\WIDTH=3\LUT=8'10010110. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$400 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$397 using $paramod\$lut\WIDTH=3\LUT=8'10010110. +Mapping memtest.$abc$394$auto$blifparse.cc:492:parse_blif$396 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110. +No more expansions possible. +Removed 0 unused cells and 26 unused wires. + +2.26. Executing HIERARCHY pass (managing design hierarchy). + +2.26.1. Analyzing design hierarchy.. +Top module: \memtest + +2.26.2. Analyzing design hierarchy.. +Top module: \memtest +Removed 0 unused modules. + +2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 4'0110 +Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0110'. + +2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 8'10010110 +Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'. + +2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'1001011001101001 +Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'. + +2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 8'10010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'. + +2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 8'01101001 +Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'01101001'. + +2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'1001011001101001 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'. + +2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'1001011001101001 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'. + +2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 8'10010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'. + +2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 8'10010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'. + +2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. +Parameter \LUT_INIT = 16'0110100110010110 +Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. + +2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Generating RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.28. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.29. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.30. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.31. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.32. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.33. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Generating RTLIL representation for module `$paramod$334b97d74ac2fc34e989b7abd0f6e0033972d758\SB_RAM40_4K'. + +2.26.34. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.35. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.36. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.37. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.38. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.39. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.40. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.26.41. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'. +Parameter \WRITE_MODE = 3 +Parameter \READ_MODE = 3 +Parameter \INIT_0 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_1 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_2 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_3 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_4 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_5 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_6 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_7 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_8 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_9 = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_A = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_B = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_C = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_D = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_E = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Parameter \INIT_F = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Found cached RTLIL representation for module `$paramod$d7198a0eec84a9dbf1058f56bf1e69e919c16fc7\SB_RAM40_4K'. + +2.27. Printing statistics. + +=== memtest === + + Number of wires: 44 + Number of wire bits: 345 + Number of public wires: 13 + Number of public wire bits: 23 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 61 + SB_CARRY 9 + SB_DFF 12 + SB_GB 1 + SB_LUT4 23 + SB_RAM40_4K 16 + +2.28. Executing CHECK pass (checking for obvious problems). +checking module memtest.. +found and reported 0 problems. + +2.29. Executing JSON backend. + +Warnings: 9 unique messages, 9 total +End of script. Logfile hash: af174dade3 +Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG) +Time spent: 2% 14x opt_expr (0 sec), 2% 14x opt_clean (0 sec), ... diff --git a/output.txt b/output.txt new file mode 100644 index 0000000..c52ff73 --- /dev/null +++ b/output.txt @@ -0,0 +1,981 @@ +CRAM data (bank 0): 692 x 336 @ 0x00000000; 232512 bits = 29064 bytes +CRAM data (bank 1): 692 x 176 @ 0x00000000; 121792 bits = 15224 bytes +CRAM data (bank 2): 692 x 336 @ 0x00000000; 232512 bits = 29064 bytes +CRAM data (bank 3): 692 x 176 @ 0x00000000; 121792 bits = 15224 bytes +BRAM data (bank 0): 160 x 128 @ 0x00000000; 20480 bits = 2560 bytes +try 1: +00000000 73 0b 00 00 c3 00 44 1a 62 87 1b 7c ad 9c d0 f0 |s.....D.b..|....| +00000010 5f 1c 07 a6 59 87 00 00 f0 00 e6 45 42 c1 23 9b |_...Y......EB.#.| +00000020 95 bf 30 ef c8 16 40 81 e7 53 00 00 6c 00 d1 0e |..0...@..S..l...| +00000030 6d d7 e4 53 63 0f b6 90 5e 0e de 56 90 74 00 00 |m..Sc...^..V.t..| +00000040 a2 00 d2 aa 5b 96 e1 15 90 be e8 09 c0 c5 96 29 |....[..........)| +00000050 04 34 00 00 a1 00 57 f6 43 c2 f7 58 00 0a 91 e7 |.4....W.C..X....| +00000060 c9 6c ab 4b 70 b4 00 00 94 00 a7 0c b8 74 a8 23 |.l.Kp........t.#| +00000070 7d 37 6a 0b bd c8 3e ad 45 6c 00 00 7f 00 77 8c |}7j...>.El....w.| +00000080 57 fc d5 8e 16 f5 2b 18 23 13 07 31 27 8d 00 00 |W.....+.#..1'...| +00000090 30 00 42 65 0d 83 d3 2d 53 d4 77 4e 94 90 6f 92 |0.Be...-S.wN..o.| +000000a0 00 92 00 00 ba 00 43 1b 65 67 fb a8 56 2a da 27 |......C.eg..V*.'| +000000b0 35 51 fa 76 d2 b3 00 00 2a 00 5a a5 01 4d 17 d0 |5Q.v....*.Z..M..| +000000c0 fe 65 7e 4c 42 0d 36 c7 45 09 00 00 3d 00 80 a9 |.e~LB.6.E...=...| +000000d0 3a 43 31 fe f1 44 e9 5a 70 5f e7 ba 8e bc 00 00 |:C1..D.Zp_......| +000000e0 a9 00 28 68 17 53 8f 00 fd 2a e4 ba 02 06 2f b9 |..(h.S...*..../.| +000000f0 e6 f3 00 00 c0 00 a5 63 e1 2a 0c e1 7a ed 63 3f |.......c.*..z.c?| +00000100 19 d7 be 14 06 8e 00 00 8a 00 87 68 4b 99 36 aa |...........hK.6.| +00000110 08 be a8 15 ae bc c3 a4 0c a1 00 00 8e 00 74 e9 |..............t.| +00000120 2d 5e 05 40 93 75 5a 78 22 b5 14 62 ce 85 00 00 |-^.@.uZx"..b....| +00000130 41 00 2a 3a cd fd 92 e9 aa db 86 bf 24 9a d5 d7 |A.*:........$...| +00000140 5a 99 00 00 64 00 e4 c9 fd 4d fe cd 1d 0f 3a 19 |Z...d....M....:.| +00000150 ff 69 15 01 54 b7 00 00 4f 00 1e 4d 55 16 10 d3 |.i..T...O..MU...| +00000160 8b 76 57 74 d6 ac 0f 49 4e 96 00 00 99 00 93 0e |.vWt...IN.......| +00000170 2e 81 35 09 dc a6 55 ee 13 12 95 c1 e2 e8 00 00 |..5...U.........| +00000180 39 00 3e e1 22 0c 0b 06 53 ac 75 bd 33 f6 b6 b3 |9.>."...S.u.3...| +00000190 8c 43 00 00 9a 00 b8 87 d6 a9 18 1c 82 4c ab 5e |.C...........L.^| +000001a0 46 91 58 ae f8 6b 00 00 f6 00 33 f9 20 52 fd 70 |F.X..k....3. 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82 |............Y...| +000008f0 01 3f 00 00 00 00 00 00 00 00 00 00 3a d9 97 e8 |.?..........:...| +00000900 f0 b4 ff 1f 04 e3 00 00 00 00 00 00 00 00 00 00 |................| +00000910 db 95 a8 4f a6 16 9f 7b ac 5e 00 00 00 00 00 00 |...O...{.^......| +00000920 00 00 00 00 fd 92 69 d0 72 03 d1 ad 58 59 00 00 |......i.r...XY..| +00000930 00 00 00 00 00 00 00 00 15 35 d1 75 19 61 1a 72 |.........5.u.a.r| +00000940 9c f5 00 00 00 00 00 00 00 00 00 00 96 e8 50 74 |..............Pt| +00000950 6c b1 2e f9 33 9f 00 00 00 00 00 00 00 00 00 00 |l...3...........| +00000960 f3 64 fc 7f ca f2 50 6e 45 a7 00 00 00 00 00 00 |.d....PnE.......| +00000970 00 00 00 00 87 81 01 69 f7 20 2b ff 78 81 00 00 |.......i. +.x...| +00000980 00 00 00 00 00 00 00 00 bc 31 4c e3 d0 17 7c ef |.........1L...|.| +00000990 37 c1 00 00 00 00 00 00 00 00 00 00 b4 a0 4c 9d |7.............L.| +000009a0 05 70 fe b2 17 72 00 00 00 00 00 00 00 00 00 00 |.p...r..........| +000009b0 63 76 e5 6d 97 9c 14 cb 49 82 00 00 00 00 00 00 |cv.m....I.......| +000009c0 00 00 00 00 7c 24 42 bf 50 62 07 1b e5 75 00 00 |....|$B.Pb...u..| +000009d0 00 00 00 00 00 00 00 00 33 aa c6 3b f9 0b 97 09 |........3..;....| +000009e0 fb 87 00 00 00 00 00 00 00 00 00 00 cb 01 37 fa |..............7.| +000009f0 85 86 21 2d 38 2e 00 00 00 00 00 00 00 00 00 00 |..!-8...........| +BRAM data (bank 2): 160 x 128 @ 0x00000080; 20480 bits = 2560 bytes +try 1: +00000000 90 df cc 33 88 36 09 60 ff 58 00 00 00 00 00 00 |...3.6.`.X......| +00000010 00 00 00 00 8c fd c7 ca 87 79 f4 ed 2b 59 00 00 |.........y..+Y..| +00000020 00 00 00 00 00 00 00 00 e9 43 bf 49 59 fe 67 c0 |.........C.IY.g.| +00000030 82 00 00 00 00 00 00 00 00 00 00 00 d9 f2 19 d3 |................| +00000040 c5 58 ed f8 f2 25 00 00 00 00 00 00 00 00 00 00 |.X...%..........| +00000050 9f cd 0d 77 e1 69 8e f1 b9 c9 00 00 00 00 00 00 |...w.i..........| +00000060 00 00 00 00 47 b8 b8 45 23 15 84 a2 35 cd 00 00 |....G..E#...5...| +00000070 00 00 00 00 00 00 00 00 0d e3 0d db 7c 64 9e 52 |............|d.R| +00000080 ec 59 00 00 00 00 00 00 00 00 00 00 58 3e b7 72 |.Y..........X>.r| +00000090 b6 12 a3 d1 cb b3 00 00 00 00 00 00 00 00 00 00 |................| +000000a0 38 13 1c 55 ea f3 0c 96 f6 82 00 00 00 00 00 00 |8..U............| +000000b0 00 00 00 00 f5 8b 46 57 d8 b8 0d cc c5 e9 00 00 |......FW........| +000000c0 00 00 00 00 00 00 00 00 35 ba b8 58 68 53 73 cb |........5..XhSs.| +000000d0 23 7a 00 00 00 00 00 00 00 00 00 00 53 0a b2 e6 |#z..........S...| +000000e0 33 76 ba 8c aa 2b 00 00 00 00 00 00 00 00 00 00 |3v...+..........| +000000f0 6a 6e 07 61 2a 8c f2 3d fa e8 00 00 00 00 00 00 |jn.a*..=........| +00000100 00 00 00 00 2b 14 0d 1a 5c 67 c3 0d 02 28 00 00 |....+...\g...(..| +00000110 00 00 00 00 00 00 00 00 48 14 21 fa d8 8f de ad |........H.!.....| +00000120 c7 a7 00 00 00 00 00 00 00 00 00 00 62 88 28 37 |............b.(7| +00000130 5f 0e 37 3c 68 ba 00 00 00 00 00 00 00 00 00 00 |_.7K......| +00000470 00 00 00 00 3a 87 d8 ef 1b b2 d0 8e 41 77 00 00 |....:.......Aw..| +00000480 00 00 00 00 00 00 00 00 00 76 3e b2 db 8d ec bd |.........v>.....| +00000490 08 ea 00 00 00 00 00 00 00 00 00 00 ea a5 eb 83 |................| +000004a0 d5 fa b6 76 a4 d4 00 00 00 00 00 00 00 00 00 00 |...v............| +000004b0 73 37 4e d6 fe 48 bb 5b bf 3a 00 00 00 00 00 00 |s7N..H.[.:......| +000004c0 00 00 00 00 e9 f0 4d 32 b7 f0 98 dd eb 63 00 00 |......M2.....c..| +000004d0 00 00 00 00 00 00 00 00 79 3e 19 eb c0 37 f4 36 |........y>...7.6| +000004e0 2d 11 00 00 00 00 00 00 00 00 00 00 a8 ab e9 56 |-..............V| +000004f0 25 b0 a1 e2 b9 90 00 00 00 00 00 00 00 00 00 00 |%...............| +00000500 7f 2a 09 26 25 e7 d9 18 38 a4 00 00 00 00 00 00 |.*.&%...8.......| +00000510 00 00 00 00 81 5a e6 22 7e 31 30 41 02 02 00 00 |.....Z."~10A....| +00000520 00 00 00 00 00 00 00 00 ac 94 89 ca 53 80 a0 34 |............S..4| +00000530 01 bc 00 00 00 00 00 00 00 00 00 00 0f 6c f7 d9 |.............l..| +00000540 f9 f6 f6 94 c0 f4 00 00 00 00 00 00 00 00 00 00 |................| +00000550 16 b3 85 0f 5e 61 19 d0 4d 7e 00 00 00 00 00 00 |....^a..M~......| +00000560 00 00 00 00 e0 c2 24 68 46 b9 84 3b 2d be 00 00 |......$hF..;-...| +00000570 00 00 00 00 00 00 00 00 99 1f 25 9c a7 3f a9 79 |..........%..?.y| +00000580 4c f5 00 00 00 00 00 00 00 00 00 00 d4 59 d8 87 |L............Y..| +00000590 58 b5 16 45 69 46 00 00 00 00 00 00 00 00 00 00 |X..EiF..........| +000005a0 cc ad 1b 81 bd 08 1a 41 d3 f5 00 00 00 00 00 00 |.......A........| +000005b0 00 00 00 00 a4 d2 3a 1e 70 93 7c 39 eb b3 00 00 |......:.p.|9....| +000005c0 00 00 00 00 00 00 00 00 7a 65 d3 f8 fb 59 70 ff |........ze...Yp.| +000005d0 7f 7b 00 00 00 00 00 00 00 00 00 00 3c 36 92 1d |.{..........<6..| +000005e0 40 29 1b ee 3a f6 00 00 00 00 00 00 00 00 00 00 |@)..:...........| +000005f0 19 b3 11 1a 2a 87 5d 64 e0 7a 00 00 00 00 00 00 |....*.]d.z......| +00000600 00 00 00 00 d2 07 a7 02 89 96 68 3d fb 1d 00 00 |..........h=....| +00000610 00 00 00 00 00 00 00 00 5f 40 34 4f 73 85 2b 90 |........_@4Os.+.| +00000620 e9 4f 00 00 00 00 00 00 00 00 00 00 cc 2f c6 f1 |.O.........../..| +00000630 3e 31 e9 13 26 18 00 00 00 00 00 00 00 00 00 00 |>1..&...........| +00000640 78 c1 3f 2e e8 6a 3c 5c 6d b0 00 00 00 00 00 00 |x.?..j<\m.......| +00000650 00 00 00 00 d1 9a 30 dc 92 b5 50 17 42 f8 00 00 |......0...P.B...| +00000660 00 00 00 00 00 00 00 00 2a d3 11 76 96 74 49 00 |........*..v.tI.| +00000670 d9 ad 00 00 00 00 00 00 00 00 00 00 ae 56 07 36 |.............V.6| +00000680 80 dd ef 02 26 ee 00 00 00 00 00 00 00 00 00 00 |....&...........| +00000690 b2 8b 76 83 1e 2c df 62 ed 1b 00 00 00 00 00 00 |..v..,.b........| +000006a0 00 00 00 00 58 ae 60 32 53 e0 8a 84 3f 7f 00 00 |....X.`2S...?...| +000006b0 00 00 00 00 00 00 00 00 9d 7a 45 c0 25 b4 63 2c |.........zE.%.c,| +000006c0 cd 3c 00 00 00 00 00 00 00 00 00 00 43 75 24 74 |.<..........Cu$t| +000006d0 fb 89 eb 17 eb 7d 00 00 00 00 00 00 00 00 00 00 |.....}..........| +000006e0 06 62 db b5 01 ef 22 fc 37 a3 00 00 00 00 00 00 |.b....".7.......| +000006f0 00 00 00 00 94 9b d5 3f e7 44 d3 75 15 d9 00 00 |.......?.D.u....| +00000700 00 00 00 00 00 00 00 00 c9 b1 83 0d 67 58 08 d0 |............gX..| +00000710 26 df 00 00 00 00 00 00 00 00 00 00 7a 0e dc 22 |&...........z.."| +00000720 d1 d6 ec 9a ea d8 00 00 00 00 00 00 00 00 00 00 |................| +00000730 2d ac 87 24 e1 de 03 e0 96 f6 00 00 00 00 00 00 |-..$............| +00000740 00 00 00 00 2a 78 72 af 7d f4 bd 23 47 6c 00 00 |....*xr.}..#Gl..| +00000750 00 00 00 00 00 00 00 00 82 5c 3b a7 bd b9 dc 25 |.........\;....%| +00000760 44 4c 00 00 00 00 00 00 00 00 00 00 73 01 76 38 |DL..........s.v8| +00000770 ca cb 52 40 29 4f 00 00 00 00 00 00 00 00 00 00 |..R@)O..........| +00000780 d5 fe 70 9f 5d 67 76 0a cf d7 00 00 00 00 00 00 |..p.]gv.........| +00000790 00 00 00 00 d8 37 0a 91 3e c2 59 2a a2 bb 00 00 |.....7..>.Y*....| +000007a0 00 00 00 00 00 00 00 00 c0 29 5d b5 f9 f4 2f 50 |.........)].../P| +000007b0 39 3b 00 00 00 00 00 00 00 00 00 00 b5 ad 06 07 |9;..............| +000007c0 57 17 0d b2 09 b7 00 00 00 00 00 00 00 00 00 00 |W...............| +000007d0 5e 01 fd 7d 83 25 b0 7e e4 13 00 00 00 00 00 00 |^..}.%.~........| +000007e0 00 00 00 00 79 d8 15 9d f4 b3 03 6f 84 f2 00 00 |....y......o....| +000007f0 00 00 00 00 00 00 00 00 93 4a 36 2f cc 2e d1 1a |.........J6/....| +00000800 b3 79 00 00 00 00 00 00 00 00 00 00 93 a7 e9 03 |.y..............| +00000810 3b 64 0c 38 66 ce 00 00 00 00 00 00 00 00 00 00 |;d.8f...........| +00000820 fa d8 dc a3 5e c1 78 a7 9d a7 00 00 00 00 00 00 |....^.x.........| +00000830 00 00 00 00 25 1f 2b 1b c8 22 4c a5 41 f2 00 00 |....%.+.."L.A...| +00000840 00 00 00 00 00 00 00 00 a5 7f ab 78 b3 44 c6 ca |...........x.D..| +00000850 79 11 00 00 00 00 00 00 00 00 00 00 cd 82 53 57 |y.............SW| +00000860 97 7b 18 3d 12 8b 00 00 00 00 00 00 00 00 00 00 |.{.=............| +00000870 2c 04 d7 70 fd af f0 06 78 85 00 00 00 00 00 00 |,..p....x.......| +00000880 00 00 00 00 51 15 83 be 2f 3e 5f bf 12 b7 00 00 |....Q.../>_.....| +00000890 00 00 00 00 00 00 00 00 c3 f1 d2 7c 90 9c c6 ac |...........|....| +000008a0 62 f3 00 00 00 00 00 00 00 00 00 00 3d 3a d4 cb |b...........=:..| +000008b0 ea 38 33 0e c1 20 00 00 00 00 00 00 00 00 00 00 |.83.. ..........| +000008c0 fc dd b7 d4 6a 03 89 e5 1d 66 00 00 00 00 00 00 |....j....f......| +000008d0 00 00 00 00 fc b6 1b eb 1a 8f a3 4c 0f dd 00 00 |...........L....| +000008e0 00 00 00 00 00 00 00 00 f2 d9 74 7c 77 30 7c 61 |..........t|w0|a| +000008f0 ed 20 00 00 00 00 00 00 00 00 00 00 9c 55 13 2c |. ...........U.,| +00000900 5c 48 78 73 0e 5d 00 00 00 00 00 00 00 00 00 00 |\Hxs.]..........| +00000910 f8 0c 14 87 b3 da c2 e3 90 a2 00 00 00 00 00 00 |................| +00000920 00 00 00 00 e3 6f a1 57 b8 fc d8 bd 4e 40 00 00 |.....o.W....N@..| +00000930 00 00 00 00 00 00 00 00 d8 ca 31 91 ab 30 36 2e |..........1..06.| +00000940 53 b5 00 00 00 00 00 00 00 00 00 00 d8 d3 89 f3 |S...............| +00000950 0b e6 00 28 34 93 00 00 00 00 00 00 00 00 00 00 |...(4...........| +00000960 97 ef f3 26 39 f2 49 87 4d d2 00 00 00 00 00 00 |...&9.I.M.......| +00000970 00 00 00 00 61 24 f0 40 d3 be 53 3e 84 1d 00 00 |....a$.@..S>....| +00000980 00 00 00 00 00 00 00 00 08 e9 dc 65 ca 72 95 11 |...........e.r..| +00000990 02 da 00 00 00 00 00 00 00 00 00 00 fc 65 32 99 |.............e2.| +000009a0 bd 68 97 b5 95 bc 00 00 00 00 00 00 00 00 00 00 |.h..............| +000009b0 ba e2 6c 56 23 eb 2b 10 d3 b1 00 00 00 00 00 00 |..lV#.+.........| +000009c0 00 00 00 00 71 8f 72 b5 c4 84 6f 45 f1 ab 00 00 |....q.r...oE....| +000009d0 00 00 00 00 00 00 00 00 40 2f b0 e6 b3 41 01 7f |........@/...A..| +000009e0 0e 6f 00 00 00 00 00 00 00 00 00 00 cc 6d f9 88 |.o...........m..| +000009f0 ae 55 c3 fd a4 a5 00 00 00 00 00 00 00 00 00 00 |.U..............| +BRAM data (bank 3): 80 x 128 @ 0x00000000; 10240 bits = 1280 bytes +try 1: +00000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000150 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000170 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000180 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000190 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000200 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000210 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000220 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000230 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000250 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000260 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000270 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000280 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000290 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000300 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000310 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000330 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000340 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000350 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000360 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000370 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000380 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000390 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000410 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000420 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000430 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000440 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000450 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000460 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000470 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000480 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000490 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +BRAM data (bank 3): 80 x 128 @ 0x00000080; 10240 bits = 1280 bytes +try 1: +00000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000150 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000170 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000180 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000190 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000200 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000210 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000220 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000230 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000250 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000260 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000270 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000280 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000290 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000300 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000310 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000330 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000340 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000350 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000360 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000370 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000380 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000390 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000003f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000410 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000420 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000430 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000440 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000450 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000460 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000470 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000480 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000490 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000004f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +crc check (0000 == 0000) diff --git a/print-hex.c b/print-hex.c new file mode 100644 index 0000000..6a7516a --- /dev/null +++ b/print-hex.c @@ -0,0 +1,37 @@ +#include +#include +#include + +int print_hex_offset(const void *block, int count, int offset, uint32_t start) +{ + int byte; + const uint8_t *b = block; + count += offset; + b -= offset; + for ( ; offset < count; offset += 16) { + printf("%08x", start + offset); + + for (byte = 0; byte < 16; byte++) { + if (byte == 8) + printf(" "); + printf(" "); + if (offset + byte < count) + printf("%02x", b[offset + byte] & 0xff); + else + printf(" "); + } + + printf(" |"); + for (byte = 0; byte < 16 && byte + offset < count; byte++) + printf("%c", isprint(b[offset + byte]) ? + b[offset + byte] : + '.'); + printf("|\n"); + } + return 0; +} + +int print_hex(const void *block, int count, uint32_t start) +{ + return print_hex_offset(block, count, 0, start); +} \ No newline at end of file diff --git a/rewrite-rom b/rewrite-rom new file mode 100644 index 0000000..a0c7842 Binary files /dev/null and b/rewrite-rom differ diff --git a/rewrite-rom.c b/rewrite-rom.c new file mode 100644 index 0000000..9a30628 --- /dev/null +++ b/rewrite-rom.c @@ -0,0 +1,300 @@ +#include +#include +#include +#include +#include +#include +#include + +#define MAX(x, y) (x) > (y) ? (x) : (y) + +typedef struct irw_file +{ + FILE *f; + uint16_t crc; + uint32_t offset; +} IRW_FILE; + +int print_hex_offset(const void *block, int count, int offset, uint32_t start); +int print_hex(const void *block, int count, uint32_t start); + +static void update_crc16(uint16_t *crc, uint8_t byte) +{ + // CRC-16-CCITT, Initialize to 0xFFFF, No zero padding + for (int i = 7; i >= 0; i--) + { + uint16_t xor_value = ((*crc >> 15) ^ ((byte >> i) & 1)) ? 0x1021 : 0; + *crc = (*crc << 1) ^ xor_value; + } +} + +static uint8_t reverse_u8(uint8_t b) +{ + b = (b & 0xF0) >> 4 | (b & 0x0F) << 4; + b = (b & 0xCC) >> 2 | (b & 0x33) << 2; + b = (b & 0xAA) >> 1 | (b & 0x55) << 1; + return b; +} + +struct irw_file *irw_open(const char *filename, const char *mode) +{ + struct irw_file *f = malloc(sizeof(*f)); + memset(f, 0, sizeof(*f)); + f->f = fopen(filename, mode); + return f; +} + +int irw_readb(struct irw_file *f) +{ + int val = fgetc(f->f); + if (val == EOF) + return EOF; + update_crc16(&f->crc, val); + return val; +} + +struct Ice40Bitstream +{ + uint32_t offset; + uint32_t current_bank; + uint32_t current_width; + uint32_t current_height; + uint32_t current_offset; + + uint32_t cram_width; + uint32_t cram_height; + + uint32_t bram_width; + uint32_t bram_height; + + uint16_t crc_value; + + uint8_t warmboot; + uint8_t nosleep; + + uint8_t frequency_range; + + uint8_t bram_banks[4][2560 * 2]; +}; + +struct Ice40Bitstream bs; + +int ice40_find_header(struct irw_file *f) +{ + uint32_t preamble = 0; + uint8_t wakeup = 0; + + memset(&bs, 0, sizeof(bs)); + + while (1) + { + int b = irw_readb(f); + if (b == EOF) + break; + + preamble = (preamble << 8) | b; + if (preamble == 0x7eaa997e) + { + // printf("found preamble at %d\n", bs.offset); + break; + } + } + + while (!wakeup) + { + int b = irw_readb(f); + if (b == EOF) + { + // printf("reached end of file\n"); + break; + } + + uint8_t cmd = b >> 4; + uint8_t payload_len = b & 0xf; + uint32_t payload = 0; + uint8_t last0, last1; + int i; + for (i = 0; i < payload_len; i++) + { + payload = (payload << 8) | (irw_readb(f) & 0xff); + } + + // printf("cmd: %02x payload: %02x payload_len: %d\n", cmd, payload, payload_len); + switch (cmd) + { + case 0: + switch (payload) + { + case 1: + printf("CRAM data (bank %d): %d x %d @ 0x%08x; %d bits = %d bytes\n", + bs.current_bank, + bs.current_width, + bs.current_height, + bs.current_offset, + bs.current_width * bs.current_height, + (bs.current_width * bs.current_height) / 8); + bs.cram_width = MAX(bs.cram_width, bs.current_width); + bs.cram_height = MAX(bs.cram_height, bs.current_height); + for (i = 0; i < ((bs.current_width * bs.current_height) / 8); i++) + { + (void)irw_readb(f); + } + last0 = irw_readb(f); + last1 = irw_readb(f); + if (last0 || last1) + { + printf("expected 0x0000 after CRAM data, got %02x %02x\n", last0, last1); + } + break; + case 3: + { + printf("BRAM data (bank %d): %d x %d @ 0x%08x; %d bits = %d bytes\n", + bs.current_bank, + bs.current_width, + bs.current_height, + bs.current_offset, + bs.current_width * bs.current_height, + (bs.current_width * bs.current_height) / 8); + bs.bram_width = MAX(bs.bram_width, bs.current_width); + bs.bram_height = MAX(bs.bram_height, bs.current_height); + uint8_t try_1[(bs.current_height * bs.current_width) / 8]; + uint8_t try_2[(bs.current_height * bs.current_width) / 8]; + uint8_t try_3[(bs.current_height * bs.current_width) / 8]; + uint8_t try_4[(bs.current_height * bs.current_width) / 8]; + memset(try_1, 0, sizeof(try_1)); + memset(try_2, 0, sizeof(try_2)); + memset(try_3, 0, sizeof(try_3)); + memset(try_4, 0, sizeof(try_4)); + for (i = 0; i < ((bs.current_width * bs.current_height) / 8); i++) + { + uint8_t byte = irw_readb(f); + // int j; + // for (j = 0; j < 8; j++) + // { + // int x = (i * 8 + j) % bs.current_width; + // int y = (i * 8 + j) / bs.current_width;// + bs.current_offset; + // printf("x: %d y: %d\n", x, y); + // try_2[(x * bs.current_width + y) / 8] |= (1 << j); + // } + try_1[i] = byte; + // try_3[i] = reverse_u8(byte); + // try_4[i] = byte; + } + // for (i = 0; i < sizeof(try_4); i += 2) + // { + // uint8_t t = try_4[i]; + // try_4[i] = try_4[i + 1]; + // try_4[i + 1] = t; + // } + printf("try 1:\n"); + print_hex(try_1, sizeof(try_1), 0); + // printf("try 2:\n"); + // print_hex(try_2, sizeof(try_2), 0); + // printf("try 3:\n"); + // print_hex(try_3, sizeof(try_3), 0); + // printf("try 4:\n"); + // print_hex(try_4, sizeof(try_4), 0); + last0 = irw_readb(f); + last1 = irw_readb(f); + if (last0 || last1) + { + printf("expected 0x0000 after BRAM data, got %02x %02x\n", last0, last1); + } + break; + } + case 5: + // printf("resetting crc\n"); + f->crc = 0xffff; + break; + + case 6: + // printf("wakeup\n"); + wakeup = 1; + break; + + default: + printf("unrecognized command 0x%02x 0x%02x\n", cmd, payload); + break; + } + break; + case 1: + bs.current_bank = payload; + // printf("setting bank number to %d\n", bs.current_bank); + break; + case 2: + printf("crc check (%04x == %04x)\n", f->crc, 0); + break; + case 5: + switch (payload) + { + case 0: + bs.frequency_range = 0; + break; + case 1: + bs.frequency_range = 1; + break; + case 2: + bs.frequency_range = 2; + break; + default: + printf("unknown frequency range payload: %02x\n", payload); + break; + } + break; + case 6: + bs.current_width = payload + 1; + // printf("setting bank width to %d\n", bs.current_width); + break; + case 7: + bs.current_height = payload; + // printf("setting bank height to %d\n", bs.current_height); + break; + case 8: + bs.current_offset = payload; + // printf("setting bank offset to %d\n", bs.current_offset); + break; + case 9: + switch (payload) + { + case 0: + bs.warmboot = 0; + bs.nosleep = 0; + break; + case 1: + bs.warmboot = 0; + bs.nosleep = 1; + break; + case 32: + bs.warmboot = 1; + bs.nosleep = 0; + break; + case 33: + bs.warmboot = 1; + bs.nosleep = 1; + break; + default: + printf("unrecognized feature flags: %02x\n", payload); + break; + } + break; + default: + printf("unrecognized command: %02x\n", cmd); + break; + } + } + + // printf("read %d bytes\n", bs.offset); + return 0; +} + +int main(int argc, char **argv) +{ + struct irw_file *f = irw_open("memtest/memtest.bin", "r"); + if (!f) + { + perror("couldn't open top.bin"); + return 1; + } + ice40_find_header(f); + return 0; +} \ No newline at end of file diff --git a/samerand b/samerand new file mode 100644 index 0000000..2655c83 Binary files /dev/null and b/samerand differ diff --git a/samerand.c b/samerand.c new file mode 100644 index 0000000..cd01aed --- /dev/null +++ b/samerand.c @@ -0,0 +1,26 @@ +#include +#include + +uint32_t polynomial = 0x04C11DB7; +static uint32_t rand_step(uint32_t input) { + int i; + uint32_t output = input + 1; + for (i = 0; i < 32; i++) { + if (output & 0x80000000) + output ^= polynomial; + output = output << 1; + } + return output; +} + +int main(int argc, char **argv) { + int i; + + uint32_t init = 0; + for (i = 0; i < 256; i++) { + init = rand_step(init); + printf("%08x\n", init); + } + + return 0; +} \ No newline at end of file diff --git a/samerand.py b/samerand.py new file mode 100644 index 0000000..d6441e5 --- /dev/null +++ b/samerand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 + +# World's worst random number generator +def rand_step(inp): + polynomial = 0x04C11DB7 + output = inp + 1 + for i in range(32): + if output & 0x80000000: + output ^= polynomial + output = (output << 1) & 0xffffffff + return output & 0xffffffff + +def main(): + init = 0 + for i in range(20): + init = rand_step(init) + print("{:08x}".format(init)) + +main() \ No newline at end of file diff --git a/top.bin b/top.bin new file mode 100644 index 0000000..00f6965 Binary files /dev/null and b/top.bin differ diff --git a/top.txt b/top.txt new file mode 100644 index 0000000..b700151 --- /dev/null +++ b/top.txt @@ -0,0 +1,14589 @@ +.comment +.device 5k +.io_tile 1 0 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 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/dev/null and b/xform differ diff --git a/xform.c b/xform.c new file mode 100644 index 0000000..df6bb47 --- /dev/null +++ b/xform.c @@ -0,0 +1,153 @@ +#include +#include + +// bit 0 = input[1792] & (1 << 31) +// bit 1 = input[1792] & (1 << 30) +// bit 2 = input[1536] & (1 << 31) +// bit 3 = input[1536] & (1 << 30) +// bit 4 = input[1280] & (1 << 31) +// bit 5 = input[1280] & (1 << 30) +// bit 6 = input[1024] & (1 << 31) +// bit 7 = input[1024] & (1 << 30) +// bit 8 = input[768] & (1 << 31) +// bit 9 = input[768] & (1 << 30) +// bit 10 = input[512] & (1 << 31) +// bit 11 = input[512] & (1 << 30) +// bit 12 = input[256] & (1 << 31) +// bit 13 = input[256] & (1 << 30) +// bit 14 = input[0] & (1 << 31) +// bit 15 = input[0] & (1 << 30) + +uint32_t polynomial = 0x04C11DB7; +static uint32_t rand_step(uint32_t input) +{ + int i; + uint32_t output = input + 1; + for (i = 0; i < 32; i++) + { + if (output & 0x80000000) + output ^= polynomial; + output = output << 1; + } + return output; +} + +static uint8_t get_bit(uint32_t *field, int offset) +{ + // printf("offset&31: %d\n", offset & 31); + // printf("offset/sizeof(*field): %d\n", offset >> 5); + return !!(field[offset >> 5] & (1 << (offset & 31))); +} + +static uint8_t set_bit(uint32_t *field, int offset) +{ + field[offset >> 5] |= (1 << (offset & 31)); +} + +static uint8_t clear_bit(uint32_t *field, int offset) +{ + field[offset >> 5] &= ~(1 << (offset & 31)); +} + +static uint8_t reverse_u8(uint8_t b) +{ + b = (b & 0xF0) >> 4 | (b & 0x0F) << 4; + b = (b & 0xCC) >> 2 | (b & 0x33) << 2; + b = (b & 0xAA) >> 1 | (b & 0x55) << 1; + return b; +} + +static uint16_t reverse_u16(uint16_t nonreversed) +{ + uint16_t reversed = 0; + + for (uint16_t i = 0; i < 16; i++) + { + reversed |= (nonreversed >> (16 - i - 1) & 1) << i; + } + + return reversed; +} + +int main(int argc, char **argv) +{ + int i; + // uint32_t test_1[] = {1}; + // uint32_t test_2[] = {0, 1}; + // uint32_t test_3[] = {2, 0}; + // uint32_t test_4[] = {1, 0x10, 0, 8}; + + // for (i = 0; i < sizeof(test_1)*8; i++) { + // if (get_bit(test_1, i)) + // printf("test_1: bit %d set\n", i); + // } + // for (i = 0; i < sizeof(test_2)*8; i++) { + // if (get_bit(test_2, i)) + // printf("test_2: bit %d set\n", i); + // } + // for (i = 0; i < sizeof(test_3)*8; i++) { + // if (get_bit(test_3, i)) + // printf("test_3: bit %d set\n", i); + // } + // for (i = 0; i < sizeof(test_4)*8; i++) { + // if (get_bit(test_4, i)) + // printf("test_4: bit %d set\n", i); + // } + + uint32_t input[256]; + uint32_t output[256] = {}; + + uint32_t init = 0; + for (i = 0; i < sizeof(input) / 4; i++) + { + init = rand_step(init); + input[i] = init; + } + // print_hex(input, sizeof(input), 0); + // return; + + uint16_t *o16 = (uint16_t *)output; + uint8_t *i8 = (uint8_t *)input; + for (i = 0; i < sizeof(input) / 2; i++) + { + int j; + for (j = 0; j < 16; j++) + { + // printf("o16[%d] |= (!!(i8[1792+%d] & (1 << %d)) << 0;\n", i, i, 2*(15-j)+1); + o16[i] |= (!!(i8[1792+i] & (1 << 2*(15-j)+1))) << 0; + o16[i] |= (!!(i8[1792+i] & (1 << 2*(15-j)+0))) << 1; + o16[i] |= (!!(i8[1536+i] & (1 << 2*(15-j)+1))) << 2; + o16[i] |= (!!(i8[1536+i] & (1 << 2*(15-j)+0))) << 3; + o16[i] |= (!!(i8[1280+i] & (1 << 2*(15-j)+1))) << 4; + o16[i] |= (!!(i8[1280+i] & (1 << 2*(15-j)+0))) << 5; + o16[i] |= (!!(i8[1024+i] & (1 << 2*(15-j)+1))) << 6; + o16[i] |= (!!(i8[1024+i] & (1 << 2*(15-j)+0))) << 7; + o16[i] |= (!!(i8[768+i] & (1 << 2*(15-j)+1))) << 8; + o16[i] |= (!!(i8[768+i] & (1 << 2*(15-j)+0))) << 9; + o16[i] |= (!!(i8[512+i] & (1 << 2*(15-j)+1))) << 10; + o16[i] |= (!!(i8[512+i] & (1 << 2*(15-j)+0))) << 11; + o16[i] |= (!!(i8[256+i] & (1 << 2*(15-j)+1))) << 12; + o16[i] |= (!!(i8[256+i] & (1 << 2*(15-j)+0))) << 13; + o16[i] |= (!!(i8[0+i] & (1 << 2*(15-j)+1))) << 14; + o16[i] |= (!!(i8[0+i] & (1 << 2*(15-j)+0))) << 15; +// o16[0] = i +// if (get_bit(input, i * 16 + j)) +// set_bit(output, j * 256 + i); +// else +// clear_bit(output, j * 256 + i); + } + } + + // uint8_t *o8 = (uint8_t *)output; + // for (i = 0; i < sizeof(output)/4; i++) + // o8[i] = reverse_u8(o8[i]); + + // for (i = 0; i < sizeof(output)/4; i++) + // o16[i] = reverse_u16(o16[i]); + + print_hex(output, sizeof(output), 0); + // for (i = 0; i < 2047; i++) + // printf("00000000\n"); + + return 0; +} \ No newline at end of file