xobs/s32k118.rs
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Regenerate crate with svd2rust v0.14.0

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Tmplt
2019-01-16 15:39:25 +01:00
parent e96ee18df6
commit e0ddb38a51
2821 changed files with 598414 additions and 601164 deletions
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4
src/sim/adcopt/mod.rs → src/sim/adcopt.rs
View File

@ -22,9 +22,7 @@ impl super::ADCOPT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

34
src/sim/chipctl/mod.rs → src/sim/chipctl.rs
View File

@ -22,9 +22,7 @@ impl super::CHIPCTL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
@ -119,7 +117,7 @@ pub enum CLKOUTSELR {
_0010,
#[doc = "SIRC DIV2 CLK"]
_0100,
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG\\[5\\]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
_0101,
#[doc = "FIRC DIV2 CLK"]
_0110,
@ -133,11 +131,11 @@ pub enum CLKOUTSELR {
_1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
_1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
#[doc = "LPO_CLK as selected by SIM_LPOCLKS\\[LPOCLKSEL\\]"]
_1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
_1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
#[doc = "RTC_CLK as selected by SIM_LPOCLKS\\[RTCCLKSEL\\]"]
_1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
_1111,
@ -448,9 +446,9 @@ impl TRACECLK_SELR {
#[doc = "Possible values of the field `PDB_BB_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PDB_BB_SELR {
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO\\[7:0\\] and PDB1 channel 0 back-to-back operation with ADC1 COCO\\[7:0\\]"]
_0,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO\\[7:0\\] of ADC0 and ADC1."]
_1,
}
impl PDB_BB_SELR {
@ -790,7 +788,7 @@ pub enum CLKOUTSELW {
_0010,
#[doc = "SIRC DIV2 CLK"]
_0100,
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG\\[5\\]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
_0101,
#[doc = "FIRC DIV2 CLK"]
_0110,
@ -804,11 +802,11 @@ pub enum CLKOUTSELW {
_1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
_1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
#[doc = "LPO_CLK as selected by SIM_LPOCLKS\\[LPOCLKSEL\\]"]
_1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
_1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
#[doc = "RTC_CLK as selected by SIM_LPOCLKS\\[RTCCLKSEL\\]"]
_1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
_1111,
@ -861,7 +859,7 @@ impl<'a> _CLKOUTSELW<'a> {
pub fn _0100(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0100)
}
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG\\[5\\]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
#[inline]
pub fn _0101(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0101)
@ -896,7 +894,7 @@ impl<'a> _CLKOUTSELW<'a> {
pub fn _1011(self) -> &'a mut W {
self.variant(CLKOUTSELW::_1011)
}
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
#[doc = "LPO_CLK as selected by SIM_LPOCLKS\\[LPOCLKSEL\\]"]
#[inline]
pub fn _1100(self) -> &'a mut W {
self.variant(CLKOUTSELW::_1100)
@ -906,7 +904,7 @@ impl<'a> _CLKOUTSELW<'a> {
pub fn _1101(self) -> &'a mut W {
self.variant(CLKOUTSELW::_1101)
}
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
#[doc = "RTC_CLK as selected by SIM_LPOCLKS\\[RTCCLKSEL\\]"]
#[inline]
pub fn _1110(self) -> &'a mut W {
self.variant(CLKOUTSELW::_1110)
@ -1142,9 +1140,9 @@ impl<'a> _TRACECLK_SELW<'a> {
}
#[doc = "Values that can be written to the field `PDB_BB_SEL`"]
pub enum PDB_BB_SELW {
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO\\[7:0\\] and PDB1 channel 0 back-to-back operation with ADC1 COCO\\[7:0\\]"]
_0,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO\\[7:0\\] of ADC0 and ADC1."]
_1,
}
impl PDB_BB_SELW {
@ -1170,12 +1168,12 @@ impl<'a> _PDB_BB_SELW<'a> {
self.bit(variant._bits())
}
}
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO\\[7:0\\] and PDB1 channel 0 back-to-back operation with ADC1 COCO\\[7:0\\]"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PDB_BB_SELW::_0)
}
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO\\[7:0\\] of ADC0 and ADC1."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PDB_BB_SELW::_1)

4
src/sim/clkdiv4/mod.rs → src/sim/clkdiv4.rs
View File

@ -22,9 +22,7 @@ impl super::CLKDIV4 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/sim/fcfg1/mod.rs → src/sim/fcfg1.rs
View File

@ -22,9 +22,7 @@ impl super::FCFG1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/sim/ftmopt0/mod.rs → src/sim/ftmopt0.rs
View File

@ -22,9 +22,7 @@ impl super::FTMOPT0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/sim/ftmopt1/mod.rs → src/sim/ftmopt1.rs
View File

@ -22,9 +22,7 @@ impl super::FTMOPT1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/sim/lpoclks/mod.rs → src/sim/lpoclks.rs
View File

@ -22,9 +22,7 @@ impl super::LPOCLKS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

52
src/sim/misctrl0/mod.rs → src/sim/misctrl0.rs
View File

@ -22,9 +22,7 @@ impl super::MISCTRL0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
@ -45,9 +43,9 @@ impl super::MISCTRL0 {
#[doc = "Possible values of the field `FTM0_OBE_CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM0_OBE_CTRLR {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM0_OBE_CTRLR {
@ -92,9 +90,9 @@ impl FTM0_OBE_CTRLR {
#[doc = "Possible values of the field `FTM1_OBE_CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM1_OBE_CTRLR {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM1_OBE_CTRLR {
@ -139,9 +137,9 @@ impl FTM1_OBE_CTRLR {
#[doc = "Possible values of the field `FTM2_OBE_CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM2_OBE_CTRLR {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM2_OBE_CTRLR {
@ -186,9 +184,9 @@ impl FTM2_OBE_CTRLR {
#[doc = "Possible values of the field `FTM3_OBE_CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM3_OBE_CTRLR {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM3_OBE_CTRLR {
@ -232,9 +230,9 @@ impl FTM3_OBE_CTRLR {
}
#[doc = "Values that can be written to the field `FTM0_OBE_CTRL`"]
pub enum FTM0_OBE_CTRLW {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM0_OBE_CTRLW {
@ -260,12 +258,12 @@ impl<'a> _FTM0_OBE_CTRLW<'a> {
self.bit(variant._bits())
}
}
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FTM0_OBE_CTRLW::_0)
}
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FTM0_OBE_CTRLW::_1)
@ -290,9 +288,9 @@ impl<'a> _FTM0_OBE_CTRLW<'a> {
}
#[doc = "Values that can be written to the field `FTM1_OBE_CTRL`"]
pub enum FTM1_OBE_CTRLW {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM1_OBE_CTRLW {
@ -318,12 +316,12 @@ impl<'a> _FTM1_OBE_CTRLW<'a> {
self.bit(variant._bits())
}
}
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FTM1_OBE_CTRLW::_0)
}
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FTM1_OBE_CTRLW::_1)
@ -348,9 +346,9 @@ impl<'a> _FTM1_OBE_CTRLW<'a> {
}
#[doc = "Values that can be written to the field `FTM2_OBE_CTRL`"]
pub enum FTM2_OBE_CTRLW {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM2_OBE_CTRLW {
@ -376,12 +374,12 @@ impl<'a> _FTM2_OBE_CTRLW<'a> {
self.bit(variant._bits())
}
}
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FTM2_OBE_CTRLW::_0)
}
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FTM2_OBE_CTRLW::_1)
@ -406,9 +404,9 @@ impl<'a> _FTM2_OBE_CTRLW<'a> {
}
#[doc = "Values that can be written to the field `FTM3_OBE_CTRL`"]
pub enum FTM3_OBE_CTRLW {
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
_0,
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
_1,
}
impl FTM3_OBE_CTRLW {
@ -434,12 +432,12 @@ impl<'a> _FTM3_OBE_CTRLW<'a> {
self.bit(variant._bits())
}
}
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FTM3_OBE_CTRLW::_0)
}
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FTM3_OBE_CTRLW::_1)

4
src/sim/misctrl1/mod.rs → src/sim/misctrl1.rs
View File

@ -22,9 +22,7 @@ impl super::MISCTRL1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

132
src/sim/mod.rs
View File

@ -1,132 +0,0 @@
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 4usize],
#[doc = "0x04 - Chip Control register"]
pub chipctl: CHIPCTL,
_reserved1: [u8; 4usize],
#[doc = "0x0c - FTM Option Register 0"]
pub ftmopt0: FTMOPT0,
#[doc = "0x10 - LPO Clock Select Register"]
pub lpoclks: LPOCLKS,
_reserved2: [u8; 4usize],
#[doc = "0x18 - ADC Options Register"]
pub adcopt: ADCOPT,
#[doc = "0x1c - FTM Option Register 1"]
pub ftmopt1: FTMOPT1,
#[doc = "0x20 - Miscellaneous control register 0"]
pub misctrl0: MISCTRL0,
#[doc = "0x24 - System Device Identification Register"]
pub sdid: SDID,
_reserved3: [u8; 24usize],
#[doc = "0x40 - Platform Clock Gating Control Register"]
pub platcgc: PLATCGC,
_reserved4: [u8; 8usize],
#[doc = "0x4c - Flash Configuration Register 1"]
pub fcfg1: FCFG1,
_reserved5: [u8; 4usize],
#[doc = "0x54 - Unique Identification Register High"]
pub uidh: UIDH,
#[doc = "0x58 - Unique Identification Register Mid-High"]
pub uidmh: UIDMH,
#[doc = "0x5c - Unique Identification Register Mid Low"]
pub uidml: UIDML,
#[doc = "0x60 - Unique Identification Register Low"]
pub uidl: UIDL,
_reserved6: [u8; 4usize],
#[doc = "0x68 - System Clock Divider Register 4"]
pub clkdiv4: CLKDIV4,
#[doc = "0x6c - Miscellaneous Control register 1"]
pub misctrl1: MISCTRL1,
}
#[doc = "Chip Control register"]
pub struct CHIPCTL {
register: VolatileCell<u32>,
}
#[doc = "Chip Control register"]
pub mod chipctl;
#[doc = "FTM Option Register 0"]
pub struct FTMOPT0 {
register: VolatileCell<u32>,
}
#[doc = "FTM Option Register 0"]
pub mod ftmopt0;
#[doc = "LPO Clock Select Register"]
pub struct LPOCLKS {
register: VolatileCell<u32>,
}
#[doc = "LPO Clock Select Register"]
pub mod lpoclks;
#[doc = "ADC Options Register"]
pub struct ADCOPT {
register: VolatileCell<u32>,
}
#[doc = "ADC Options Register"]
pub mod adcopt;
#[doc = "FTM Option Register 1"]
pub struct FTMOPT1 {
register: VolatileCell<u32>,
}
#[doc = "FTM Option Register 1"]
pub mod ftmopt1;
#[doc = "Miscellaneous control register 0"]
pub struct MISCTRL0 {
register: VolatileCell<u32>,
}
#[doc = "Miscellaneous control register 0"]
pub mod misctrl0;
#[doc = "System Device Identification Register"]
pub struct SDID {
register: VolatileCell<u32>,
}
#[doc = "System Device Identification Register"]
pub mod sdid;
#[doc = "Platform Clock Gating Control Register"]
pub struct PLATCGC {
register: VolatileCell<u32>,
}
#[doc = "Platform Clock Gating Control Register"]
pub mod platcgc;
#[doc = "Flash Configuration Register 1"]
pub struct FCFG1 {
register: VolatileCell<u32>,
}
#[doc = "Flash Configuration Register 1"]
pub mod fcfg1;
#[doc = "Unique Identification Register High"]
pub struct UIDH {
register: VolatileCell<u32>,
}
#[doc = "Unique Identification Register High"]
pub mod uidh;
#[doc = "Unique Identification Register Mid-High"]
pub struct UIDMH {
register: VolatileCell<u32>,
}
#[doc = "Unique Identification Register Mid-High"]
pub mod uidmh;
#[doc = "Unique Identification Register Mid Low"]
pub struct UIDML {
register: VolatileCell<u32>,
}
#[doc = "Unique Identification Register Mid Low"]
pub mod uidml;
#[doc = "Unique Identification Register Low"]
pub struct UIDL {
register: VolatileCell<u32>,
}
#[doc = "Unique Identification Register Low"]
pub mod uidl;
#[doc = "System Clock Divider Register 4"]
pub struct CLKDIV4 {
register: VolatileCell<u32>,
}
#[doc = "System Clock Divider Register 4"]
pub mod clkdiv4;
#[doc = "Miscellaneous Control register 1"]
pub struct MISCTRL1 {
register: VolatileCell<u32>,
}
#[doc = "Miscellaneous Control register 1"]
pub mod misctrl1;

4
src/sim/platcgc/mod.rs → src/sim/platcgc.rs
View File

@ -22,9 +22,7 @@ impl super::PLATCGC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/sim/sdid/mod.rs → src/sim/sdid.rs
View File

@ -6,9 +6,7 @@ impl super::SDID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/sim/uidh/mod.rs → src/sim/uidh.rs
View File

@ -6,9 +6,7 @@ impl super::UIDH {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/sim/uidl/mod.rs → src/sim/uidl.rs
View File

@ -6,9 +6,7 @@ impl super::UIDL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/sim/uidmh/mod.rs → src/sim/uidmh.rs
View File

@ -6,9 +6,7 @@ impl super::UIDMH {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/sim/uidml/mod.rs → src/sim/uidml.rs
View File

@ -6,9 +6,7 @@ impl super::UIDML {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]