Regenerate crate with svd2rust v0.14.0
This commit is contained in:
Tmplt
parent
e96ee18df6
commit
e0ddb38a51
10
Cargo.toml
10
Cargo.toml
@ -1,7 +1,7 @@
|
||||
[package]
|
||||
authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"]
|
||||
name = "s32k144"
|
||||
version = "0.9.0"
|
||||
version = "0.10.0"
|
||||
|
||||
description = "Peripheral access API for NXP S32K144 microcontrollers (generated using svd2rust)"
|
||||
repository = "https://github.com/kjetilkjeka/s32k144.rs"
|
||||
@ -12,13 +12,13 @@ categories = ["embedded", "hardware-support", "no-std"]
|
||||
license = "Apache-2.0/MIT"
|
||||
|
||||
[dependencies]
|
||||
cortex-m = "0.4.3"
|
||||
bare-metal = "0.1.1"
|
||||
cortex-m = "0.5.8"
|
||||
bare-metal = "0.2.0"
|
||||
vcell = "0.1.0"
|
||||
|
||||
[dependencies.cortex-m-rt]
|
||||
optional = true
|
||||
version = "0.3.6"
|
||||
version = "0.6.5"
|
||||
|
||||
[features]
|
||||
rt = ["cortex-m-rt"]
|
||||
rt = ["cortex-m-rt/device"]
|
||||
|
||||
13
build.rs
Normal file
13
build.rs
Normal file
@ -0,0 +1,13 @@
|
||||
use std::env;
|
||||
use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::PathBuf;
|
||||
fn main() {
|
||||
if env::var_os("CARGO_FEATURE_RT").is_some() {
|
||||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
File::create(out.join("device.x")).unwrap().write_all(include_bytes!("device.x")).unwrap();
|
||||
println!("cargo:rustc-link-search={}", out.display());
|
||||
println!("cargo:rerun-if-changed=device.x");
|
||||
}
|
||||
println!("cargo:rerun-if-changed=build.rs");
|
||||
}
|
||||
89
device.x
Normal file
89
device.x
Normal file
@ -0,0 +1,89 @@
|
||||
PROVIDE(DMA0 = DefaultHandler);
|
||||
PROVIDE(DMA1 = DefaultHandler);
|
||||
PROVIDE(DMA2 = DefaultHandler);
|
||||
PROVIDE(DMA3 = DefaultHandler);
|
||||
PROVIDE(DMA4 = DefaultHandler);
|
||||
PROVIDE(DMA5 = DefaultHandler);
|
||||
PROVIDE(DMA6 = DefaultHandler);
|
||||
PROVIDE(DMA7 = DefaultHandler);
|
||||
PROVIDE(DMA8 = DefaultHandler);
|
||||
PROVIDE(DMA9 = DefaultHandler);
|
||||
PROVIDE(DMA10 = DefaultHandler);
|
||||
PROVIDE(DMA11 = DefaultHandler);
|
||||
PROVIDE(DMA12 = DefaultHandler);
|
||||
PROVIDE(DMA13 = DefaultHandler);
|
||||
PROVIDE(DMA14 = DefaultHandler);
|
||||
PROVIDE(DMA15 = DefaultHandler);
|
||||
PROVIDE(DMA_ERROR = DefaultHandler);
|
||||
PROVIDE(MCM = DefaultHandler);
|
||||
PROVIDE(FTFC = DefaultHandler);
|
||||
PROVIDE(READ_COLLISION = DefaultHandler);
|
||||
PROVIDE(LVD_LVW = DefaultHandler);
|
||||
PROVIDE(FTFC_FAULT = DefaultHandler);
|
||||
PROVIDE(WDOG_EWM = DefaultHandler);
|
||||
PROVIDE(RCM = DefaultHandler);
|
||||
PROVIDE(LPI2C0_MASTER = DefaultHandler);
|
||||
PROVIDE(LPI2C0_SLAVE = DefaultHandler);
|
||||
PROVIDE(LPSPI0 = DefaultHandler);
|
||||
PROVIDE(LPSPI1 = DefaultHandler);
|
||||
PROVIDE(LPSPI2 = DefaultHandler);
|
||||
PROVIDE(LPUART0_RXTX = DefaultHandler);
|
||||
PROVIDE(LPUART1_RXTX = DefaultHandler);
|
||||
PROVIDE(LPUART2_RXTX = DefaultHandler);
|
||||
PROVIDE(ADC0 = DefaultHandler);
|
||||
PROVIDE(ADC1 = DefaultHandler);
|
||||
PROVIDE(CMP0 = DefaultHandler);
|
||||
PROVIDE(ERM_SINGLE_FAULT = DefaultHandler);
|
||||
PROVIDE(ERM_DOUBLE_FAULT = DefaultHandler);
|
||||
PROVIDE(RTC = DefaultHandler);
|
||||
PROVIDE(RTC_SECONDS = DefaultHandler);
|
||||
PROVIDE(LPIT0_CH0 = DefaultHandler);
|
||||
PROVIDE(LPIT0_CH1 = DefaultHandler);
|
||||
PROVIDE(LPIT0_CH2 = DefaultHandler);
|
||||
PROVIDE(LPIT0_CH3 = DefaultHandler);
|
||||
PROVIDE(PDB0 = DefaultHandler);
|
||||
PROVIDE(SCG = DefaultHandler);
|
||||
PROVIDE(LPTMR0 = DefaultHandler);
|
||||
PROVIDE(PORTA = DefaultHandler);
|
||||
PROVIDE(PORTB = DefaultHandler);
|
||||
PROVIDE(PORTC = DefaultHandler);
|
||||
PROVIDE(PORTD = DefaultHandler);
|
||||
PROVIDE(PORTE = DefaultHandler);
|
||||
PROVIDE(PDB1 = DefaultHandler);
|
||||
PROVIDE(FLEXIO = DefaultHandler);
|
||||
PROVIDE(CAN0_ORED = DefaultHandler);
|
||||
PROVIDE(CAN0_ERROR = DefaultHandler);
|
||||
PROVIDE(CAN0_WAKE_UP = DefaultHandler);
|
||||
PROVIDE(CAN0_ORED_0_15_MB = DefaultHandler);
|
||||
PROVIDE(CAN0_ORED_16_31_MB = DefaultHandler);
|
||||
PROVIDE(CAN1_ORED = DefaultHandler);
|
||||
PROVIDE(CAN1_ERROR = DefaultHandler);
|
||||
PROVIDE(CAN1_ORED_0_15_MB = DefaultHandler);
|
||||
PROVIDE(CAN2_ORED = DefaultHandler);
|
||||
PROVIDE(CAN2_ERROR = DefaultHandler);
|
||||
PROVIDE(CAN2_ORED_0_15_MB = DefaultHandler);
|
||||
PROVIDE(FTM0_CH0_CH1 = DefaultHandler);
|
||||
PROVIDE(FTM0_CH2_CH3 = DefaultHandler);
|
||||
PROVIDE(FTM0_CH4_CH5 = DefaultHandler);
|
||||
PROVIDE(FTM0_CH6_CH7 = DefaultHandler);
|
||||
PROVIDE(FTM0_FAULT = DefaultHandler);
|
||||
PROVIDE(FTM0_OVF_RELOAD = DefaultHandler);
|
||||
PROVIDE(FTM1_CH0_CH1 = DefaultHandler);
|
||||
PROVIDE(FTM1_CH2_CH3 = DefaultHandler);
|
||||
PROVIDE(FTM1_CH4_CH5 = DefaultHandler);
|
||||
PROVIDE(FTM1_CH6_CH7 = DefaultHandler);
|
||||
PROVIDE(FTM1_FAULT = DefaultHandler);
|
||||
PROVIDE(FTM1_OVF_RELOAD = DefaultHandler);
|
||||
PROVIDE(FTM2_CH0_CH1 = DefaultHandler);
|
||||
PROVIDE(FTM2_CH2_CH3 = DefaultHandler);
|
||||
PROVIDE(FTM2_CH4_CH5 = DefaultHandler);
|
||||
PROVIDE(FTM2_CH6_CH7 = DefaultHandler);
|
||||
PROVIDE(FTM2_FAULT = DefaultHandler);
|
||||
PROVIDE(FTM2_OVF_RELOAD = DefaultHandler);
|
||||
PROVIDE(FTM3_CH0_CH1 = DefaultHandler);
|
||||
PROVIDE(FTM3_CH2_CH3 = DefaultHandler);
|
||||
PROVIDE(FTM3_CH4_CH5 = DefaultHandler);
|
||||
PROVIDE(FTM3_CH6_CH7 = DefaultHandler);
|
||||
PROVIDE(FTM3_FAULT = DefaultHandler);
|
||||
PROVIDE(FTM3_OVF_RELOAD = DefaultHandler);
|
||||
|
||||
290
src/adc0.rs
Normal file
290
src/adc0.rs
Normal file
@ -0,0 +1,290 @@
|
||||
#[doc = r" Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - ADC Status and Control Register 1"]
|
||||
pub sc1a: SC1,
|
||||
#[doc = "0x04 - ADC Status and Control Register 1"]
|
||||
pub sc1b: SC1,
|
||||
#[doc = "0x08 - ADC Status and Control Register 1"]
|
||||
pub sc1c: SC1,
|
||||
#[doc = "0x0c - ADC Status and Control Register 1"]
|
||||
pub sc1d: SC1,
|
||||
#[doc = "0x10 - ADC Status and Control Register 1"]
|
||||
pub sc1e: SC1,
|
||||
#[doc = "0x14 - ADC Status and Control Register 1"]
|
||||
pub sc1f: SC1,
|
||||
#[doc = "0x18 - ADC Status and Control Register 1"]
|
||||
pub sc1g: SC1,
|
||||
#[doc = "0x1c - ADC Status and Control Register 1"]
|
||||
pub sc1h: SC1,
|
||||
#[doc = "0x20 - ADC Status and Control Register 1"]
|
||||
pub sc1i: SC1,
|
||||
#[doc = "0x24 - ADC Status and Control Register 1"]
|
||||
pub sc1j: SC1,
|
||||
#[doc = "0x28 - ADC Status and Control Register 1"]
|
||||
pub sc1k: SC1,
|
||||
#[doc = "0x2c - ADC Status and Control Register 1"]
|
||||
pub sc1l: SC1,
|
||||
#[doc = "0x30 - ADC Status and Control Register 1"]
|
||||
pub sc1m: SC1,
|
||||
#[doc = "0x34 - ADC Status and Control Register 1"]
|
||||
pub sc1n: SC1,
|
||||
#[doc = "0x38 - ADC Status and Control Register 1"]
|
||||
pub sc1o: SC1,
|
||||
#[doc = "0x3c - ADC Status and Control Register 1"]
|
||||
pub sc1p: SC1,
|
||||
#[doc = "0x40 - ADC Configuration Register 1"]
|
||||
pub cfg1: CFG1,
|
||||
#[doc = "0x44 - ADC Configuration Register 2"]
|
||||
pub cfg2: CFG2,
|
||||
#[doc = "0x48 - ADC Data Result Registers"]
|
||||
pub ra: R,
|
||||
#[doc = "0x4c - ADC Data Result Registers"]
|
||||
pub rb: R,
|
||||
#[doc = "0x50 - ADC Data Result Registers"]
|
||||
pub rc: R,
|
||||
#[doc = "0x54 - ADC Data Result Registers"]
|
||||
pub rd: R,
|
||||
#[doc = "0x58 - ADC Data Result Registers"]
|
||||
pub re: R,
|
||||
#[doc = "0x5c - ADC Data Result Registers"]
|
||||
pub rf: R,
|
||||
#[doc = "0x60 - ADC Data Result Registers"]
|
||||
pub rg: R,
|
||||
#[doc = "0x64 - ADC Data Result Registers"]
|
||||
pub rh: R,
|
||||
#[doc = "0x68 - ADC Data Result Registers"]
|
||||
pub ri: R,
|
||||
#[doc = "0x6c - ADC Data Result Registers"]
|
||||
pub rj: R,
|
||||
#[doc = "0x70 - ADC Data Result Registers"]
|
||||
pub rk: R,
|
||||
#[doc = "0x74 - ADC Data Result Registers"]
|
||||
pub rl: R,
|
||||
#[doc = "0x78 - ADC Data Result Registers"]
|
||||
pub rm: R,
|
||||
#[doc = "0x7c - ADC Data Result Registers"]
|
||||
pub rn: R,
|
||||
#[doc = "0x80 - ADC Data Result Registers"]
|
||||
pub ro: R,
|
||||
#[doc = "0x84 - ADC Data Result Registers"]
|
||||
pub rp: R,
|
||||
#[doc = "0x88 - Compare Value Registers"]
|
||||
pub cv1: CV,
|
||||
#[doc = "0x8c - Compare Value Registers"]
|
||||
pub cv2: CV,
|
||||
#[doc = "0x90 - Status and Control Register 2"]
|
||||
pub sc2: SC2,
|
||||
#[doc = "0x94 - Status and Control Register 3"]
|
||||
pub sc3: SC3,
|
||||
#[doc = "0x98 - BASE Offset Register"]
|
||||
pub base_ofs: BASE_OFS,
|
||||
#[doc = "0x9c - ADC Offset Correction Register"]
|
||||
pub ofs: OFS,
|
||||
#[doc = "0xa0 - USER Offset Correction Register"]
|
||||
pub usr_ofs: USR_OFS,
|
||||
#[doc = "0xa4 - ADC X Offset Correction Register"]
|
||||
pub xofs: XOFS,
|
||||
#[doc = "0xa8 - ADC Y Offset Correction Register"]
|
||||
pub yofs: YOFS,
|
||||
#[doc = "0xac - ADC Gain Register"]
|
||||
pub g: G,
|
||||
#[doc = "0xb0 - ADC User Gain Register"]
|
||||
pub ug: UG,
|
||||
#[doc = "0xb4 - ADC General Calibration Value Register S"]
|
||||
pub clps: CLPS,
|
||||
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub clp3: CLP3,
|
||||
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub clp2: CLP2,
|
||||
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
|
||||
pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
|
||||
pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub clp3_ofs: CLP3_OFS,
|
||||
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub clp2_ofs: CLP2_OFS,
|
||||
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub clp1_ofs: CLP1_OFS,
|
||||
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub clp0_ofs: CLP0_OFS,
|
||||
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub clpx_ofs: CLPX_OFS,
|
||||
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub clp9_ofs: CLP9_OFS,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub struct SC1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub mod sc1;
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub struct CFG1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub mod cfg1;
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub struct CFG2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub mod cfg2;
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub struct R {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub mod r;
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub struct CV {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub mod cv;
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub struct SC2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub mod sc2;
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub struct SC3 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub mod sc3;
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub struct BASE_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub mod base_ofs;
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub struct OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub mod ofs;
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub struct USR_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub mod usr_ofs;
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub struct XOFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub mod xofs;
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub struct YOFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub mod yofs;
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub struct G {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub mod g;
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub struct UG {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub mod ug;
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub struct CLPS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub mod clps;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub struct CLP3 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub mod clp3;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub struct CLP2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub mod clp2;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub struct CLP1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub mod clp1;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub struct CLP0 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub mod clp0;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub struct CLPX {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub mod clpx;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub struct CLP9 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub mod clp9;
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub struct CLPS_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub mod clps_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub struct CLP3_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub mod clp3_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub struct CLP2_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub mod clp2_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub struct CLP1_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub mod clp1_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub struct CLP0_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub struct CLPX_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub struct CLP9_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
103
src/adc0/base_ofs.rs
Normal file
103
src/adc0/base_ofs.rs
Normal file
@ -0,0 +1,103 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::BASE_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct BA_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl BA_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _BA_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _BA_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&self) -> BA_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
BA_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 64 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&mut self) -> _BA_OFSW {
|
||||
_BA_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
@ -1,105 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::BASE_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct BA_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl BA_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _BA_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _BA_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&self) -> BA_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
BA_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 64 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&mut self) -> _BA_OFSW {
|
||||
_BA_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
482
src/adc0/cfg1.rs
Normal file
482
src/adc0/cfg1.rs
Normal file
@ -0,0 +1,482 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADICLK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADICLKR {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKR::_00 => 0,
|
||||
ADICLKR::_01 => 1,
|
||||
ADICLKR::_10 => 2,
|
||||
ADICLKR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADICLKR {
|
||||
match value {
|
||||
0 => ADICLKR::_00,
|
||||
1 => ADICLKR::_01,
|
||||
2 => ADICLKR::_10,
|
||||
3 => ADICLKR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLKR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLKR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLKR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLKR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `MODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MODER {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl MODER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODER::_00 => 0,
|
||||
MODER::_01 => 1,
|
||||
MODER::_10 => 2,
|
||||
MODER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> MODER {
|
||||
match value {
|
||||
0 => MODER::_00,
|
||||
1 => MODER::_01,
|
||||
2 => MODER::_10,
|
||||
i => MODER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODER::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODER::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODER::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADIV`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADIVR {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVR::_00 => 0,
|
||||
ADIVR::_01 => 1,
|
||||
ADIVR::_10 => 2,
|
||||
ADIVR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADIVR {
|
||||
match value {
|
||||
0 => ADIVR::_00,
|
||||
1 => ADIVR::_01,
|
||||
2 => ADIVR::_10,
|
||||
3 => ADIVR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIVR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIVR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIVR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIVR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADICLK`"]
|
||||
pub enum ADICLKW {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKW::_00 => 0,
|
||||
ADICLKW::_01 => 1,
|
||||
ADICLKW::_10 => 2,
|
||||
ADICLKW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADICLKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADICLKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MODE`"]
|
||||
pub enum MODEW {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
}
|
||||
impl MODEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODEW::_00 => 0,
|
||||
MODEW::_01 => 1,
|
||||
MODEW::_10 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _MODEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _MODEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: MODEW) -> &'a mut W {
|
||||
unsafe { self.bits(variant._bits()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODEW::_00)
|
||||
}
|
||||
#[doc = "12-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(MODEW::_01)
|
||||
}
|
||||
#[doc = "10-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(MODEW::_10)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADIV`"]
|
||||
pub enum ADIVW {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVW::_00 => 0,
|
||||
ADIVW::_01 => 1,
|
||||
ADIVW::_10 => 2,
|
||||
ADIVW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADIVW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADIVW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADIVW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_00)
|
||||
}
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_01)
|
||||
}
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_10)
|
||||
}
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLRLTRGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLRLTRGW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 8;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&self) -> ADICLKR {
|
||||
ADICLKR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&self) -> MODER {
|
||||
MODER::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&self) -> ADIVR {
|
||||
ADIVR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&mut self) -> _ADICLKW {
|
||||
_ADICLKW { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&mut self) -> _MODEW {
|
||||
_MODEW { w: self }
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&mut self) -> _ADIVW {
|
||||
_ADIVW { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
|
||||
#[inline]
|
||||
pub fn clrltrg(&mut self) -> _CLRLTRGW {
|
||||
_CLRLTRGW { w: self }
|
||||
}
|
||||
}
|
||||
@ -1,484 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADICLK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADICLKR {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKR::_00 => 0,
|
||||
ADICLKR::_01 => 1,
|
||||
ADICLKR::_10 => 2,
|
||||
ADICLKR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADICLKR {
|
||||
match value {
|
||||
0 => ADICLKR::_00,
|
||||
1 => ADICLKR::_01,
|
||||
2 => ADICLKR::_10,
|
||||
3 => ADICLKR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLKR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLKR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLKR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLKR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `MODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MODER {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl MODER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODER::_00 => 0,
|
||||
MODER::_01 => 1,
|
||||
MODER::_10 => 2,
|
||||
MODER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> MODER {
|
||||
match value {
|
||||
0 => MODER::_00,
|
||||
1 => MODER::_01,
|
||||
2 => MODER::_10,
|
||||
i => MODER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODER::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODER::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODER::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADIV`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADIVR {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVR::_00 => 0,
|
||||
ADIVR::_01 => 1,
|
||||
ADIVR::_10 => 2,
|
||||
ADIVR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADIVR {
|
||||
match value {
|
||||
0 => ADIVR::_00,
|
||||
1 => ADIVR::_01,
|
||||
2 => ADIVR::_10,
|
||||
3 => ADIVR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIVR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIVR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIVR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIVR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADICLK`"]
|
||||
pub enum ADICLKW {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKW::_00 => 0,
|
||||
ADICLKW::_01 => 1,
|
||||
ADICLKW::_10 => 2,
|
||||
ADICLKW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADICLKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADICLKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MODE`"]
|
||||
pub enum MODEW {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
}
|
||||
impl MODEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODEW::_00 => 0,
|
||||
MODEW::_01 => 1,
|
||||
MODEW::_10 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _MODEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _MODEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: MODEW) -> &'a mut W {
|
||||
unsafe { self.bits(variant._bits()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODEW::_00)
|
||||
}
|
||||