949 lines
25 KiB
Rust
949 lines
25 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::ADCOPT {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `ADC0TRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0TRGSELR {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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}
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impl ADC0TRGSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC0TRGSELR::_0 => false,
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ADC0TRGSELR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC0TRGSELR {
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match value {
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false => ADC0TRGSELR::_0,
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true => ADC0TRGSELR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ADC0TRGSELR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ADC0TRGSELR::_1
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}
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}
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#[doc = "Possible values of the field `ADC0SWPRETRG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0SWPRETRGR {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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}
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impl ADC0SWPRETRGR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC0SWPRETRGR::_000 => 0,
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ADC0SWPRETRGR::_001 => 1,
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ADC0SWPRETRGR::_010 => 2,
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ADC0SWPRETRGR::_011 => 3,
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ADC0SWPRETRGR::_100 => 4,
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ADC0SWPRETRGR::_101 => 5,
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ADC0SWPRETRGR::_110 => 6,
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ADC0SWPRETRGR::_111 => 7,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADC0SWPRETRGR {
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match value {
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0 => ADC0SWPRETRGR::_000,
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1 => ADC0SWPRETRGR::_001,
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2 => ADC0SWPRETRGR::_010,
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3 => ADC0SWPRETRGR::_011,
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4 => ADC0SWPRETRGR::_100,
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5 => ADC0SWPRETRGR::_101,
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6 => ADC0SWPRETRGR::_110,
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7 => ADC0SWPRETRGR::_111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_000`"]
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#[inline]
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pub fn is_000(&self) -> bool {
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*self == ADC0SWPRETRGR::_000
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}
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#[doc = "Checks if the value of the field is `_001`"]
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#[inline]
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pub fn is_001(&self) -> bool {
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*self == ADC0SWPRETRGR::_001
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}
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#[doc = "Checks if the value of the field is `_010`"]
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#[inline]
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pub fn is_010(&self) -> bool {
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*self == ADC0SWPRETRGR::_010
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}
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#[doc = "Checks if the value of the field is `_011`"]
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#[inline]
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pub fn is_011(&self) -> bool {
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*self == ADC0SWPRETRGR::_011
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}
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#[doc = "Checks if the value of the field is `_100`"]
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#[inline]
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pub fn is_100(&self) -> bool {
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*self == ADC0SWPRETRGR::_100
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}
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#[doc = "Checks if the value of the field is `_101`"]
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#[inline]
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pub fn is_101(&self) -> bool {
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*self == ADC0SWPRETRGR::_101
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}
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#[doc = "Checks if the value of the field is `_110`"]
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#[inline]
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pub fn is_110(&self) -> bool {
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*self == ADC0SWPRETRGR::_110
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}
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#[doc = "Checks if the value of the field is `_111`"]
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#[inline]
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pub fn is_111(&self) -> bool {
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*self == ADC0SWPRETRGR::_111
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}
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}
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#[doc = "Possible values of the field `ADC0PRETRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0PRETRGSELR {
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#[doc = "PDB pretrigger (default)"]
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_00,
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#[doc = "TRGMUX pretrigger"]
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_01,
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#[doc = "Software pretrigger"]
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_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl ADC0PRETRGSELR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC0PRETRGSELR::_00 => 0,
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ADC0PRETRGSELR::_01 => 1,
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ADC0PRETRGSELR::_10 => 2,
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ADC0PRETRGSELR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADC0PRETRGSELR {
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match value {
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0 => ADC0PRETRGSELR::_00,
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1 => ADC0PRETRGSELR::_01,
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2 => ADC0PRETRGSELR::_10,
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i => ADC0PRETRGSELR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == ADC0PRETRGSELR::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == ADC0PRETRGSELR::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == ADC0PRETRGSELR::_10
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}
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}
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#[doc = "Possible values of the field `ADC1TRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1TRGSELR {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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}
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impl ADC1TRGSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADC1TRGSELR::_0 => false,
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ADC1TRGSELR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADC1TRGSELR {
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match value {
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false => ADC1TRGSELR::_0,
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true => ADC1TRGSELR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ADC1TRGSELR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ADC1TRGSELR::_1
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}
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}
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#[doc = "Possible values of the field `ADC1SWPRETRG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1SWPRETRGR {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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}
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impl ADC1SWPRETRGR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC1SWPRETRGR::_000 => 0,
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ADC1SWPRETRGR::_001 => 1,
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ADC1SWPRETRGR::_010 => 2,
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ADC1SWPRETRGR::_011 => 3,
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ADC1SWPRETRGR::_100 => 4,
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ADC1SWPRETRGR::_101 => 5,
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ADC1SWPRETRGR::_110 => 6,
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ADC1SWPRETRGR::_111 => 7,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADC1SWPRETRGR {
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match value {
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0 => ADC1SWPRETRGR::_000,
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1 => ADC1SWPRETRGR::_001,
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2 => ADC1SWPRETRGR::_010,
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3 => ADC1SWPRETRGR::_011,
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4 => ADC1SWPRETRGR::_100,
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5 => ADC1SWPRETRGR::_101,
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6 => ADC1SWPRETRGR::_110,
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7 => ADC1SWPRETRGR::_111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_000`"]
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#[inline]
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pub fn is_000(&self) -> bool {
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*self == ADC1SWPRETRGR::_000
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}
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#[doc = "Checks if the value of the field is `_001`"]
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#[inline]
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pub fn is_001(&self) -> bool {
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*self == ADC1SWPRETRGR::_001
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}
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#[doc = "Checks if the value of the field is `_010`"]
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#[inline]
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pub fn is_010(&self) -> bool {
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*self == ADC1SWPRETRGR::_010
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}
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#[doc = "Checks if the value of the field is `_011`"]
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#[inline]
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pub fn is_011(&self) -> bool {
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*self == ADC1SWPRETRGR::_011
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}
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#[doc = "Checks if the value of the field is `_100`"]
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#[inline]
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pub fn is_100(&self) -> bool {
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*self == ADC1SWPRETRGR::_100
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}
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#[doc = "Checks if the value of the field is `_101`"]
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#[inline]
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pub fn is_101(&self) -> bool {
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*self == ADC1SWPRETRGR::_101
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}
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#[doc = "Checks if the value of the field is `_110`"]
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#[inline]
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pub fn is_110(&self) -> bool {
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*self == ADC1SWPRETRGR::_110
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}
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#[doc = "Checks if the value of the field is `_111`"]
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#[inline]
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pub fn is_111(&self) -> bool {
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*self == ADC1SWPRETRGR::_111
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}
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}
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#[doc = "Possible values of the field `ADC1PRETRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1PRETRGSELR {
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#[doc = "PDB pretrigger (default)"]
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_00,
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|
#[doc = "TRGMUX pretrigger"]
|
|
_01,
|
|
#[doc = "Software pretrigger"]
|
|
_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl ADC1PRETRGSELR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADC1PRETRGSELR::_00 => 0,
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ADC1PRETRGSELR::_01 => 1,
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ADC1PRETRGSELR::_10 => 2,
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ADC1PRETRGSELR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
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pub fn _from(value: u8) -> ADC1PRETRGSELR {
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match value {
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0 => ADC1PRETRGSELR::_00,
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1 => ADC1PRETRGSELR::_01,
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2 => ADC1PRETRGSELR::_10,
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i => ADC1PRETRGSELR::_Reserved(i),
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `_00`"]
|
|
#[inline]
|
|
pub fn is_00(&self) -> bool {
|
|
*self == ADC1PRETRGSELR::_00
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|
}
|
|
#[doc = "Checks if the value of the field is `_01`"]
|
|
#[inline]
|
|
pub fn is_01(&self) -> bool {
|
|
*self == ADC1PRETRGSELR::_01
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|
}
|
|
#[doc = "Checks if the value of the field is `_10`"]
|
|
#[inline]
|
|
pub fn is_10(&self) -> bool {
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|
*self == ADC1PRETRGSELR::_10
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|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC0TRGSEL`"]
|
|
pub enum ADC0TRGSELW {
|
|
#[doc = "PDB output"]
|
|
_0,
|
|
#[doc = "TRGMUX output"]
|
|
_1,
|
|
}
|
|
impl ADC0TRGSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC0TRGSELW::_0 => false,
|
|
ADC0TRGSELW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC0TRGSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC0TRGSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC0TRGSELW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "PDB output"]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ADC0TRGSELW::_0)
|
|
}
|
|
#[doc = "TRGMUX output"]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ADC0TRGSELW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
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|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC0SWPRETRG`"]
|
|
pub enum ADC0SWPRETRGW {
|
|
#[doc = "Software pretrigger disabled"]
|
|
_000,
|
|
#[doc = "Reserved (do not use)"]
|
|
_001,
|
|
#[doc = "Reserved (do not use)"]
|
|
_010,
|
|
#[doc = "Reserved (do not use)"]
|
|
_011,
|
|
#[doc = "Software pretrigger 0"]
|
|
_100,
|
|
#[doc = "Software pretrigger 1"]
|
|
_101,
|
|
#[doc = "Software pretrigger 2"]
|
|
_110,
|
|
#[doc = "Software pretrigger 3"]
|
|
_111,
|
|
}
|
|
impl ADC0SWPRETRGW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC0SWPRETRGW::_000 => 0,
|
|
ADC0SWPRETRGW::_001 => 1,
|
|
ADC0SWPRETRGW::_010 => 2,
|
|
ADC0SWPRETRGW::_011 => 3,
|
|
ADC0SWPRETRGW::_100 => 4,
|
|
ADC0SWPRETRGW::_101 => 5,
|
|
ADC0SWPRETRGW::_110 => 6,
|
|
ADC0SWPRETRGW::_111 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC0SWPRETRGW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC0SWPRETRGW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC0SWPRETRGW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Software pretrigger disabled"]
|
|
#[inline]
|
|
pub fn _000(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_000)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _001(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_001)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _010(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_010)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _011(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_011)
|
|
}
|
|
#[doc = "Software pretrigger 0"]
|
|
#[inline]
|
|
pub fn _100(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_100)
|
|
}
|
|
#[doc = "Software pretrigger 1"]
|
|
#[inline]
|
|
pub fn _101(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_101)
|
|
}
|
|
#[doc = "Software pretrigger 2"]
|
|
#[inline]
|
|
pub fn _110(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_110)
|
|
}
|
|
#[doc = "Software pretrigger 3"]
|
|
#[inline]
|
|
pub fn _111(self) -> &'a mut W {
|
|
self.variant(ADC0SWPRETRGW::_111)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 1;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC0PRETRGSEL`"]
|
|
pub enum ADC0PRETRGSELW {
|
|
#[doc = "PDB pretrigger (default)"]
|
|
_00,
|
|
#[doc = "TRGMUX pretrigger"]
|
|
_01,
|
|
#[doc = "Software pretrigger"]
|
|
_10,
|
|
}
|
|
impl ADC0PRETRGSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC0PRETRGSELW::_00 => 0,
|
|
ADC0PRETRGSELW::_01 => 1,
|
|
ADC0PRETRGSELW::_10 => 2,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC0PRETRGSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC0PRETRGSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC0PRETRGSELW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "PDB pretrigger (default)"]
|
|
#[inline]
|
|
pub fn _00(self) -> &'a mut W {
|
|
self.variant(ADC0PRETRGSELW::_00)
|
|
}
|
|
#[doc = "TRGMUX pretrigger"]
|
|
#[inline]
|
|
pub fn _01(self) -> &'a mut W {
|
|
self.variant(ADC0PRETRGSELW::_01)
|
|
}
|
|
#[doc = "Software pretrigger"]
|
|
#[inline]
|
|
pub fn _10(self) -> &'a mut W {
|
|
self.variant(ADC0PRETRGSELW::_10)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 4;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC1TRGSEL`"]
|
|
pub enum ADC1TRGSELW {
|
|
#[doc = "PDB output"]
|
|
_0,
|
|
#[doc = "TRGMUX output"]
|
|
_1,
|
|
}
|
|
impl ADC1TRGSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADC1TRGSELW::_0 => false,
|
|
ADC1TRGSELW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC1TRGSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC1TRGSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC1TRGSELW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "PDB output"]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ADC1TRGSELW::_0)
|
|
}
|
|
#[doc = "TRGMUX output"]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ADC1TRGSELW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC1SWPRETRG`"]
|
|
pub enum ADC1SWPRETRGW {
|
|
#[doc = "Software pretrigger disabled"]
|
|
_000,
|
|
#[doc = "Reserved (do not use)"]
|
|
_001,
|
|
#[doc = "Reserved (do not use)"]
|
|
_010,
|
|
#[doc = "Reserved (do not use)"]
|
|
_011,
|
|
#[doc = "Software pretrigger 0"]
|
|
_100,
|
|
#[doc = "Software pretrigger 1"]
|
|
_101,
|
|
#[doc = "Software pretrigger 2"]
|
|
_110,
|
|
#[doc = "Software pretrigger 3"]
|
|
_111,
|
|
}
|
|
impl ADC1SWPRETRGW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC1SWPRETRGW::_000 => 0,
|
|
ADC1SWPRETRGW::_001 => 1,
|
|
ADC1SWPRETRGW::_010 => 2,
|
|
ADC1SWPRETRGW::_011 => 3,
|
|
ADC1SWPRETRGW::_100 => 4,
|
|
ADC1SWPRETRGW::_101 => 5,
|
|
ADC1SWPRETRGW::_110 => 6,
|
|
ADC1SWPRETRGW::_111 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC1SWPRETRGW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC1SWPRETRGW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC1SWPRETRGW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Software pretrigger disabled"]
|
|
#[inline]
|
|
pub fn _000(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_000)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _001(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_001)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _010(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_010)
|
|
}
|
|
#[doc = "Reserved (do not use)"]
|
|
#[inline]
|
|
pub fn _011(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_011)
|
|
}
|
|
#[doc = "Software pretrigger 0"]
|
|
#[inline]
|
|
pub fn _100(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_100)
|
|
}
|
|
#[doc = "Software pretrigger 1"]
|
|
#[inline]
|
|
pub fn _101(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_101)
|
|
}
|
|
#[doc = "Software pretrigger 2"]
|
|
#[inline]
|
|
pub fn _110(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_110)
|
|
}
|
|
#[doc = "Software pretrigger 3"]
|
|
#[inline]
|
|
pub fn _111(self) -> &'a mut W {
|
|
self.variant(ADC1SWPRETRGW::_111)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 9;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADC1PRETRGSEL`"]
|
|
pub enum ADC1PRETRGSELW {
|
|
#[doc = "PDB pretrigger (default)"]
|
|
_00,
|
|
#[doc = "TRGMUX pretrigger"]
|
|
_01,
|
|
#[doc = "Software pretrigger"]
|
|
_10,
|
|
}
|
|
impl ADC1PRETRGSELW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
ADC1PRETRGSELW::_00 => 0,
|
|
ADC1PRETRGSELW::_01 => 1,
|
|
ADC1PRETRGSELW::_10 => 2,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADC1PRETRGSELW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADC1PRETRGSELW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADC1PRETRGSELW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "PDB pretrigger (default)"]
|
|
#[inline]
|
|
pub fn _00(self) -> &'a mut W {
|
|
self.variant(ADC1PRETRGSELW::_00)
|
|
}
|
|
#[doc = "TRGMUX pretrigger"]
|
|
#[inline]
|
|
pub fn _01(self) -> &'a mut W {
|
|
self.variant(ADC1PRETRGSELW::_01)
|
|
}
|
|
#[doc = "Software pretrigger"]
|
|
#[inline]
|
|
pub fn _10(self) -> &'a mut W {
|
|
self.variant(ADC1PRETRGSELW::_10)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 12;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bit 0 - ADC0 trigger source select"]
|
|
#[inline]
|
|
pub fn adc0trgsel(&self) -> ADC0TRGSELR {
|
|
ADC0TRGSELR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 1:3 - ADC0 software pretrigger sources"]
|
|
#[inline]
|
|
pub fn adc0swpretrg(&self) -> ADC0SWPRETRGR {
|
|
ADC0SWPRETRGR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 1;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 4:5 - ADC0 pretrigger source select"]
|
|
#[inline]
|
|
pub fn adc0pretrgsel(&self) -> ADC0PRETRGSELR {
|
|
ADC0PRETRGSELR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 4;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 8 - ADC1 trigger source select"]
|
|
#[inline]
|
|
pub fn adc1trgsel(&self) -> ADC1TRGSELR {
|
|
ADC1TRGSELR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 9:11 - ADC1 software pretrigger sources"]
|
|
#[inline]
|
|
pub fn adc1swpretrg(&self) -> ADC1SWPRETRGR {
|
|
ADC1SWPRETRGR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 9;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 12:13 - ADC1 pretrigger source select"]
|
|
#[inline]
|
|
pub fn adc1pretrgsel(&self) -> ADC1PRETRGSELR {
|
|
ADC1PRETRGSELR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 12;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bit 0 - ADC0 trigger source select"]
|
|
#[inline]
|
|
pub fn adc0trgsel(&mut self) -> _ADC0TRGSELW {
|
|
_ADC0TRGSELW { w: self }
|
|
}
|
|
#[doc = "Bits 1:3 - ADC0 software pretrigger sources"]
|
|
#[inline]
|
|
pub fn adc0swpretrg(&mut self) -> _ADC0SWPRETRGW {
|
|
_ADC0SWPRETRGW { w: self }
|
|
}
|
|
#[doc = "Bits 4:5 - ADC0 pretrigger source select"]
|
|
#[inline]
|
|
pub fn adc0pretrgsel(&mut self) -> _ADC0PRETRGSELW {
|
|
_ADC0PRETRGSELW { w: self }
|
|
}
|
|
#[doc = "Bit 8 - ADC1 trigger source select"]
|
|
#[inline]
|
|
pub fn adc1trgsel(&mut self) -> _ADC1TRGSELW {
|
|
_ADC1TRGSELW { w: self }
|
|
}
|
|
#[doc = "Bits 9:11 - ADC1 software pretrigger sources"]
|
|
#[inline]
|
|
pub fn adc1swpretrg(&mut self) -> _ADC1SWPRETRGW {
|
|
_ADC1SWPRETRGW { w: self }
|
|
}
|
|
#[doc = "Bits 12:13 - ADC1 pretrigger source select"]
|
|
#[inline]
|
|
pub fn adc1pretrgsel(&mut self) -> _ADC1PRETRGSELW {
|
|
_ADC1PRETRGSELW { w: self }
|
|
}
|
|
}
|