Regenerate crate with svd2rust v0.14.0
This commit is contained in:
@ -22,9 +22,7 @@ impl super::C0SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C0V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C1SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C1V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C2SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C2V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C3SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C3V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C4SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C4V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C5SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C5V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C6SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C6V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C7SC {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::C7V {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CNT {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CNTIN {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::COMBINE {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CONF {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::DEADTIME {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::EXTTRIG {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::FILTER {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::FLTCTRL {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::FLTPOL {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::FMS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::HCR {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::INVCTRL {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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360
src/ftm1/mod.rs
360
src/ftm1/mod.rs
@ -1,360 +0,0 @@
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use vcell::VolatileCell;
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - Status And Control"]
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pub sc: SC,
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#[doc = "0x04 - Counter"]
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pub cnt: CNT,
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#[doc = "0x08 - Modulo"]
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pub mod_: MOD,
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#[doc = "0x0c - Channel (n) Status And Control"]
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pub c0sc: C0SC,
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#[doc = "0x10 - Channel (n) Value"]
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pub c0v: C0V,
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#[doc = "0x14 - Channel (n) Status And Control"]
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pub c1sc: C1SC,
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#[doc = "0x18 - Channel (n) Value"]
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pub c1v: C1V,
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#[doc = "0x1c - Channel (n) Status And Control"]
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pub c2sc: C2SC,
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#[doc = "0x20 - Channel (n) Value"]
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pub c2v: C2V,
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#[doc = "0x24 - Channel (n) Status And Control"]
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pub c3sc: C3SC,
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#[doc = "0x28 - Channel (n) Value"]
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pub c3v: C3V,
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#[doc = "0x2c - Channel (n) Status And Control"]
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pub c4sc: C4SC,
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#[doc = "0x30 - Channel (n) Value"]
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pub c4v: C4V,
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#[doc = "0x34 - Channel (n) Status And Control"]
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pub c5sc: C5SC,
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#[doc = "0x38 - Channel (n) Value"]
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pub c5v: C5V,
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#[doc = "0x3c - Channel (n) Status And Control"]
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pub c6sc: C6SC,
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#[doc = "0x40 - Channel (n) Value"]
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pub c6v: C6V,
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#[doc = "0x44 - Channel (n) Status And Control"]
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pub c7sc: C7SC,
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#[doc = "0x48 - Channel (n) Value"]
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pub c7v: C7V,
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#[doc = "0x4c - Counter Initial Value"]
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pub cntin: CNTIN,
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#[doc = "0x50 - Capture And Compare Status"]
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pub status: STATUS,
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#[doc = "0x54 - Features Mode Selection"]
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pub mode: MODE,
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#[doc = "0x58 - Synchronization"]
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pub sync: SYNC,
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#[doc = "0x5c - Initial State For Channels Output"]
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pub outinit: OUTINIT,
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#[doc = "0x60 - Output Mask"]
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pub outmask: OUTMASK,
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#[doc = "0x64 - Function For Linked Channels"]
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pub combine: COMBINE,
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#[doc = "0x68 - Deadtime Configuration"]
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pub deadtime: DEADTIME,
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#[doc = "0x6c - FTM External Trigger"]
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pub exttrig: EXTTRIG,
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#[doc = "0x70 - Channels Polarity"]
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pub pol: POL,
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#[doc = "0x74 - Fault Mode Status"]
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pub fms: FMS,
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#[doc = "0x78 - Input Capture Filter Control"]
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pub filter: FILTER,
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#[doc = "0x7c - Fault Control"]
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pub fltctrl: FLTCTRL,
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#[doc = "0x80 - Quadrature Decoder Control And Status"]
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pub qdctrl: QDCTRL,
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#[doc = "0x84 - Configuration"]
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pub conf: CONF,
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#[doc = "0x88 - FTM Fault Input Polarity"]
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pub fltpol: FLTPOL,
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#[doc = "0x8c - Synchronization Configuration"]
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pub synconf: SYNCONF,
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#[doc = "0x90 - FTM Inverting Control"]
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pub invctrl: INVCTRL,
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#[doc = "0x94 - FTM Software Output Control"]
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pub swoctrl: SWOCTRL,
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#[doc = "0x98 - FTM PWM Load"]
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pub pwmload: PWMLOAD,
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#[doc = "0x9c - Half Cycle Register"]
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pub hcr: HCR,
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#[doc = "0xa0 - Pair 0 Deadtime Configuration"]
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pub pair0deadtime: PAIR0DEADTIME,
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_reserved0: [u8; 4usize],
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#[doc = "0xa8 - Pair 1 Deadtime Configuration"]
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pub pair1deadtime: PAIR1DEADTIME,
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_reserved1: [u8; 4usize],
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#[doc = "0xb0 - Pair 2 Deadtime Configuration"]
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pub pair2deadtime: PAIR2DEADTIME,
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_reserved2: [u8; 4usize],
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#[doc = "0xb8 - Pair 3 Deadtime Configuration"]
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pub pair3deadtime: PAIR3DEADTIME,
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}
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#[doc = "Status And Control"]
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pub struct SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Status And Control"]
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pub mod sc;
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#[doc = "Counter"]
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pub struct CNT {
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register: VolatileCell<u32>,
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}
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#[doc = "Counter"]
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pub mod cnt;
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#[doc = "Modulo"]
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pub struct MOD {
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register: VolatileCell<u32>,
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}
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#[doc = "Modulo"]
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pub mod mod_;
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#[doc = "Channel (n) Status And Control"]
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pub struct C0SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Status And Control"]
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pub mod c0sc;
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#[doc = "Channel (n) Value"]
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pub struct C0V {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Value"]
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pub mod c0v;
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#[doc = "Channel (n) Status And Control"]
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pub struct C1SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Status And Control"]
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pub mod c1sc;
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#[doc = "Channel (n) Value"]
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pub struct C1V {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Value"]
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pub mod c1v;
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#[doc = "Channel (n) Status And Control"]
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pub struct C2SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Status And Control"]
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pub mod c2sc;
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#[doc = "Channel (n) Value"]
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pub struct C2V {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Value"]
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pub mod c2v;
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#[doc = "Channel (n) Status And Control"]
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pub struct C3SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Status And Control"]
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pub mod c3sc;
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#[doc = "Channel (n) Value"]
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pub struct C3V {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Value"]
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pub mod c3v;
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#[doc = "Channel (n) Status And Control"]
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pub struct C4SC {
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register: VolatileCell<u32>,
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}
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#[doc = "Channel (n) Status And Control"]
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pub mod c4sc;
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#[doc = "Channel (n) Value"]
|
||||
pub struct C4V {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub mod c4v;
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub struct C5SC {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub mod c5sc;
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub struct C5V {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub mod c5v;
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub struct C6SC {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub mod c6sc;
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub struct C6V {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub mod c6v;
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub struct C7SC {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Status And Control"]
|
||||
pub mod c7sc;
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub struct C7V {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channel (n) Value"]
|
||||
pub mod c7v;
|
||||
#[doc = "Counter Initial Value"]
|
||||
pub struct CNTIN {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Counter Initial Value"]
|
||||
pub mod cntin;
|
||||
#[doc = "Capture And Compare Status"]
|
||||
pub struct STATUS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Capture And Compare Status"]
|
||||
pub mod status;
|
||||
#[doc = "Features Mode Selection"]
|
||||
pub struct MODE {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Features Mode Selection"]
|
||||
pub mod mode;
|
||||
#[doc = "Synchronization"]
|
||||
pub struct SYNC {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Synchronization"]
|
||||
pub mod sync;
|
||||
#[doc = "Initial State For Channels Output"]
|
||||
pub struct OUTINIT {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Initial State For Channels Output"]
|
||||
pub mod outinit;
|
||||
#[doc = "Output Mask"]
|
||||
pub struct OUTMASK {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Output Mask"]
|
||||
pub mod outmask;
|
||||
#[doc = "Function For Linked Channels"]
|
||||
pub struct COMBINE {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Function For Linked Channels"]
|
||||
pub mod combine;
|
||||
#[doc = "Deadtime Configuration"]
|
||||
pub struct DEADTIME {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Deadtime Configuration"]
|
||||
pub mod deadtime;
|
||||
#[doc = "FTM External Trigger"]
|
||||
pub struct EXTTRIG {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "FTM External Trigger"]
|
||||
pub mod exttrig;
|
||||
#[doc = "Channels Polarity"]
|
||||
pub struct POL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Channels Polarity"]
|
||||
pub mod pol;
|
||||
#[doc = "Fault Mode Status"]
|
||||
pub struct FMS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Fault Mode Status"]
|
||||
pub mod fms;
|
||||
#[doc = "Input Capture Filter Control"]
|
||||
pub struct FILTER {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Input Capture Filter Control"]
|
||||
pub mod filter;
|
||||
#[doc = "Fault Control"]
|
||||
pub struct FLTCTRL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Fault Control"]
|
||||
pub mod fltctrl;
|
||||
#[doc = "Quadrature Decoder Control And Status"]
|
||||
pub struct QDCTRL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Quadrature Decoder Control And Status"]
|
||||
pub mod qdctrl;
|
||||
#[doc = "Configuration"]
|
||||
pub struct CONF {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Configuration"]
|
||||
pub mod conf;
|
||||
#[doc = "FTM Fault Input Polarity"]
|
||||
pub struct FLTPOL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "FTM Fault Input Polarity"]
|
||||
pub mod fltpol;
|
||||
#[doc = "Synchronization Configuration"]
|
||||
pub struct SYNCONF {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Synchronization Configuration"]
|
||||
pub mod synconf;
|
||||
#[doc = "FTM Inverting Control"]
|
||||
pub struct INVCTRL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "FTM Inverting Control"]
|
||||
pub mod invctrl;
|
||||
#[doc = "FTM Software Output Control"]
|
||||
pub struct SWOCTRL {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "FTM Software Output Control"]
|
||||
pub mod swoctrl;
|
||||
#[doc = "FTM PWM Load"]
|
||||
pub struct PWMLOAD {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "FTM PWM Load"]
|
||||
pub mod pwmload;
|
||||
#[doc = "Half Cycle Register"]
|
||||
pub struct HCR {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Half Cycle Register"]
|
||||
pub mod hcr;
|
||||
#[doc = "Pair 0 Deadtime Configuration"]
|
||||
pub struct PAIR0DEADTIME {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Pair 0 Deadtime Configuration"]
|
||||
pub mod pair0deadtime;
|
||||
#[doc = "Pair 1 Deadtime Configuration"]
|
||||
pub struct PAIR1DEADTIME {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Pair 1 Deadtime Configuration"]
|
||||
pub mod pair1deadtime;
|
||||
#[doc = "Pair 2 Deadtime Configuration"]
|
||||
pub struct PAIR2DEADTIME {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Pair 2 Deadtime Configuration"]
|
||||
pub mod pair2deadtime;
|
||||
#[doc = "Pair 3 Deadtime Configuration"]
|
||||
pub struct PAIR3DEADTIME {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Pair 3 Deadtime Configuration"]
|
||||
pub mod pair3deadtime;
|
@ -22,9 +22,7 @@ impl super::MOD {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::MODE {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::OUTINIT {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::OUTMASK {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::PAIR0DEADTIME {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::PAIR1DEADTIME {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::PAIR2DEADTIME {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::PAIR3DEADTIME {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::POL {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::PWMLOAD {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::QDCTRL {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::SC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -6,9 +6,7 @@ impl super::STATUS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `CH0F`"]
|
@ -22,9 +22,7 @@ impl super::SWOCTRL {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::SYNC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
@ -22,9 +22,7 @@ impl super::SYNCONF {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
Reference in New Issue
Block a user