820 lines
21 KiB
Rust
820 lines
21 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::SC2 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `REFSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum REFSELR {
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#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
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_00,
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#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
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_01,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl REFSELR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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REFSELR::_00 => 0,
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REFSELR::_01 => 1,
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REFSELR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> REFSELR {
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match value {
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0 => REFSELR::_00,
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1 => REFSELR::_01,
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i => REFSELR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == REFSELR::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == REFSELR::_01
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}
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}
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#[doc = "Possible values of the field `DMAEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DMAENR {
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#[doc = "DMA is disabled."]
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_0,
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#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
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_1,
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}
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impl DMAENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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DMAENR::_0 => false,
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DMAENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> DMAENR {
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match value {
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false => DMAENR::_0,
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true => DMAENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == DMAENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == DMAENR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct ACRENR {
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bits: bool,
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}
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impl ACRENR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = r" Value of the field"]
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pub struct ACFGTR {
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bits: bool,
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}
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impl ACFGTR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = "Possible values of the field `ACFE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ACFER {
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#[doc = "Compare function disabled."]
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_0,
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#[doc = "Compare function enabled."]
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_1,
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}
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impl ACFER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ACFER::_0 => false,
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ACFER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ACFER {
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match value {
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false => ACFER::_0,
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true => ACFER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ACFER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ACFER::_1
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}
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}
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#[doc = "Possible values of the field `ADTRG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADTRGR {
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#[doc = "Software trigger selected."]
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_0,
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#[doc = "Hardware trigger selected."]
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_1,
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}
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impl ADTRGR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADTRGR::_0 => false,
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ADTRGR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADTRGR {
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match value {
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false => ADTRGR::_0,
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true => ADTRGR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ADTRGR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ADTRGR::_1
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}
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}
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#[doc = "Possible values of the field `ADACT`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADACTR {
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#[doc = "Conversion not in progress."]
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_0,
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#[doc = "Conversion in progress."]
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_1,
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}
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impl ADACTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ADACTR::_0 => false,
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ADACTR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ADACTR {
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match value {
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false => ADACTR::_0,
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true => ADACTR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ADACTR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ADACTR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct TRGPRNUMR {
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bits: u8,
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}
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impl TRGPRNUMR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `TRGSTLAT`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRGSTLATR {
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#[doc = "No trigger request has been latched"]
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_0,
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#[doc = "A trigger request has been latched"]
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_1,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl TRGSTLATR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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TRGSTLATR::_0 => 0,
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TRGSTLATR::_1 => 1,
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TRGSTLATR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> TRGSTLATR {
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match value {
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0 => TRGSTLATR::_0,
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1 => TRGSTLATR::_1,
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i => TRGSTLATR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TRGSTLATR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TRGSTLATR::_1
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}
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}
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#[doc = "Possible values of the field `TRGSTERR`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRGSTERRR {
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#[doc = "No error has occurred"]
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_0,
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#[doc = "An error has occurred"]
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_1,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl TRGSTERRR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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TRGSTERRR::_0 => 0,
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TRGSTERRR::_1 => 1,
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TRGSTERRR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> TRGSTERRR {
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match value {
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0 => TRGSTERRR::_0,
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1 => TRGSTERRR::_1,
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i => TRGSTERRR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TRGSTERRR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TRGSTERRR::_1
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}
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}
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#[doc = "Values that can be written to the field `REFSEL`"]
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pub enum REFSELW {
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#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
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_00,
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#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
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_01,
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}
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impl REFSELW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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REFSELW::_00 => 0,
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REFSELW::_01 => 1,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _REFSELW<'a> {
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w: &'a mut W,
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}
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impl<'a> _REFSELW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: REFSELW) -> &'a mut W {
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unsafe { self.bits(variant._bits()) }
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}
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#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(REFSELW::_00)
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}
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#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(REFSELW::_01)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `DMAEN`"]
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pub enum DMAENW {
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#[doc = "DMA is disabled."]
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_0,
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#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
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_1,
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}
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impl DMAENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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DMAENW::_0 => false,
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DMAENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _DMAENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _DMAENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: DMAENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "DMA is disabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(DMAENW::_0)
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}
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#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(DMAENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 2;
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self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ACRENW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ACRENW<'a> {
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 3;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ACFGTW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ACFGTW<'a> {
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ACFE`"]
|
|
pub enum ACFEW {
|
|
#[doc = "Compare function disabled."]
|
|
_0,
|
|
#[doc = "Compare function enabled."]
|
|
_1,
|
|
}
|
|
impl ACFEW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ACFEW::_0 => false,
|
|
ACFEW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ACFEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ACFEW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ACFEW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Compare function disabled."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ACFEW::_0)
|
|
}
|
|
#[doc = "Compare function enabled."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ACFEW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 5;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ADTRG`"]
|
|
pub enum ADTRGW {
|
|
#[doc = "Software trigger selected."]
|
|
_0,
|
|
#[doc = "Hardware trigger selected."]
|
|
_1,
|
|
}
|
|
impl ADTRGW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ADTRGW::_0 => false,
|
|
ADTRGW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ADTRGW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ADTRGW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ADTRGW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Software trigger selected."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ADTRGW::_0)
|
|
}
|
|
#[doc = "Hardware trigger selected."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ADTRGW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 6;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:1 - Voltage Reference Selection"]
|
|
#[inline]
|
|
pub fn refsel(&self) -> REFSELR {
|
|
REFSELR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 2 - DMA Enable"]
|
|
#[inline]
|
|
pub fn dmaen(&self) -> DMAENR {
|
|
DMAENR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 2;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 3 - Compare Function Range Enable"]
|
|
#[inline]
|
|
pub fn acren(&self) -> ACRENR {
|
|
let bits = {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 3;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
};
|
|
ACRENR { bits }
|
|
}
|
|
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
|
|
#[inline]
|
|
pub fn acfgt(&self) -> ACFGTR {
|
|
let bits = {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
};
|
|
ACFGTR { bits }
|
|
}
|
|
#[doc = "Bit 5 - Compare Function Enable"]
|
|
#[inline]
|
|
pub fn acfe(&self) -> ACFER {
|
|
ACFER::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 5;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 6 - Conversion Trigger Select"]
|
|
#[inline]
|
|
pub fn adtrg(&self) -> ADTRGR {
|
|
ADTRGR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 6;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 7 - Conversion Active"]
|
|
#[inline]
|
|
pub fn adact(&self) -> ADACTR {
|
|
ADACTR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 13:14 - Trigger Process Number"]
|
|
#[inline]
|
|
pub fn trgprnum(&self) -> TRGPRNUMR {
|
|
let bits = {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 13;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
};
|
|
TRGPRNUMR { bits }
|
|
}
|
|
#[doc = "Bits 16:19 - Trigger Status"]
|
|
#[inline]
|
|
pub fn trgstlat(&self) -> TRGSTLATR {
|
|
TRGSTLATR::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
|
|
#[inline]
|
|
pub fn trgsterr(&self) -> TRGSTERRR {
|
|
TRGSTERRR::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 24;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 0:1 - Voltage Reference Selection"]
|
|
#[inline]
|
|
pub fn refsel(&mut self) -> _REFSELW {
|
|
_REFSELW { w: self }
|
|
}
|
|
#[doc = "Bit 2 - DMA Enable"]
|
|
#[inline]
|
|
pub fn dmaen(&mut self) -> _DMAENW {
|
|
_DMAENW { w: self }
|
|
}
|
|
#[doc = "Bit 3 - Compare Function Range Enable"]
|
|
#[inline]
|
|
pub fn acren(&mut self) -> _ACRENW {
|
|
_ACRENW { w: self }
|
|
}
|
|
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
|
|
#[inline]
|
|
pub fn acfgt(&mut self) -> _ACFGTW {
|
|
_ACFGTW { w: self }
|
|
}
|
|
#[doc = "Bit 5 - Compare Function Enable"]
|
|
#[inline]
|
|
pub fn acfe(&mut self) -> _ACFEW {
|
|
_ACFEW { w: self }
|
|
}
|
|
#[doc = "Bit 6 - Conversion Trigger Select"]
|
|
#[inline]
|
|
pub fn adtrg(&mut self) -> _ADTRGW {
|
|
_ADTRGW { w: self }
|
|
}
|
|
}
|