485 lines
12 KiB
Rust
485 lines
12 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::CFG1 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `ADICLK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADICLKR {
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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_00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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_01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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_10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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_11,
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}
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impl ADICLKR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADICLKR::_00 => 0,
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ADICLKR::_01 => 1,
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ADICLKR::_10 => 2,
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ADICLKR::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADICLKR {
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match value {
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0 => ADICLKR::_00,
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1 => ADICLKR::_01,
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2 => ADICLKR::_10,
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3 => ADICLKR::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == ADICLKR::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == ADICLKR::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == ADICLKR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == ADICLKR::_11
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}
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}
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#[doc = "Possible values of the field `MODE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MODER {
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#[doc = "8-bit conversion."]
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_00,
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#[doc = "12-bit conversion."]
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_01,
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#[doc = "10-bit conversion."]
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_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl MODER {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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MODER::_00 => 0,
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MODER::_01 => 1,
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MODER::_10 => 2,
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MODER::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> MODER {
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match value {
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0 => MODER::_00,
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1 => MODER::_01,
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2 => MODER::_10,
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i => MODER::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == MODER::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == MODER::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == MODER::_10
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}
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}
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#[doc = "Possible values of the field `ADIV`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADIVR {
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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_00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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_01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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_10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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_11,
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}
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impl ADIVR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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ADIVR::_00 => 0,
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ADIVR::_01 => 1,
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ADIVR::_10 => 2,
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ADIVR::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> ADIVR {
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match value {
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0 => ADIVR::_00,
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1 => ADIVR::_01,
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2 => ADIVR::_10,
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3 => ADIVR::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == ADIVR::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == ADIVR::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == ADIVR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == ADIVR::_11
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}
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}
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#[doc = "Values that can be written to the field `ADICLK`"]
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pub enum ADICLKW {
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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_00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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_01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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_10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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_11,
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}
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impl ADICLKW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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ADICLKW::_00 => 0,
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ADICLKW::_01 => 1,
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ADICLKW::_10 => 2,
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ADICLKW::_11 => 3,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _ADICLKW<'a> {
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w: &'a mut W,
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}
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impl<'a> _ADICLKW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: ADICLKW) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(ADICLKW::_00)
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}
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(ADICLKW::_01)
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}
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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#[inline]
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pub fn _10(self) -> &'a mut W {
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self.variant(ADICLKW::_10)
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}
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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#[inline]
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pub fn _11(self) -> &'a mut W {
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self.variant(ADICLKW::_11)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `MODE`"]
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pub enum MODEW {
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#[doc = "8-bit conversion."]
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_00,
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#[doc = "12-bit conversion."]
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_01,
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#[doc = "10-bit conversion."]
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_10,
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}
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impl MODEW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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MODEW::_00 => 0,
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MODEW::_01 => 1,
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MODEW::_10 => 2,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _MODEW<'a> {
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w: &'a mut W,
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}
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impl<'a> _MODEW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: MODEW) -> &'a mut W {
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unsafe { self.bits(variant._bits()) }
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}
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#[doc = "8-bit conversion."]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(MODEW::_00)
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}
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#[doc = "12-bit conversion."]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(MODEW::_01)
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}
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#[doc = "10-bit conversion."]
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#[inline]
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pub fn _10(self) -> &'a mut W {
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self.variant(MODEW::_10)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 2;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `ADIV`"]
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pub enum ADIVW {
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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_00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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_01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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_10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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_11,
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}
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impl ADIVW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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ADIVW::_00 => 0,
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ADIVW::_01 => 1,
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ADIVW::_10 => 2,
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ADIVW::_11 => 3,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _ADIVW<'a> {
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w: &'a mut W,
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}
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impl<'a> _ADIVW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: ADIVW) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(ADIVW::_00)
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}
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(ADIVW::_01)
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}
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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#[inline]
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pub fn _10(self) -> &'a mut W {
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self.variant(ADIVW::_10)
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}
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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#[inline]
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pub fn _11(self) -> &'a mut W {
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self.variant(ADIVW::_11)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 5;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = r" Proxy"]
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pub struct _CLRLTRGW<'a> {
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w: &'a mut W,
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}
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impl<'a> _CLRLTRGW<'a> {
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 8;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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#[doc = "Bits 0:1 - Input Clock Select"]
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#[inline]
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pub fn adiclk(&self) -> ADICLKR {
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ADICLKR::_from({
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const MASK: u8 = 3;
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const OFFSET: u8 = 0;
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((self.bits >> OFFSET) & MASK as u32) as u8
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})
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}
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#[doc = "Bits 2:3 - Conversion mode selection"]
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#[inline]
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pub fn mode(&self) -> MODER {
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MODER::_from({
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const MASK: u8 = 3;
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const OFFSET: u8 = 2;
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((self.bits >> OFFSET) & MASK as u32) as u8
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})
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}
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#[doc = "Bits 5:6 - Clock Divide Select"]
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#[inline]
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pub fn adiv(&self) -> ADIVR {
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ADIVR::_from({
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const MASK: u8 = 3;
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const OFFSET: u8 = 5;
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((self.bits >> OFFSET) & MASK as u32) as u8
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})
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}
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}
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impl W {
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#[doc = r" Reset value of the register"]
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#[inline]
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pub fn reset_value() -> W {
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W { bits: 0 }
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}
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#[doc = r" Writes raw bits to the register"]
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#[inline]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.bits = bits;
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self
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}
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#[doc = "Bits 0:1 - Input Clock Select"]
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#[inline]
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pub fn adiclk(&mut self) -> _ADICLKW {
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_ADICLKW { w: self }
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}
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#[doc = "Bits 2:3 - Conversion mode selection"]
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#[inline]
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pub fn mode(&mut self) -> _MODEW {
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_MODEW { w: self }
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}
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#[doc = "Bits 5:6 - Clock Divide Select"]
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#[inline]
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pub fn adiv(&mut self) -> _ADIVW {
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_ADIVW { w: self }
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}
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#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
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#[inline]
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pub fn clrltrg(&mut self) -> _CLRLTRGW {
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_CLRLTRGW { w: self }
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}
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}
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