Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::ADCOPT {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::ADCOPT {
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#[doc = "Possible values of the field `ADC0TRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0TRGSELR {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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#[doc = "PDB output"] _0,
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#[doc = "TRGMUX output"] _1,
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}
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impl ADC0TRGSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,22 +90,14 @@ impl ADC0TRGSELR {
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#[doc = "Possible values of the field `ADC0SWPRETRG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0SWPRETRGR {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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#[doc = "Software pretrigger disabled"] _000,
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#[doc = "Reserved (do not use)"] _001,
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#[doc = "Reserved (do not use)"] _010,
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#[doc = "Reserved (do not use)"] _011,
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#[doc = "Software pretrigger 0"] _100,
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#[doc = "Software pretrigger 1"] _101,
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#[doc = "Software pretrigger 2"] _110,
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#[doc = "Software pretrigger 3"] _111,
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}
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impl ADC0SWPRETRGR {
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#[doc = r" Value of the field as raw bits"]
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@ -182,14 +174,10 @@ impl ADC0SWPRETRGR {
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#[doc = "Possible values of the field `ADC0PRETRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC0PRETRGSELR {
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#[doc = "PDB pretrigger (default)"]
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_00,
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#[doc = "TRGMUX pretrigger"]
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_01,
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#[doc = "Software pretrigger"]
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_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "PDB pretrigger (default)"] _00,
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#[doc = "TRGMUX pretrigger"] _01,
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#[doc = "Software pretrigger"] _10,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl ADC0PRETRGSELR {
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#[doc = r" Value of the field as raw bits"]
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@ -232,10 +220,8 @@ impl ADC0PRETRGSELR {
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#[doc = "Possible values of the field `ADC1TRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1TRGSELR {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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#[doc = "PDB output"] _0,
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#[doc = "TRGMUX output"] _1,
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}
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impl ADC1TRGSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -279,22 +265,14 @@ impl ADC1TRGSELR {
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#[doc = "Possible values of the field `ADC1SWPRETRG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1SWPRETRGR {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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#[doc = "Software pretrigger disabled"] _000,
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#[doc = "Reserved (do not use)"] _001,
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#[doc = "Reserved (do not use)"] _010,
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#[doc = "Reserved (do not use)"] _011,
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#[doc = "Software pretrigger 0"] _100,
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#[doc = "Software pretrigger 1"] _101,
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#[doc = "Software pretrigger 2"] _110,
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#[doc = "Software pretrigger 3"] _111,
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}
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impl ADC1SWPRETRGR {
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#[doc = r" Value of the field as raw bits"]
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@ -371,14 +349,10 @@ impl ADC1SWPRETRGR {
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#[doc = "Possible values of the field `ADC1PRETRGSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADC1PRETRGSELR {
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#[doc = "PDB pretrigger (default)"]
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_00,
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#[doc = "TRGMUX pretrigger"]
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_01,
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#[doc = "Software pretrigger"]
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_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "PDB pretrigger (default)"] _00,
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#[doc = "TRGMUX pretrigger"] _01,
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#[doc = "Software pretrigger"] _10,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl ADC1PRETRGSELR {
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#[doc = r" Value of the field as raw bits"]
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@ -420,10 +394,8 @@ impl ADC1PRETRGSELR {
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}
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#[doc = "Values that can be written to the field `ADC0TRGSEL`"]
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pub enum ADC0TRGSELW {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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#[doc = "PDB output"] _0,
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#[doc = "TRGMUX output"] _1,
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}
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impl ADC0TRGSELW {
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#[allow(missing_docs)]
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@ -478,22 +450,14 @@ impl<'a> _ADC0TRGSELW<'a> {
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}
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#[doc = "Values that can be written to the field `ADC0SWPRETRG`"]
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pub enum ADC0SWPRETRGW {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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#[doc = "Software pretrigger disabled"] _000,
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#[doc = "Reserved (do not use)"] _001,
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#[doc = "Reserved (do not use)"] _010,
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#[doc = "Reserved (do not use)"] _011,
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#[doc = "Software pretrigger 0"] _100,
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#[doc = "Software pretrigger 1"] _101,
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#[doc = "Software pretrigger 2"] _110,
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#[doc = "Software pretrigger 3"] _111,
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}
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impl ADC0SWPRETRGW {
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#[allow(missing_docs)]
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@ -576,12 +540,9 @@ impl<'a> _ADC0SWPRETRGW<'a> {
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}
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#[doc = "Values that can be written to the field `ADC0PRETRGSEL`"]
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pub enum ADC0PRETRGSELW {
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#[doc = "PDB pretrigger (default)"]
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_00,
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#[doc = "TRGMUX pretrigger"]
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_01,
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#[doc = "Software pretrigger"]
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_10,
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#[doc = "PDB pretrigger (default)"] _00,
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#[doc = "TRGMUX pretrigger"] _01,
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#[doc = "Software pretrigger"] _10,
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}
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impl ADC0PRETRGSELW {
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#[allow(missing_docs)]
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@ -632,10 +593,8 @@ impl<'a> _ADC0PRETRGSELW<'a> {
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}
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#[doc = "Values that can be written to the field `ADC1TRGSEL`"]
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pub enum ADC1TRGSELW {
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#[doc = "PDB output"]
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_0,
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#[doc = "TRGMUX output"]
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_1,
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#[doc = "PDB output"] _0,
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#[doc = "TRGMUX output"] _1,
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}
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impl ADC1TRGSELW {
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#[allow(missing_docs)]
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@ -690,22 +649,14 @@ impl<'a> _ADC1TRGSELW<'a> {
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}
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#[doc = "Values that can be written to the field `ADC1SWPRETRG`"]
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pub enum ADC1SWPRETRGW {
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#[doc = "Software pretrigger disabled"]
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_000,
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#[doc = "Reserved (do not use)"]
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_001,
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#[doc = "Reserved (do not use)"]
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_010,
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#[doc = "Reserved (do not use)"]
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_011,
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#[doc = "Software pretrigger 0"]
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_100,
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#[doc = "Software pretrigger 1"]
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_101,
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#[doc = "Software pretrigger 2"]
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_110,
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#[doc = "Software pretrigger 3"]
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_111,
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#[doc = "Software pretrigger disabled"] _000,
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#[doc = "Reserved (do not use)"] _001,
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#[doc = "Reserved (do not use)"] _010,
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#[doc = "Reserved (do not use)"] _011,
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#[doc = "Software pretrigger 0"] _100,
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#[doc = "Software pretrigger 1"] _101,
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#[doc = "Software pretrigger 2"] _110,
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#[doc = "Software pretrigger 3"] _111,
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}
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impl ADC1SWPRETRGW {
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#[allow(missing_docs)]
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@ -788,12 +739,9 @@ impl<'a> _ADC1SWPRETRGW<'a> {
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}
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#[doc = "Values that can be written to the field `ADC1PRETRGSEL`"]
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pub enum ADC1PRETRGSELW {
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#[doc = "PDB pretrigger (default)"]
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_00,
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#[doc = "TRGMUX pretrigger"]
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_01,
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#[doc = "Software pretrigger"]
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_10,
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#[doc = "PDB pretrigger (default)"] _00,
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#[doc = "TRGMUX pretrigger"] _01,
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#[doc = "Software pretrigger"] _10,
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}
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impl ADC1PRETRGSELW {
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#[allow(missing_docs)]
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@ -22,7 +22,9 @@ impl super::CHIPCTL {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -45,16 +47,11 @@ impl super::CHIPCTL {
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pub enum ADC_INTERLEAVE_ENR {
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#[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."]
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_0000,
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#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"]
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_1XXX,
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#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"]
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X1XX,
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#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"]
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XX1X,
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#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"]
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XXX1,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX,
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#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX,
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#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X,
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#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl ADC_INTERLEAVE_ENR {
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#[doc = r" Value of the field as raw bits"]
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@ -111,36 +108,22 @@ impl ADC_INTERLEAVE_ENR {
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#[doc = "Possible values of the field `CLKOUTSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CLKOUTSELR {
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#[doc = "SCG CLKOUT"]
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_0000,
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#[doc = "SOSC DIV2 CLK"]
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_0010,
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#[doc = "SIRC DIV2 CLK"]
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_0100,
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#[doc = "SCG CLKOUT"] _0000,
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#[doc = "SOSC DIV2 CLK"] _0010,
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#[doc = "SIRC DIV2 CLK"] _0100,
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#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
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_0101,
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#[doc = "FIRC DIV2 CLK"]
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_0110,
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#[doc = "HCLK"]
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_0111,
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#[doc = "SPLL DIV2 CLK"]
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_1000,
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#[doc = "BUS_CLK"]
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_1001,
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#[doc = "LPO128K_CLK"]
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_1010,
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#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
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_1011,
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#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
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_1100,
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#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
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_1101,
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#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
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_1110,
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#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
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_1111,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "FIRC DIV2 CLK"] _0110,
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#[doc = "HCLK"] _0111,
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#[doc = "SPLL DIV2 CLK"] _1000,
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#[doc = "BUS_CLK"] _1001,
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#[doc = "LPO128K_CLK"] _1010,
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#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011,
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#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100,
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#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101,
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#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110,
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#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl CLKOUTSELR {
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#[doc = r" Value of the field as raw bits"]
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@ -260,22 +243,14 @@ impl CLKOUTSELR {
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#[doc = "Possible values of the field `CLKOUTDIV`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CLKOUTDIVR {
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#[doc = "Divide by 1"]
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_000,
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#[doc = "Divide by 2"]
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_001,
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#[doc = "Divide by 3"]
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_010,
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#[doc = "Divide by 4"]
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_011,
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#[doc = "Divide by 5"]
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_100,
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#[doc = "Divide by 6"]
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_101,
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#[doc = "Divide by 7"]
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_110,
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#[doc = "Divide by 8"]
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_111,
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#[doc = "Divide by 1"] _000,
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#[doc = "Divide by 2"] _001,
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#[doc = "Divide by 3"] _010,
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#[doc = "Divide by 4"] _011,
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#[doc = "Divide by 5"] _100,
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#[doc = "Divide by 6"] _101,
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#[doc = "Divide by 7"] _110,
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#[doc = "Divide by 8"] _111,
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}
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impl CLKOUTDIVR {
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#[doc = r" Value of the field as raw bits"]
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@ -352,10 +327,8 @@ impl CLKOUTDIVR {
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#[doc = "Possible values of the field `CLKOUTEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CLKOUTENR {
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#[doc = "Clockout disable"]
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_0,
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#[doc = "Clockout enable"]
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_1,
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#[doc = "Clockout disable"] _0,
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#[doc = "Clockout enable"] _1,
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}
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impl CLKOUTENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -399,10 +372,8 @@ impl CLKOUTENR {
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#[doc = "Possible values of the field `TRACECLK_SEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRACECLK_SELR {
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#[doc = "Core clock"]
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_0,
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#[doc = "Platform clock"]
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_1,
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#[doc = "Core clock"] _0,
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#[doc = "Platform clock"] _1,
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}
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impl TRACECLK_SELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -448,8 +419,7 @@ impl TRACECLK_SELR {
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pub enum PDB_BB_SELR {
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#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
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_0,
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#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
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_1,
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||||
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1,
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||||
}
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impl PDB_BB_SELR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -493,20 +463,13 @@ impl PDB_BB_SELR {
|
||||
#[doc = "Possible values of the field `ADC_SUPPLY`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADC_SUPPLYR {
|
||||
#[doc = "5 V input VDD supply (VDD)"]
|
||||
_000,
|
||||
#[doc = "5 V input analog supply (VDDA)"]
|
||||
_001,
|
||||
#[doc = "ADC Reference Supply (VREFH)"]
|
||||
_010,
|
||||
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"]
|
||||
_011,
|
||||
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"]
|
||||
_100,
|
||||
#[doc = "1.2 V core regulator output (VDD_LV)"]
|
||||
_101,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "5 V input VDD supply (VDD)"] _000,
|
||||
#[doc = "5 V input analog supply (VDDA)"] _001,
|
||||
#[doc = "ADC Reference Supply (VREFH)"] _010,
|
||||
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011,
|
||||
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100,
|
||||
#[doc = "1.2 V core regulator output (VDD_LV)"] _101,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl ADC_SUPPLYR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -570,10 +533,8 @@ impl ADC_SUPPLYR {
|
||||
#[doc = "Possible values of the field `ADC_SUPPLYEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADC_SUPPLYENR {
|
||||
#[doc = "Disable internal supply monitoring"]
|
||||
_0,
|
||||
#[doc = "Enable internal supply monitoring"]
|
||||
_1,
|
||||
#[doc = "Disable internal supply monitoring"] _0,
|
||||
#[doc = "Enable internal supply monitoring"] _1,
|
||||
}
|
||||
impl ADC_SUPPLYENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -617,10 +578,8 @@ impl ADC_SUPPLYENR {
|
||||
#[doc = "Possible values of the field `SRAMU_RETEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SRAMU_RETENR {
|
||||
#[doc = "SRAMU contents are retained across resets"]
|
||||
_0,
|
||||
#[doc = "No SRAMU retention"]
|
||||
_1,
|
||||
#[doc = "SRAMU contents are retained across resets"] _0,
|
||||
#[doc = "No SRAMU retention"] _1,
|
||||
}
|
||||
impl SRAMU_RETENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -664,10 +623,8 @@ impl SRAMU_RETENR {
|
||||
#[doc = "Possible values of the field `SRAML_RETEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SRAML_RETENR {
|
||||
#[doc = "SRAML contents are retained across resets"]
|
||||
_0,
|
||||
#[doc = "No SRAML retention"]
|
||||
_1,
|
||||
#[doc = "SRAML contents are retained across resets"] _0,
|
||||
#[doc = "No SRAML retention"] _1,
|
||||
}
|
||||
impl SRAML_RETENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -712,14 +669,10 @@ impl SRAML_RETENR {
|
||||
pub enum ADC_INTERLEAVE_ENW {
|
||||
#[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."]
|
||||
_0000,
|
||||
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"]
|
||||
_1XXX,
|
||||
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"]
|
||||
X1XX,
|
||||
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"]
|
||||
XX1X,
|
||||
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"]
|
||||
XXX1,
|
||||
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX,
|
||||
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX,
|
||||
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X,
|
||||
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1,
|
||||
}
|
||||
impl ADC_INTERLEAVE_ENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -782,34 +735,21 @@ impl<'a> _ADC_INTERLEAVE_ENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CLKOUTSEL`"]
|
||||
pub enum CLKOUTSELW {
|
||||
#[doc = "SCG CLKOUT"]
|
||||
_0000,
|
||||
#[doc = "SOSC DIV2 CLK"]
|
||||
_0010,
|
||||
#[doc = "SIRC DIV2 CLK"]
|
||||
_0100,
|
||||
#[doc = "SCG CLKOUT"] _0000,
|
||||
#[doc = "SOSC DIV2 CLK"] _0010,
|
||||
#[doc = "SIRC DIV2 CLK"] _0100,
|
||||
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
|
||||
_0101,
|
||||
#[doc = "FIRC DIV2 CLK"]
|
||||
_0110,
|
||||
#[doc = "HCLK"]
|
||||
_0111,
|
||||
#[doc = "SPLL DIV2 CLK"]
|
||||
_1000,
|
||||
#[doc = "BUS_CLK"]
|
||||
_1001,
|
||||
#[doc = "LPO128K_CLK"]
|
||||
_1010,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
|
||||
_1011,
|
||||
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
|
||||
_1100,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
|
||||
_1101,
|
||||
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
|
||||
_1110,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
|
||||
_1111,
|
||||
#[doc = "FIRC DIV2 CLK"] _0110,
|
||||
#[doc = "HCLK"] _0111,
|
||||
#[doc = "SPLL DIV2 CLK"] _1000,
|
||||
#[doc = "BUS_CLK"] _1001,
|
||||
#[doc = "LPO128K_CLK"] _1010,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011,
|
||||
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101,
|
||||
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110,
|
||||
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111,
|
||||
}
|
||||
impl CLKOUTSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -926,22 +866,14 @@ impl<'a> _CLKOUTSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CLKOUTDIV`"]
|
||||
pub enum CLKOUTDIVW {
|
||||
#[doc = "Divide by 1"]
|
||||
_000,
|
||||
#[doc = "Divide by 2"]
|
||||
_001,
|
||||
#[doc = "Divide by 3"]
|
||||
_010,
|
||||
#[doc = "Divide by 4"]
|
||||
_011,
|
||||
#[doc = "Divide by 5"]
|
||||
_100,
|
||||
#[doc = "Divide by 6"]
|
||||
_101,
|
||||
#[doc = "Divide by 7"]
|
||||
_110,
|
||||
#[doc = "Divide by 8"]
|
||||
_111,
|
||||
#[doc = "Divide by 1"] _000,
|
||||
#[doc = "Divide by 2"] _001,
|
||||
#[doc = "Divide by 3"] _010,
|
||||
#[doc = "Divide by 4"] _011,
|
||||
#[doc = "Divide by 5"] _100,
|
||||
#[doc = "Divide by 6"] _101,
|
||||
#[doc = "Divide by 7"] _110,
|
||||
#[doc = "Divide by 8"] _111,
|
||||
}
|
||||
impl CLKOUTDIVW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1024,10 +956,8 @@ impl<'a> _CLKOUTDIVW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CLKOUTEN`"]
|
||||
pub enum CLKOUTENW {
|
||||
#[doc = "Clockout disable"]
|
||||
_0,
|
||||
#[doc = "Clockout enable"]
|
||||
_1,
|
||||
#[doc = "Clockout disable"] _0,
|
||||
#[doc = "Clockout enable"] _1,
|
||||
}
|
||||
impl CLKOUTENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1082,10 +1012,8 @@ impl<'a> _CLKOUTENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRACECLK_SEL`"]
|
||||
pub enum TRACECLK_SELW {
|
||||
#[doc = "Core clock"]
|
||||
_0,
|
||||
#[doc = "Platform clock"]
|
||||
_1,
|
||||
#[doc = "Core clock"] _0,
|
||||
#[doc = "Platform clock"] _1,
|
||||
}
|
||||
impl TRACECLK_SELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1142,8 +1070,7 @@ impl<'a> _TRACECLK_SELW<'a> {
|
||||
pub enum PDB_BB_SELW {
|
||||
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
|
||||
_0,
|
||||
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
|
||||
_1,
|
||||
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1,
|
||||
}
|
||||
impl PDB_BB_SELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1198,18 +1125,12 @@ impl<'a> _PDB_BB_SELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADC_SUPPLY`"]
|
||||
pub enum ADC_SUPPLYW {
|
||||
#[doc = "5 V input VDD supply (VDD)"]
|
||||
_000,
|
||||
#[doc = "5 V input analog supply (VDDA)"]
|
||||
_001,
|
||||
#[doc = "ADC Reference Supply (VREFH)"]
|
||||
_010,
|
||||
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"]
|
||||
_011,
|
||||
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"]
|
||||
_100,
|
||||
#[doc = "1.2 V core regulator output (VDD_LV)"]
|
||||
_101,
|
||||
#[doc = "5 V input VDD supply (VDD)"] _000,
|
||||
#[doc = "5 V input analog supply (VDDA)"] _001,
|
||||
#[doc = "ADC Reference Supply (VREFH)"] _010,
|
||||
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011,
|
||||
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100,
|
||||
#[doc = "1.2 V core regulator output (VDD_LV)"] _101,
|
||||
}
|
||||
impl ADC_SUPPLYW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1278,10 +1199,8 @@ impl<'a> _ADC_SUPPLYW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADC_SUPPLYEN`"]
|
||||
pub enum ADC_SUPPLYENW {
|
||||
#[doc = "Disable internal supply monitoring"]
|
||||
_0,
|
||||
#[doc = "Enable internal supply monitoring"]
|
||||
_1,
|
||||
#[doc = "Disable internal supply monitoring"] _0,
|
||||
#[doc = "Enable internal supply monitoring"] _1,
|
||||
}
|
||||
impl ADC_SUPPLYENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1336,10 +1255,8 @@ impl<'a> _ADC_SUPPLYENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SRAMU_RETEN`"]
|
||||
pub enum SRAMU_RETENW {
|
||||
#[doc = "SRAMU contents are retained across resets"]
|
||||
_0,
|
||||
#[doc = "No SRAMU retention"]
|
||||
_1,
|
||||
#[doc = "SRAMU contents are retained across resets"] _0,
|
||||
#[doc = "No SRAMU retention"] _1,
|
||||
}
|
||||
impl SRAMU_RETENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1394,10 +1311,8 @@ impl<'a> _SRAMU_RETENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SRAML_RETEN`"]
|
||||
pub enum SRAML_RETENW {
|
||||
#[doc = "SRAML contents are retained across resets"]
|
||||
_0,
|
||||
#[doc = "No SRAML retention"]
|
||||
_1,
|
||||
#[doc = "SRAML contents are retained across resets"] _0,
|
||||
#[doc = "No SRAML retention"] _1,
|
||||
}
|
||||
impl SRAML_RETENW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::CLKDIV4 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -75,10 +77,8 @@ impl TRACEDIVR {
|
||||
#[doc = "Possible values of the field `TRACEDIVEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRACEDIVENR {
|
||||
#[doc = "Debug trace divider disabled"]
|
||||
_0,
|
||||
#[doc = "Debug trace divider enabled"]
|
||||
_1,
|
||||
#[doc = "Debug trace divider disabled"] _0,
|
||||
#[doc = "Debug trace divider enabled"] _1,
|
||||
}
|
||||
impl TRACEDIVENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -159,10 +159,8 @@ impl<'a> _TRACEDIVW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRACEDIVEN`"]
|
||||
pub enum TRACEDIVENW {
|
||||
#[doc = "Debug trace divider disabled"]
|
||||
_0,
|
||||
#[doc = "Debug trace divider enabled"]
|
||||
_1,
|
||||
#[doc = "Debug trace divider disabled"] _0,
|
||||
#[doc = "Debug trace divider enabled"] _1,
|
||||
}
|
||||
impl TRACEDIVENW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::FCFG1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -54,26 +56,16 @@ impl DEPARTR {
|
||||
#[doc = "Possible values of the field `EEERAMSIZE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum EEERAMSIZER {
|
||||
#[doc = "4 KB"]
|
||||
_0010,
|
||||
#[doc = "2 KB"]
|
||||
_0011,
|
||||
#[doc = "1 KB"]
|
||||
_0100,
|
||||
#[doc = "512 Bytes"]
|
||||
_0101,
|
||||
#[doc = "256 Bytes"]
|
||||
_0110,
|
||||
#[doc = "128 Bytes"]
|
||||
_0111,
|
||||
#[doc = "64 Bytes"]
|
||||
_1000,
|
||||
#[doc = "32 Bytes"]
|
||||
_1001,
|
||||
#[doc = "0 Bytes"]
|
||||
_1111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "4 KB"] _0010,
|
||||
#[doc = "2 KB"] _0011,
|
||||
#[doc = "1 KB"] _0100,
|
||||
#[doc = "512 Bytes"] _0101,
|
||||
#[doc = "256 Bytes"] _0110,
|
||||
#[doc = "128 Bytes"] _0111,
|
||||
#[doc = "64 Bytes"] _1000,
|
||||
#[doc = "32 Bytes"] _1001,
|
||||
#[doc = "0 Bytes"] _1111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl EEERAMSIZER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::FTMOPT0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,12 +45,9 @@ impl super::FTMOPT0 {
|
||||
#[doc = "Possible values of the field `FTM0FLTxSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM0FLTXSELR {
|
||||
#[doc = "FTM0_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM0 out"]
|
||||
_001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM0_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM0 out"] _001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM0FLTXSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -84,12 +83,9 @@ impl FTM0FLTXSELR {
|
||||
#[doc = "Possible values of the field `FTM1FLTxSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM1FLTXSELR {
|
||||
#[doc = "FTM1_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM1 out"]
|
||||
_001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM1_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM1 out"] _001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM1FLTXSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -125,12 +121,9 @@ impl FTM1FLTXSELR {
|
||||
#[doc = "Possible values of the field `FTM2FLTxSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2FLTXSELR {
|
||||
#[doc = "FTM2_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM2 out"]
|
||||
_001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM2_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM2 out"] _001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM2FLTXSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -166,12 +159,9 @@ impl FTM2FLTXSELR {
|
||||
#[doc = "Possible values of the field `FTM3FLTxSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM3FLTXSELR {
|
||||
#[doc = "FTM3_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM3 out"]
|
||||
_001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM3_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM3 out"] _001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM3FLTXSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -207,14 +197,10 @@ impl FTM3FLTXSELR {
|
||||
#[doc = "Possible values of the field `FTM0CLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM0CLKSELR {
|
||||
#[doc = "FTM0 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM0 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM0 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM0 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM0 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM0 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM0CLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -263,14 +249,10 @@ impl FTM0CLKSELR {
|
||||
#[doc = "Possible values of the field `FTM1CLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM1CLKSELR {
|
||||
#[doc = "FTM1 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM1 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM1 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM1 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM1 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM1 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM1CLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -319,14 +301,10 @@ impl FTM1CLKSELR {
|
||||
#[doc = "Possible values of the field `FTM2CLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2CLKSELR {
|
||||
#[doc = "FTM2 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM2 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM2 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM2 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM2 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM2 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM2CLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -375,14 +353,10 @@ impl FTM2CLKSELR {
|
||||
#[doc = "Possible values of the field `FTM3CLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM3CLKSELR {
|
||||
#[doc = "FTM3 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM3 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM3 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM3 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM3 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM3 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM3CLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -430,10 +404,8 @@ impl FTM3CLKSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM0FLTxSEL`"]
|
||||
pub enum FTM0FLTXSELW {
|
||||
#[doc = "FTM0_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM0 out"]
|
||||
_001,
|
||||
#[doc = "FTM0_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM0 out"] _001,
|
||||
}
|
||||
impl FTM0FLTXSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -478,10 +450,8 @@ impl<'a> _FTM0FLTXSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM1FLTxSEL`"]
|
||||
pub enum FTM1FLTXSELW {
|
||||
#[doc = "FTM1_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM1 out"]
|
||||
_001,
|
||||
#[doc = "FTM1_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM1 out"] _001,
|
||||
}
|
||||
impl FTM1FLTXSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -526,10 +496,8 @@ impl<'a> _FTM1FLTXSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM2FLTxSEL`"]
|
||||
pub enum FTM2FLTXSELW {
|
||||
#[doc = "FTM2_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM2 out"]
|
||||
_001,
|
||||
#[doc = "FTM2_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM2 out"] _001,
|
||||
}
|
||||
impl FTM2FLTXSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -574,10 +542,8 @@ impl<'a> _FTM2FLTXSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM3FLTxSEL`"]
|
||||
pub enum FTM3FLTXSELW {
|
||||
#[doc = "FTM3_FLTx pin"]
|
||||
_000,
|
||||
#[doc = "TRGMUX_FTM3 out"]
|
||||
_001,
|
||||
#[doc = "FTM3_FLTx pin"] _000,
|
||||
#[doc = "TRGMUX_FTM3 out"] _001,
|
||||
}
|
||||
impl FTM3FLTXSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -622,14 +588,10 @@ impl<'a> _FTM3FLTXSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM0CLKSEL`"]
|
||||
pub enum FTM0CLKSELW {
|
||||
#[doc = "FTM0 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM0 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM0 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM0 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM0 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM0 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM0CLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -688,14 +650,10 @@ impl<'a> _FTM0CLKSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM1CLKSEL`"]
|
||||
pub enum FTM1CLKSELW {
|
||||
#[doc = "FTM1 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM1 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM1 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM1 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM1 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM1 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM1CLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -754,14 +712,10 @@ impl<'a> _FTM1CLKSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM2CLKSEL`"]
|
||||
pub enum FTM2CLKSELW {
|
||||
#[doc = "FTM2 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM2 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM2 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM2 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM2 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM2 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM2CLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -820,14 +774,10 @@ impl<'a> _FTM2CLKSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM3CLKSEL`"]
|
||||
pub enum FTM3CLKSELW {
|
||||
#[doc = "FTM3 external clock driven by TCLK0 pin."]
|
||||
_00,
|
||||
#[doc = "FTM3 external clock driven by TCLK1 pin."]
|
||||
_01,
|
||||
#[doc = "FTM3 external clock driven by TCLK2 pin."]
|
||||
_10,
|
||||
#[doc = "No clock input"]
|
||||
_11,
|
||||
#[doc = "FTM3 external clock driven by TCLK0 pin."] _00,
|
||||
#[doc = "FTM3 external clock driven by TCLK1 pin."] _01,
|
||||
#[doc = "FTM3 external clock driven by TCLK2 pin."] _10,
|
||||
#[doc = "No clock input"] _11,
|
||||
}
|
||||
impl FTM3CLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::FTMOPT1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -127,12 +129,9 @@ impl FTM3SYNCBITR {
|
||||
#[doc = "Possible values of the field `FTM1CH0SEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM1CH0SELR {
|
||||
#[doc = "FTM1_CH0 input"]
|
||||
_00,
|
||||
#[doc = "CMP0 output"]
|
||||
_01,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM1_CH0 input"] _00,
|
||||
#[doc = "CMP0 output"] _01,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM1CH0SELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -168,12 +167,9 @@ impl FTM1CH0SELR {
|
||||
#[doc = "Possible values of the field `FTM2CH0SEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2CH0SELR {
|
||||
#[doc = "FTM2_CH0 input"]
|
||||
_00,
|
||||
#[doc = "CMP0 output"]
|
||||
_01,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "FTM2_CH0 input"] _00,
|
||||
#[doc = "CMP0 output"] _01,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM2CH0SELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -209,10 +205,8 @@ impl FTM2CH0SELR {
|
||||
#[doc = "Possible values of the field `FTM2CH1SEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2CH1SELR {
|
||||
#[doc = "FTM2_CH1 input"]
|
||||
_0,
|
||||
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
|
||||
_1,
|
||||
#[doc = "FTM2_CH1 input"] _0,
|
||||
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1,
|
||||
}
|
||||
impl FTM2CH1SELR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -256,10 +250,8 @@ impl FTM2CH1SELR {
|
||||
#[doc = "Possible values of the field `FTMGLDOK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTMGLDOKR {
|
||||
#[doc = "FTM Global load mechanism disabled."]
|
||||
_0,
|
||||
#[doc = "FTM Global load mechanism enabled"]
|
||||
_1,
|
||||
#[doc = "FTM Global load mechanism disabled."] _0,
|
||||
#[doc = "FTM Global load mechanism enabled"] _1,
|
||||
}
|
||||
impl FTMGLDOKR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -303,12 +295,9 @@ impl FTMGLDOKR {
|
||||
#[doc = "Possible values of the field `FTM0_OUTSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM0_OUTSELR {
|
||||
#[doc = "No modulation with FTM1_CH1"]
|
||||
_00000000,
|
||||
#[doc = "Modulation with FTM1_CH1"]
|
||||
_00000001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "No modulation with FTM1_CH1"] _00000000,
|
||||
#[doc = "Modulation with FTM1_CH1"] _00000001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM0_OUTSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -344,12 +333,9 @@ impl FTM0_OUTSELR {
|
||||
#[doc = "Possible values of the field `FTM3_OUTSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM3_OUTSELR {
|
||||
#[doc = "No modulation with FTM2_CH1"]
|
||||
_00000000,
|
||||
#[doc = "Modulation with FTM2_CH1"]
|
||||
_00000001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "No modulation with FTM2_CH1"] _00000000,
|
||||
#[doc = "Modulation with FTM2_CH1"] _00000001,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl FTM3_OUTSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -476,10 +462,8 @@ impl<'a> _FTM3SYNCBITW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM1CH0SEL`"]
|
||||
pub enum FTM1CH0SELW {
|
||||
#[doc = "FTM1_CH0 input"]
|
||||
_00,
|
||||
#[doc = "CMP0 output"]
|
||||
_01,
|
||||
#[doc = "FTM1_CH0 input"] _00,
|
||||
#[doc = "CMP0 output"] _01,
|
||||
}
|
||||
impl FTM1CH0SELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -524,10 +508,8 @@ impl<'a> _FTM1CH0SELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM2CH0SEL`"]
|
||||
pub enum FTM2CH0SELW {
|
||||
#[doc = "FTM2_CH0 input"]
|
||||
_00,
|
||||
#[doc = "CMP0 output"]
|
||||
_01,
|
||||
#[doc = "FTM2_CH0 input"] _00,
|
||||
#[doc = "CMP0 output"] _01,
|
||||
}
|
||||
impl FTM2CH0SELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -572,10 +554,8 @@ impl<'a> _FTM2CH0SELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM2CH1SEL`"]
|
||||
pub enum FTM2CH1SELW {
|
||||
#[doc = "FTM2_CH1 input"]
|
||||
_0,
|
||||
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
|
||||
_1,
|
||||
#[doc = "FTM2_CH1 input"] _0,
|
||||
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1,
|
||||
}
|
||||
impl FTM2CH1SELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -630,10 +610,8 @@ impl<'a> _FTM2CH1SELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTMGLDOK`"]
|
||||
pub enum FTMGLDOKW {
|
||||
#[doc = "FTM Global load mechanism disabled."]
|
||||
_0,
|
||||
#[doc = "FTM Global load mechanism enabled"]
|
||||
_1,
|
||||
#[doc = "FTM Global load mechanism disabled."] _0,
|
||||
#[doc = "FTM Global load mechanism enabled"] _1,
|
||||
}
|
||||
impl FTMGLDOKW {
|
||||
#[allow(missing_docs)]
|
||||
@ -688,10 +666,8 @@ impl<'a> _FTMGLDOKW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM0_OUTSEL`"]
|
||||
pub enum FTM0_OUTSELW {
|
||||
#[doc = "No modulation with FTM1_CH1"]
|
||||
_00000000,
|
||||
#[doc = "Modulation with FTM1_CH1"]
|
||||
_00000001,
|
||||
#[doc = "No modulation with FTM1_CH1"] _00000000,
|
||||
#[doc = "Modulation with FTM1_CH1"] _00000001,
|
||||
}
|
||||
impl FTM0_OUTSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -736,10 +712,8 @@ impl<'a> _FTM0_OUTSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM3_OUTSEL`"]
|
||||
pub enum FTM3_OUTSELW {
|
||||
#[doc = "No modulation with FTM2_CH1"]
|
||||
_00000000,
|
||||
#[doc = "Modulation with FTM2_CH1"]
|
||||
_00000001,
|
||||
#[doc = "No modulation with FTM2_CH1"] _00000000,
|
||||
#[doc = "Modulation with FTM2_CH1"] _00000001,
|
||||
}
|
||||
impl FTM3_OUTSELW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::LPOCLKS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::LPOCLKS {
|
||||
#[doc = "Possible values of the field `LPO1KCLKEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO1KCLKENR {
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
_1,
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"] _0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"] _1,
|
||||
}
|
||||
impl LPO1KCLKENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl LPO1KCLKENR {
|
||||
#[doc = "Possible values of the field `LPO32KCLKEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO32KCLKENR {
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
_1,
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"] _0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"] _1,
|
||||
}
|
||||
impl LPO32KCLKENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,14 +135,10 @@ impl LPO32KCLKENR {
|
||||
#[doc = "Possible values of the field `LPOCLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPOCLKSELR {
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
_00,
|
||||
#[doc = "No clock"]
|
||||
_01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_11,
|
||||
#[doc = "128 kHz LPO_CLK"] _00,
|
||||
#[doc = "No clock"] _01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11,
|
||||
}
|
||||
impl LPOCLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -193,14 +187,10 @@ impl LPOCLKSELR {
|
||||
#[doc = "Possible values of the field `RTCCLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RTCCLKSELR {
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
_00,
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
_01,
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
_10,
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
_11,
|
||||
#[doc = "SOSCDIV1_CLK"] _00,
|
||||
#[doc = "32 kHz LPO_CLK"] _01,
|
||||
#[doc = "RTC_CLKIN clock"] _10,
|
||||
#[doc = "FIRCDIV1_CLK"] _11,
|
||||
}
|
||||
impl RTCCLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -248,10 +238,8 @@ impl RTCCLKSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPO1KCLKEN`"]
|
||||
pub enum LPO1KCLKENW {
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
_1,
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"] _0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"] _1,
|
||||
}
|
||||
impl LPO1KCLKENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -306,10 +294,8 @@ impl<'a> _LPO1KCLKENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPO32KCLKEN`"]
|
||||
pub enum LPO32KCLKENW {
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
_1,
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"] _0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"] _1,
|
||||
}
|
||||
impl LPO32KCLKENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -364,14 +350,10 @@ impl<'a> _LPO32KCLKENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPOCLKSEL`"]
|
||||
pub enum LPOCLKSELW {
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
_00,
|
||||
#[doc = "No clock"]
|
||||
_01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_11,
|
||||
#[doc = "128 kHz LPO_CLK"] _00,
|
||||
#[doc = "No clock"] _01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11,
|
||||
}
|
||||
impl LPOCLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -430,14 +412,10 @@ impl<'a> _LPOCLKSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RTCCLKSEL`"]
|
||||
pub enum RTCCLKSELW {
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
_00,
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
_01,
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
_10,
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
_11,
|
||||
#[doc = "SOSCDIV1_CLK"] _00,
|
||||
#[doc = "32 kHz LPO_CLK"] _01,
|
||||
#[doc = "RTC_CLKIN clock"] _10,
|
||||
#[doc = "FIRCDIV1_CLK"] _11,
|
||||
}
|
||||
impl RTCCLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::MISCTRL0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::MISCTRL1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -3,42 +3,27 @@ use vcell::VolatileCell;
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
_reserved0: [u8; 4usize],
|
||||
#[doc = "0x04 - Chip Control register"]
|
||||
pub chipctl: CHIPCTL,
|
||||
#[doc = "0x04 - Chip Control register"] pub chipctl: CHIPCTL,
|
||||
_reserved1: [u8; 4usize],
|
||||
#[doc = "0x0c - FTM Option Register 0"]
|
||||
pub ftmopt0: FTMOPT0,
|
||||
#[doc = "0x10 - LPO Clock Select Register"]
|
||||
pub lpoclks: LPOCLKS,
|
||||
#[doc = "0x0c - FTM Option Register 0"] pub ftmopt0: FTMOPT0,
|
||||
#[doc = "0x10 - LPO Clock Select Register"] pub lpoclks: LPOCLKS,
|
||||
_reserved2: [u8; 4usize],
|
||||
#[doc = "0x18 - ADC Options Register"]
|
||||
pub adcopt: ADCOPT,
|
||||
#[doc = "0x1c - FTM Option Register 1"]
|
||||
pub ftmopt1: FTMOPT1,
|
||||
#[doc = "0x20 - Miscellaneous control register 0"]
|
||||
pub misctrl0: MISCTRL0,
|
||||
#[doc = "0x24 - System Device Identification Register"]
|
||||
pub sdid: SDID,
|
||||
#[doc = "0x18 - ADC Options Register"] pub adcopt: ADCOPT,
|
||||
#[doc = "0x1c - FTM Option Register 1"] pub ftmopt1: FTMOPT1,
|
||||
#[doc = "0x20 - Miscellaneous control register 0"] pub misctrl0: MISCTRL0,
|
||||
#[doc = "0x24 - System Device Identification Register"] pub sdid: SDID,
|
||||
_reserved3: [u8; 24usize],
|
||||
#[doc = "0x40 - Platform Clock Gating Control Register"]
|
||||
pub platcgc: PLATCGC,
|
||||
#[doc = "0x40 - Platform Clock Gating Control Register"] pub platcgc: PLATCGC,
|
||||
_reserved4: [u8; 8usize],
|
||||
#[doc = "0x4c - Flash Configuration Register 1"]
|
||||
pub fcfg1: FCFG1,
|
||||
#[doc = "0x4c - Flash Configuration Register 1"] pub fcfg1: FCFG1,
|
||||
_reserved5: [u8; 4usize],
|
||||
#[doc = "0x54 - Unique Identification Register High"]
|
||||
pub uidh: UIDH,
|
||||
#[doc = "0x58 - Unique Identification Register Mid-High"]
|
||||
pub uidmh: UIDMH,
|
||||
#[doc = "0x5c - Unique Identification Register Mid Low"]
|
||||
pub uidml: UIDML,
|
||||
#[doc = "0x60 - Unique Identification Register Low"]
|
||||
pub uidl: UIDL,
|
||||
#[doc = "0x54 - Unique Identification Register High"] pub uidh: UIDH,
|
||||
#[doc = "0x58 - Unique Identification Register Mid-High"] pub uidmh: UIDMH,
|
||||
#[doc = "0x5c - Unique Identification Register Mid Low"] pub uidml: UIDML,
|
||||
#[doc = "0x60 - Unique Identification Register Low"] pub uidl: UIDL,
|
||||
_reserved6: [u8; 4usize],
|
||||
#[doc = "0x68 - System Clock Divider Register 4"]
|
||||
pub clkdiv4: CLKDIV4,
|
||||
#[doc = "0x6c - Miscellaneous Control register 1"]
|
||||
pub misctrl1: MISCTRL1,
|
||||
#[doc = "0x68 - System Clock Divider Register 4"] pub clkdiv4: CLKDIV4,
|
||||
#[doc = "0x6c - Miscellaneous Control register 1"] pub misctrl1: MISCTRL1,
|
||||
}
|
||||
#[doc = "Chip Control register"]
|
||||
pub struct CHIPCTL {
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PLATCGC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PLATCGC {
|
||||
#[doc = "Possible values of the field `CGCMSCM`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCMSCMR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCMSCMR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCMSCMR {
|
||||
#[doc = "Possible values of the field `CGCMPU`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCMPUR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCMPUR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,10 +135,8 @@ impl CGCMPUR {
|
||||
#[doc = "Possible values of the field `CGCDMA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCDMAR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCDMAR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -184,10 +180,8 @@ impl CGCDMAR {
|
||||
#[doc = "Possible values of the field `CGCERM`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCERMR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCERMR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -231,10 +225,8 @@ impl CGCERMR {
|
||||
#[doc = "Possible values of the field `CGCEIM`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCEIMR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCEIMR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -277,10 +269,8 @@ impl CGCEIMR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGCMSCM`"]
|
||||
pub enum CGCMSCMW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCMSCMW {
|
||||
#[allow(missing_docs)]
|
||||
@ -335,10 +325,8 @@ impl<'a> _CGCMSCMW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGCMPU`"]
|
||||
pub enum CGCMPUW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCMPUW {
|
||||
#[allow(missing_docs)]
|
||||
@ -393,10 +381,8 @@ impl<'a> _CGCMPUW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGCDMA`"]
|
||||
pub enum CGCDMAW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCDMAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -451,10 +437,8 @@ impl<'a> _CGCDMAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGCERM`"]
|
||||
pub enum CGCERMW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCERMW {
|
||||
#[allow(missing_docs)]
|
||||
@ -509,10 +493,8 @@ impl<'a> _CGCERMW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGCEIM`"]
|
||||
pub enum CGCEIMW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled"]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled"] _1,
|
||||
}
|
||||
impl CGCEIMW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::SDID {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
@ -23,20 +25,13 @@ impl FEATURESR {
|
||||
#[doc = "Possible values of the field `PACKAGE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PACKAGER {
|
||||
#[doc = "48 LQFP"]
|
||||
_0010,
|
||||
#[doc = "64 LQFP"]
|
||||
_0011,
|
||||
#[doc = "100 LQFP"]
|
||||
_0100,
|
||||
#[doc = "144 LQFP"]
|
||||
_0110,
|
||||
#[doc = "176 LQFP"]
|
||||
_0111,
|
||||
#[doc = "100 MAP BGA"]
|
||||
_1000,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "48 LQFP"] _0010,
|
||||
#[doc = "64 LQFP"] _0011,
|
||||
#[doc = "100 LQFP"] _0100,
|
||||
#[doc = "144 LQFP"] _0110,
|
||||
#[doc = "176 LQFP"] _0111,
|
||||
#[doc = "100 MAP BGA"] _1000,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl PACKAGER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -111,18 +106,12 @@ impl REVIDR {
|
||||
#[doc = "Possible values of the field `RAMSIZE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RAMSIZER {
|
||||
#[doc = "128 KB (S32K148), Reserved (others)"]
|
||||
_0111,
|
||||
#[doc = "160 KB (S32K148) , Reserved (others)"]
|
||||
_1001,
|
||||
#[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"]
|
||||
_1011,
|
||||
#[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"]
|
||||
_1101,
|
||||
#[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"]
|
||||
_1111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "128 KB (S32K148), Reserved (others)"] _0111,
|
||||
#[doc = "160 KB (S32K148) , Reserved (others)"] _1001,
|
||||
#[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"] _1011,
|
||||
#[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"] _1101,
|
||||
#[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"] _1111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl RAMSIZER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::UIDH {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::UIDL {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::UIDMH {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::UIDML {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
Reference in New Issue
Block a user