xobs/s32k118.rs
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This commit is contained in:
Kjetil Kjeka
2017-09-23 20:31:10 +02:00
parent 7facea48b2
commit 2fc3ce22de
1658 changed files with 25191 additions and 42351 deletions
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274
src/scg/hccr/mod.rs
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@ -22,7 +22,9 @@ impl super::HCCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,24 +45,15 @@ impl super::HCCR {
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
@ -138,38 +131,22 @@ impl DIVSLOWR {
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
@ -302,38 +279,22 @@ impl DIVBUSR {
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
@ -466,16 +427,11 @@ impl DIVCORER {
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
#[doc = r" Reserved"] _Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]
@ -524,22 +480,14 @@ impl SCSR {
}
#[doc = "Values that can be written to the field `DIVSLOW`"]
pub enum DIVSLOWW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
}
impl DIVSLOWW {
#[allow(missing_docs)]
@ -620,38 +568,22 @@ impl<'a> _DIVSLOWW<'a> {
}
#[doc = "Values that can be written to the field `DIVBUS`"]
pub enum DIVBUSW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVBUSW {
#[allow(missing_docs)]
@ -782,38 +714,22 @@ impl<'a> _DIVBUSW<'a> {
}
#[doc = "Values that can be written to the field `DIVCORE`"]
pub enum DIVCOREW {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
#[doc = "Divide-by-1"] _0000,
#[doc = "Divide-by-2"] _0001,
#[doc = "Divide-by-3"] _0010,
#[doc = "Divide-by-4"] _0011,
#[doc = "Divide-by-5"] _0100,
#[doc = "Divide-by-6"] _0101,
#[doc = "Divide-by-7"] _0110,
#[doc = "Divide-by-8"] _0111,
#[doc = "Divide-by-9"] _1000,
#[doc = "Divide-by-10"] _1001,
#[doc = "Divide-by-11"] _1010,
#[doc = "Divide-by-12"] _1011,
#[doc = "Divide-by-13"] _1100,
#[doc = "Divide-by-14"] _1101,
#[doc = "Divide-by-15"] _1110,
#[doc = "Divide-by-16"] _1111,
}
impl DIVCOREW {
#[allow(missing_docs)]
@ -944,14 +860,10 @@ impl<'a> _DIVCOREW<'a> {
}
#[doc = "Values that can be written to the field `SCS`"]
pub enum SCSW {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = "System OSC (SOSC_CLK)"] _0001,
#[doc = "Slow IRC (SIRC_CLK)"] _0010,
#[doc = "Fast IRC (FIRC_CLK)"] _0011,
#[doc = "System PLL (SPLL_CLK)"] _0110,
}
impl SCSW {
#[allow(missing_docs)]