Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::CR {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::CR {
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#[doc = "Possible values of the field `SWR`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWRR {
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#[doc = "No effect."]
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_0,
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#[doc = r" Reserved"]
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_Reserved(bool),
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#[doc = "No effect."] _0,
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#[doc = r" Reserved"] _Reserved(bool),
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}
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impl SWRR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -85,10 +85,8 @@ impl SWRR {
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#[doc = "Possible values of the field `SUP`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SUPR {
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#[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
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_0,
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#[doc = "Non-supervisor mode write accesses are supported."]
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_1,
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#[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0,
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#[doc = "Non-supervisor mode write accesses are supported."] _1,
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}
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impl SUPR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -132,10 +130,8 @@ impl SUPR {
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#[doc = "Possible values of the field `UM`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum UMR {
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#[doc = "Registers cannot be written when locked."]
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_0,
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#[doc = "Registers can be written when locked under limited conditions."]
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_1,
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#[doc = "Registers cannot be written when locked."] _0,
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#[doc = "Registers can be written when locked under limited conditions."] _1,
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}
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impl UMR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -179,8 +175,7 @@ impl UMR {
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#[doc = "Possible values of the field `CPS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CPSR {
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#[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
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_0,
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#[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0,
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#[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
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_1,
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}
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@ -226,10 +221,8 @@ impl CPSR {
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#[doc = "Possible values of the field `LPOS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LPOSR {
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#[doc = "RTC prescaler increments using 32kHz crystal."]
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_0,
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#[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
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_1,
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#[doc = "RTC prescaler increments using 32kHz crystal."] _0,
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#[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1,
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}
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impl LPOSR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -273,10 +266,8 @@ impl LPOSR {
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#[doc = "Possible values of the field `CPE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CPER {
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#[doc = "Disable RTC_CLKOUT pin."]
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_0,
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#[doc = "Enable RTC_CLKOUT pin."]
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_1,
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#[doc = "Disable RTC_CLKOUT pin."] _0,
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#[doc = "Enable RTC_CLKOUT pin."] _1,
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}
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impl CPER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -319,8 +310,7 @@ impl CPER {
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}
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#[doc = "Values that can be written to the field `SWR`"]
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pub enum SWRW {
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#[doc = "No effect."]
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_0,
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#[doc = "No effect."] _0,
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}
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impl SWRW {
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#[allow(missing_docs)]
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@ -369,10 +359,8 @@ impl<'a> _SWRW<'a> {
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}
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#[doc = "Values that can be written to the field `SUP`"]
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pub enum SUPW {
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#[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
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_0,
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#[doc = "Non-supervisor mode write accesses are supported."]
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_1,
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#[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0,
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#[doc = "Non-supervisor mode write accesses are supported."] _1,
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}
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impl SUPW {
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#[allow(missing_docs)]
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@ -427,10 +415,8 @@ impl<'a> _SUPW<'a> {
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}
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#[doc = "Values that can be written to the field `UM`"]
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pub enum UMW {
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#[doc = "Registers cannot be written when locked."]
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_0,
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#[doc = "Registers can be written when locked under limited conditions."]
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_1,
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#[doc = "Registers cannot be written when locked."] _0,
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#[doc = "Registers can be written when locked under limited conditions."] _1,
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}
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impl UMW {
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#[allow(missing_docs)]
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@ -485,8 +471,7 @@ impl<'a> _UMW<'a> {
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}
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#[doc = "Values that can be written to the field `CPS`"]
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pub enum CPSW {
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#[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
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_0,
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#[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0,
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#[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
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_1,
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}
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@ -543,10 +528,8 @@ impl<'a> _CPSW<'a> {
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}
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#[doc = "Values that can be written to the field `LPOS`"]
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pub enum LPOSW {
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#[doc = "RTC prescaler increments using 32kHz crystal."]
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_0,
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#[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
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_1,
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#[doc = "RTC prescaler increments using 32kHz crystal."] _0,
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#[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1,
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}
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impl LPOSW {
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#[allow(missing_docs)]
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@ -601,10 +584,8 @@ impl<'a> _LPOSW<'a> {
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}
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#[doc = "Values that can be written to the field `CPE`"]
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pub enum CPEW {
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#[doc = "Disable RTC_CLKOUT pin."]
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_0,
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#[doc = "Enable RTC_CLKOUT pin."]
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_1,
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#[doc = "Disable RTC_CLKOUT pin."] _0,
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#[doc = "Enable RTC_CLKOUT pin."] _1,
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}
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impl CPEW {
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#[allow(missing_docs)]
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@ -22,7 +22,9 @@ impl super::IER {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::IER {
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#[doc = "Possible values of the field `TIIE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TIIER {
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#[doc = "Time invalid flag does not generate an interrupt."]
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_0,
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#[doc = "Time invalid flag does generate an interrupt."]
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_1,
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#[doc = "Time invalid flag does not generate an interrupt."] _0,
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#[doc = "Time invalid flag does generate an interrupt."] _1,
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}
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impl TIIER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,10 +90,8 @@ impl TIIER {
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#[doc = "Possible values of the field `TOIE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TOIER {
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#[doc = "Time overflow flag does not generate an interrupt."]
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_0,
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#[doc = "Time overflow flag does generate an interrupt."]
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_1,
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#[doc = "Time overflow flag does not generate an interrupt."] _0,
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#[doc = "Time overflow flag does generate an interrupt."] _1,
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}
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impl TOIER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -137,10 +135,8 @@ impl TOIER {
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#[doc = "Possible values of the field `TAIE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TAIER {
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#[doc = "Time alarm flag does not generate an interrupt."]
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_0,
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#[doc = "Time alarm flag does generate an interrupt."]
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_1,
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#[doc = "Time alarm flag does not generate an interrupt."] _0,
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#[doc = "Time alarm flag does generate an interrupt."] _1,
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}
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impl TAIER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -184,10 +180,8 @@ impl TAIER {
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#[doc = "Possible values of the field `TSIE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TSIER {
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#[doc = "Seconds interrupt is disabled."]
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_0,
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#[doc = "Seconds interrupt is enabled."]
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_1,
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#[doc = "Seconds interrupt is disabled."] _0,
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#[doc = "Seconds interrupt is enabled."] _1,
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}
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impl TSIER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -231,22 +225,14 @@ impl TSIER {
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#[doc = "Possible values of the field `TSIC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TSICR {
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#[doc = "1 Hz."]
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_000,
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#[doc = "2 Hz."]
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_001,
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#[doc = "4 Hz."]
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_010,
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#[doc = "8 Hz."]
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_011,
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#[doc = "16 Hz."]
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_100,
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#[doc = "32 Hz."]
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_101,
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#[doc = "64 Hz."]
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_110,
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#[doc = "128 Hz."]
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_111,
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#[doc = "1 Hz."] _000,
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#[doc = "2 Hz."] _001,
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#[doc = "4 Hz."] _010,
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#[doc = "8 Hz."] _011,
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#[doc = "16 Hz."] _100,
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#[doc = "32 Hz."] _101,
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#[doc = "64 Hz."] _110,
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#[doc = "128 Hz."] _111,
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}
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impl TSICR {
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#[doc = r" Value of the field as raw bits"]
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@ -322,10 +308,8 @@ impl TSICR {
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}
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#[doc = "Values that can be written to the field `TIIE`"]
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pub enum TIIEW {
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#[doc = "Time invalid flag does not generate an interrupt."]
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_0,
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#[doc = "Time invalid flag does generate an interrupt."]
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_1,
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#[doc = "Time invalid flag does not generate an interrupt."] _0,
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#[doc = "Time invalid flag does generate an interrupt."] _1,
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}
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impl TIIEW {
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#[allow(missing_docs)]
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@ -380,10 +364,8 @@ impl<'a> _TIIEW<'a> {
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}
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#[doc = "Values that can be written to the field `TOIE`"]
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pub enum TOIEW {
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#[doc = "Time overflow flag does not generate an interrupt."]
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_0,
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#[doc = "Time overflow flag does generate an interrupt."]
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_1,
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#[doc = "Time overflow flag does not generate an interrupt."] _0,
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#[doc = "Time overflow flag does generate an interrupt."] _1,
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}
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impl TOIEW {
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#[allow(missing_docs)]
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@ -438,10 +420,8 @@ impl<'a> _TOIEW<'a> {
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}
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#[doc = "Values that can be written to the field `TAIE`"]
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pub enum TAIEW {
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#[doc = "Time alarm flag does not generate an interrupt."]
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_0,
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#[doc = "Time alarm flag does generate an interrupt."]
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_1,
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#[doc = "Time alarm flag does not generate an interrupt."] _0,
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#[doc = "Time alarm flag does generate an interrupt."] _1,
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}
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impl TAIEW {
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#[allow(missing_docs)]
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@ -496,10 +476,8 @@ impl<'a> _TAIEW<'a> {
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}
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#[doc = "Values that can be written to the field `TSIE`"]
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pub enum TSIEW {
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#[doc = "Seconds interrupt is disabled."]
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_0,
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#[doc = "Seconds interrupt is enabled."]
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_1,
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#[doc = "Seconds interrupt is disabled."] _0,
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#[doc = "Seconds interrupt is enabled."] _1,
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}
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impl TSIEW {
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#[allow(missing_docs)]
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@ -554,22 +532,14 @@ impl<'a> _TSIEW<'a> {
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}
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#[doc = "Values that can be written to the field `TSIC`"]
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pub enum TSICW {
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#[doc = "1 Hz."]
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_000,
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#[doc = "2 Hz."]
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_001,
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#[doc = "4 Hz."]
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_010,
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#[doc = "8 Hz."]
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_011,
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#[doc = "16 Hz."]
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_100,
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#[doc = "32 Hz."]
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_101,
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#[doc = "64 Hz."]
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_110,
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#[doc = "128 Hz."]
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_111,
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#[doc = "1 Hz."] _000,
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#[doc = "2 Hz."] _001,
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#[doc = "4 Hz."] _010,
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#[doc = "8 Hz."] _011,
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#[doc = "16 Hz."] _100,
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#[doc = "32 Hz."] _101,
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#[doc = "64 Hz."] _110,
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#[doc = "128 Hz."] _111,
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}
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impl TSICW {
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#[allow(missing_docs)]
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@ -22,7 +22,9 @@ impl super::LR {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::LR {
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#[doc = "Possible values of the field `TCL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TCLR {
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#[doc = "Time Compensation Register is locked and writes are ignored."]
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_0,
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
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_1,
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#[doc = "Time Compensation Register is locked and writes are ignored."] _0,
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#[doc = "Time Compensation Register is not locked and writes complete as normal."] _1,
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}
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impl TCLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,10 +90,8 @@ impl TCLR {
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#[doc = "Possible values of the field `CRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CRLR {
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#[doc = "Control Register is locked and writes are ignored."]
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_0,
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#[doc = "Control Register is not locked and writes complete as normal."]
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_1,
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#[doc = "Control Register is locked and writes are ignored."] _0,
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#[doc = "Control Register is not locked and writes complete as normal."] _1,
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}
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impl CRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -137,10 +135,8 @@ impl CRLR {
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#[doc = "Possible values of the field `SRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SRLR {
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#[doc = "Status Register is locked and writes are ignored."]
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_0,
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#[doc = "Status Register is not locked and writes complete as normal."]
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_1,
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#[doc = "Status Register is locked and writes are ignored."] _0,
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#[doc = "Status Register is not locked and writes complete as normal."] _1,
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}
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impl SRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -184,10 +180,8 @@ impl SRLR {
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#[doc = "Possible values of the field `LRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
|
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pub enum LRLR {
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#[doc = "Lock Register is locked and writes are ignored."]
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_0,
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#[doc = "Lock Register is not locked and writes complete as normal."]
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_1,
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#[doc = "Lock Register is locked and writes are ignored."] _0,
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#[doc = "Lock Register is not locked and writes complete as normal."] _1,
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}
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impl LRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -230,10 +224,8 @@ impl LRLR {
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}
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#[doc = "Values that can be written to the field `TCL`"]
|
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pub enum TCLW {
|
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#[doc = "Time Compensation Register is locked and writes are ignored."]
|
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_0,
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
|
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_1,
|
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#[doc = "Time Compensation Register is locked and writes are ignored."] _0,
|
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#[doc = "Time Compensation Register is not locked and writes complete as normal."] _1,
|
||||
}
|
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impl TCLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -288,10 +280,8 @@ impl<'a> _TCLW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CRL`"]
|
||||
pub enum CRLW {
|
||||
#[doc = "Control Register is locked and writes are ignored."]
|
||||
_0,
|
||||
#[doc = "Control Register is not locked and writes complete as normal."]
|
||||
_1,
|
||||
#[doc = "Control Register is locked and writes are ignored."] _0,
|
||||
#[doc = "Control Register is not locked and writes complete as normal."] _1,
|
||||
}
|
||||
impl CRLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -346,10 +336,8 @@ impl<'a> _CRLW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SRL`"]
|
||||
pub enum SRLW {
|
||||
#[doc = "Status Register is locked and writes are ignored."]
|
||||
_0,
|
||||
#[doc = "Status Register is not locked and writes complete as normal."]
|
||||
_1,
|
||||
#[doc = "Status Register is locked and writes are ignored."] _0,
|
||||
#[doc = "Status Register is not locked and writes complete as normal."] _1,
|
||||
}
|
||||
impl SRLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -404,10 +392,8 @@ impl<'a> _SRLW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LRL`"]
|
||||
pub enum LRLW {
|
||||
#[doc = "Lock Register is locked and writes are ignored."]
|
||||
_0,
|
||||
#[doc = "Lock Register is not locked and writes complete as normal."]
|
||||
_1,
|
||||
#[doc = "Lock Register is locked and writes are ignored."] _0,
|
||||
#[doc = "Lock Register is not locked and writes complete as normal."] _1,
|
||||
}
|
||||
impl LRLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -2,22 +2,14 @@ use vcell::VolatileCell;
|
||||
#[doc = r" Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - RTC Time Seconds Register"]
|
||||
pub tsr: TSR,
|
||||
#[doc = "0x04 - RTC Time Prescaler Register"]
|
||||
pub tpr: TPR,
|
||||
#[doc = "0x08 - RTC Time Alarm Register"]
|
||||
pub tar: TAR,
|
||||
#[doc = "0x0c - RTC Time Compensation Register"]
|
||||
pub tcr: TCR,
|
||||
#[doc = "0x10 - RTC Control Register"]
|
||||
pub cr: CR,
|
||||
#[doc = "0x14 - RTC Status Register"]
|
||||
pub sr: SR,
|
||||
#[doc = "0x18 - RTC Lock Register"]
|
||||
pub lr: LR,
|
||||
#[doc = "0x1c - RTC Interrupt Enable Register"]
|
||||
pub ier: IER,
|
||||
#[doc = "0x00 - RTC Time Seconds Register"] pub tsr: TSR,
|
||||
#[doc = "0x04 - RTC Time Prescaler Register"] pub tpr: TPR,
|
||||
#[doc = "0x08 - RTC Time Alarm Register"] pub tar: TAR,
|
||||
#[doc = "0x0c - RTC Time Compensation Register"] pub tcr: TCR,
|
||||
#[doc = "0x10 - RTC Control Register"] pub cr: CR,
|
||||
#[doc = "0x14 - RTC Status Register"] pub sr: SR,
|
||||
#[doc = "0x18 - RTC Lock Register"] pub lr: LR,
|
||||
#[doc = "0x1c - RTC Interrupt Enable Register"] pub ier: IER,
|
||||
}
|
||||
#[doc = "RTC Time Seconds Register"]
|
||||
pub struct TSR {
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::SR {
|
||||
#[doc = "Possible values of the field `TIF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIFR {
|
||||
#[doc = "Time is valid."]
|
||||
_0,
|
||||
#[doc = "Time is invalid and time counter is read as zero."]
|
||||
_1,
|
||||
#[doc = "Time is valid."] _0,
|
||||
#[doc = "Time is invalid and time counter is read as zero."] _1,
|
||||
}
|
||||
impl TIFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl TIFR {
|
||||
#[doc = "Possible values of the field `TOF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TOFR {
|
||||
#[doc = "Time overflow has not occurred."]
|
||||
_0,
|
||||
#[doc = "Time overflow has occurred and time counter is read as zero."]
|
||||
_1,
|
||||
#[doc = "Time overflow has not occurred."] _0,
|
||||
#[doc = "Time overflow has occurred and time counter is read as zero."] _1,
|
||||
}
|
||||
impl TOFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,10 +135,8 @@ impl TOFR {
|
||||
#[doc = "Possible values of the field `TAF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TAFR {
|
||||
#[doc = "Time alarm has not occurred."]
|
||||
_0,
|
||||
#[doc = "Time alarm has occurred."]
|
||||
_1,
|
||||
#[doc = "Time alarm has not occurred."] _0,
|
||||
#[doc = "Time alarm has occurred."] _1,
|
||||
}
|
||||
impl TAFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -184,10 +180,8 @@ impl TAFR {
|
||||
#[doc = "Possible values of the field `TCE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TCER {
|
||||
#[doc = "Time counter is disabled."]
|
||||
_0,
|
||||
#[doc = "Time counter is enabled."]
|
||||
_1,
|
||||
#[doc = "Time counter is disabled."] _0,
|
||||
#[doc = "Time counter is enabled."] _1,
|
||||
}
|
||||
impl TCER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -230,10 +224,8 @@ impl TCER {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TCE`"]
|
||||
pub enum TCEW {
|
||||
#[doc = "Time counter is disabled."]
|
||||
_0,
|
||||
#[doc = "Time counter is enabled."]
|
||||
_1,
|
||||
#[doc = "Time counter is disabled."] _0,
|
||||
#[doc = "Time counter is enabled."] _1,
|
||||
}
|
||||
impl TCEW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TAR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TCR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::TCR {
|
||||
#[doc = "Possible values of the field `TCR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TCRR {
|
||||
#[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
|
||||
_10000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
|
||||
_10000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
|
||||
_11111111,
|
||||
#[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
|
||||
_00000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
|
||||
_00000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
|
||||
_01111110,
|
||||
#[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
|
||||
_01111111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111,
|
||||
#[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110,
|
||||
#[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TCRR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -161,20 +155,13 @@ impl CICR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TCR`"]
|
||||
pub enum TCRW {
|
||||
#[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
|
||||
_10000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
|
||||
_10000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
|
||||
_11111111,
|
||||
#[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
|
||||
_00000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
|
||||
_00000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
|
||||
_01111110,
|
||||
#[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
|
||||
_01111111,
|
||||
#[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111,
|
||||
#[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000,
|
||||
#[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001,
|
||||
#[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110,
|
||||
#[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111,
|
||||
}
|
||||
impl TCRW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TPR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TSR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
Reference in New Issue
Block a user