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This commit is contained in:
Kjetil Kjeka
348
src/pcc/mod.rs
348
src/pcc/mod.rs
@ -2,238 +2,122 @@ use vcell::VolatileCell;
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - PCC Reserved Register 0"]
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pub pccdummy0: PCCDUMMY0,
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#[doc = "0x04 - PCC Reserved Register 1"]
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pub pccdummy1: PCCDUMMY1,
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#[doc = "0x08 - PCC Reserved Register 2"]
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pub pccdummy2: PCCDUMMY2,
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#[doc = "0x0c - PCC Reserved Register 3"]
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pub pccdummy3: PCCDUMMY3,
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#[doc = "0x10 - PCC Reserved Register 4"]
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pub pccdummy4: PCCDUMMY4,
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#[doc = "0x14 - PCC Reserved Register 5"]
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pub pccdummy5: PCCDUMMY5,
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#[doc = "0x18 - PCC Reserved Register 6"]
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pub pccdummy6: PCCDUMMY6,
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#[doc = "0x1c - PCC Reserved Register 7"]
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pub pccdummy7: PCCDUMMY7,
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#[doc = "0x20 - PCC Reserved Register 8"]
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pub pccdummy8: PCCDUMMY8,
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#[doc = "0x24 - PCC Reserved Register 9"]
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pub pccdummy9: PCCDUMMY9,
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#[doc = "0x28 - PCC Reserved Register 10"]
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pub pccdummy10: PCCDUMMY10,
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#[doc = "0x2c - PCC Reserved Register 11"]
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pub pccdummy11: PCCDUMMY11,
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#[doc = "0x30 - PCC Reserved Register 12"]
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pub pccdummy12: PCCDUMMY12,
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#[doc = "0x34 - PCC Reserved Register 13"]
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pub pccdummy13: PCCDUMMY13,
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#[doc = "0x38 - PCC Reserved Register 14"]
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pub pccdummy14: PCCDUMMY14,
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#[doc = "0x3c - PCC Reserved Register 15"]
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pub pccdummy15: PCCDUMMY15,
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#[doc = "0x40 - PCC Reserved Register 16"]
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pub pccdummy16: PCCDUMMY16,
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#[doc = "0x44 - PCC Reserved Register 17"]
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pub pccdummy17: PCCDUMMY17,
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#[doc = "0x48 - PCC Reserved Register 18"]
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pub pccdummy18: PCCDUMMY18,
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#[doc = "0x4c - PCC Reserved Register 19"]
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pub pccdummy19: PCCDUMMY19,
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#[doc = "0x50 - PCC Reserved Register 20"]
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pub pccdummy20: PCCDUMMY20,
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#[doc = "0x54 - PCC Reserved Register 21"]
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pub pccdummy21: PCCDUMMY21,
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#[doc = "0x58 - PCC Reserved Register 22"]
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pub pccdummy22: PCCDUMMY22,
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#[doc = "0x5c - PCC Reserved Register 23"]
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pub pccdummy23: PCCDUMMY23,
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#[doc = "0x60 - PCC Reserved Register 24"]
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pub pccdummy24: PCCDUMMY24,
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#[doc = "0x64 - PCC Reserved Register 25"]
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pub pccdummy25: PCCDUMMY25,
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#[doc = "0x68 - PCC Reserved Register 26"]
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pub pccdummy26: PCCDUMMY26,
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#[doc = "0x6c - PCC Reserved Register 27"]
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pub pccdummy27: PCCDUMMY27,
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#[doc = "0x70 - PCC Reserved Register 28"]
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pub pccdummy28: PCCDUMMY28,
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#[doc = "0x74 - PCC Reserved Register 29"]
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pub pccdummy29: PCCDUMMY29,
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#[doc = "0x78 - PCC Reserved Register 30"]
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pub pccdummy30: PCCDUMMY30,
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#[doc = "0x7c - PCC Reserved Register 31"]
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pub pccdummy31: PCCDUMMY31,
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#[doc = "0x80 - PCC FTFC Register"]
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pub pcc_ftfc: PCC_FTFC,
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#[doc = "0x84 - PCC DMAMUX Register"]
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pub pcc_dmamux: PCC_DMAMUX,
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#[doc = "0x88 - PCC Reserved Register 34"]
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pub pccdummy34: PCCDUMMY34,
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#[doc = "0x8c - PCC Reserved Register 35"]
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pub pccdummy35: PCCDUMMY35,
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#[doc = "0x90 - PCC FlexCAN0 Register"]
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pub pcc_flex_can0: PCC_FLEXCAN0,
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#[doc = "0x94 - PCC FlexCAN1 Register"]
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pub pcc_flex_can1: PCC_FLEXCAN1,
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#[doc = "0x98 - PCC FTM3 Register"]
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pub pcc_ftm3: PCC_FTM3,
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#[doc = "0x9c - PCC ADC1 Register"]
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pub pcc_adc1: PCC_ADC1,
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#[doc = "0xa0 - PCC Reserved Register 40"]
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pub pccdummy40: PCCDUMMY40,
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#[doc = "0xa4 - PCC Reserved Register 41"]
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pub pccdummy41: PCCDUMMY41,
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#[doc = "0xa8 - PCC Reserved Register 42"]
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pub pccdummy42: PCCDUMMY42,
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#[doc = "0xac - PCC FlexCAN2 Register"]
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pub pcc_flex_can2: PCC_FLEXCAN2,
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#[doc = "0xb0 - PCC LPSPI0 Register"]
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pub pcc_lpspi0: PCC_LPSPI0,
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#[doc = "0xb4 - PCC LPSPI1 Register"]
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pub pcc_lpspi1: PCC_LPSPI1,
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#[doc = "0xb8 - PCC LPSPI2 Register"]
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pub pcc_lpspi2: PCC_LPSPI2,
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#[doc = "0xbc - PCC Reserved Register 47"]
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pub pccdummy47: PCCDUMMY47,
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#[doc = "0xc0 - PCC Reserved Register 48"]
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pub pccdummy48: PCCDUMMY48,
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#[doc = "0xc4 - PCC PDB1 Register"]
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pub pcc_pdb1: PCC_PDB1,
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#[doc = "0xc8 - PCC CRC Register"]
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pub pcc_crc: PCC_CRC,
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#[doc = "0xcc - PCC Reserved Register 51"]
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pub pccdummy51: PCCDUMMY51,
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#[doc = "0xd0 - PCC Reserved Register 52"]
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pub pccdummy52: PCCDUMMY52,
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#[doc = "0xd4 - PCC Reserved Register 53"]
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pub pccdummy53: PCCDUMMY53,
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#[doc = "0xd8 - PCC PDB0 Register"]
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pub pcc_pdb0: PCC_PDB0,
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#[doc = "0xdc - PCC LPIT Register"]
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pub pcc_lpit: PCC_LPIT,
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#[doc = "0xe0 - PCC FTM0 Register"]
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pub pcc_ftm0: PCC_FTM0,
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#[doc = "0xe4 - PCC FTM1 Register"]
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pub pcc_ftm1: PCC_FTM1,
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#[doc = "0xe8 - PCC FTM2 Register"]
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pub pcc_ftm2: PCC_FTM2,
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#[doc = "0xec - PCC ADC0 Register"]
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pub pcc_adc0: PCC_ADC0,
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#[doc = "0xf0 - PCC Reserved Register 60"]
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pub pccdummy60: PCCDUMMY60,
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#[doc = "0xf4 - PCC RTC Register"]
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pub pcc_rtc: PCC_RTC,
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#[doc = "0xf8 - PCC Reserved Register 62"]
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pub pccdummy62: PCCDUMMY62,
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#[doc = "0xfc - PCC Reserved Register 63"]
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pub pccdummy63: PCCDUMMY63,
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#[doc = "0x100 - PCC LPTMR0 Register"]
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pub pcc_lptmr0: PCC_LPTMR0,
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#[doc = "0x104 - PCC Reserved Register 65"]
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pub pccdummy65: PCCDUMMY65,
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#[doc = "0x108 - PCC Reserved Register 66"]
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pub pccdummy66: PCCDUMMY66,
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#[doc = "0x10c - PCC Reserved Register 67"]
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pub pccdummy67: PCCDUMMY67,
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#[doc = "0x110 - PCC Reserved Register 68"]
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pub pccdummy68: PCCDUMMY68,
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#[doc = "0x114 - PCC Reserved Register 69"]
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pub pccdummy69: PCCDUMMY69,
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#[doc = "0x118 - PCC Reserved Register 70"]
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pub pccdummy70: PCCDUMMY70,
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#[doc = "0x11c - PCC Reserved Register 71"]
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pub pccdummy71: PCCDUMMY71,
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#[doc = "0x120 - PCC Reserved Register 72"]
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pub pccdummy72: PCCDUMMY72,
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#[doc = "0x124 - PCC PORTA Register"]
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pub pcc_porta: PCC_PORTA,
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#[doc = "0x128 - PCC PORTB Register"]
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pub pcc_portb: PCC_PORTB,
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#[doc = "0x12c - PCC PORTC Register"]
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pub pcc_portc: PCC_PORTC,
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#[doc = "0x130 - PCC PORTD Register"]
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pub pcc_portd: PCC_PORTD,
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#[doc = "0x134 - PCC PORTE Register"]
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pub pcc_porte: PCC_PORTE,
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#[doc = "0x138 - PCC Reserved Register 78"]
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pub pccdummy78: PCCDUMMY78,
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#[doc = "0x13c - PCC Reserved Register 79"]
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pub pccdummy79: PCCDUMMY79,
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#[doc = "0x140 - PCC Reserved Register 80"]
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pub pccdummy80: PCCDUMMY80,
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#[doc = "0x144 - PCC Reserved Register 81"]
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pub pccdummy81: PCCDUMMY81,
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#[doc = "0x148 - PCC Reserved Register 82"]
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pub pccdummy82: PCCDUMMY82,
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#[doc = "0x14c - PCC Reserved Register 83"]
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pub pccdummy83: PCCDUMMY83,
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#[doc = "0x150 - PCC Reserved Register 84"]
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pub pccdummy84: PCCDUMMY84,
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#[doc = "0x154 - PCC Reserved Register 85"]
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pub pccdummy85: PCCDUMMY85,
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#[doc = "0x158 - PCC Reserved Register 86"]
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pub pccdummy86: PCCDUMMY86,
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#[doc = "0x15c - PCC Reserved Register 87"]
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pub pccdummy87: PCCDUMMY87,
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#[doc = "0x160 - PCC Reserved Register 88"]
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pub pccdummy88: PCCDUMMY88,
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#[doc = "0x164 - PCC Reserved Register 89"]
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pub pccdummy89: PCCDUMMY89,
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#[doc = "0x168 - PCC FlexIO Register"]
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pub pcc_flexio: PCC_FLEXIO,
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#[doc = "0x16c - PCC Reserved Register 91"]
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pub pccdummy91: PCCDUMMY91,
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#[doc = "0x170 - PCC Reserved Register 92"]
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pub pccdummy92: PCCDUMMY92,
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#[doc = "0x174 - PCC Reserved Register 93"]
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pub pccdummy93: PCCDUMMY93,
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#[doc = "0x178 - PCC Reserved Register 94"]
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pub pccdummy94: PCCDUMMY94,
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#[doc = "0x17c - PCC Reserved Register 95"]
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pub pccdummy95: PCCDUMMY95,
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#[doc = "0x180 - PCC Reserved Register 96"]
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pub pccdummy96: PCCDUMMY96,
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#[doc = "0x184 - PCC EWM Register"]
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pub pcc_ewm: PCC_EWM,
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#[doc = "0x188 - PCC Reserved Register 98"]
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pub pccdummy98: PCCDUMMY98,
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#[doc = "0x18c - PCC Reserved Register 99"]
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pub pccdummy99: PCCDUMMY99,
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#[doc = "0x190 - PCC Reserved Register 100"]
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pub pccdummy100: PCCDUMMY100,
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#[doc = "0x194 - PCC Reserved Register 101"]
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pub pccdummy101: PCCDUMMY101,
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#[doc = "0x198 - PCC LPI2C0 Register"]
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pub pcc_lpi2c0: PCC_LPI2C0,
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#[doc = "0x19c - PCC Reserved Register 103"]
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pub pccdummy103: PCCDUMMY103,
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#[doc = "0x1a0 - PCC Reserved Register 104"]
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pub pccdummy104: PCCDUMMY104,
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#[doc = "0x1a4 - PCC Reserved Register 105"]
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pub pccdummy105: PCCDUMMY105,
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#[doc = "0x1a8 - PCC LPUART0 Register"]
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pub pcc_lpuart0: PCC_LPUART0,
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#[doc = "0x1ac - PCC LPUART1 Register"]
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pub pcc_lpuart1: PCC_LPUART1,
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#[doc = "0x1b0 - PCC LPUART2 Register"]
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pub pcc_lpuart2: PCC_LPUART2,
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#[doc = "0x1b4 - PCC Reserved Register 109"]
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pub pccdummy109: PCCDUMMY109,
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#[doc = "0x1b8 - PCC Reserved Register 110"]
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pub pccdummy110: PCCDUMMY110,
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#[doc = "0x1bc - PCC Reserved Register 111"]
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pub pccdummy111: PCCDUMMY111,
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#[doc = "0x1c0 - PCC Reserved Register 112"]
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pub pccdummy112: PCCDUMMY112,
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#[doc = "0x1c4 - PCC Reserved Register 113"]
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pub pccdummy113: PCCDUMMY113,
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#[doc = "0x1c8 - PCC Reserved Register 114"]
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pub pccdummy114: PCCDUMMY114,
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#[doc = "0x1cc - PCC CMP0 Register"]
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pub pcc_cmp0: PCC_CMP0,
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#[doc = "0x00 - PCC Reserved Register 0"] pub pccdummy0: PCCDUMMY0,
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#[doc = "0x04 - PCC Reserved Register 1"] pub pccdummy1: PCCDUMMY1,
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#[doc = "0x08 - PCC Reserved Register 2"] pub pccdummy2: PCCDUMMY2,
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#[doc = "0x0c - PCC Reserved Register 3"] pub pccdummy3: PCCDUMMY3,
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#[doc = "0x10 - PCC Reserved Register 4"] pub pccdummy4: PCCDUMMY4,
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#[doc = "0x14 - PCC Reserved Register 5"] pub pccdummy5: PCCDUMMY5,
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#[doc = "0x18 - PCC Reserved Register 6"] pub pccdummy6: PCCDUMMY6,
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#[doc = "0x1c - PCC Reserved Register 7"] pub pccdummy7: PCCDUMMY7,
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#[doc = "0x20 - PCC Reserved Register 8"] pub pccdummy8: PCCDUMMY8,
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#[doc = "0x24 - PCC Reserved Register 9"] pub pccdummy9: PCCDUMMY9,
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#[doc = "0x28 - PCC Reserved Register 10"] pub pccdummy10: PCCDUMMY10,
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#[doc = "0x2c - PCC Reserved Register 11"] pub pccdummy11: PCCDUMMY11,
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#[doc = "0x30 - PCC Reserved Register 12"] pub pccdummy12: PCCDUMMY12,
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#[doc = "0x34 - PCC Reserved Register 13"] pub pccdummy13: PCCDUMMY13,
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#[doc = "0x38 - PCC Reserved Register 14"] pub pccdummy14: PCCDUMMY14,
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#[doc = "0x3c - PCC Reserved Register 15"] pub pccdummy15: PCCDUMMY15,
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#[doc = "0x40 - PCC Reserved Register 16"] pub pccdummy16: PCCDUMMY16,
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#[doc = "0x44 - PCC Reserved Register 17"] pub pccdummy17: PCCDUMMY17,
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#[doc = "0x48 - PCC Reserved Register 18"] pub pccdummy18: PCCDUMMY18,
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#[doc = "0x4c - PCC Reserved Register 19"] pub pccdummy19: PCCDUMMY19,
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#[doc = "0x50 - PCC Reserved Register 20"] pub pccdummy20: PCCDUMMY20,
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#[doc = "0x54 - PCC Reserved Register 21"] pub pccdummy21: PCCDUMMY21,
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#[doc = "0x58 - PCC Reserved Register 22"] pub pccdummy22: PCCDUMMY22,
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#[doc = "0x5c - PCC Reserved Register 23"] pub pccdummy23: PCCDUMMY23,
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#[doc = "0x60 - PCC Reserved Register 24"] pub pccdummy24: PCCDUMMY24,
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#[doc = "0x64 - PCC Reserved Register 25"] pub pccdummy25: PCCDUMMY25,
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#[doc = "0x68 - PCC Reserved Register 26"] pub pccdummy26: PCCDUMMY26,
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#[doc = "0x6c - PCC Reserved Register 27"] pub pccdummy27: PCCDUMMY27,
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#[doc = "0x70 - PCC Reserved Register 28"] pub pccdummy28: PCCDUMMY28,
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#[doc = "0x74 - PCC Reserved Register 29"] pub pccdummy29: PCCDUMMY29,
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#[doc = "0x78 - PCC Reserved Register 30"] pub pccdummy30: PCCDUMMY30,
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#[doc = "0x7c - PCC Reserved Register 31"] pub pccdummy31: PCCDUMMY31,
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#[doc = "0x80 - PCC FTFC Register"] pub pcc_ftfc: PCC_FTFC,
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#[doc = "0x84 - PCC DMAMUX Register"] pub pcc_dmamux: PCC_DMAMUX,
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#[doc = "0x88 - PCC Reserved Register 34"] pub pccdummy34: PCCDUMMY34,
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#[doc = "0x8c - PCC Reserved Register 35"] pub pccdummy35: PCCDUMMY35,
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#[doc = "0x90 - PCC FlexCAN0 Register"] pub pcc_flex_can0: PCC_FLEXCAN0,
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#[doc = "0x94 - PCC FlexCAN1 Register"] pub pcc_flex_can1: PCC_FLEXCAN1,
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#[doc = "0x98 - PCC FTM3 Register"] pub pcc_ftm3: PCC_FTM3,
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#[doc = "0x9c - PCC ADC1 Register"] pub pcc_adc1: PCC_ADC1,
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#[doc = "0xa0 - PCC Reserved Register 40"] pub pccdummy40: PCCDUMMY40,
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#[doc = "0xa4 - PCC Reserved Register 41"] pub pccdummy41: PCCDUMMY41,
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#[doc = "0xa8 - PCC Reserved Register 42"] pub pccdummy42: PCCDUMMY42,
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#[doc = "0xac - PCC FlexCAN2 Register"] pub pcc_flex_can2: PCC_FLEXCAN2,
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#[doc = "0xb0 - PCC LPSPI0 Register"] pub pcc_lpspi0: PCC_LPSPI0,
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#[doc = "0xb4 - PCC LPSPI1 Register"] pub pcc_lpspi1: PCC_LPSPI1,
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#[doc = "0xb8 - PCC LPSPI2 Register"] pub pcc_lpspi2: PCC_LPSPI2,
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#[doc = "0xbc - PCC Reserved Register 47"] pub pccdummy47: PCCDUMMY47,
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#[doc = "0xc0 - PCC Reserved Register 48"] pub pccdummy48: PCCDUMMY48,
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#[doc = "0xc4 - PCC PDB1 Register"] pub pcc_pdb1: PCC_PDB1,
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#[doc = "0xc8 - PCC CRC Register"] pub pcc_crc: PCC_CRC,
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#[doc = "0xcc - PCC Reserved Register 51"] pub pccdummy51: PCCDUMMY51,
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#[doc = "0xd0 - PCC Reserved Register 52"] pub pccdummy52: PCCDUMMY52,
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#[doc = "0xd4 - PCC Reserved Register 53"] pub pccdummy53: PCCDUMMY53,
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#[doc = "0xd8 - PCC PDB0 Register"] pub pcc_pdb0: PCC_PDB0,
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#[doc = "0xdc - PCC LPIT Register"] pub pcc_lpit: PCC_LPIT,
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#[doc = "0xe0 - PCC FTM0 Register"] pub pcc_ftm0: PCC_FTM0,
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#[doc = "0xe4 - PCC FTM1 Register"] pub pcc_ftm1: PCC_FTM1,
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#[doc = "0xe8 - PCC FTM2 Register"] pub pcc_ftm2: PCC_FTM2,
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#[doc = "0xec - PCC ADC0 Register"] pub pcc_adc0: PCC_ADC0,
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#[doc = "0xf0 - PCC Reserved Register 60"] pub pccdummy60: PCCDUMMY60,
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#[doc = "0xf4 - PCC RTC Register"] pub pcc_rtc: PCC_RTC,
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#[doc = "0xf8 - PCC Reserved Register 62"] pub pccdummy62: PCCDUMMY62,
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#[doc = "0xfc - PCC Reserved Register 63"] pub pccdummy63: PCCDUMMY63,
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#[doc = "0x100 - PCC LPTMR0 Register"] pub pcc_lptmr0: PCC_LPTMR0,
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#[doc = "0x104 - PCC Reserved Register 65"] pub pccdummy65: PCCDUMMY65,
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#[doc = "0x108 - PCC Reserved Register 66"] pub pccdummy66: PCCDUMMY66,
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#[doc = "0x10c - PCC Reserved Register 67"] pub pccdummy67: PCCDUMMY67,
|
||||
#[doc = "0x110 - PCC Reserved Register 68"] pub pccdummy68: PCCDUMMY68,
|
||||
#[doc = "0x114 - PCC Reserved Register 69"] pub pccdummy69: PCCDUMMY69,
|
||||
#[doc = "0x118 - PCC Reserved Register 70"] pub pccdummy70: PCCDUMMY70,
|
||||
#[doc = "0x11c - PCC Reserved Register 71"] pub pccdummy71: PCCDUMMY71,
|
||||
#[doc = "0x120 - PCC Reserved Register 72"] pub pccdummy72: PCCDUMMY72,
|
||||
#[doc = "0x124 - PCC PORTA Register"] pub pcc_porta: PCC_PORTA,
|
||||
#[doc = "0x128 - PCC PORTB Register"] pub pcc_portb: PCC_PORTB,
|
||||
#[doc = "0x12c - PCC PORTC Register"] pub pcc_portc: PCC_PORTC,
|
||||
#[doc = "0x130 - PCC PORTD Register"] pub pcc_portd: PCC_PORTD,
|
||||
#[doc = "0x134 - PCC PORTE Register"] pub pcc_porte: PCC_PORTE,
|
||||
#[doc = "0x138 - PCC Reserved Register 78"] pub pccdummy78: PCCDUMMY78,
|
||||
#[doc = "0x13c - PCC Reserved Register 79"] pub pccdummy79: PCCDUMMY79,
|
||||
#[doc = "0x140 - PCC Reserved Register 80"] pub pccdummy80: PCCDUMMY80,
|
||||
#[doc = "0x144 - PCC Reserved Register 81"] pub pccdummy81: PCCDUMMY81,
|
||||
#[doc = "0x148 - PCC Reserved Register 82"] pub pccdummy82: PCCDUMMY82,
|
||||
#[doc = "0x14c - PCC Reserved Register 83"] pub pccdummy83: PCCDUMMY83,
|
||||
#[doc = "0x150 - PCC Reserved Register 84"] pub pccdummy84: PCCDUMMY84,
|
||||
#[doc = "0x154 - PCC Reserved Register 85"] pub pccdummy85: PCCDUMMY85,
|
||||
#[doc = "0x158 - PCC Reserved Register 86"] pub pccdummy86: PCCDUMMY86,
|
||||
#[doc = "0x15c - PCC Reserved Register 87"] pub pccdummy87: PCCDUMMY87,
|
||||
#[doc = "0x160 - PCC Reserved Register 88"] pub pccdummy88: PCCDUMMY88,
|
||||
#[doc = "0x164 - PCC Reserved Register 89"] pub pccdummy89: PCCDUMMY89,
|
||||
#[doc = "0x168 - PCC FlexIO Register"] pub pcc_flexio: PCC_FLEXIO,
|
||||
#[doc = "0x16c - PCC Reserved Register 91"] pub pccdummy91: PCCDUMMY91,
|
||||
#[doc = "0x170 - PCC Reserved Register 92"] pub pccdummy92: PCCDUMMY92,
|
||||
#[doc = "0x174 - PCC Reserved Register 93"] pub pccdummy93: PCCDUMMY93,
|
||||
#[doc = "0x178 - PCC Reserved Register 94"] pub pccdummy94: PCCDUMMY94,
|
||||
#[doc = "0x17c - PCC Reserved Register 95"] pub pccdummy95: PCCDUMMY95,
|
||||
#[doc = "0x180 - PCC Reserved Register 96"] pub pccdummy96: PCCDUMMY96,
|
||||
#[doc = "0x184 - PCC EWM Register"] pub pcc_ewm: PCC_EWM,
|
||||
#[doc = "0x188 - PCC Reserved Register 98"] pub pccdummy98: PCCDUMMY98,
|
||||
#[doc = "0x18c - PCC Reserved Register 99"] pub pccdummy99: PCCDUMMY99,
|
||||
#[doc = "0x190 - PCC Reserved Register 100"] pub pccdummy100: PCCDUMMY100,
|
||||
#[doc = "0x194 - PCC Reserved Register 101"] pub pccdummy101: PCCDUMMY101,
|
||||
#[doc = "0x198 - PCC LPI2C0 Register"] pub pcc_lpi2c0: PCC_LPI2C0,
|
||||
#[doc = "0x19c - PCC Reserved Register 103"] pub pccdummy103: PCCDUMMY103,
|
||||
#[doc = "0x1a0 - PCC Reserved Register 104"] pub pccdummy104: PCCDUMMY104,
|
||||
#[doc = "0x1a4 - PCC Reserved Register 105"] pub pccdummy105: PCCDUMMY105,
|
||||
#[doc = "0x1a8 - PCC LPUART0 Register"] pub pcc_lpuart0: PCC_LPUART0,
|
||||
#[doc = "0x1ac - PCC LPUART1 Register"] pub pcc_lpuart1: PCC_LPUART1,
|
||||
#[doc = "0x1b0 - PCC LPUART2 Register"] pub pcc_lpuart2: PCC_LPUART2,
|
||||
#[doc = "0x1b4 - PCC Reserved Register 109"] pub pccdummy109: PCCDUMMY109,
|
||||
#[doc = "0x1b8 - PCC Reserved Register 110"] pub pccdummy110: PCCDUMMY110,
|
||||
#[doc = "0x1bc - PCC Reserved Register 111"] pub pccdummy111: PCCDUMMY111,
|
||||
#[doc = "0x1c0 - PCC Reserved Register 112"] pub pccdummy112: PCCDUMMY112,
|
||||
#[doc = "0x1c4 - PCC Reserved Register 113"] pub pccdummy113: PCCDUMMY113,
|
||||
#[doc = "0x1c8 - PCC Reserved Register 114"] pub pccdummy114: PCCDUMMY114,
|
||||
#[doc = "0x1cc - PCC CMP0 Register"] pub pcc_cmp0: PCC_CMP0,
|
||||
}
|
||||
#[doc = "PCC Reserved Register 0"]
|
||||
pub struct PCCDUMMY0 {
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_ADC0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_ADC0 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_ADC1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_ADC1 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_CMP0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_CMP0 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_CRC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_CRC {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_DMAMUX {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_DMAMUX {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_EWM {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_EWM {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN0 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN1 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FLEXCAN2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_FLEXCAN2 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FLEXIO {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_FLEXIO {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FTFC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_FTFC {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FTM0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_FTM0 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FTM1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_FTM1 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FTM2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_FTM2 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_FTM3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_FTM3 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off. An external clock can be enabled for this peripheral."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPI2C0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPI2C0 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPIT {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPIT {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPSPI0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPSPI0 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPSPI1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPSPI1 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPSPI2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPSPI2 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPTMR0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPTMR0 {
|
||||
#[doc = "Possible values of the field `PCD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCDR {
|
||||
#[doc = "Divide by 1."]
|
||||
_000,
|
||||
#[doc = "Divide by 2."]
|
||||
_001,
|
||||
#[doc = "Divide by 3."]
|
||||
_010,
|
||||
#[doc = "Divide by 4."]
|
||||
_011,
|
||||
#[doc = "Divide by 5."]
|
||||
_100,
|
||||
#[doc = "Divide by 6."]
|
||||
_101,
|
||||
#[doc = "Divide by 7."]
|
||||
_110,
|
||||
#[doc = "Divide by 8."]
|
||||
_111,
|
||||
#[doc = "Divide by 1."] _000,
|
||||
#[doc = "Divide by 2."] _001,
|
||||
#[doc = "Divide by 3."] _010,
|
||||
#[doc = "Divide by 4."] _011,
|
||||
#[doc = "Divide by 5."] _100,
|
||||
#[doc = "Divide by 6."] _101,
|
||||
#[doc = "Divide by 7."] _110,
|
||||
#[doc = "Divide by 8."] _111,
|
||||
}
|
||||
impl PCDR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCDR {
|
||||
#[doc = "Possible values of the field `FRAC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FRACR {
|
||||
#[doc = "Fractional value is 0."]
|
||||
_0,
|
||||
#[doc = "Fractional value is 1."]
|
||||
_1,
|
||||
#[doc = "Fractional value is 0."] _0,
|
||||
#[doc = "Fractional value is 1."] _1,
|
||||
}
|
||||
impl FRACR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,22 +174,14 @@ impl FRACR {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -274,10 +258,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -321,10 +303,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -367,22 +347,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCD`"]
|
||||
pub enum PCDW {
|
||||
#[doc = "Divide by 1."]
|
||||
_000,
|
||||
#[doc = "Divide by 2."]
|
||||
_001,
|
||||
#[doc = "Divide by 3."]
|
||||
_010,
|
||||
#[doc = "Divide by 4."]
|
||||
_011,
|
||||
#[doc = "Divide by 5."]
|
||||
_100,
|
||||
#[doc = "Divide by 6."]
|
||||
_101,
|
||||
#[doc = "Divide by 7."]
|
||||
_110,
|
||||
#[doc = "Divide by 8."]
|
||||
_111,
|
||||
#[doc = "Divide by 1."] _000,
|
||||
#[doc = "Divide by 2."] _001,
|
||||
#[doc = "Divide by 3."] _010,
|
||||
#[doc = "Divide by 4."] _011,
|
||||
#[doc = "Divide by 5."] _100,
|
||||
#[doc = "Divide by 6."] _101,
|
||||
#[doc = "Divide by 7."] _110,
|
||||
#[doc = "Divide by 8."] _111,
|
||||
}
|
||||
impl PCDW {
|
||||
#[allow(missing_docs)]
|
||||
@ -465,10 +437,8 @@ impl<'a> _PCDW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FRAC`"]
|
||||
pub enum FRACW {
|
||||
#[doc = "Fractional value is 0."]
|
||||
_0,
|
||||
#[doc = "Fractional value is 1."]
|
||||
_1,
|
||||
#[doc = "Fractional value is 0."] _0,
|
||||
#[doc = "Fractional value is 1."] _1,
|
||||
}
|
||||
impl FRACW {
|
||||
#[allow(missing_docs)]
|
||||
@ -523,22 +493,14 @@ impl<'a> _FRACW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -621,10 +583,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPUART0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPUART0 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPUART1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPUART1 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_LPUART2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,22 +45,14 @@ impl super::PCC_LPUART2 {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -135,10 +129,8 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -182,10 +174,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -228,22 +218,14 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Clock is off."]
|
||||
_000,
|
||||
#[doc = "Clock option 1"]
|
||||
_001,
|
||||
#[doc = "Clock option 2"]
|
||||
_010,
|
||||
#[doc = "Clock option 3"]
|
||||
_011,
|
||||
#[doc = "Clock option 4"]
|
||||
_100,
|
||||
#[doc = "Clock option 5"]
|
||||
_101,
|
||||
#[doc = "Clock option 6"]
|
||||
_110,
|
||||
#[doc = "Clock option 7"]
|
||||
_111,
|
||||
#[doc = "Clock is off."] _000,
|
||||
#[doc = "Clock option 1"] _001,
|
||||
#[doc = "Clock option 2"] _010,
|
||||
#[doc = "Clock option 3"] _011,
|
||||
#[doc = "Clock option 4"] _100,
|
||||
#[doc = "Clock option 5"] _101,
|
||||
#[doc = "Clock option 6"] _110,
|
||||
#[doc = "Clock option 7"] _111,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -326,10 +308,8 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PDB0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PDB0 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PDB1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PDB1 {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PORTA {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PORTA {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PORTB {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PORTB {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PORTC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PORTC {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PORTD {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PORTD {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_PORTE {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_PORTE {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCC_RTC {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::PCC_RTC {
|
||||
#[doc = "Possible values of the field `CGC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CGCR {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl CGCR {
|
||||
#[doc = "Possible values of the field `PR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRR {
|
||||
#[doc = "Peripheral is not present."]
|
||||
_0,
|
||||
#[doc = "Peripheral is present."]
|
||||
_1,
|
||||
#[doc = "Peripheral is not present."] _0,
|
||||
#[doc = "Peripheral is present."] _1,
|
||||
}
|
||||
impl PRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl PRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CGC`"]
|
||||
pub enum CGCW {
|
||||
#[doc = "Clock disabled"]
|
||||
_0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."]
|
||||
_1,
|
||||
#[doc = "Clock disabled"] _0,
|
||||
#[doc = "Clock enabled. The current clock selection and divider options are locked."] _1,
|
||||
}
|
||||
impl CGCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY10 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY100 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY101 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY103 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY104 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY105 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY109 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY11 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY110 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY111 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY112 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY113 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY114 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY12 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY13 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY14 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY15 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY16 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY17 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY18 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY19 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY20 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY21 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY22 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY23 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY24 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY25 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY26 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY27 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY28 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY29 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY30 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY31 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY34 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY35 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY4 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY40 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY41 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY42 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY47 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY48 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY5 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY51 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY52 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY53 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY6 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY60 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY62 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY63 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY65 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY66 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY67 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY68 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY69 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY7 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY70 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY71 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY72 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY78 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY79 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY8 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY80 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::PCCDUMMY81 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user