Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::CCR {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CFGR0 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::CFGR0 {
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#[doc = "Possible values of the field `HREN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HRENR {
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#[doc = "Host request is disabled."]
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_0,
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#[doc = "Host request is enabled."]
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_1,
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#[doc = "Host request is disabled."] _0,
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#[doc = "Host request is enabled."] _1,
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}
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impl HRENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,10 +90,8 @@ impl HRENR {
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#[doc = "Possible values of the field `HRPOL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HRPOLR {
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#[doc = "Active low."]
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_0,
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#[doc = "Active high."]
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_1,
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#[doc = "Active low."] _0,
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#[doc = "Active high."] _1,
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}
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impl HRPOLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -137,10 +135,8 @@ impl HRPOLR {
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#[doc = "Possible values of the field `HRSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HRSELR {
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#[doc = "Host request input is pin LPSPI_HREQ."]
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_0,
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#[doc = "Host request input is input trigger."]
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_1,
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#[doc = "Host request input is pin LPSPI_HREQ."] _0,
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#[doc = "Host request input is input trigger."] _1,
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}
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impl HRSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -184,10 +180,8 @@ impl HRSELR {
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#[doc = "Possible values of the field `CIRFIFO`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CIRFIFOR {
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#[doc = "Circular FIFO is disabled."]
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_0,
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#[doc = "Circular FIFO is enabled."]
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_1,
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#[doc = "Circular FIFO is disabled."] _0,
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#[doc = "Circular FIFO is enabled."] _1,
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}
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impl CIRFIFOR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -231,10 +225,8 @@ impl CIRFIFOR {
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#[doc = "Possible values of the field `RDMO`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum RDMOR {
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#[doc = "Received data is stored in the receive FIFO as normal."]
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_0,
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#[doc = "Received data is discarded unless the DMF is set."]
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_1,
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#[doc = "Received data is stored in the receive FIFO as normal."] _0,
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#[doc = "Received data is discarded unless the DMF is set."] _1,
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}
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impl RDMOR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -277,10 +269,8 @@ impl RDMOR {
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}
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#[doc = "Values that can be written to the field `HREN`"]
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pub enum HRENW {
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#[doc = "Host request is disabled."]
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_0,
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#[doc = "Host request is enabled."]
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_1,
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#[doc = "Host request is disabled."] _0,
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#[doc = "Host request is enabled."] _1,
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}
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impl HRENW {
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#[allow(missing_docs)]
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@ -335,10 +325,8 @@ impl<'a> _HRENW<'a> {
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}
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#[doc = "Values that can be written to the field `HRPOL`"]
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pub enum HRPOLW {
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#[doc = "Active low."]
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_0,
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#[doc = "Active high."]
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_1,
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#[doc = "Active low."] _0,
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#[doc = "Active high."] _1,
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}
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impl HRPOLW {
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#[allow(missing_docs)]
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@ -393,10 +381,8 @@ impl<'a> _HRPOLW<'a> {
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}
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#[doc = "Values that can be written to the field `HRSEL`"]
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pub enum HRSELW {
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#[doc = "Host request input is pin LPSPI_HREQ."]
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_0,
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#[doc = "Host request input is input trigger."]
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_1,
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#[doc = "Host request input is pin LPSPI_HREQ."] _0,
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#[doc = "Host request input is input trigger."] _1,
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}
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impl HRSELW {
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#[allow(missing_docs)]
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@ -451,10 +437,8 @@ impl<'a> _HRSELW<'a> {
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}
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#[doc = "Values that can be written to the field `CIRFIFO`"]
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pub enum CIRFIFOW {
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#[doc = "Circular FIFO is disabled."]
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_0,
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#[doc = "Circular FIFO is enabled."]
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_1,
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#[doc = "Circular FIFO is disabled."] _0,
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#[doc = "Circular FIFO is enabled."] _1,
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}
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impl CIRFIFOW {
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#[allow(missing_docs)]
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@ -509,10 +493,8 @@ impl<'a> _CIRFIFOW<'a> {
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}
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#[doc = "Values that can be written to the field `RDMO`"]
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pub enum RDMOW {
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#[doc = "Received data is stored in the receive FIFO as normal."]
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_0,
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#[doc = "Received data is discarded unless the DMF is set."]
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_1,
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#[doc = "Received data is stored in the receive FIFO as normal."] _0,
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#[doc = "Received data is discarded unless the DMF is set."] _1,
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}
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impl RDMOW {
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#[allow(missing_docs)]
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@ -22,7 +22,9 @@ impl super::CFGR1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::CFGR1 {
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#[doc = "Possible values of the field `MASTER`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MASTERR {
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#[doc = "Slave mode."]
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_0,
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#[doc = "Master mode."]
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_1,
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#[doc = "Slave mode."] _0,
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#[doc = "Master mode."] _1,
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}
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impl MASTERR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,10 +90,8 @@ impl MASTERR {
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#[doc = "Possible values of the field `SAMPLE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SAMPLER {
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#[doc = "Input data sampled on SCK edge."]
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_0,
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#[doc = "Input data sampled on delayed SCK edge."]
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_1,
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#[doc = "Input data sampled on SCK edge."] _0,
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#[doc = "Input data sampled on delayed SCK edge."] _1,
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}
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impl SAMPLER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -137,10 +135,8 @@ impl SAMPLER {
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#[doc = "Possible values of the field `AUTOPCS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum AUTOPCSR {
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#[doc = "Automatic PCS generation disabled."]
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_0,
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#[doc = "Automatic PCS generation enabled."]
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_1,
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#[doc = "Automatic PCS generation disabled."] _0,
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#[doc = "Automatic PCS generation enabled."] _1,
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}
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impl AUTOPCSR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -184,8 +180,7 @@ impl AUTOPCSR {
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#[doc = "Possible values of the field `NOSTALL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum NOSTALLR {
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#[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."]
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_0,
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#[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0,
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#[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."]
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_1,
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}
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@ -231,12 +226,9 @@ impl NOSTALLR {
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#[doc = "Possible values of the field `PCSPOL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PCSPOLR {
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#[doc = "The PCSx is active low."]
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_0000,
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#[doc = "The PCSx is active high."]
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_0001,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "The PCSx is active low."] _0000,
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#[doc = "The PCSx is active high."] _0001,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl PCSPOLR {
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#[doc = r" Value of the field as raw bits"]
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@ -272,8 +264,7 @@ impl PCSPOLR {
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#[doc = "Possible values of the field `MATCFG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MATCFGR {
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#[doc = "Match is disabled."]
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_000,
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#[doc = "Match is disabled."] _000,
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#[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"]
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_010,
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#[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
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@ -286,8 +277,7 @@ pub enum MATCFGR {
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_110,
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#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"]
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_111,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl MATCFGR {
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#[doc = r" Value of the field as raw bits"]
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@ -358,14 +348,10 @@ impl MATCFGR {
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#[doc = "Possible values of the field `PINCFG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PINCFGR {
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#[doc = "SIN is used for input data and SOUT for output data."]
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_00,
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#[doc = "SIN is used for both input and output data."]
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_01,
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#[doc = "SOUT is used for both input and output data."]
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_10,
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#[doc = "SOUT is used for input data and SIN for output data."]
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_11,
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#[doc = "SIN is used for input data and SOUT for output data."] _00,
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#[doc = "SIN is used for both input and output data."] _01,
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#[doc = "SOUT is used for both input and output data."] _10,
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#[doc = "SOUT is used for input data and SIN for output data."] _11,
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}
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impl PINCFGR {
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#[doc = r" Value of the field as raw bits"]
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@ -414,10 +400,8 @@ impl PINCFGR {
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#[doc = "Possible values of the field `OUTCFG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum OUTCFGR {
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#[doc = "Output data retains last value when chip select is negated."]
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_0,
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#[doc = "Output data is tristated when chip select is negated."]
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_1,
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#[doc = "Output data retains last value when chip select is negated."] _0,
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#[doc = "Output data is tristated when chip select is negated."] _1,
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}
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impl OUTCFGR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -461,10 +445,8 @@ impl OUTCFGR {
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#[doc = "Possible values of the field `PCSCFG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PCSCFGR {
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#[doc = "PCS[3:2] are enabled."]
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_0,
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#[doc = "PCS[3:2] are disabled."]
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_1,
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#[doc = "PCS[3:2] are enabled."] _0,
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#[doc = "PCS[3:2] are disabled."] _1,
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}
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impl PCSCFGR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -507,10 +489,8 @@ impl PCSCFGR {
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}
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#[doc = "Values that can be written to the field `MASTER`"]
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pub enum MASTERW {
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#[doc = "Slave mode."]
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_0,
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#[doc = "Master mode."]
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_1,
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#[doc = "Slave mode."] _0,
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#[doc = "Master mode."] _1,
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}
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impl MASTERW {
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#[allow(missing_docs)]
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@ -565,10 +545,8 @@ impl<'a> _MASTERW<'a> {
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}
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#[doc = "Values that can be written to the field `SAMPLE`"]
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pub enum SAMPLEW {
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#[doc = "Input data sampled on SCK edge."]
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_0,
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#[doc = "Input data sampled on delayed SCK edge."]
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_1,
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#[doc = "Input data sampled on SCK edge."] _0,
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#[doc = "Input data sampled on delayed SCK edge."] _1,
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}
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impl SAMPLEW {
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#[allow(missing_docs)]
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@ -623,10 +601,8 @@ impl<'a> _SAMPLEW<'a> {
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}
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#[doc = "Values that can be written to the field `AUTOPCS`"]
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pub enum AUTOPCSW {
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#[doc = "Automatic PCS generation disabled."]
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_0,
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#[doc = "Automatic PCS generation enabled."]
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_1,
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#[doc = "Automatic PCS generation disabled."] _0,
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#[doc = "Automatic PCS generation enabled."] _1,
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}
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impl AUTOPCSW {
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#[allow(missing_docs)]
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@ -681,8 +657,7 @@ impl<'a> _AUTOPCSW<'a> {
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}
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#[doc = "Values that can be written to the field `NOSTALL`"]
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pub enum NOSTALLW {
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#[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."]
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_0,
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#[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."] _0,
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#[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."]
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_1,
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}
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@ -739,10 +714,8 @@ impl<'a> _NOSTALLW<'a> {
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}
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#[doc = "Values that can be written to the field `PCSPOL`"]
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pub enum PCSPOLW {
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#[doc = "The PCSx is active low."]
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_0000,
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#[doc = "The PCSx is active high."]
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_0001,
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#[doc = "The PCSx is active low."] _0000,
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#[doc = "The PCSx is active high."] _0001,
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}
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impl PCSPOLW {
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#[allow(missing_docs)]
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@ -787,8 +760,7 @@ impl<'a> _PCSPOLW<'a> {
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}
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#[doc = "Values that can be written to the field `MATCFG`"]
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pub enum MATCFGW {
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#[doc = "Match is disabled."]
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_000,
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#[doc = "Match is disabled."] _000,
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#[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"]
|
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_010,
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#[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
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@ -875,14 +847,10 @@ impl<'a> _MATCFGW<'a> {
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}
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#[doc = "Values that can be written to the field `PINCFG`"]
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pub enum PINCFGW {
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#[doc = "SIN is used for input data and SOUT for output data."]
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_00,
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#[doc = "SIN is used for both input and output data."]
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_01,
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#[doc = "SOUT is used for both input and output data."]
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_10,
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#[doc = "SOUT is used for input data and SIN for output data."]
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_11,
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#[doc = "SIN is used for input data and SOUT for output data."] _00,
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#[doc = "SIN is used for both input and output data."] _01,
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#[doc = "SOUT is used for both input and output data."] _10,
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#[doc = "SOUT is used for input data and SIN for output data."] _11,
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}
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impl PINCFGW {
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#[allow(missing_docs)]
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@ -941,10 +909,8 @@ impl<'a> _PINCFGW<'a> {
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}
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#[doc = "Values that can be written to the field `OUTCFG`"]
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pub enum OUTCFGW {
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#[doc = "Output data retains last value when chip select is negated."]
|
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_0,
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#[doc = "Output data is tristated when chip select is negated."]
|
||||
_1,
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#[doc = "Output data retains last value when chip select is negated."] _0,
|
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#[doc = "Output data is tristated when chip select is negated."] _1,
|
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}
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impl OUTCFGW {
|
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#[allow(missing_docs)]
|
||||
@ -999,10 +965,8 @@ impl<'a> _OUTCFGW<'a> {
|
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}
|
||||
#[doc = "Values that can be written to the field `PCSCFG`"]
|
||||
pub enum PCSCFGW {
|
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#[doc = "PCS[3:2] are enabled."]
|
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_0,
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||||
#[doc = "PCS[3:2] are disabled."]
|
||||
_1,
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||||
#[doc = "PCS[3:2] are enabled."] _0,
|
||||
#[doc = "PCS[3:2] are disabled."] _1,
|
||||
}
|
||||
impl PCSCFGW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::CR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::CR {
|
||||
#[doc = "Possible values of the field `MEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MENR {
|
||||
#[doc = "Module is disabled."]
|
||||
_0,
|
||||
#[doc = "Module is enabled."]
|
||||
_1,
|
||||
#[doc = "Module is disabled."] _0,
|
||||
#[doc = "Module is enabled."] _1,
|
||||
}
|
||||
impl MENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl MENR {
|
||||
#[doc = "Possible values of the field `RST`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RSTR {
|
||||
#[doc = "Master logic is not reset."]
|
||||
_0,
|
||||
#[doc = "Master logic is reset."]
|
||||
_1,
|
||||
#[doc = "Master logic is not reset."] _0,
|
||||
#[doc = "Master logic is reset."] _1,
|
||||
}
|
||||
impl RSTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,10 +135,8 @@ impl RSTR {
|
||||
#[doc = "Possible values of the field `DOZEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DOZENR {
|
||||
#[doc = "Module is enabled in Doze mode."]
|
||||
_0,
|
||||
#[doc = "Module is disabled in Doze mode."]
|
||||
_1,
|
||||
#[doc = "Module is enabled in Doze mode."] _0,
|
||||
#[doc = "Module is disabled in Doze mode."] _1,
|
||||
}
|
||||
impl DOZENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -184,10 +180,8 @@ impl DOZENR {
|
||||
#[doc = "Possible values of the field `DBGEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DBGENR {
|
||||
#[doc = "Module is disabled in debug mode."]
|
||||
_0,
|
||||
#[doc = "Module is enabled in debug mode."]
|
||||
_1,
|
||||
#[doc = "Module is disabled in debug mode."] _0,
|
||||
#[doc = "Module is enabled in debug mode."] _1,
|
||||
}
|
||||
impl DBGENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -230,10 +224,8 @@ impl DBGENR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MEN`"]
|
||||
pub enum MENW {
|
||||
#[doc = "Module is disabled."]
|
||||
_0,
|
||||
#[doc = "Module is enabled."]
|
||||
_1,
|
||||
#[doc = "Module is disabled."] _0,
|
||||
#[doc = "Module is enabled."] _1,
|
||||
}
|
||||
impl MENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -288,10 +280,8 @@ impl<'a> _MENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RST`"]
|
||||
pub enum RSTW {
|
||||
#[doc = "Master logic is not reset."]
|
||||
_0,
|
||||
#[doc = "Master logic is reset."]
|
||||
_1,
|
||||
#[doc = "Master logic is not reset."] _0,
|
||||
#[doc = "Master logic is reset."] _1,
|
||||
}
|
||||
impl RSTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -346,10 +336,8 @@ impl<'a> _RSTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DOZEN`"]
|
||||
pub enum DOZENW {
|
||||
#[doc = "Module is enabled in Doze mode."]
|
||||
_0,
|
||||
#[doc = "Module is disabled in Doze mode."]
|
||||
_1,
|
||||
#[doc = "Module is enabled in Doze mode."] _0,
|
||||
#[doc = "Module is disabled in Doze mode."] _1,
|
||||
}
|
||||
impl DOZENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -404,10 +392,8 @@ impl<'a> _DOZENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DBGEN`"]
|
||||
pub enum DBGENW {
|
||||
#[doc = "Module is disabled in debug mode."]
|
||||
_0,
|
||||
#[doc = "Module is enabled in debug mode."]
|
||||
_1,
|
||||
#[doc = "Module is disabled in debug mode."] _0,
|
||||
#[doc = "Module is enabled in debug mode."] _1,
|
||||
}
|
||||
impl DBGENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -462,10 +448,8 @@ impl<'a> _DBGENW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RTF`"]
|
||||
pub enum RTFW {
|
||||
#[doc = "No effect."]
|
||||
_0,
|
||||
#[doc = "Transmit FIFO is reset."]
|
||||
_1,
|
||||
#[doc = "No effect."] _0,
|
||||
#[doc = "Transmit FIFO is reset."] _1,
|
||||
}
|
||||
impl RTFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -520,10 +504,8 @@ impl<'a> _RTFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RRF`"]
|
||||
pub enum RRFW {
|
||||
#[doc = "No effect."]
|
||||
_0,
|
||||
#[doc = "Receive FIFO is reset."]
|
||||
_1,
|
||||
#[doc = "No effect."] _0,
|
||||
#[doc = "Receive FIFO is reset."] _1,
|
||||
}
|
||||
impl RRFW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::DER {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::DER {
|
||||
#[doc = "Possible values of the field `TDDE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TDDER {
|
||||
#[doc = "DMA request disabled."]
|
||||
_0,
|
||||
#[doc = "DMA request enabled"]
|
||||
_1,
|
||||
#[doc = "DMA request disabled."] _0,
|
||||
#[doc = "DMA request enabled"] _1,
|
||||
}
|
||||
impl TDDER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl TDDER {
|
||||
#[doc = "Possible values of the field `RDDE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RDDER {
|
||||
#[doc = "DMA request disabled."]
|
||||
_0,
|
||||
#[doc = "DMA request enabled."]
|
||||
_1,
|
||||
#[doc = "DMA request disabled."] _0,
|
||||
#[doc = "DMA request enabled."] _1,
|
||||
}
|
||||
impl RDDER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -136,10 +134,8 @@ impl RDDER {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TDDE`"]
|
||||
pub enum TDDEW {
|
||||
#[doc = "DMA request disabled."]
|
||||
_0,
|
||||
#[doc = "DMA request enabled"]
|
||||
_1,
|
||||
#[doc = "DMA request disabled."] _0,
|
||||
#[doc = "DMA request enabled"] _1,
|
||||
}
|
||||
impl TDDEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -194,10 +190,8 @@ impl<'a> _TDDEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RDDE`"]
|
||||
pub enum RDDEW {
|
||||
#[doc = "DMA request disabled."]
|
||||
_0,
|
||||
#[doc = "DMA request enabled."]
|
||||
_1,
|
||||
#[doc = "DMA request disabled."] _0,
|
||||
#[doc = "DMA request enabled."] _1,
|
||||
}
|
||||
impl RDDEW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::DMR0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::DMR1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::FCR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::FSR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::IER {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::IER {
|
||||
#[doc = "Possible values of the field `TDIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TDIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled"]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled"] _1,
|
||||
}
|
||||
impl TDIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl TDIER {
|
||||
#[doc = "Possible values of the field `RDIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RDIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl RDIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,10 +135,8 @@ impl RDIER {
|
||||
#[doc = "Possible values of the field `WCIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum WCIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl WCIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -184,10 +180,8 @@ impl WCIER {
|
||||
#[doc = "Possible values of the field `FCIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FCIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl FCIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -231,10 +225,8 @@ impl FCIER {
|
||||
#[doc = "Possible values of the field `TCIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TCIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl TCIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -278,10 +270,8 @@ impl TCIER {
|
||||
#[doc = "Possible values of the field `TEIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TEIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl TEIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -325,10 +315,8 @@ impl TEIER {
|
||||
#[doc = "Possible values of the field `REIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum REIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl REIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -372,10 +360,8 @@ impl REIER {
|
||||
#[doc = "Possible values of the field `DMIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DMIER {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl DMIER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -418,10 +404,8 @@ impl DMIER {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TDIE`"]
|
||||
pub enum TDIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled"]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled"] _1,
|
||||
}
|
||||
impl TDIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -476,10 +460,8 @@ impl<'a> _TDIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RDIE`"]
|
||||
pub enum RDIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl RDIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -534,10 +516,8 @@ impl<'a> _RDIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `WCIE`"]
|
||||
pub enum WCIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl WCIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -592,10 +572,8 @@ impl<'a> _WCIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FCIE`"]
|
||||
pub enum FCIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl FCIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -650,10 +628,8 @@ impl<'a> _FCIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TCIE`"]
|
||||
pub enum TCIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl TCIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -708,10 +684,8 @@ impl<'a> _TCIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TEIE`"]
|
||||
pub enum TEIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl TEIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -766,10 +740,8 @@ impl<'a> _TEIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `REIE`"]
|
||||
pub enum REIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl REIEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -824,10 +796,8 @@ impl<'a> _REIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DMIE`"]
|
||||
pub enum DMIEW {
|
||||
#[doc = "Interrupt disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt disabled."] _0,
|
||||
#[doc = "Interrupt enabled."] _1,
|
||||
}
|
||||
impl DMIEW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -2,45 +2,28 @@ use vcell::VolatileCell;
|
||||
#[doc = r" Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - Version ID Register"]
|
||||
pub verid: VERID,
|
||||
#[doc = "0x04 - Parameter Register"]
|
||||
pub param: PARAM,
|
||||
#[doc = "0x00 - Version ID Register"] pub verid: VERID,
|
||||
#[doc = "0x04 - Parameter Register"] pub param: PARAM,
|
||||
_reserved0: [u8; 8usize],
|
||||
#[doc = "0x10 - Control Register"]
|
||||
pub cr: CR,
|
||||
#[doc = "0x14 - Status Register"]
|
||||
pub sr: SR,
|
||||
#[doc = "0x18 - Interrupt Enable Register"]
|
||||
pub ier: IER,
|
||||
#[doc = "0x1c - DMA Enable Register"]
|
||||
pub der: DER,
|
||||
#[doc = "0x20 - Configuration Register 0"]
|
||||
pub cfgr0: CFGR0,
|
||||
#[doc = "0x24 - Configuration Register 1"]
|
||||
pub cfgr1: CFGR1,
|
||||
#[doc = "0x10 - Control Register"] pub cr: CR,
|
||||
#[doc = "0x14 - Status Register"] pub sr: SR,
|
||||
#[doc = "0x18 - Interrupt Enable Register"] pub ier: IER,
|
||||
#[doc = "0x1c - DMA Enable Register"] pub der: DER,
|
||||
#[doc = "0x20 - Configuration Register 0"] pub cfgr0: CFGR0,
|
||||
#[doc = "0x24 - Configuration Register 1"] pub cfgr1: CFGR1,
|
||||
_reserved1: [u8; 8usize],
|
||||
#[doc = "0x30 - Data Match Register 0"]
|
||||
pub dmr0: DMR0,
|
||||
#[doc = "0x34 - Data Match Register 1"]
|
||||
pub dmr1: DMR1,
|
||||
#[doc = "0x30 - Data Match Register 0"] pub dmr0: DMR0,
|
||||
#[doc = "0x34 - Data Match Register 1"] pub dmr1: DMR1,
|
||||
_reserved2: [u8; 8usize],
|
||||
#[doc = "0x40 - Clock Configuration Register"]
|
||||
pub ccr: CCR,
|
||||
#[doc = "0x40 - Clock Configuration Register"] pub ccr: CCR,
|
||||
_reserved3: [u8; 20usize],
|
||||
#[doc = "0x58 - FIFO Control Register"]
|
||||
pub fcr: FCR,
|
||||
#[doc = "0x5c - FIFO Status Register"]
|
||||
pub fsr: FSR,
|
||||
#[doc = "0x60 - Transmit Command Register"]
|
||||
pub tcr: TCR,
|
||||
#[doc = "0x64 - Transmit Data Register"]
|
||||
pub tdr: TDR,
|
||||
#[doc = "0x58 - FIFO Control Register"] pub fcr: FCR,
|
||||
#[doc = "0x5c - FIFO Status Register"] pub fsr: FSR,
|
||||
#[doc = "0x60 - Transmit Command Register"] pub tcr: TCR,
|
||||
#[doc = "0x64 - Transmit Data Register"] pub tdr: TDR,
|
||||
_reserved4: [u8; 8usize],
|
||||
#[doc = "0x70 - Receive Status Register"]
|
||||
pub rsr: RSR,
|
||||
#[doc = "0x74 - Receive Data Register"]
|
||||
pub rdr: RDR,
|
||||
#[doc = "0x70 - Receive Status Register"] pub rsr: RSR,
|
||||
#[doc = "0x74 - Receive Data Register"] pub rdr: RDR,
|
||||
}
|
||||
#[doc = "Version ID Register"]
|
||||
pub struct VERID {
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::PARAM {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::RDR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -6,16 +6,16 @@ impl super::RSR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `SOF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SOFR {
|
||||
#[doc = "Subsequent data word received after LPSPI_PCS assertion."]
|
||||
_0,
|
||||
#[doc = "First data word received after LPSPI_PCS assertion."]
|
||||
_1,
|
||||
#[doc = "Subsequent data word received after LPSPI_PCS assertion."] _0,
|
||||
#[doc = "First data word received after LPSPI_PCS assertion."] _1,
|
||||
}
|
||||
impl SOFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -59,10 +59,8 @@ impl SOFR {
|
||||
#[doc = "Possible values of the field `RXEMPTY`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RXEMPTYR {
|
||||
#[doc = "RX FIFO is not empty."]
|
||||
_0,
|
||||
#[doc = "RX FIFO is empty."]
|
||||
_1,
|
||||
#[doc = "RX FIFO is not empty."] _0,
|
||||
#[doc = "RX FIFO is empty."] _1,
|
||||
}
|
||||
impl RXEMPTYR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::SR {
|
||||
#[doc = "Possible values of the field `TDF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TDFR {
|
||||
#[doc = "Transmit data not requested."]
|
||||
_0,
|
||||
#[doc = "Transmit data is requested."]
|
||||
_1,
|
||||
#[doc = "Transmit data not requested."] _0,
|
||||
#[doc = "Transmit data is requested."] _1,
|
||||
}
|
||||
impl TDFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,10 +90,8 @@ impl TDFR {
|
||||
#[doc = "Possible values of the field `RDF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RDFR {
|
||||
#[doc = "Receive Data is not ready."]
|
||||
_0,
|
||||
#[doc = "Receive data is ready."]
|
||||
_1,
|
||||
#[doc = "Receive Data is not ready."] _0,
|
||||
#[doc = "Receive data is ready."] _1,
|
||||
}
|
||||
impl RDFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -137,10 +135,8 @@ impl RDFR {
|
||||
#[doc = "Possible values of the field `WCF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum WCFR {
|
||||
#[doc = "Transfer word not completed."]
|
||||
_0,
|
||||
#[doc = "Transfer word completed."]
|
||||
_1,
|
||||
#[doc = "Transfer word not completed."] _0,
|
||||
#[doc = "Transfer word completed."] _1,
|
||||
}
|
||||
impl WCFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -184,10 +180,8 @@ impl WCFR {
|
||||
#[doc = "Possible values of the field `FCF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FCFR {
|
||||
#[doc = "Frame transfer has not completed."]
|
||||
_0,
|
||||
#[doc = "Frame transfer has completed."]
|
||||
_1,
|
||||
#[doc = "Frame transfer has not completed."] _0,
|
||||
#[doc = "Frame transfer has completed."] _1,
|
||||
}
|
||||
impl FCFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -231,10 +225,8 @@ impl FCFR {
|
||||
#[doc = "Possible values of the field `TCF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TCFR {
|
||||
#[doc = "All transfers have not completed."]
|
||||
_0,
|
||||
#[doc = "All transfers have completed."]
|
||||
_1,
|
||||
#[doc = "All transfers have not completed."] _0,
|
||||
#[doc = "All transfers have completed."] _1,
|
||||
}
|
||||
impl TCFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -278,10 +270,8 @@ impl TCFR {
|
||||
#[doc = "Possible values of the field `TEF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TEFR {
|
||||
#[doc = "Transmit FIFO underrun has not occurred."]
|
||||
_0,
|
||||
#[doc = "Transmit FIFO underrun has occurred"]
|
||||
_1,
|
||||
#[doc = "Transmit FIFO underrun has not occurred."] _0,
|
||||
#[doc = "Transmit FIFO underrun has occurred"] _1,
|
||||
}
|
||||
impl TEFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -325,10 +315,8 @@ impl TEFR {
|
||||
#[doc = "Possible values of the field `REF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum REFR {
|
||||
#[doc = "Receive FIFO has not overflowed."]
|
||||
_0,
|
||||
#[doc = "Receive FIFO has overflowed."]
|
||||
_1,
|
||||
#[doc = "Receive FIFO has not overflowed."] _0,
|
||||
#[doc = "Receive FIFO has overflowed."] _1,
|
||||
}
|
||||
impl REFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -372,10 +360,8 @@ impl REFR {
|
||||
#[doc = "Possible values of the field `DMF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DMFR {
|
||||
#[doc = "Have not received matching data."]
|
||||
_0,
|
||||
#[doc = "Have received matching data."]
|
||||
_1,
|
||||
#[doc = "Have not received matching data."] _0,
|
||||
#[doc = "Have received matching data."] _1,
|
||||
}
|
||||
impl DMFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -419,10 +405,8 @@ impl DMFR {
|
||||
#[doc = "Possible values of the field `MBF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MBFR {
|
||||
#[doc = "LPSPI is idle."]
|
||||
_0,
|
||||
#[doc = "LPSPI is busy."]
|
||||
_1,
|
||||
#[doc = "LPSPI is idle."] _0,
|
||||
#[doc = "LPSPI is busy."] _1,
|
||||
}
|
||||
impl MBFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -465,10 +449,8 @@ impl MBFR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `WCF`"]
|
||||
pub enum WCFW {
|
||||
#[doc = "Transfer word not completed."]
|
||||
_0,
|
||||
#[doc = "Transfer word completed."]
|
||||
_1,
|
||||
#[doc = "Transfer word not completed."] _0,
|
||||
#[doc = "Transfer word completed."] _1,
|
||||
}
|
||||
impl WCFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -523,10 +505,8 @@ impl<'a> _WCFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FCF`"]
|
||||
pub enum FCFW {
|
||||
#[doc = "Frame transfer has not completed."]
|
||||
_0,
|
||||
#[doc = "Frame transfer has completed."]
|
||||
_1,
|
||||
#[doc = "Frame transfer has not completed."] _0,
|
||||
#[doc = "Frame transfer has completed."] _1,
|
||||
}
|
||||
impl FCFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -581,10 +561,8 @@ impl<'a> _FCFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TCF`"]
|
||||
pub enum TCFW {
|
||||
#[doc = "All transfers have not completed."]
|
||||
_0,
|
||||
#[doc = "All transfers have completed."]
|
||||
_1,
|
||||
#[doc = "All transfers have not completed."] _0,
|
||||
#[doc = "All transfers have completed."] _1,
|
||||
}
|
||||
impl TCFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -639,10 +617,8 @@ impl<'a> _TCFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TEF`"]
|
||||
pub enum TEFW {
|
||||
#[doc = "Transmit FIFO underrun has not occurred."]
|
||||
_0,
|
||||
#[doc = "Transmit FIFO underrun has occurred"]
|
||||
_1,
|
||||
#[doc = "Transmit FIFO underrun has not occurred."] _0,
|
||||
#[doc = "Transmit FIFO underrun has occurred"] _1,
|
||||
}
|
||||
impl TEFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -697,10 +673,8 @@ impl<'a> _TEFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `REF`"]
|
||||
pub enum REFW {
|
||||
#[doc = "Receive FIFO has not overflowed."]
|
||||
_0,
|
||||
#[doc = "Receive FIFO has overflowed."]
|
||||
_1,
|
||||
#[doc = "Receive FIFO has not overflowed."] _0,
|
||||
#[doc = "Receive FIFO has overflowed."] _1,
|
||||
}
|
||||
impl REFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -755,10 +729,8 @@ impl<'a> _REFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DMF`"]
|
||||
pub enum DMFW {
|
||||
#[doc = "Have not received matching data."]
|
||||
_0,
|
||||
#[doc = "Have received matching data."]
|
||||
_1,
|
||||
#[doc = "Have not received matching data."] _0,
|
||||
#[doc = "Have received matching data."] _1,
|
||||
}
|
||||
impl DMFW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TCR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -54,14 +56,10 @@ impl FRAMESZR {
|
||||
#[doc = "Possible values of the field `WIDTH`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum WIDTHR {
|
||||
#[doc = "Single bit transfer."]
|
||||
_00,
|
||||
#[doc = "Two bit transfer."]
|
||||
_01,
|
||||
#[doc = "Four bit transfer."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Single bit transfer."] _00,
|
||||
#[doc = "Two bit transfer."] _01,
|
||||
#[doc = "Four bit transfer."] _10,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl WIDTHR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -104,10 +102,8 @@ impl WIDTHR {
|
||||
#[doc = "Possible values of the field `TXMSK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TXMSKR {
|
||||
#[doc = "Normal transfer."]
|
||||
_0,
|
||||
#[doc = "Mask transmit data."]
|
||||
_1,
|
||||
#[doc = "Normal transfer."] _0,
|
||||
#[doc = "Mask transmit data."] _1,
|
||||
}
|
||||
impl TXMSKR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -151,10 +147,8 @@ impl TXMSKR {
|
||||
#[doc = "Possible values of the field `RXMSK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RXMSKR {
|
||||
#[doc = "Normal transfer."]
|
||||
_0,
|
||||
#[doc = "Receive data is masked."]
|
||||
_1,
|
||||
#[doc = "Normal transfer."] _0,
|
||||
#[doc = "Receive data is masked."] _1,
|
||||
}
|
||||
impl RXMSKR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -198,10 +192,8 @@ impl RXMSKR {
|
||||
#[doc = "Possible values of the field `CONTC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CONTCR {
|
||||
#[doc = "Command word for start of new transfer."]
|
||||
_0,
|
||||
#[doc = "Command word for continuing transfer."]
|
||||
_1,
|
||||
#[doc = "Command word for start of new transfer."] _0,
|
||||
#[doc = "Command word for continuing transfer."] _1,
|
||||
}
|
||||
impl CONTCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -245,10 +237,8 @@ impl CONTCR {
|
||||
#[doc = "Possible values of the field `CONT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CONTR {
|
||||
#[doc = "Continuous transfer disabled."]
|
||||
_0,
|
||||
#[doc = "Continuous transfer enabled."]
|
||||
_1,
|
||||
#[doc = "Continuous transfer disabled."] _0,
|
||||
#[doc = "Continuous transfer enabled."] _1,
|
||||
}
|
||||
impl CONTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -292,10 +282,8 @@ impl CONTR {
|
||||
#[doc = "Possible values of the field `BYSW`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum BYSWR {
|
||||
#[doc = "Byte swap disabled."]
|
||||
_0,
|
||||
#[doc = "Byte swap enabled."]
|
||||
_1,
|
||||
#[doc = "Byte swap disabled."] _0,
|
||||
#[doc = "Byte swap enabled."] _1,
|
||||
}
|
||||
impl BYSWR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -339,10 +327,8 @@ impl BYSWR {
|
||||
#[doc = "Possible values of the field `LSBF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LSBFR {
|
||||
#[doc = "Data is transferred MSB first."]
|
||||
_0,
|
||||
#[doc = "Data is transferred LSB first."]
|
||||
_1,
|
||||
#[doc = "Data is transferred MSB first."] _0,
|
||||
#[doc = "Data is transferred LSB first."] _1,
|
||||
}
|
||||
impl LSBFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -386,14 +372,10 @@ impl LSBFR {
|
||||
#[doc = "Possible values of the field `PCS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PCSR {
|
||||
#[doc = "Transfer using LPSPI_PCS[0]"]
|
||||
_00,
|
||||
#[doc = "Transfer using LPSPI_PCS[1]"]
|
||||
_01,
|
||||
#[doc = "Transfer using LPSPI_PCS[2]"]
|
||||
_10,
|
||||
#[doc = "Transfer using LPSPI_PCS[3]"]
|
||||
_11,
|
||||
#[doc = "Transfer using LPSPI_PCS[0]"] _00,
|
||||
#[doc = "Transfer using LPSPI_PCS[1]"] _01,
|
||||
#[doc = "Transfer using LPSPI_PCS[2]"] _10,
|
||||
#[doc = "Transfer using LPSPI_PCS[3]"] _11,
|
||||
}
|
||||
impl PCSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -442,22 +424,14 @@ impl PCSR {
|
||||
#[doc = "Possible values of the field `PRESCALE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PRESCALER {
|
||||
#[doc = "Divide by 1."]
|
||||
_000,
|
||||
#[doc = "Divide by 2."]
|
||||
_001,
|
||||
#[doc = "Divide by 4."]
|
||||
_010,
|
||||
#[doc = "Divide by 8."]
|
||||
_011,
|
||||
#[doc = "Divide by 16."]
|
||||
_100,
|
||||
#[doc = "Divide by 32."]
|
||||
_101,
|
||||
#[doc = "Divide by 64."]
|
||||
_110,
|
||||
#[doc = "Divide by 128."]
|
||||
_111,
|
||||
#[doc = "Divide by 1."] _000,
|
||||
#[doc = "Divide by 2."] _001,
|
||||
#[doc = "Divide by 4."] _010,
|
||||
#[doc = "Divide by 8."] _011,
|
||||
#[doc = "Divide by 16."] _100,
|
||||
#[doc = "Divide by 32."] _101,
|
||||
#[doc = "Divide by 64."] _110,
|
||||
#[doc = "Divide by 128."] _111,
|
||||
}
|
||||
impl PRESCALER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -534,10 +508,8 @@ impl PRESCALER {
|
||||
#[doc = "Possible values of the field `CPHA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CPHAR {
|
||||
#[doc = "Data is captured on the leading edge of SCK and changed on the following edge."]
|
||||
_0,
|
||||
#[doc = "Data is changed on the leading edge of SCK and captured on the following edge."]
|
||||
_1,
|
||||
#[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0,
|
||||
#[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1,
|
||||
}
|
||||
impl CPHAR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -581,10 +553,8 @@ impl CPHAR {
|
||||
#[doc = "Possible values of the field `CPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CPOLR {
|
||||
#[doc = "The inactive state value of SCK is low."]
|
||||
_0,
|
||||
#[doc = "The inactive state value of SCK is high."]
|
||||
_1,
|
||||
#[doc = "The inactive state value of SCK is low."] _0,
|
||||
#[doc = "The inactive state value of SCK is high."] _1,
|
||||
}
|
||||
impl CPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -642,12 +612,9 @@ impl<'a> _FRAMESZW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `WIDTH`"]
|
||||
pub enum WIDTHW {
|
||||
#[doc = "Single bit transfer."]
|
||||
_00,
|
||||
#[doc = "Two bit transfer."]
|
||||
_01,
|
||||
#[doc = "Four bit transfer."]
|
||||
_10,
|
||||
#[doc = "Single bit transfer."] _00,
|
||||
#[doc = "Two bit transfer."] _01,
|
||||
#[doc = "Four bit transfer."] _10,
|
||||
}
|
||||
impl WIDTHW {
|
||||
#[allow(missing_docs)]
|
||||
@ -698,10 +665,8 @@ impl<'a> _WIDTHW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TXMSK`"]
|
||||
pub enum TXMSKW {
|
||||
#[doc = "Normal transfer."]
|
||||
_0,
|
||||
#[doc = "Mask transmit data."]
|
||||
_1,
|
||||
#[doc = "Normal transfer."] _0,
|
||||
#[doc = "Mask transmit data."] _1,
|
||||
}
|
||||
impl TXMSKW {
|
||||
#[allow(missing_docs)]
|
||||
@ -756,10 +721,8 @@ impl<'a> _TXMSKW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RXMSK`"]
|
||||
pub enum RXMSKW {
|
||||
#[doc = "Normal transfer."]
|
||||
_0,
|
||||
#[doc = "Receive data is masked."]
|
||||
_1,
|
||||
#[doc = "Normal transfer."] _0,
|
||||
#[doc = "Receive data is masked."] _1,
|
||||
}
|
||||
impl RXMSKW {
|
||||
#[allow(missing_docs)]
|
||||
@ -814,10 +777,8 @@ impl<'a> _RXMSKW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CONTC`"]
|
||||
pub enum CONTCW {
|
||||
#[doc = "Command word for start of new transfer."]
|
||||
_0,
|
||||
#[doc = "Command word for continuing transfer."]
|
||||
_1,
|
||||
#[doc = "Command word for start of new transfer."] _0,
|
||||
#[doc = "Command word for continuing transfer."] _1,
|
||||
}
|
||||
impl CONTCW {
|
||||
#[allow(missing_docs)]
|
||||
@ -872,10 +833,8 @@ impl<'a> _CONTCW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CONT`"]
|
||||
pub enum CONTW {
|
||||
#[doc = "Continuous transfer disabled."]
|
||||
_0,
|
||||
#[doc = "Continuous transfer enabled."]
|
||||
_1,
|
||||
#[doc = "Continuous transfer disabled."] _0,
|
||||
#[doc = "Continuous transfer enabled."] _1,
|
||||
}
|
||||
impl CONTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -930,10 +889,8 @@ impl<'a> _CONTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `BYSW`"]
|
||||
pub enum BYSWW {
|
||||
#[doc = "Byte swap disabled."]
|
||||
_0,
|
||||
#[doc = "Byte swap enabled."]
|
||||
_1,
|
||||
#[doc = "Byte swap disabled."] _0,
|
||||
#[doc = "Byte swap enabled."] _1,
|
||||
}
|
||||
impl BYSWW {
|
||||
#[allow(missing_docs)]
|
||||
@ -988,10 +945,8 @@ impl<'a> _BYSWW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LSBF`"]
|
||||
pub enum LSBFW {
|
||||
#[doc = "Data is transferred MSB first."]
|
||||
_0,
|
||||
#[doc = "Data is transferred LSB first."]
|
||||
_1,
|
||||
#[doc = "Data is transferred MSB first."] _0,
|
||||
#[doc = "Data is transferred LSB first."] _1,
|
||||
}
|
||||
impl LSBFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1046,14 +1001,10 @@ impl<'a> _LSBFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PCS`"]
|
||||
pub enum PCSW {
|
||||
#[doc = "Transfer using LPSPI_PCS[0]"]
|
||||
_00,
|
||||
#[doc = "Transfer using LPSPI_PCS[1]"]
|
||||
_01,
|
||||
#[doc = "Transfer using LPSPI_PCS[2]"]
|
||||
_10,
|
||||
#[doc = "Transfer using LPSPI_PCS[3]"]
|
||||
_11,
|
||||
#[doc = "Transfer using LPSPI_PCS[0]"] _00,
|
||||
#[doc = "Transfer using LPSPI_PCS[1]"] _01,
|
||||
#[doc = "Transfer using LPSPI_PCS[2]"] _10,
|
||||
#[doc = "Transfer using LPSPI_PCS[3]"] _11,
|
||||
}
|
||||
impl PCSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1112,22 +1063,14 @@ impl<'a> _PCSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PRESCALE`"]
|
||||
pub enum PRESCALEW {
|
||||
#[doc = "Divide by 1."]
|
||||
_000,
|
||||
#[doc = "Divide by 2."]
|
||||
_001,
|
||||
#[doc = "Divide by 4."]
|
||||
_010,
|
||||
#[doc = "Divide by 8."]
|
||||
_011,
|
||||
#[doc = "Divide by 16."]
|
||||
_100,
|
||||
#[doc = "Divide by 32."]
|
||||
_101,
|
||||
#[doc = "Divide by 64."]
|
||||
_110,
|
||||
#[doc = "Divide by 128."]
|
||||
_111,
|
||||
#[doc = "Divide by 1."] _000,
|
||||
#[doc = "Divide by 2."] _001,
|
||||
#[doc = "Divide by 4."] _010,
|
||||
#[doc = "Divide by 8."] _011,
|
||||
#[doc = "Divide by 16."] _100,
|
||||
#[doc = "Divide by 32."] _101,
|
||||
#[doc = "Divide by 64."] _110,
|
||||
#[doc = "Divide by 128."] _111,
|
||||
}
|
||||
impl PRESCALEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1210,10 +1153,8 @@ impl<'a> _PRESCALEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CPHA`"]
|
||||
pub enum CPHAW {
|
||||
#[doc = "Data is captured on the leading edge of SCK and changed on the following edge."]
|
||||
_0,
|
||||
#[doc = "Data is changed on the leading edge of SCK and captured on the following edge."]
|
||||
_1,
|
||||
#[doc = "Data is captured on the leading edge of SCK and changed on the following edge."] _0,
|
||||
#[doc = "Data is changed on the leading edge of SCK and captured on the following edge."] _1,
|
||||
}
|
||||
impl CPHAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1268,10 +1209,8 @@ impl<'a> _CPHAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CPOL`"]
|
||||
pub enum CPOLW {
|
||||
#[doc = "The inactive state value of SCK is low."]
|
||||
_0,
|
||||
#[doc = "The inactive state value of SCK is high."]
|
||||
_1,
|
||||
#[doc = "The inactive state value of SCK is low."] _0,
|
||||
#[doc = "The inactive state value of SCK is high."] _1,
|
||||
}
|
||||
impl CPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -6,16 +6,16 @@ impl super::VERID {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FEATURE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FEATURER {
|
||||
#[doc = "Standard feature set supporting 32-bit shift register."]
|
||||
_0000000000000100,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u16),
|
||||
#[doc = "Standard feature set supporting 32-bit shift register."] _0000000000000100,
|
||||
#[doc = r" Reserved"] _Reserved(u16),
|
||||
}
|
||||
impl FEATURER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
|
||||
Reference in New Issue
Block a user