Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::SYNCONF {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -92,8 +94,7 @@ impl HWTRIGMODER {
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pub enum CNTINCR {
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#[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl CNTINCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -139,8 +140,7 @@ impl CNTINCR {
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pub enum INVCR {
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#[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl INVCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -186,8 +186,7 @@ impl INVCR {
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pub enum SWOCR {
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#[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl SWOCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -231,10 +230,8 @@ impl SWOCR {
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#[doc = "Possible values of the field `SYNCMODE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SYNCMODER {
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#[doc = "Legacy PWM synchronization is selected."]
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_0,
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#[doc = "Enhanced PWM synchronization is selected."]
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_1,
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#[doc = "Legacy PWM synchronization is selected."] _0,
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#[doc = "Enhanced PWM synchronization is selected."] _1,
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}
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impl SYNCMODER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -278,10 +275,8 @@ impl SYNCMODER {
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#[doc = "Possible values of the field `SWRSTCNT`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWRSTCNTR {
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#[doc = "The software trigger does not activate the FTM counter synchronization."]
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_0,
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#[doc = "The software trigger activates the FTM counter synchronization."]
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_1,
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#[doc = "The software trigger does not activate the FTM counter synchronization."] _0,
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#[doc = "The software trigger activates the FTM counter synchronization."] _1,
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}
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impl SWRSTCNTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -327,8 +322,7 @@ impl SWRSTCNTR {
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pub enum SWWRBUFR {
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#[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
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_0,
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#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
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_1,
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#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
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}
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impl SWWRBUFR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -372,10 +366,8 @@ impl SWWRBUFR {
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#[doc = "Possible values of the field `SWOM`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWOMR {
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#[doc = "The software trigger does not activate the OUTMASK register synchronization."]
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_0,
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#[doc = "The software trigger activates the OUTMASK register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0,
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#[doc = "The software trigger activates the OUTMASK register synchronization."] _1,
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}
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impl SWOMR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -419,10 +411,8 @@ impl SWOMR {
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#[doc = "Possible values of the field `SWINVC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWINVCR {
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#[doc = "The software trigger does not activate the INVCTRL register synchronization."]
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_0,
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#[doc = "The software trigger activates the INVCTRL register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0,
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#[doc = "The software trigger activates the INVCTRL register synchronization."] _1,
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}
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impl SWINVCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -466,10 +456,8 @@ impl SWINVCR {
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#[doc = "Possible values of the field `SWSOC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWSOCR {
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#[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
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_0,
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#[doc = "The software trigger activates the SWOCTRL register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0,
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#[doc = "The software trigger activates the SWOCTRL register synchronization."] _1,
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}
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impl SWSOCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -513,10 +501,8 @@ impl SWSOCR {
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#[doc = "Possible values of the field `HWRSTCNT`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HWRSTCNTR {
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#[doc = "A hardware trigger does not activate the FTM counter synchronization."]
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_0,
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#[doc = "A hardware trigger activates the FTM counter synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0,
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#[doc = "A hardware trigger activates the FTM counter synchronization."] _1,
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}
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impl HWRSTCNTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -562,8 +548,7 @@ impl HWRSTCNTR {
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pub enum HWWRBUFR {
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#[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
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_0,
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#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
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_1,
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#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
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}
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impl HWWRBUFR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -607,10 +592,8 @@ impl HWWRBUFR {
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#[doc = "Possible values of the field `HWOM`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HWOMR {
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#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the OUTMASK register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0,
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#[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1,
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}
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impl HWOMR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -654,10 +637,8 @@ impl HWOMR {
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#[doc = "Possible values of the field `HWINVC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HWINVCR {
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#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the INVCTRL register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0,
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#[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1,
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}
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impl HWINVCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -701,10 +682,8 @@ impl HWINVCR {
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#[doc = "Possible values of the field `HWSOC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum HWSOCR {
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#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0,
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#[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1,
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}
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impl HWSOCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> {
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pub enum CNTINCW {
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#[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl CNTINCW {
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#[allow(missing_docs)]
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@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> {
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pub enum INVCW {
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#[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl INVCW {
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#[allow(missing_docs)]
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@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> {
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pub enum SWOCW {
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#[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
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_0,
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#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
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_1,
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#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1,
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}
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impl SWOCW {
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#[allow(missing_docs)]
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@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> {
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}
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#[doc = "Values that can be written to the field `SYNCMODE`"]
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pub enum SYNCMODEW {
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#[doc = "Legacy PWM synchronization is selected."]
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_0,
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#[doc = "Enhanced PWM synchronization is selected."]
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_1,
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#[doc = "Legacy PWM synchronization is selected."] _0,
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#[doc = "Enhanced PWM synchronization is selected."] _1,
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}
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impl SYNCMODEW {
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#[allow(missing_docs)]
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@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> {
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}
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#[doc = "Values that can be written to the field `SWRSTCNT`"]
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pub enum SWRSTCNTW {
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#[doc = "The software trigger does not activate the FTM counter synchronization."]
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_0,
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#[doc = "The software trigger activates the FTM counter synchronization."]
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_1,
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#[doc = "The software trigger does not activate the FTM counter synchronization."] _0,
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#[doc = "The software trigger activates the FTM counter synchronization."] _1,
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}
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impl SWRSTCNTW {
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#[allow(missing_docs)]
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@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> {
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pub enum SWWRBUFW {
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#[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
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_0,
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#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
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_1,
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#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
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}
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impl SWWRBUFW {
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#[allow(missing_docs)]
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@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> {
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}
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#[doc = "Values that can be written to the field `SWOM`"]
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pub enum SWOMW {
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#[doc = "The software trigger does not activate the OUTMASK register synchronization."]
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_0,
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#[doc = "The software trigger activates the OUTMASK register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0,
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#[doc = "The software trigger activates the OUTMASK register synchronization."] _1,
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}
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impl SWOMW {
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#[allow(missing_docs)]
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@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> {
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}
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#[doc = "Values that can be written to the field `SWINVC`"]
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pub enum SWINVCW {
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#[doc = "The software trigger does not activate the INVCTRL register synchronization."]
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_0,
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#[doc = "The software trigger activates the INVCTRL register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0,
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#[doc = "The software trigger activates the INVCTRL register synchronization."] _1,
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}
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impl SWINVCW {
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#[allow(missing_docs)]
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@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> {
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}
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#[doc = "Values that can be written to the field `SWSOC`"]
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pub enum SWSOCW {
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#[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
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_0,
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#[doc = "The software trigger activates the SWOCTRL register synchronization."]
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_1,
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#[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0,
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#[doc = "The software trigger activates the SWOCTRL register synchronization."] _1,
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}
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impl SWSOCW {
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#[allow(missing_docs)]
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@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> {
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}
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#[doc = "Values that can be written to the field `HWRSTCNT`"]
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pub enum HWRSTCNTW {
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#[doc = "A hardware trigger does not activate the FTM counter synchronization."]
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_0,
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#[doc = "A hardware trigger activates the FTM counter synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0,
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#[doc = "A hardware trigger activates the FTM counter synchronization."] _1,
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}
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impl HWRSTCNTW {
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#[allow(missing_docs)]
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@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> {
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pub enum HWWRBUFW {
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#[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
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_0,
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#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
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_1,
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#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
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}
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impl HWWRBUFW {
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#[allow(missing_docs)]
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@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> {
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}
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#[doc = "Values that can be written to the field `HWOM`"]
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pub enum HWOMW {
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#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the OUTMASK register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0,
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#[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1,
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}
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impl HWOMW {
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#[allow(missing_docs)]
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@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> {
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}
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#[doc = "Values that can be written to the field `HWINVC`"]
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pub enum HWINVCW {
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#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the INVCTRL register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0,
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#[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1,
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}
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impl HWINVCW {
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#[allow(missing_docs)]
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@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> {
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}
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#[doc = "Values that can be written to the field `HWSOC`"]
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pub enum HWSOCW {
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#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
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_0,
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#[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
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_1,
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#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0,
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#[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1,
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}
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impl HWSOCW {
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#[allow(missing_docs)]
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Reference in New Issue
Block a user