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This commit is contained in:
Kjetil Kjeka
2017-09-23 20:31:10 +02:00
parent 7facea48b2
commit 2fc3ce22de
1658 changed files with 25191 additions and 42351 deletions
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64
src/ftm1/c0sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C0SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C0SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c0v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C0V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c1sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C1SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C1SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c1v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C1V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c2sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C2SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C2SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c2v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C2V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c3sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C3SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C3SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c3v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C3V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c4sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C4SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C4SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c4v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C4V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c5sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C5SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C5SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c5v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C5V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c6sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C6SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C6SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c6v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C6V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

64
src/ftm1/c7sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C7SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::C7SC {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl DMAR {
#[doc = "Possible values of the field `ICRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICRSTR {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -221,10 +219,8 @@ impl MSBR {
#[doc = "Possible values of the field `CHIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHIER {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -268,10 +264,8 @@ impl CHIER {
#[doc = "Possible values of the field `CHF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHFR {
#[doc = "No channel (n) event has occurred."]
_0,
#[doc = "A channel (n) event has occurred."]
_1,
#[doc = "No channel (n) event has occurred."] _0,
#[doc = "A channel (n) event has occurred."] _1,
}
impl CHFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -315,8 +309,7 @@ impl CHFR {
#[doc = "Possible values of the field `TRIGMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGMODER {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}
@ -362,10 +355,8 @@ impl TRIGMODER {
#[doc = "Possible values of the field `CHIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHISR {
#[doc = "The channel (n) input is zero."]
_0,
#[doc = "The channel (n) input is one."]
_1,
#[doc = "The channel (n) input is zero."] _0,
#[doc = "The channel (n) input is one."] _1,
}
impl CHISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -409,10 +400,8 @@ impl CHISR {
#[doc = "Possible values of the field `CHOV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHOVR {
#[doc = "The channel (n) output is zero."]
_0,
#[doc = "The channel (n) output is one."]
_1,
#[doc = "The channel (n) output is zero."] _0,
#[doc = "The channel (n) output is one."] _1,
}
impl CHOVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -455,10 +444,8 @@ impl CHOVR {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Disable DMA transfers."]
_0,
#[doc = "Enable DMA transfers."]
_1,
#[doc = "Disable DMA transfers."] _0,
#[doc = "Enable DMA transfers."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -513,10 +500,8 @@ impl<'a> _DMAW<'a> {
}
#[doc = "Values that can be written to the field `ICRST`"]
pub enum ICRSTW {
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
_0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
_1,
#[doc = "FTM counter is not reset when the selected channel (n) input event is detected."] _0,
#[doc = "FTM counter is reset when the selected channel (n) input event is detected."] _1,
}
impl ICRSTW {
#[allow(missing_docs)]
@ -663,10 +648,8 @@ impl<'a> _MSBW<'a> {
}
#[doc = "Values that can be written to the field `CHIE`"]
pub enum CHIEW {
#[doc = "Disable channel (n) interrupt. Use software polling."]
_0,
#[doc = "Enable channel (n) interrupt."]
_1,
#[doc = "Disable channel (n) interrupt. Use software polling."] _0,
#[doc = "Enable channel (n) interrupt."] _1,
}
impl CHIEW {
#[allow(missing_docs)]
@ -721,8 +704,7 @@ impl<'a> _CHIEW<'a> {
}
#[doc = "Values that can be written to the field `TRIGMODE`"]
pub enum TRIGMODEW {
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
_0,
#[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."] _0,
#[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
_1,
}

4
src/ftm1/c7v/mod.rs
View File

@ -22,7 +22,9 @@ impl super::C7V {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/ftm1/cnt/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CNT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/ftm1/cntin/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CNTIN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

244
src/ftm1/combine/mod.rs
View File

@ -22,7 +22,9 @@ impl super::COMBINE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -64,10 +66,8 @@ impl COMBINE0R {
#[doc = "Possible values of the field `COMP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMP0R {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -132,10 +132,8 @@ impl DECAPEN0R {
#[doc = "Possible values of the field `DECAP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DECAP0R {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -179,10 +177,8 @@ impl DECAP0R {
#[doc = "Possible values of the field `DTEN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTEN0R {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -226,10 +222,8 @@ impl DTEN0R {
#[doc = "Possible values of the field `SYNCEN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCEN0R {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -273,10 +267,8 @@ impl SYNCEN0R {
#[doc = "Possible values of the field `FAULTEN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTEN0R {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -362,10 +354,8 @@ impl COMBINE1R {
#[doc = "Possible values of the field `COMP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMP1R {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -430,10 +420,8 @@ impl DECAPEN1R {
#[doc = "Possible values of the field `DECAP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DECAP1R {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -477,10 +465,8 @@ impl DECAP1R {
#[doc = "Possible values of the field `DTEN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTEN1R {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -524,10 +510,8 @@ impl DTEN1R {
#[doc = "Possible values of the field `SYNCEN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCEN1R {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -571,10 +555,8 @@ impl SYNCEN1R {
#[doc = "Possible values of the field `FAULTEN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTEN1R {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -660,10 +642,8 @@ impl COMBINE2R {
#[doc = "Possible values of the field `COMP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMP2R {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -728,10 +708,8 @@ impl DECAPEN2R {
#[doc = "Possible values of the field `DECAP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DECAP2R {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -775,10 +753,8 @@ impl DECAP2R {
#[doc = "Possible values of the field `DTEN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTEN2R {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -822,10 +798,8 @@ impl DTEN2R {
#[doc = "Possible values of the field `SYNCEN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCEN2R {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -869,10 +843,8 @@ impl SYNCEN2R {
#[doc = "Possible values of the field `FAULTEN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTEN2R {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -958,10 +930,8 @@ impl COMBINE3R {
#[doc = "Possible values of the field `COMP3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMP3R {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1026,10 +996,8 @@ impl DECAPEN3R {
#[doc = "Possible values of the field `DECAP3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DECAP3R {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1073,10 +1041,8 @@ impl DECAP3R {
#[doc = "Possible values of the field `DTEN3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTEN3R {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1120,10 +1086,8 @@ impl DTEN3R {
#[doc = "Possible values of the field `SYNCEN3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCEN3R {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1167,10 +1131,8 @@ impl SYNCEN3R {
#[doc = "Possible values of the field `FAULTEN3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTEN3R {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1257,10 +1219,8 @@ impl<'a> _COMBINE0W<'a> {
}
#[doc = "Values that can be written to the field `COMP0`"]
pub enum COMP0W {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP0W {
#[allow(missing_docs)]
@ -1338,10 +1298,8 @@ impl<'a> _DECAPEN0W<'a> {
}
#[doc = "Values that can be written to the field `DECAP0`"]
pub enum DECAP0W {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP0W {
#[allow(missing_docs)]
@ -1396,10 +1354,8 @@ impl<'a> _DECAP0W<'a> {
}
#[doc = "Values that can be written to the field `DTEN0`"]
pub enum DTEN0W {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN0W {
#[allow(missing_docs)]
@ -1454,10 +1410,8 @@ impl<'a> _DTEN0W<'a> {
}
#[doc = "Values that can be written to the field `SYNCEN0`"]
pub enum SYNCEN0W {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN0W {
#[allow(missing_docs)]
@ -1512,10 +1466,8 @@ impl<'a> _SYNCEN0W<'a> {
}
#[doc = "Values that can be written to the field `FAULTEN0`"]
pub enum FAULTEN0W {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN0W {
#[allow(missing_docs)]
@ -1616,10 +1568,8 @@ impl<'a> _COMBINE1W<'a> {
}
#[doc = "Values that can be written to the field `COMP1`"]
pub enum COMP1W {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP1W {
#[allow(missing_docs)]
@ -1697,10 +1647,8 @@ impl<'a> _DECAPEN1W<'a> {
}
#[doc = "Values that can be written to the field `DECAP1`"]
pub enum DECAP1W {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP1W {
#[allow(missing_docs)]
@ -1755,10 +1703,8 @@ impl<'a> _DECAP1W<'a> {
}
#[doc = "Values that can be written to the field `DTEN1`"]
pub enum DTEN1W {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN1W {
#[allow(missing_docs)]
@ -1813,10 +1759,8 @@ impl<'a> _DTEN1W<'a> {
}
#[doc = "Values that can be written to the field `SYNCEN1`"]
pub enum SYNCEN1W {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN1W {
#[allow(missing_docs)]
@ -1871,10 +1815,8 @@ impl<'a> _SYNCEN1W<'a> {
}
#[doc = "Values that can be written to the field `FAULTEN1`"]
pub enum FAULTEN1W {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN1W {
#[allow(missing_docs)]
@ -1975,10 +1917,8 @@ impl<'a> _COMBINE2W<'a> {
}
#[doc = "Values that can be written to the field `COMP2`"]
pub enum COMP2W {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP2W {
#[allow(missing_docs)]
@ -2056,10 +1996,8 @@ impl<'a> _DECAPEN2W<'a> {
}
#[doc = "Values that can be written to the field `DECAP2`"]
pub enum DECAP2W {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP2W {
#[allow(missing_docs)]
@ -2114,10 +2052,8 @@ impl<'a> _DECAP2W<'a> {
}
#[doc = "Values that can be written to the field `DTEN2`"]
pub enum DTEN2W {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN2W {
#[allow(missing_docs)]
@ -2172,10 +2108,8 @@ impl<'a> _DTEN2W<'a> {
}
#[doc = "Values that can be written to the field `SYNCEN2`"]
pub enum SYNCEN2W {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN2W {
#[allow(missing_docs)]
@ -2230,10 +2164,8 @@ impl<'a> _SYNCEN2W<'a> {
}
#[doc = "Values that can be written to the field `FAULTEN2`"]
pub enum FAULTEN2W {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN2W {
#[allow(missing_docs)]
@ -2334,10 +2266,8 @@ impl<'a> _COMBINE3W<'a> {
}
#[doc = "Values that can be written to the field `COMP3`"]
pub enum COMP3W {
#[doc = "The channel (n+1) output is the same as the channel (n) output."]
_0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."]
_1,
#[doc = "The channel (n+1) output is the same as the channel (n) output."] _0,
#[doc = "The channel (n+1) output is the complement of the channel (n) output."] _1,
}
impl COMP3W {
#[allow(missing_docs)]
@ -2415,10 +2345,8 @@ impl<'a> _DECAPEN3W<'a> {
}
#[doc = "Values that can be written to the field `DECAP3`"]
pub enum DECAP3W {
#[doc = "The dual edge captures are inactive."]
_0,
#[doc = "The dual edge captures are active."]
_1,
#[doc = "The dual edge captures are inactive."] _0,
#[doc = "The dual edge captures are active."] _1,
}
impl DECAP3W {
#[allow(missing_docs)]
@ -2473,10 +2401,8 @@ impl<'a> _DECAP3W<'a> {
}
#[doc = "Values that can be written to the field `DTEN3`"]
pub enum DTEN3W {
#[doc = "The deadtime insertion in this pair of channels is disabled."]
_0,
#[doc = "The deadtime insertion in this pair of channels is enabled."]
_1,
#[doc = "The deadtime insertion in this pair of channels is disabled."] _0,
#[doc = "The deadtime insertion in this pair of channels is enabled."] _1,
}
impl DTEN3W {
#[allow(missing_docs)]
@ -2531,10 +2457,8 @@ impl<'a> _DTEN3W<'a> {
}
#[doc = "Values that can be written to the field `SYNCEN3`"]
pub enum SYNCEN3W {
#[doc = "The PWM synchronization in this pair of channels is disabled."]
_0,
#[doc = "The PWM synchronization in this pair of channels is enabled."]
_1,
#[doc = "The PWM synchronization in this pair of channels is disabled."] _0,
#[doc = "The PWM synchronization in this pair of channels is enabled."] _1,
}
impl SYNCEN3W {
#[allow(missing_docs)]
@ -2589,10 +2513,8 @@ impl<'a> _SYNCEN3W<'a> {
}
#[doc = "Values that can be written to the field `FAULTEN3`"]
pub enum FAULTEN3W {
#[doc = "The fault control in this pair of channels is disabled."]
_0,
#[doc = "The fault control in this pair of channels is enabled."]
_1,
#[doc = "The fault control in this pair of channels is disabled."] _0,
#[doc = "The fault control in this pair of channels is enabled."] _1,
}
impl FAULTEN3W {
#[allow(missing_docs)]

16
src/ftm1/conf/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CONF {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -107,10 +109,8 @@ impl GTBEOUTR {
#[doc = "Possible values of the field `ITRIGR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ITRIGRR {
#[doc = "Initialization trigger is generated on counter wrap events."]
_0,
#[doc = "Initialization trigger is generated when a reload point is reached."]
_1,
#[doc = "Initialization trigger is generated on counter wrap events."] _0,
#[doc = "Initialization trigger is generated when a reload point is reached."] _1,
}
impl ITRIGRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -229,10 +229,8 @@ impl<'a> _GTBEOUTW<'a> {
}
#[doc = "Values that can be written to the field `ITRIGR`"]
pub enum ITRIGRW {
#[doc = "Initialization trigger is generated on counter wrap events."]
_0,
#[doc = "Initialization trigger is generated when a reload point is reached."]
_1,
#[doc = "Initialization trigger is generated on counter wrap events."] _0,
#[doc = "Initialization trigger is generated when a reload point is reached."] _1,
}
impl ITRIGRW {
#[allow(missing_docs)]

25
src/ftm1/deadtime/mod.rs
View File

@ -22,7 +22,9 @@ impl super::DEADTIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,10 @@ impl DTVALR {
#[doc = "Possible values of the field `DTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTPSR {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DTPSR {
#[doc = r" Value of the field as raw bits"]
@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> {
}
#[doc = "Values that can be written to the field `DTPS`"]
pub enum DTPSW {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
}
impl DTPSW {
#[allow(missing_docs)]

118
src/ftm1/exttrig/mod.rs
View File

@ -22,7 +22,9 @@ impl super::EXTTRIG {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::EXTTRIG {
#[doc = "Possible values of the field `CH2TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH2TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CH2TRIGR {
#[doc = "Possible values of the field `CH3TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH3TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl CH3TRIGR {
#[doc = "Possible values of the field `CH4TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH4TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl CH4TRIGR {
#[doc = "Possible values of the field `CH5TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH5TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl CH5TRIGR {
#[doc = "Possible values of the field `CH0TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH0TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl CH0TRIGR {
#[doc = "Possible values of the field `CH1TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH1TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl CH1TRIGR {
#[doc = "Possible values of the field `INITTRIGEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INITTRIGENR {
#[doc = "The generation of initialization trigger is disabled."]
_0,
#[doc = "The generation of initialization trigger is enabled."]
_1,
#[doc = "The generation of initialization trigger is disabled."] _0,
#[doc = "The generation of initialization trigger is enabled."] _1,
}
impl INITTRIGENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl INITTRIGENR {
#[doc = "Possible values of the field `TRIGF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGFR {
#[doc = "No channel trigger was generated."]
_0,
#[doc = "A channel trigger was generated."]
_1,
#[doc = "No channel trigger was generated."] _0,
#[doc = "A channel trigger was generated."] _1,
}
impl TRIGFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -419,10 +405,8 @@ impl TRIGFR {
#[doc = "Possible values of the field `CH6TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH6TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -466,10 +450,8 @@ impl CH6TRIGR {
#[doc = "Possible values of the field `CH7TRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7TRIGR {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH7TRIGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -512,10 +494,8 @@ impl CH7TRIGR {
}
#[doc = "Values that can be written to the field `CH2TRIG`"]
pub enum CH2TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH2TRIGW {
#[allow(missing_docs)]
@ -570,10 +550,8 @@ impl<'a> _CH2TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH3TRIG`"]
pub enum CH3TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH3TRIGW {
#[allow(missing_docs)]
@ -628,10 +606,8 @@ impl<'a> _CH3TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH4TRIG`"]
pub enum CH4TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH4TRIGW {
#[allow(missing_docs)]
@ -686,10 +662,8 @@ impl<'a> _CH4TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH5TRIG`"]
pub enum CH5TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH5TRIGW {
#[allow(missing_docs)]
@ -744,10 +718,8 @@ impl<'a> _CH5TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH0TRIG`"]
pub enum CH0TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH0TRIGW {
#[allow(missing_docs)]
@ -802,10 +774,8 @@ impl<'a> _CH0TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH1TRIG`"]
pub enum CH1TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH1TRIGW {
#[allow(missing_docs)]
@ -860,10 +830,8 @@ impl<'a> _CH1TRIGW<'a> {
}
#[doc = "Values that can be written to the field `INITTRIGEN`"]
pub enum INITTRIGENW {
#[doc = "The generation of initialization trigger is disabled."]
_0,
#[doc = "The generation of initialization trigger is enabled."]
_1,
#[doc = "The generation of initialization trigger is disabled."] _0,
#[doc = "The generation of initialization trigger is enabled."] _1,
}
impl INITTRIGENW {
#[allow(missing_docs)]
@ -918,10 +886,8 @@ impl<'a> _INITTRIGENW<'a> {
}
#[doc = "Values that can be written to the field `CH6TRIG`"]
pub enum CH6TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH6TRIGW {
#[allow(missing_docs)]
@ -976,10 +942,8 @@ impl<'a> _CH6TRIGW<'a> {
}
#[doc = "Values that can be written to the field `CH7TRIG`"]
pub enum CH7TRIGW {
#[doc = "The generation of this external trigger is disabled."]
_0,
#[doc = "The generation of this external trigger is enabled."]
_1,
#[doc = "The generation of this external trigger is disabled."] _0,
#[doc = "The generation of this external trigger is enabled."] _1,
}
impl CH7TRIGW {
#[allow(missing_docs)]

4
src/ftm1/filter/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FILTER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

106
src/ftm1/fltctrl/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FLTCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::FLTCTRL {
#[doc = "Possible values of the field `FAULT0EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULT0ENR {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT0ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl FAULT0ENR {
#[doc = "Possible values of the field `FAULT1EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULT1ENR {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT1ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl FAULT1ENR {
#[doc = "Possible values of the field `FAULT2EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULT2ENR {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT2ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl FAULT2ENR {
#[doc = "Possible values of the field `FAULT3EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULT3ENR {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT3ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl FAULT3ENR {
#[doc = "Possible values of the field `FFLTR0EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FFLTR0ENR {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR0ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl FFLTR0ENR {
#[doc = "Possible values of the field `FFLTR1EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FFLTR1ENR {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR1ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl FFLTR1ENR {
#[doc = "Possible values of the field `FFLTR2EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FFLTR2ENR {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR2ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl FFLTR2ENR {
#[doc = "Possible values of the field `FFLTR3EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FFLTR3ENR {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR3ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -432,8 +418,7 @@ impl FFVALR {
pub enum FSTATER {
#[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."]
_0,
#[doc = "FTM outputs will be tri-stated when fault event is ongoing"]
_1,
#[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1,
}
impl FSTATER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -476,10 +461,8 @@ impl FSTATER {
}
#[doc = "Values that can be written to the field `FAULT0EN`"]
pub enum FAULT0ENW {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT0ENW {
#[allow(missing_docs)]
@ -534,10 +517,8 @@ impl<'a> _FAULT0ENW<'a> {
}
#[doc = "Values that can be written to the field `FAULT1EN`"]
pub enum FAULT1ENW {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT1ENW {
#[allow(missing_docs)]
@ -592,10 +573,8 @@ impl<'a> _FAULT1ENW<'a> {
}
#[doc = "Values that can be written to the field `FAULT2EN`"]
pub enum FAULT2ENW {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT2ENW {
#[allow(missing_docs)]
@ -650,10 +629,8 @@ impl<'a> _FAULT2ENW<'a> {
}
#[doc = "Values that can be written to the field `FAULT3EN`"]
pub enum FAULT3ENW {
#[doc = "Fault input is disabled."]
_0,
#[doc = "Fault input is enabled."]
_1,
#[doc = "Fault input is disabled."] _0,
#[doc = "Fault input is enabled."] _1,
}
impl FAULT3ENW {
#[allow(missing_docs)]
@ -708,10 +685,8 @@ impl<'a> _FAULT3ENW<'a> {
}
#[doc = "Values that can be written to the field `FFLTR0EN`"]
pub enum FFLTR0ENW {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR0ENW {
#[allow(missing_docs)]
@ -766,10 +741,8 @@ impl<'a> _FFLTR0ENW<'a> {
}
#[doc = "Values that can be written to the field `FFLTR1EN`"]
pub enum FFLTR1ENW {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR1ENW {
#[allow(missing_docs)]
@ -824,10 +797,8 @@ impl<'a> _FFLTR1ENW<'a> {
}
#[doc = "Values that can be written to the field `FFLTR2EN`"]
pub enum FFLTR2ENW {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR2ENW {
#[allow(missing_docs)]
@ -882,10 +853,8 @@ impl<'a> _FFLTR2ENW<'a> {
}
#[doc = "Values that can be written to the field `FFLTR3EN`"]
pub enum FFLTR3ENW {
#[doc = "Fault input filter is disabled."]
_0,
#[doc = "Fault input filter is enabled."]
_1,
#[doc = "Fault input filter is disabled."] _0,
#[doc = "Fault input filter is enabled."] _1,
}
impl FFLTR3ENW {
#[allow(missing_docs)]
@ -957,8 +926,7 @@ impl<'a> _FFVALW<'a> {
pub enum FSTATEW {
#[doc = "FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits)."]
_0,
#[doc = "FTM outputs will be tri-stated when fault event is ongoing"]
_1,
#[doc = "FTM outputs will be tri-stated when fault event is ongoing"] _1,
}
impl FSTATEW {
#[allow(missing_docs)]

52
src/ftm1/fltpol/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FLTPOL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::FLTPOL {
#[doc = "Possible values of the field `FLT0POL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT0POLR {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT0POLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl FLT0POLR {
#[doc = "Possible values of the field `FLT1POL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT1POLR {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT1POLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl FLT1POLR {
#[doc = "Possible values of the field `FLT2POL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT2POLR {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT2POLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl FLT2POLR {
#[doc = "Possible values of the field `FLT3POL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT3POLR {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT3POLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -230,10 +224,8 @@ impl FLT3POLR {
}
#[doc = "Values that can be written to the field `FLT0POL`"]
pub enum FLT0POLW {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT0POLW {
#[allow(missing_docs)]
@ -288,10 +280,8 @@ impl<'a> _FLT0POLW<'a> {
}
#[doc = "Values that can be written to the field `FLT1POL`"]
pub enum FLT1POLW {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT1POLW {
#[allow(missing_docs)]
@ -346,10 +336,8 @@ impl<'a> _FLT1POLW<'a> {
}
#[doc = "Values that can be written to the field `FLT2POL`"]
pub enum FLT2POLW {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT2POLW {
#[allow(missing_docs)]
@ -404,10 +392,8 @@ impl<'a> _FLT2POLW<'a> {
}
#[doc = "Values that can be written to the field `FLT3POL`"]
pub enum FLT3POLW {
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
_0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
_1,
#[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."] _0,
#[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."] _1,
}
impl FLT3POLW {
#[allow(missing_docs)]

52
src/ftm1/fms/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FMS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::FMS {
#[doc = "Possible values of the field `FAULTF0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTF0R {
#[doc = "No fault condition was detected at the fault input."]
_0,
#[doc = "A fault condition was detected at the fault input."]
_1,
#[doc = "No fault condition was detected at the fault input."] _0,
#[doc = "A fault condition was detected at the fault input."] _1,
}
impl FAULTF0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl FAULTF0R {
#[doc = "Possible values of the field `FAULTF1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTF1R {
#[doc = "No fault condition was detected at the fault input."]
_0,
#[doc = "A fault condition was detected at the fault input."]
_1,
#[doc = "No fault condition was detected at the fault input."] _0,
#[doc = "A fault condition was detected at the fault input."] _1,
}
impl FAULTF1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl FAULTF1R {
#[doc = "Possible values of the field `FAULTF2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTF2R {
#[doc = "No fault condition was detected at the fault input."]
_0,
#[doc = "A fault condition was detected at the fault input."]
_1,
#[doc = "No fault condition was detected at the fault input."] _0,
#[doc = "A fault condition was detected at the fault input."] _1,
}
impl FAULTF2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl FAULTF2R {
#[doc = "Possible values of the field `FAULTF3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTF3R {
#[doc = "No fault condition was detected at the fault input."]
_0,
#[doc = "A fault condition was detected at the fault input."]
_1,
#[doc = "No fault condition was detected at the fault input."] _0,
#[doc = "A fault condition was detected at the fault input."] _1,
}
impl FAULTF3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl FAULTF3R {
#[doc = "Possible values of the field `FAULTIN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTINR {
#[doc = "The logic OR of the enabled fault inputs is 0."]
_0,
#[doc = "The logic OR of the enabled fault inputs is 1."]
_1,
#[doc = "The logic OR of the enabled fault inputs is 0."] _0,
#[doc = "The logic OR of the enabled fault inputs is 1."] _1,
}
impl FAULTINR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl FAULTINR {
#[doc = "Possible values of the field `WPEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WPENR {
#[doc = "Write protection is disabled. Write protected bits can be written."]
_0,
#[doc = "Write protection is enabled. Write protected bits cannot be written."]
_1,
#[doc = "Write protection is disabled. Write protected bits can be written."] _0,
#[doc = "Write protection is enabled. Write protected bits cannot be written."] _1,
}
impl WPENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl WPENR {
#[doc = "Possible values of the field `FAULTF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTFR {
#[doc = "No fault condition was detected."]
_0,
#[doc = "A fault condition was detected."]
_1,
#[doc = "No fault condition was detected."] _0,
#[doc = "A fault condition was detected."] _1,
}
impl FAULTFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -371,10 +359,8 @@ impl FAULTFR {
}
#[doc = "Values that can be written to the field `WPEN`"]
pub enum WPENW {
#[doc = "Write protection is disabled. Write protected bits can be written."]
_0,
#[doc = "Write protection is enabled. Write protected bits cannot be written."]
_1,
#[doc = "Write protection is disabled. Write protected bits can be written."] _0,
#[doc = "Write protection is enabled. Write protected bits cannot be written."] _1,
}
impl WPENW {
#[allow(missing_docs)]

4
src/ftm1/hcr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::HCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

52
src/ftm1/invctrl/mod.rs
View File

@ -22,7 +22,9 @@ impl super::INVCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::INVCTRL {
#[doc = "Possible values of the field `INV0EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INV0ENR {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV0ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl INV0ENR {
#[doc = "Possible values of the field `INV1EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INV1ENR {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV1ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl INV1ENR {
#[doc = "Possible values of the field `INV2EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INV2ENR {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV2ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl INV2ENR {
#[doc = "Possible values of the field `INV3EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INV3ENR {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV3ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -230,10 +224,8 @@ impl INV3ENR {
}
#[doc = "Values that can be written to the field `INV0EN`"]
pub enum INV0ENW {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV0ENW {
#[allow(missing_docs)]
@ -288,10 +280,8 @@ impl<'a> _INV0ENW<'a> {
}
#[doc = "Values that can be written to the field `INV1EN`"]
pub enum INV1ENW {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV1ENW {
#[allow(missing_docs)]
@ -346,10 +336,8 @@ impl<'a> _INV1ENW<'a> {
}
#[doc = "Values that can be written to the field `INV2EN`"]
pub enum INV2ENW {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV2ENW {
#[allow(missing_docs)]
@ -404,10 +392,8 @@ impl<'a> _INV2ENW<'a> {
}
#[doc = "Values that can be written to the field `INV3EN`"]
pub enum INV3ENW {
#[doc = "Inverting is disabled."]
_0,
#[doc = "Inverting is enabled."]
_1,
#[doc = "Inverting is disabled."] _0,
#[doc = "Inverting is enabled."] _1,
}
impl INV3ENW {
#[allow(missing_docs)]

132
src/ftm1/mod.rs
View File

@ -2,97 +2,53 @@ use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Status And Control"]
pub sc: SC,
#[doc = "0x04 - Counter"]
pub cnt: CNT,
#[doc = "0x08 - Modulo"]
pub mod_: MOD,
#[doc = "0x0c - Channel (n) Status And Control"]
pub c0sc: C0SC,
#[doc = "0x10 - Channel (n) Value"]
pub c0v: C0V,
#[doc = "0x14 - Channel (n) Status And Control"]
pub c1sc: C1SC,
#[doc = "0x18 - Channel (n) Value"]
pub c1v: C1V,
#[doc = "0x1c - Channel (n) Status And Control"]
pub c2sc: C2SC,
#[doc = "0x20 - Channel (n) Value"]
pub c2v: C2V,
#[doc = "0x24 - Channel (n) Status And Control"]
pub c3sc: C3SC,
#[doc = "0x28 - Channel (n) Value"]
pub c3v: C3V,
#[doc = "0x2c - Channel (n) Status And Control"]
pub c4sc: C4SC,
#[doc = "0x30 - Channel (n) Value"]
pub c4v: C4V,
#[doc = "0x34 - Channel (n) Status And Control"]
pub c5sc: C5SC,
#[doc = "0x38 - Channel (n) Value"]
pub c5v: C5V,
#[doc = "0x3c - Channel (n) Status And Control"]
pub c6sc: C6SC,
#[doc = "0x40 - Channel (n) Value"]
pub c6v: C6V,
#[doc = "0x44 - Channel (n) Status And Control"]
pub c7sc: C7SC,
#[doc = "0x48 - Channel (n) Value"]
pub c7v: C7V,
#[doc = "0x4c - Counter Initial Value"]
pub cntin: CNTIN,
#[doc = "0x50 - Capture And Compare Status"]
pub status: STATUS,
#[doc = "0x54 - Features Mode Selection"]
pub mode: MODE,
#[doc = "0x58 - Synchronization"]
pub sync: SYNC,
#[doc = "0x5c - Initial State For Channels Output"]
pub outinit: OUTINIT,
#[doc = "0x60 - Output Mask"]
pub outmask: OUTMASK,
#[doc = "0x64 - Function For Linked Channels"]
pub combine: COMBINE,
#[doc = "0x68 - Deadtime Configuration"]
pub deadtime: DEADTIME,
#[doc = "0x6c - FTM External Trigger"]
pub exttrig: EXTTRIG,
#[doc = "0x70 - Channels Polarity"]
pub pol: POL,
#[doc = "0x74 - Fault Mode Status"]
pub fms: FMS,
#[doc = "0x78 - Input Capture Filter Control"]
pub filter: FILTER,
#[doc = "0x7c - Fault Control"]
pub fltctrl: FLTCTRL,
#[doc = "0x80 - Quadrature Decoder Control And Status"]
pub qdctrl: QDCTRL,
#[doc = "0x84 - Configuration"]
pub conf: CONF,
#[doc = "0x88 - FTM Fault Input Polarity"]
pub fltpol: FLTPOL,
#[doc = "0x8c - Synchronization Configuration"]
pub synconf: SYNCONF,
#[doc = "0x90 - FTM Inverting Control"]
pub invctrl: INVCTRL,
#[doc = "0x94 - FTM Software Output Control"]
pub swoctrl: SWOCTRL,
#[doc = "0x98 - FTM PWM Load"]
pub pwmload: PWMLOAD,
#[doc = "0x9c - Half Cycle Register"]
pub hcr: HCR,
#[doc = "0xa0 - Pair 0 Deadtime Configuration"]
pub pair0deadtime: PAIR0DEADTIME,
#[doc = "0x00 - Status And Control"] pub sc: SC,
#[doc = "0x04 - Counter"] pub cnt: CNT,
#[doc = "0x08 - Modulo"] pub mod_: MOD,
#[doc = "0x0c - Channel (n) Status And Control"] pub c0sc: C0SC,
#[doc = "0x10 - Channel (n) Value"] pub c0v: C0V,
#[doc = "0x14 - Channel (n) Status And Control"] pub c1sc: C1SC,
#[doc = "0x18 - Channel (n) Value"] pub c1v: C1V,
#[doc = "0x1c - Channel (n) Status And Control"] pub c2sc: C2SC,
#[doc = "0x20 - Channel (n) Value"] pub c2v: C2V,
#[doc = "0x24 - Channel (n) Status And Control"] pub c3sc: C3SC,
#[doc = "0x28 - Channel (n) Value"] pub c3v: C3V,
#[doc = "0x2c - Channel (n) Status And Control"] pub c4sc: C4SC,
#[doc = "0x30 - Channel (n) Value"] pub c4v: C4V,
#[doc = "0x34 - Channel (n) Status And Control"] pub c5sc: C5SC,
#[doc = "0x38 - Channel (n) Value"] pub c5v: C5V,
#[doc = "0x3c - Channel (n) Status And Control"] pub c6sc: C6SC,
#[doc = "0x40 - Channel (n) Value"] pub c6v: C6V,
#[doc = "0x44 - Channel (n) Status And Control"] pub c7sc: C7SC,
#[doc = "0x48 - Channel (n) Value"] pub c7v: C7V,
#[doc = "0x4c - Counter Initial Value"] pub cntin: CNTIN,
#[doc = "0x50 - Capture And Compare Status"] pub status: STATUS,
#[doc = "0x54 - Features Mode Selection"] pub mode: MODE,
#[doc = "0x58 - Synchronization"] pub sync: SYNC,
#[doc = "0x5c - Initial State For Channels Output"] pub outinit: OUTINIT,
#[doc = "0x60 - Output Mask"] pub outmask: OUTMASK,
#[doc = "0x64 - Function For Linked Channels"] pub combine: COMBINE,
#[doc = "0x68 - Deadtime Configuration"] pub deadtime: DEADTIME,
#[doc = "0x6c - FTM External Trigger"] pub exttrig: EXTTRIG,
#[doc = "0x70 - Channels Polarity"] pub pol: POL,
#[doc = "0x74 - Fault Mode Status"] pub fms: FMS,
#[doc = "0x78 - Input Capture Filter Control"] pub filter: FILTER,
#[doc = "0x7c - Fault Control"] pub fltctrl: FLTCTRL,
#[doc = "0x80 - Quadrature Decoder Control And Status"] pub qdctrl: QDCTRL,
#[doc = "0x84 - Configuration"] pub conf: CONF,
#[doc = "0x88 - FTM Fault Input Polarity"] pub fltpol: FLTPOL,
#[doc = "0x8c - Synchronization Configuration"] pub synconf: SYNCONF,
#[doc = "0x90 - FTM Inverting Control"] pub invctrl: INVCTRL,
#[doc = "0x94 - FTM Software Output Control"] pub swoctrl: SWOCTRL,
#[doc = "0x98 - FTM PWM Load"] pub pwmload: PWMLOAD,
#[doc = "0x9c - Half Cycle Register"] pub hcr: HCR,
#[doc = "0xa0 - Pair 0 Deadtime Configuration"] pub pair0deadtime: PAIR0DEADTIME,
_reserved0: [u8; 4usize],
#[doc = "0xa8 - Pair 1 Deadtime Configuration"]
pub pair1deadtime: PAIR1DEADTIME,
#[doc = "0xa8 - Pair 1 Deadtime Configuration"] pub pair1deadtime: PAIR1DEADTIME,
_reserved1: [u8; 4usize],
#[doc = "0xb0 - Pair 2 Deadtime Configuration"]
pub pair2deadtime: PAIR2DEADTIME,
#[doc = "0xb0 - Pair 2 Deadtime Configuration"] pub pair2deadtime: PAIR2DEADTIME,
_reserved2: [u8; 4usize],
#[doc = "0xb8 - Pair 3 Deadtime Configuration"]
pub pair3deadtime: PAIR3DEADTIME,
#[doc = "0xb8 - Pair 3 Deadtime Configuration"] pub pair3deadtime: PAIR3DEADTIME,
}
#[doc = "Status And Control"]
pub struct SC {

4
src/ftm1/mod_/mod.rs
View File

@ -22,7 +22,9 @@ impl super::MOD {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

58
src/ftm1/mode/mod.rs
View File

@ -22,7 +22,9 @@ impl super::MODE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::MODE {
#[doc = "Possible values of the field `FTMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTMENR {
#[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."]
_0,
#[doc = "Free running counter and synchronization are different from TPM behavior."]
_1,
#[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0,
#[doc = "Free running counter and synchronization are different from TPM behavior."] _1,
}
impl FTMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl FTMENR {
#[doc = "Possible values of the field `WPDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WPDISR {
#[doc = "Write protection is enabled."]
_0,
#[doc = "Write protection is disabled."]
_1,
#[doc = "Write protection is enabled."] _0,
#[doc = "Write protection is disabled."] _1,
}
impl WPDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +182,8 @@ impl PWMSYNCR {
#[doc = "Possible values of the field `CAPTEST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAPTESTR {
#[doc = "Capture test mode is disabled."]
_0,
#[doc = "Capture test mode is enabled."]
_1,
#[doc = "Capture test mode is disabled."] _0,
#[doc = "Capture test mode is enabled."] _1,
}
impl CAPTESTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,8 +227,7 @@ impl CAPTESTR {
#[doc = "Possible values of the field `FAULTM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTMR {
#[doc = "Fault control is disabled for all channels."]
_00,
#[doc = "Fault control is disabled for all channels."] _00,
#[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."]
_01,
#[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."]
@ -287,10 +282,8 @@ impl FAULTMR {
#[doc = "Possible values of the field `FAULTIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FAULTIER {
#[doc = "Fault control interrupt is disabled."]
_0,
#[doc = "Fault control interrupt is enabled."]
_1,
#[doc = "Fault control interrupt is disabled."] _0,
#[doc = "Fault control interrupt is enabled."] _1,
}
impl FAULTIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -333,10 +326,8 @@ impl FAULTIER {
}
#[doc = "Values that can be written to the field `FTMEN`"]
pub enum FTMENW {
#[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."]
_0,
#[doc = "Free running counter and synchronization are different from TPM behavior."]
_1,
#[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."] _0,
#[doc = "Free running counter and synchronization are different from TPM behavior."] _1,
}
impl FTMENW {
#[allow(missing_docs)]
@ -414,10 +405,8 @@ impl<'a> _INITW<'a> {
}
#[doc = "Values that can be written to the field `WPDIS`"]
pub enum WPDISW {
#[doc = "Write protection is enabled."]
_0,
#[doc = "Write protection is disabled."]
_1,
#[doc = "Write protection is enabled."] _0,
#[doc = "Write protection is disabled."] _1,
}
impl WPDISW {
#[allow(missing_docs)]
@ -530,10 +519,8 @@ impl<'a> _PWMSYNCW<'a> {
}
#[doc = "Values that can be written to the field `CAPTEST`"]
pub enum CAPTESTW {
#[doc = "Capture test mode is disabled."]
_0,
#[doc = "Capture test mode is enabled."]
_1,
#[doc = "Capture test mode is disabled."] _0,
#[doc = "Capture test mode is enabled."] _1,
}
impl CAPTESTW {
#[allow(missing_docs)]
@ -588,8 +575,7 @@ impl<'a> _CAPTESTW<'a> {
}
#[doc = "Values that can be written to the field `FAULTM`"]
pub enum FAULTMW {
#[doc = "Fault control is disabled for all channels."]
_00,
#[doc = "Fault control is disabled for all channels."] _00,
#[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."]
_01,
#[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."]
@ -654,10 +640,8 @@ impl<'a> _FAULTMW<'a> {
}
#[doc = "Values that can be written to the field `FAULTIE`"]
pub enum FAULTIEW {
#[doc = "Fault control interrupt is disabled."]
_0,
#[doc = "Fault control interrupt is enabled."]
_1,
#[doc = "Fault control interrupt is disabled."] _0,
#[doc = "Fault control interrupt is enabled."] _1,
}
impl FAULTIEW {
#[allow(missing_docs)]

100
src/ftm1/outinit/mod.rs
View File

@ -22,7 +22,9 @@ impl super::OUTINIT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::OUTINIT {
#[doc = "Possible values of the field `CH0OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH0OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CH0OIR {
#[doc = "Possible values of the field `CH1OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH1OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl CH1OIR {
#[doc = "Possible values of the field `CH2OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH2OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl CH2OIR {
#[doc = "Possible values of the field `CH3OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH3OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl CH3OIR {
#[doc = "Possible values of the field `CH4OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH4OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl CH4OIR {
#[doc = "Possible values of the field `CH5OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH5OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl CH5OIR {
#[doc = "Possible values of the field `CH6OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH6OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl CH6OIR {
#[doc = "Possible values of the field `CH7OI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7OIR {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH7OIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -418,10 +404,8 @@ impl CH7OIR {
}
#[doc = "Values that can be written to the field `CH0OI`"]
pub enum CH0OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH0OIW {
#[allow(missing_docs)]
@ -476,10 +460,8 @@ impl<'a> _CH0OIW<'a> {
}
#[doc = "Values that can be written to the field `CH1OI`"]
pub enum CH1OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH1OIW {
#[allow(missing_docs)]
@ -534,10 +516,8 @@ impl<'a> _CH1OIW<'a> {
}
#[doc = "Values that can be written to the field `CH2OI`"]
pub enum CH2OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH2OIW {
#[allow(missing_docs)]
@ -592,10 +572,8 @@ impl<'a> _CH2OIW<'a> {
}
#[doc = "Values that can be written to the field `CH3OI`"]
pub enum CH3OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH3OIW {
#[allow(missing_docs)]
@ -650,10 +628,8 @@ impl<'a> _CH3OIW<'a> {
}
#[doc = "Values that can be written to the field `CH4OI`"]
pub enum CH4OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH4OIW {
#[allow(missing_docs)]
@ -708,10 +684,8 @@ impl<'a> _CH4OIW<'a> {
}
#[doc = "Values that can be written to the field `CH5OI`"]
pub enum CH5OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH5OIW {
#[allow(missing_docs)]
@ -766,10 +740,8 @@ impl<'a> _CH5OIW<'a> {
}
#[doc = "Values that can be written to the field `CH6OI`"]
pub enum CH6OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH6OIW {
#[allow(missing_docs)]
@ -824,10 +796,8 @@ impl<'a> _CH6OIW<'a> {
}
#[doc = "Values that can be written to the field `CH7OI`"]
pub enum CH7OIW {
#[doc = "The initialization value is 0."]
_0,
#[doc = "The initialization value is 1."]
_1,
#[doc = "The initialization value is 0."] _0,
#[doc = "The initialization value is 1."] _1,
}
impl CH7OIW {
#[allow(missing_docs)]

100
src/ftm1/outmask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::OUTMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::OUTMASK {
#[doc = "Possible values of the field `CH0OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH0OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CH0OMR {
#[doc = "Possible values of the field `CH1OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH1OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl CH1OMR {
#[doc = "Possible values of the field `CH2OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH2OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl CH2OMR {
#[doc = "Possible values of the field `CH3OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH3OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl CH3OMR {
#[doc = "Possible values of the field `CH4OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH4OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl CH4OMR {
#[doc = "Possible values of the field `CH5OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH5OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl CH5OMR {
#[doc = "Possible values of the field `CH6OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH6OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl CH6OMR {
#[doc = "Possible values of the field `CH7OM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7OMR {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH7OMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -418,10 +404,8 @@ impl CH7OMR {
}
#[doc = "Values that can be written to the field `CH0OM`"]
pub enum CH0OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH0OMW {
#[allow(missing_docs)]
@ -476,10 +460,8 @@ impl<'a> _CH0OMW<'a> {
}
#[doc = "Values that can be written to the field `CH1OM`"]
pub enum CH1OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH1OMW {
#[allow(missing_docs)]
@ -534,10 +516,8 @@ impl<'a> _CH1OMW<'a> {
}
#[doc = "Values that can be written to the field `CH2OM`"]
pub enum CH2OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH2OMW {
#[allow(missing_docs)]
@ -592,10 +572,8 @@ impl<'a> _CH2OMW<'a> {
}
#[doc = "Values that can be written to the field `CH3OM`"]
pub enum CH3OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH3OMW {
#[allow(missing_docs)]
@ -650,10 +628,8 @@ impl<'a> _CH3OMW<'a> {
}
#[doc = "Values that can be written to the field `CH4OM`"]
pub enum CH4OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH4OMW {
#[allow(missing_docs)]
@ -708,10 +684,8 @@ impl<'a> _CH4OMW<'a> {
}
#[doc = "Values that can be written to the field `CH5OM`"]
pub enum CH5OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH5OMW {
#[allow(missing_docs)]
@ -766,10 +740,8 @@ impl<'a> _CH5OMW<'a> {
}
#[doc = "Values that can be written to the field `CH6OM`"]
pub enum CH6OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH6OMW {
#[allow(missing_docs)]
@ -824,10 +796,8 @@ impl<'a> _CH6OMW<'a> {
}
#[doc = "Values that can be written to the field `CH7OM`"]
pub enum CH7OMW {
#[doc = "Channel output is not masked. It continues to operate normally."]
_0,
#[doc = "Channel output is masked. It is forced to its inactive state."]
_1,
#[doc = "Channel output is not masked. It continues to operate normally."] _0,
#[doc = "Channel output is masked. It is forced to its inactive state."] _1,
}
impl CH7OMW {
#[allow(missing_docs)]

25
src/ftm1/pair0deadtime/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PAIR0DEADTIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,10 @@ impl DTVALR {
#[doc = "Possible values of the field `DTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTPSR {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DTPSR {
#[doc = r" Value of the field as raw bits"]
@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> {
}
#[doc = "Values that can be written to the field `DTPS`"]
pub enum DTPSW {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
}
impl DTPSW {
#[allow(missing_docs)]

25
src/ftm1/pair1deadtime/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PAIR1DEADTIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,10 @@ impl DTVALR {
#[doc = "Possible values of the field `DTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTPSR {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DTPSR {
#[doc = r" Value of the field as raw bits"]
@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> {
}
#[doc = "Values that can be written to the field `DTPS`"]
pub enum DTPSW {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
}
impl DTPSW {
#[allow(missing_docs)]

25
src/ftm1/pair2deadtime/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PAIR2DEADTIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,10 @@ impl DTVALR {
#[doc = "Possible values of the field `DTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTPSR {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DTPSR {
#[doc = r" Value of the field as raw bits"]
@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> {
}
#[doc = "Values that can be written to the field `DTPS`"]
pub enum DTPSW {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
}
impl DTPSW {
#[allow(missing_docs)]

25
src/ftm1/pair3deadtime/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PAIR3DEADTIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,10 @@ impl DTVALR {
#[doc = "Possible values of the field `DTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTPSR {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
#[doc = r" Reserved"] _Reserved(u8),
}
impl DTPSR {
#[doc = r" Value of the field as raw bits"]
@ -129,12 +127,9 @@ impl<'a> _DTVALW<'a> {
}
#[doc = "Values that can be written to the field `DTPS`"]
pub enum DTPSW {
#[doc = "Divide the FTM input clock by 1."]
_0X,
#[doc = "Divide the FTM input clock by 4."]
_10,
#[doc = "Divide the FTM input clock by 16."]
_11,
#[doc = "Divide the FTM input clock by 1."] _0X,
#[doc = "Divide the FTM input clock by 4."] _10,
#[doc = "Divide the FTM input clock by 16."] _11,
}
impl DTPSW {
#[allow(missing_docs)]

100
src/ftm1/pol/mod.rs
View File

@ -22,7 +22,9 @@ impl super::POL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::POL {
#[doc = "Possible values of the field `POL0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL0R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl POL0R {
#[doc = "Possible values of the field `POL1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL1R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl POL1R {
#[doc = "Possible values of the field `POL2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL2R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl POL2R {
#[doc = "Possible values of the field `POL3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL3R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl POL3R {
#[doc = "Possible values of the field `POL4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL4R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl POL4R {
#[doc = "Possible values of the field `POL5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL5R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl POL5R {
#[doc = "Possible values of the field `POL6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL6R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl POL6R {
#[doc = "Possible values of the field `POL7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL7R {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL7R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -418,10 +404,8 @@ impl POL7R {
}
#[doc = "Values that can be written to the field `POL0`"]
pub enum POL0W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL0W {
#[allow(missing_docs)]
@ -476,10 +460,8 @@ impl<'a> _POL0W<'a> {
}
#[doc = "Values that can be written to the field `POL1`"]
pub enum POL1W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL1W {
#[allow(missing_docs)]
@ -534,10 +516,8 @@ impl<'a> _POL1W<'a> {
}
#[doc = "Values that can be written to the field `POL2`"]
pub enum POL2W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL2W {
#[allow(missing_docs)]
@ -592,10 +572,8 @@ impl<'a> _POL2W<'a> {
}
#[doc = "Values that can be written to the field `POL3`"]
pub enum POL3W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL3W {
#[allow(missing_docs)]
@ -650,10 +628,8 @@ impl<'a> _POL3W<'a> {
}
#[doc = "Values that can be written to the field `POL4`"]
pub enum POL4W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL4W {
#[allow(missing_docs)]
@ -708,10 +684,8 @@ impl<'a> _POL4W<'a> {
}
#[doc = "Values that can be written to the field `POL5`"]
pub enum POL5W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL5W {
#[allow(missing_docs)]
@ -766,10 +740,8 @@ impl<'a> _POL5W<'a> {
}
#[doc = "Values that can be written to the field `POL6`"]
pub enum POL6W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL6W {
#[allow(missing_docs)]
@ -824,10 +796,8 @@ impl<'a> _POL6W<'a> {
}
#[doc = "Values that can be written to the field `POL7`"]
pub enum POL7W {
#[doc = "The channel polarity is active high."]
_0,
#[doc = "The channel polarity is active low."]
_1,
#[doc = "The channel polarity is active high."] _0,
#[doc = "The channel polarity is active low."] _1,
}
impl POL7W {
#[allow(missing_docs)]

136
src/ftm1/pwmload/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PWMLOAD {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::PWMLOAD {
#[doc = "Possible values of the field `CH0SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH0SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CH0SELR {
#[doc = "Possible values of the field `CH1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH1SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl CH1SELR {
#[doc = "Possible values of the field `CH2SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH2SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl CH2SELR {
#[doc = "Possible values of the field `CH3SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH3SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl CH3SELR {
#[doc = "Possible values of the field `CH4SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH4SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl CH4SELR {
#[doc = "Possible values of the field `CH5SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH5SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl CH5SELR {
#[doc = "Possible values of the field `CH6SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH6SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl CH6SELR {
#[doc = "Possible values of the field `CH7SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7SELR {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH7SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -419,10 +405,8 @@ impl CH7SELR {
#[doc = "Possible values of the field `HCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HCSELR {
#[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."]
_0,
#[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."]
_1,
#[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0,
#[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1,
}
impl HCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -466,10 +450,8 @@ impl HCSELR {
#[doc = "Possible values of the field `LDOK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LDOKR {
#[doc = "Loading updated values is disabled."]
_0,
#[doc = "Loading updated values is enabled."]
_1,
#[doc = "Loading updated values is disabled."] _0,
#[doc = "Loading updated values is enabled."] _1,
}
impl LDOKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -513,8 +495,7 @@ impl LDOKR {
#[doc = "Possible values of the field `GLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GLENR {
#[doc = "Global Load Ok disabled."]
_0,
#[doc = "Global Load Ok disabled."] _0,
#[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."]
_1,
}
@ -559,10 +540,8 @@ impl GLENR {
}
#[doc = "Values that can be written to the field `CH0SEL`"]
pub enum CH0SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH0SELW {
#[allow(missing_docs)]
@ -617,10 +596,8 @@ impl<'a> _CH0SELW<'a> {
}
#[doc = "Values that can be written to the field `CH1SEL`"]
pub enum CH1SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH1SELW {
#[allow(missing_docs)]
@ -675,10 +652,8 @@ impl<'a> _CH1SELW<'a> {
}
#[doc = "Values that can be written to the field `CH2SEL`"]
pub enum CH2SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH2SELW {
#[allow(missing_docs)]
@ -733,10 +708,8 @@ impl<'a> _CH2SELW<'a> {
}
#[doc = "Values that can be written to the field `CH3SEL`"]
pub enum CH3SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH3SELW {
#[allow(missing_docs)]
@ -791,10 +764,8 @@ impl<'a> _CH3SELW<'a> {
}
#[doc = "Values that can be written to the field `CH4SEL`"]
pub enum CH4SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH4SELW {
#[allow(missing_docs)]
@ -849,10 +820,8 @@ impl<'a> _CH4SELW<'a> {
}
#[doc = "Values that can be written to the field `CH5SEL`"]
pub enum CH5SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH5SELW {
#[allow(missing_docs)]
@ -907,10 +876,8 @@ impl<'a> _CH5SELW<'a> {
}
#[doc = "Values that can be written to the field `CH6SEL`"]
pub enum CH6SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH6SELW {
#[allow(missing_docs)]
@ -965,10 +932,8 @@ impl<'a> _CH6SELW<'a> {
}
#[doc = "Values that can be written to the field `CH7SEL`"]
pub enum CH7SELW {
#[doc = "Channel match is not included as a reload opportunity."]
_0,
#[doc = "Channel match is included as a reload opportunity."]
_1,
#[doc = "Channel match is not included as a reload opportunity."] _0,
#[doc = "Channel match is included as a reload opportunity."] _1,
}
impl CH7SELW {
#[allow(missing_docs)]
@ -1023,10 +988,8 @@ impl<'a> _CH7SELW<'a> {
}
#[doc = "Values that can be written to the field `HCSEL`"]
pub enum HCSELW {
#[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."]
_0,
#[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."]
_1,
#[doc = "Half cycle reload is disabled and it is not considered as a reload opportunity."] _0,
#[doc = "Half cycle reload is enabled and it is considered as a reload opportunity."] _1,
}
impl HCSELW {
#[allow(missing_docs)]
@ -1081,10 +1044,8 @@ impl<'a> _HCSELW<'a> {
}
#[doc = "Values that can be written to the field `LDOK`"]
pub enum LDOKW {
#[doc = "Loading updated values is disabled."]
_0,
#[doc = "Loading updated values is enabled."]
_1,
#[doc = "Loading updated values is disabled."] _0,
#[doc = "Loading updated values is enabled."] _1,
}
impl LDOKW {
#[allow(missing_docs)]
@ -1139,8 +1100,7 @@ impl<'a> _LDOKW<'a> {
}
#[doc = "Values that can be written to the field `GLEN`"]
pub enum GLENW {
#[doc = "Global Load Ok disabled."]
_0,
#[doc = "Global Load Ok disabled."] _0,
#[doc = "Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit."]
_1,
}
@ -1197,10 +1157,8 @@ impl<'a> _GLENW<'a> {
}
#[doc = "Values that can be written to the field `GLDOK`"]
pub enum GLDOKW {
#[doc = "No action."]
_0,
#[doc = "LDOK bit is set."]
_1,
#[doc = "No action."] _0,
#[doc = "LDOK bit is set."] _1,
}
impl GLDOKW {
#[allow(missing_docs)]

58
src/ftm1/qdctrl/mod.rs
View File

@ -22,7 +22,9 @@ impl super::QDCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::QDCTRL {
#[doc = "Possible values of the field `QUADEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum QUADENR {
#[doc = "Quadrature Decoder mode is disabled."]
_0,
#[doc = "Quadrature Decoder mode is enabled."]
_1,
#[doc = "Quadrature Decoder mode is disabled."] _0,
#[doc = "Quadrature Decoder mode is enabled."] _1,
}
impl QUADENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +137,8 @@ impl TOFDIRR {
#[doc = "Possible values of the field `QUADIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum QUADIRR {
#[doc = "Counting direction is decreasing (FTM counter decrement)."]
_0,
#[doc = "Counting direction is increasing (FTM counter increment)."]
_1,
#[doc = "Counting direction is decreasing (FTM counter decrement)."] _0,
#[doc = "Counting direction is increasing (FTM counter increment)."] _1,
}
impl QUADIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +182,8 @@ impl QUADIRR {
#[doc = "Possible values of the field `QUADMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum QUADMODER {
#[doc = "Phase A and phase B encoding mode."]
_0,
#[doc = "Count and direction encoding mode."]
_1,
#[doc = "Phase A and phase B encoding mode."] _0,
#[doc = "Count and direction encoding mode."] _1,
}
impl QUADMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +321,8 @@ impl PHAPOLR {
#[doc = "Possible values of the field `PHBFLTREN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PHBFLTRENR {
#[doc = "Phase B input filter is disabled."]
_0,
#[doc = "Phase B input filter is enabled."]
_1,
#[doc = "Phase B input filter is disabled."] _0,
#[doc = "Phase B input filter is enabled."] _1,
}
impl PHBFLTRENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +366,8 @@ impl PHBFLTRENR {
#[doc = "Possible values of the field `PHAFLTREN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PHAFLTRENR {
#[doc = "Phase A input filter is disabled."]
_0,
#[doc = "Phase A input filter is enabled."]
_1,
#[doc = "Phase A input filter is disabled."] _0,
#[doc = "Phase A input filter is enabled."] _1,
}
impl PHAFLTRENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -418,10 +410,8 @@ impl PHAFLTRENR {
}
#[doc = "Values that can be written to the field `QUADEN`"]
pub enum QUADENW {
#[doc = "Quadrature Decoder mode is disabled."]
_0,
#[doc = "Quadrature Decoder mode is enabled."]
_1,
#[doc = "Quadrature Decoder mode is disabled."] _0,
#[doc = "Quadrature Decoder mode is enabled."] _1,
}
impl QUADENW {
#[allow(missing_docs)]
@ -476,10 +466,8 @@ impl<'a> _QUADENW<'a> {
}
#[doc = "Values that can be written to the field `QUADMODE`"]
pub enum QUADMODEW {
#[doc = "Phase A and phase B encoding mode."]
_0,
#[doc = "Count and direction encoding mode."]
_1,
#[doc = "Phase A and phase B encoding mode."] _0,
#[doc = "Count and direction encoding mode."] _1,
}
impl QUADMODEW {
#[allow(missing_docs)]
@ -650,10 +638,8 @@ impl<'a> _PHAPOLW<'a> {
}
#[doc = "Values that can be written to the field `PHBFLTREN`"]
pub enum PHBFLTRENW {
#[doc = "Phase B input filter is disabled."]
_0,
#[doc = "Phase B input filter is enabled."]
_1,
#[doc = "Phase B input filter is disabled."] _0,
#[doc = "Phase B input filter is enabled."] _1,
}
impl PHBFLTRENW {
#[allow(missing_docs)]
@ -708,10 +694,8 @@ impl<'a> _PHBFLTRENW<'a> {
}
#[doc = "Values that can be written to the field `PHAFLTREN`"]
pub enum PHAFLTRENW {
#[doc = "Phase A input filter is disabled."]
_0,
#[doc = "Phase A input filter is enabled."]
_1,
#[doc = "Phase A input filter is disabled."] _0,
#[doc = "Phase A input filter is enabled."] _1,
}
impl PHAFLTRENW {
#[allow(missing_docs)]

316
src/ftm1/sc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,22 +45,14 @@ impl super::SC {
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSR {
#[doc = "Divide by 1"]
_000,
#[doc = "Divide by 2"]
_001,
#[doc = "Divide by 4"]
_010,
#[doc = "Divide by 8"]
_011,
#[doc = "Divide by 16"]
_100,
#[doc = "Divide by 32"]
_101,
#[doc = "Divide by 64"]
_110,
#[doc = "Divide by 128"]
_111,
#[doc = "Divide by 1"] _000,
#[doc = "Divide by 2"] _001,
#[doc = "Divide by 4"] _010,
#[doc = "Divide by 8"] _011,
#[doc = "Divide by 16"] _100,
#[doc = "Divide by 32"] _101,
#[doc = "Divide by 64"] _110,
#[doc = "Divide by 128"] _111,
}
impl PSR {
#[doc = r" Value of the field as raw bits"]
@ -135,14 +129,10 @@ impl PSR {
#[doc = "Possible values of the field `CLKS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKSR {
#[doc = "No clock selected. This in effect disables the FTM counter."]
_00,
#[doc = "FTM input clock"]
_01,
#[doc = "Fixed frequency clock"]
_10,
#[doc = "External clock"]
_11,
#[doc = "No clock selected. This in effect disables the FTM counter."] _00,
#[doc = "FTM input clock"] _01,
#[doc = "Fixed frequency clock"] _10,
#[doc = "External clock"] _11,
}
impl CLKSR {
#[doc = r" Value of the field as raw bits"]
@ -191,10 +181,8 @@ impl CLKSR {
#[doc = "Possible values of the field `CPWMS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPWMSR {
#[doc = "FTM counter operates in Up Counting mode."]
_0,
#[doc = "FTM counter operates in Up-Down Counting mode."]
_1,
#[doc = "FTM counter operates in Up Counting mode."] _0,
#[doc = "FTM counter operates in Up-Down Counting mode."] _1,
}
impl CPWMSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -238,10 +226,8 @@ impl CPWMSR {
#[doc = "Possible values of the field `RIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RIER {
#[doc = "Reload point interrupt is disabled."]
_0,
#[doc = "Reload point interrupt is enabled."]
_1,
#[doc = "Reload point interrupt is disabled."] _0,
#[doc = "Reload point interrupt is enabled."] _1,
}
impl RIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -285,10 +271,8 @@ impl RIER {
#[doc = "Possible values of the field `RF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RFR {
#[doc = "A selected reload point did not happen."]
_0,
#[doc = "A selected reload point happened."]
_1,
#[doc = "A selected reload point did not happen."] _0,
#[doc = "A selected reload point happened."] _1,
}
impl RFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -332,10 +316,8 @@ impl RFR {
#[doc = "Possible values of the field `TOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TOIER {
#[doc = "Disable TOF interrupts. Use software polling."]
_0,
#[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."]
_1,
#[doc = "Disable TOF interrupts. Use software polling."] _0,
#[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1,
}
impl TOIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -379,10 +361,8 @@ impl TOIER {
#[doc = "Possible values of the field `TOF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TOFR {
#[doc = "FTM counter has not overflowed."]
_0,
#[doc = "FTM counter has overflowed."]
_1,
#[doc = "FTM counter has not overflowed."] _0,
#[doc = "FTM counter has overflowed."] _1,
}
impl TOFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -426,10 +406,8 @@ impl TOFR {
#[doc = "Possible values of the field `PWMEN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN0R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -473,10 +451,8 @@ impl PWMEN0R {
#[doc = "Possible values of the field `PWMEN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN1R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -520,10 +496,8 @@ impl PWMEN1R {
#[doc = "Possible values of the field `PWMEN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN2R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -567,10 +541,8 @@ impl PWMEN2R {
#[doc = "Possible values of the field `PWMEN3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN3R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -614,10 +586,8 @@ impl PWMEN3R {
#[doc = "Possible values of the field `PWMEN4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN4R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -661,10 +631,8 @@ impl PWMEN4R {
#[doc = "Possible values of the field `PWMEN5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN5R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -708,10 +676,8 @@ impl PWMEN5R {
#[doc = "Possible values of the field `PWMEN6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN6R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -755,10 +721,8 @@ impl PWMEN6R {
#[doc = "Possible values of the field `PWMEN7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMEN7R {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN7R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -802,38 +766,22 @@ impl PWMEN7R {
#[doc = "Possible values of the field `FLTPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLTPSR {
#[doc = "Divide by 1"]
_0000,
#[doc = "Divide by 2"]
_0001,
#[doc = "Divide by 3"]
_0010,
#[doc = "Divide by 4"]
_0011,
#[doc = "Divide by 5"]
_0100,
#[doc = "Divide by 6"]
_0101,
#[doc = "Divide by 7"]
_0110,
#[doc = "Divide by 8"]
_0111,
#[doc = "Divide by 9"]
_1000,
#[doc = "Divide by 10"]
_1001,
#[doc = "Divide by 11"]
_1010,
#[doc = "Divide by 12"]
_1011,
#[doc = "Divide by 13"]
_1100,
#[doc = "Divide by 14"]
_1101,
#[doc = "Divide by 15"]
_1110,
#[doc = "Divide by 16"]
_1111,
#[doc = "Divide by 1"] _0000,
#[doc = "Divide by 2"] _0001,
#[doc = "Divide by 3"] _0010,
#[doc = "Divide by 4"] _0011,
#[doc = "Divide by 5"] _0100,
#[doc = "Divide by 6"] _0101,
#[doc = "Divide by 7"] _0110,
#[doc = "Divide by 8"] _0111,
#[doc = "Divide by 9"] _1000,
#[doc = "Divide by 10"] _1001,
#[doc = "Divide by 11"] _1010,
#[doc = "Divide by 12"] _1011,
#[doc = "Divide by 13"] _1100,
#[doc = "Divide by 14"] _1101,
#[doc = "Divide by 15"] _1110,
#[doc = "Divide by 16"] _1111,
}
impl FLTPSR {
#[doc = r" Value of the field as raw bits"]
@ -965,22 +913,14 @@ impl FLTPSR {
}
#[doc = "Values that can be written to the field `PS`"]
pub enum PSW {
#[doc = "Divide by 1"]
_000,
#[doc = "Divide by 2"]
_001,
#[doc = "Divide by 4"]
_010,
#[doc = "Divide by 8"]
_011,
#[doc = "Divide by 16"]
_100,
#[doc = "Divide by 32"]
_101,
#[doc = "Divide by 64"]
_110,
#[doc = "Divide by 128"]
_111,
#[doc = "Divide by 1"] _000,
#[doc = "Divide by 2"] _001,
#[doc = "Divide by 4"] _010,
#[doc = "Divide by 8"] _011,
#[doc = "Divide by 16"] _100,
#[doc = "Divide by 32"] _101,
#[doc = "Divide by 64"] _110,
#[doc = "Divide by 128"] _111,
}
impl PSW {
#[allow(missing_docs)]
@ -1063,14 +1003,10 @@ impl<'a> _PSW<'a> {
}
#[doc = "Values that can be written to the field `CLKS`"]
pub enum CLKSW {
#[doc = "No clock selected. This in effect disables the FTM counter."]
_00,
#[doc = "FTM input clock"]
_01,
#[doc = "Fixed frequency clock"]
_10,
#[doc = "External clock"]
_11,
#[doc = "No clock selected. This in effect disables the FTM counter."] _00,
#[doc = "FTM input clock"] _01,
#[doc = "Fixed frequency clock"] _10,
#[doc = "External clock"] _11,
}
impl CLKSW {
#[allow(missing_docs)]
@ -1129,10 +1065,8 @@ impl<'a> _CLKSW<'a> {
}
#[doc = "Values that can be written to the field `CPWMS`"]
pub enum CPWMSW {
#[doc = "FTM counter operates in Up Counting mode."]
_0,
#[doc = "FTM counter operates in Up-Down Counting mode."]
_1,
#[doc = "FTM counter operates in Up Counting mode."] _0,
#[doc = "FTM counter operates in Up-Down Counting mode."] _1,
}
impl CPWMSW {
#[allow(missing_docs)]
@ -1187,10 +1121,8 @@ impl<'a> _CPWMSW<'a> {
}
#[doc = "Values that can be written to the field `RIE`"]
pub enum RIEW {
#[doc = "Reload point interrupt is disabled."]
_0,
#[doc = "Reload point interrupt is enabled."]
_1,
#[doc = "Reload point interrupt is disabled."] _0,
#[doc = "Reload point interrupt is enabled."] _1,
}
impl RIEW {
#[allow(missing_docs)]
@ -1245,10 +1177,8 @@ impl<'a> _RIEW<'a> {
}
#[doc = "Values that can be written to the field `TOIE`"]
pub enum TOIEW {
#[doc = "Disable TOF interrupts. Use software polling."]
_0,
#[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."]
_1,
#[doc = "Disable TOF interrupts. Use software polling."] _0,
#[doc = "Enable TOF interrupts. An interrupt is generated when TOF equals one."] _1,
}
impl TOIEW {
#[allow(missing_docs)]
@ -1303,10 +1233,8 @@ impl<'a> _TOIEW<'a> {
}
#[doc = "Values that can be written to the field `PWMEN0`"]
pub enum PWMEN0W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN0W {
#[allow(missing_docs)]
@ -1361,10 +1289,8 @@ impl<'a> _PWMEN0W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN1`"]
pub enum PWMEN1W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN1W {
#[allow(missing_docs)]
@ -1419,10 +1345,8 @@ impl<'a> _PWMEN1W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN2`"]
pub enum PWMEN2W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN2W {
#[allow(missing_docs)]
@ -1477,10 +1401,8 @@ impl<'a> _PWMEN2W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN3`"]
pub enum PWMEN3W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN3W {
#[allow(missing_docs)]
@ -1535,10 +1457,8 @@ impl<'a> _PWMEN3W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN4`"]
pub enum PWMEN4W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN4W {
#[allow(missing_docs)]
@ -1593,10 +1513,8 @@ impl<'a> _PWMEN4W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN5`"]
pub enum PWMEN5W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN5W {
#[allow(missing_docs)]
@ -1651,10 +1569,8 @@ impl<'a> _PWMEN5W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN6`"]
pub enum PWMEN6W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN6W {
#[allow(missing_docs)]
@ -1709,10 +1625,8 @@ impl<'a> _PWMEN6W<'a> {
}
#[doc = "Values that can be written to the field `PWMEN7`"]
pub enum PWMEN7W {
#[doc = "Channel output port is disabled"]
_0,
#[doc = "Channel output port is enabled"]
_1,
#[doc = "Channel output port is disabled"] _0,
#[doc = "Channel output port is enabled"] _1,
}
impl PWMEN7W {
#[allow(missing_docs)]
@ -1767,38 +1681,22 @@ impl<'a> _PWMEN7W<'a> {
}
#[doc = "Values that can be written to the field `FLTPS`"]
pub enum FLTPSW {
#[doc = "Divide by 1"]
_0000,
#[doc = "Divide by 2"]
_0001,
#[doc = "Divide by 3"]
_0010,
#[doc = "Divide by 4"]
_0011,
#[doc = "Divide by 5"]
_0100,
#[doc = "Divide by 6"]
_0101,
#[doc = "Divide by 7"]
_0110,
#[doc = "Divide by 8"]
_0111,
#[doc = "Divide by 9"]
_1000,
#[doc = "Divide by 10"]
_1001,
#[doc = "Divide by 11"]
_1010,
#[doc = "Divide by 12"]
_1011,
#[doc = "Divide by 13"]
_1100,
#[doc = "Divide by 14"]
_1101,
#[doc = "Divide by 15"]
_1110,
#[doc = "Divide by 16"]
_1111,
#[doc = "Divide by 1"] _0000,
#[doc = "Divide by 2"] _0001,
#[doc = "Divide by 3"] _0010,
#[doc = "Divide by 4"] _0011,
#[doc = "Divide by 5"] _0100,
#[doc = "Divide by 6"] _0101,
#[doc = "Divide by 7"] _0110,
#[doc = "Divide by 8"] _0111,
#[doc = "Divide by 9"] _1000,
#[doc = "Divide by 10"] _1001,
#[doc = "Divide by 11"] _1010,
#[doc = "Divide by 12"] _1011,
#[doc = "Divide by 13"] _1100,
#[doc = "Divide by 14"] _1101,
#[doc = "Divide by 15"] _1110,
#[doc = "Divide by 16"] _1111,
}
impl FLTPSW {
#[allow(missing_docs)]

52
src/ftm1/status/mod.rs
View File

@ -6,16 +6,16 @@ impl super::STATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `CH0F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH0FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -59,10 +59,8 @@ impl CH0FR {
#[doc = "Possible values of the field `CH1F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH1FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -106,10 +104,8 @@ impl CH1FR {
#[doc = "Possible values of the field `CH2F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH2FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -153,10 +149,8 @@ impl CH2FR {
#[doc = "Possible values of the field `CH3F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH3FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -200,10 +194,8 @@ impl CH3FR {
#[doc = "Possible values of the field `CH4F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH4FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -247,10 +239,8 @@ impl CH4FR {
#[doc = "Possible values of the field `CH5F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH5FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -294,10 +284,8 @@ impl CH5FR {
#[doc = "Possible values of the field `CH6F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH6FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -341,10 +329,8 @@ impl CH6FR {
#[doc = "Possible values of the field `CH7F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7FR {
#[doc = "No channel event has occurred."]
_0,
#[doc = "A channel event has occurred."]
_1,
#[doc = "No channel event has occurred."] _0,
#[doc = "A channel event has occurred."] _1,
}
impl CH7FR {
#[doc = r" Returns `true` if the bit is clear (0)"]

196
src/ftm1/swoctrl/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SWOCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SWOCTRL {
#[doc = "Possible values of the field `CH0OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH0OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CH0OCR {
#[doc = "Possible values of the field `CH1OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH1OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl CH1OCR {
#[doc = "Possible values of the field `CH2OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH2OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,10 +180,8 @@ impl CH2OCR {
#[doc = "Possible values of the field `CH3OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH3OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +225,8 @@ impl CH3OCR {
#[doc = "Possible values of the field `CH4OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH4OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +270,8 @@ impl CH4OCR {
#[doc = "Possible values of the field `CH5OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH5OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +315,8 @@ impl CH5OCR {
#[doc = "Possible values of the field `CH6OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH6OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +360,8 @@ impl CH6OCR {
#[doc = "Possible values of the field `CH7OC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7OCR {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH7OCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -419,10 +405,8 @@ impl CH7OCR {
#[doc = "Possible values of the field `CH0OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH0OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH0OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -466,10 +450,8 @@ impl CH0OCVR {
#[doc = "Possible values of the field `CH1OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH1OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH1OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -513,10 +495,8 @@ impl CH1OCVR {
#[doc = "Possible values of the field `CH2OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH2OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH2OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -560,10 +540,8 @@ impl CH2OCVR {
#[doc = "Possible values of the field `CH3OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH3OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH3OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -607,10 +585,8 @@ impl CH3OCVR {
#[doc = "Possible values of the field `CH4OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH4OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH4OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -654,10 +630,8 @@ impl CH4OCVR {
#[doc = "Possible values of the field `CH5OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH5OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH5OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -701,10 +675,8 @@ impl CH5OCVR {
#[doc = "Possible values of the field `CH6OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH6OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH6OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -748,10 +720,8 @@ impl CH6OCVR {
#[doc = "Possible values of the field `CH7OCV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CH7OCVR {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH7OCVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -794,10 +764,8 @@ impl CH7OCVR {
}
#[doc = "Values that can be written to the field `CH0OC`"]
pub enum CH0OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH0OCW {
#[allow(missing_docs)]
@ -852,10 +820,8 @@ impl<'a> _CH0OCW<'a> {
}
#[doc = "Values that can be written to the field `CH1OC`"]
pub enum CH1OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH1OCW {
#[allow(missing_docs)]
@ -910,10 +876,8 @@ impl<'a> _CH1OCW<'a> {
}
#[doc = "Values that can be written to the field `CH2OC`"]
pub enum CH2OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH2OCW {
#[allow(missing_docs)]
@ -968,10 +932,8 @@ impl<'a> _CH2OCW<'a> {
}
#[doc = "Values that can be written to the field `CH3OC`"]
pub enum CH3OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH3OCW {
#[allow(missing_docs)]
@ -1026,10 +988,8 @@ impl<'a> _CH3OCW<'a> {
}
#[doc = "Values that can be written to the field `CH4OC`"]
pub enum CH4OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH4OCW {
#[allow(missing_docs)]
@ -1084,10 +1044,8 @@ impl<'a> _CH4OCW<'a> {
}
#[doc = "Values that can be written to the field `CH5OC`"]
pub enum CH5OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH5OCW {
#[allow(missing_docs)]
@ -1142,10 +1100,8 @@ impl<'a> _CH5OCW<'a> {
}
#[doc = "Values that can be written to the field `CH6OC`"]
pub enum CH6OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH6OCW {
#[allow(missing_docs)]
@ -1200,10 +1156,8 @@ impl<'a> _CH6OCW<'a> {
}
#[doc = "Values that can be written to the field `CH7OC`"]
pub enum CH7OCW {
#[doc = "The channel output is not affected by software output control."]
_0,
#[doc = "The channel output is affected by software output control."]
_1,
#[doc = "The channel output is not affected by software output control."] _0,
#[doc = "The channel output is affected by software output control."] _1,
}
impl CH7OCW {
#[allow(missing_docs)]
@ -1258,10 +1212,8 @@ impl<'a> _CH7OCW<'a> {
}
#[doc = "Values that can be written to the field `CH0OCV`"]
pub enum CH0OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH0OCVW {
#[allow(missing_docs)]
@ -1316,10 +1268,8 @@ impl<'a> _CH0OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH1OCV`"]
pub enum CH1OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH1OCVW {
#[allow(missing_docs)]
@ -1374,10 +1324,8 @@ impl<'a> _CH1OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH2OCV`"]
pub enum CH2OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH2OCVW {
#[allow(missing_docs)]
@ -1432,10 +1380,8 @@ impl<'a> _CH2OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH3OCV`"]
pub enum CH3OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH3OCVW {
#[allow(missing_docs)]
@ -1490,10 +1436,8 @@ impl<'a> _CH3OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH4OCV`"]
pub enum CH4OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH4OCVW {
#[allow(missing_docs)]
@ -1548,10 +1492,8 @@ impl<'a> _CH4OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH5OCV`"]
pub enum CH5OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH5OCVW {
#[allow(missing_docs)]
@ -1606,10 +1548,8 @@ impl<'a> _CH5OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH6OCV`"]
pub enum CH6OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH6OCVW {
#[allow(missing_docs)]
@ -1664,10 +1604,8 @@ impl<'a> _CH6OCVW<'a> {
}
#[doc = "Values that can be written to the field `CH7OCV`"]
pub enum CH7OCVW {
#[doc = "The software output control forces 0 to the channel output."]
_0,
#[doc = "The software output control forces 1 to the channel output."]
_1,
#[doc = "The software output control forces 0 to the channel output."] _0,
#[doc = "The software output control forces 1 to the channel output."] _1,
}
impl CH7OCVW {
#[allow(missing_docs)]

82
src/ftm1/sync/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SYNC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::SYNC {
#[doc = "Possible values of the field `CNTMIN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNTMINR {
#[doc = "The minimum loading point is disabled."]
_0,
#[doc = "The minimum loading point is enabled."]
_1,
#[doc = "The minimum loading point is disabled."] _0,
#[doc = "The minimum loading point is enabled."] _1,
}
impl CNTMINR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl CNTMINR {
#[doc = "Possible values of the field `CNTMAX`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNTMAXR {
#[doc = "The maximum loading point is disabled."]
_0,
#[doc = "The maximum loading point is enabled."]
_1,
#[doc = "The maximum loading point is disabled."] _0,
#[doc = "The maximum loading point is enabled."] _1,
}
impl CNTMAXR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,8 +135,7 @@ impl CNTMAXR {
#[doc = "Possible values of the field `REINIT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REINITR {
#[doc = "FTM counter continues to count normally."]
_0,
#[doc = "FTM counter continues to count normally."] _0,
#[doc = "FTM counter is updated with its initial value when the selected trigger is detected."]
_1,
}
@ -231,10 +228,8 @@ impl SYNCHOMR {
#[doc = "Possible values of the field `TRIG0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIG0R {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +273,8 @@ impl TRIG0R {
#[doc = "Possible values of the field `TRIG1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIG1R {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +318,8 @@ impl TRIG1R {
#[doc = "Possible values of the field `TRIG2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIG2R {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +363,8 @@ impl TRIG2R {
#[doc = "Possible values of the field `SWSYNC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWSYNCR {
#[doc = "Software trigger is not selected."]
_0,
#[doc = "Software trigger is selected."]
_1,
#[doc = "Software trigger is not selected."] _0,
#[doc = "Software trigger is selected."] _1,
}
impl SWSYNCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -418,10 +407,8 @@ impl SWSYNCR {
}
#[doc = "Values that can be written to the field `CNTMIN`"]
pub enum CNTMINW {
#[doc = "The minimum loading point is disabled."]
_0,
#[doc = "The minimum loading point is enabled."]
_1,
#[doc = "The minimum loading point is disabled."] _0,
#[doc = "The minimum loading point is enabled."] _1,
}
impl CNTMINW {
#[allow(missing_docs)]
@ -476,10 +463,8 @@ impl<'a> _CNTMINW<'a> {
}
#[doc = "Values that can be written to the field `CNTMAX`"]
pub enum CNTMAXW {
#[doc = "The maximum loading point is disabled."]
_0,
#[doc = "The maximum loading point is enabled."]
_1,
#[doc = "The maximum loading point is disabled."] _0,
#[doc = "The maximum loading point is enabled."] _1,
}
impl CNTMAXW {
#[allow(missing_docs)]
@ -534,8 +519,7 @@ impl<'a> _CNTMAXW<'a> {
}
#[doc = "Values that can be written to the field `REINIT`"]
pub enum REINITW {
#[doc = "FTM counter continues to count normally."]
_0,
#[doc = "FTM counter continues to count normally."] _0,
#[doc = "FTM counter is updated with its initial value when the selected trigger is detected."]
_1,
}
@ -650,10 +634,8 @@ impl<'a> _SYNCHOMW<'a> {
}
#[doc = "Values that can be written to the field `TRIG0`"]
pub enum TRIG0W {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG0W {
#[allow(missing_docs)]
@ -708,10 +690,8 @@ impl<'a> _TRIG0W<'a> {
}
#[doc = "Values that can be written to the field `TRIG1`"]
pub enum TRIG1W {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG1W {
#[allow(missing_docs)]
@ -766,10 +746,8 @@ impl<'a> _TRIG1W<'a> {
}
#[doc = "Values that can be written to the field `TRIG2`"]
pub enum TRIG2W {
#[doc = "Trigger is disabled."]
_0,
#[doc = "Trigger is enabled."]
_1,
#[doc = "Trigger is disabled."] _0,
#[doc = "Trigger is enabled."] _1,
}
impl TRIG2W {
#[allow(missing_docs)]
@ -824,10 +802,8 @@ impl<'a> _TRIG2W<'a> {
}
#[doc = "Values that can be written to the field `SWSYNC`"]
pub enum SWSYNCW {
#[doc = "Software trigger is not selected."]
_0,
#[doc = "Software trigger is selected."]
_1,
#[doc = "Software trigger is not selected."] _0,
#[doc = "Software trigger is selected."] _1,
}
impl SWSYNCW {
#[allow(missing_docs)]

142
src/ftm1/synconf/mod.rs
View File

@ -22,7 +22,9 @@ impl super::SYNCONF {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -92,8 +94,7 @@ impl HWTRIGMODER {
pub enum CNTINCR {
#[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1,
}
impl CNTINCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -139,8 +140,7 @@ impl CNTINCR {
pub enum INVCR {
#[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1,
}
impl INVCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -186,8 +186,7 @@ impl INVCR {
pub enum SWOCR {
#[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1,
}
impl SWOCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -231,10 +230,8 @@ impl SWOCR {
#[doc = "Possible values of the field `SYNCMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCMODER {
#[doc = "Legacy PWM synchronization is selected."]
_0,
#[doc = "Enhanced PWM synchronization is selected."]
_1,
#[doc = "Legacy PWM synchronization is selected."] _0,
#[doc = "Enhanced PWM synchronization is selected."] _1,
}
impl SYNCMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +275,8 @@ impl SYNCMODER {
#[doc = "Possible values of the field `SWRSTCNT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWRSTCNTR {
#[doc = "The software trigger does not activate the FTM counter synchronization."]
_0,
#[doc = "The software trigger activates the FTM counter synchronization."]
_1,
#[doc = "The software trigger does not activate the FTM counter synchronization."] _0,
#[doc = "The software trigger activates the FTM counter synchronization."] _1,
}
impl SWRSTCNTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -327,8 +322,7 @@ impl SWRSTCNTR {
pub enum SWWRBUFR {
#[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
_0,
#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
_1,
#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
}
impl SWWRBUFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,10 +366,8 @@ impl SWWRBUFR {
#[doc = "Possible values of the field `SWOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWOMR {
#[doc = "The software trigger does not activate the OUTMASK register synchronization."]
_0,
#[doc = "The software trigger activates the OUTMASK register synchronization."]
_1,
#[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0,
#[doc = "The software trigger activates the OUTMASK register synchronization."] _1,
}
impl SWOMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -419,10 +411,8 @@ impl SWOMR {
#[doc = "Possible values of the field `SWINVC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWINVCR {
#[doc = "The software trigger does not activate the INVCTRL register synchronization."]
_0,
#[doc = "The software trigger activates the INVCTRL register synchronization."]
_1,
#[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0,
#[doc = "The software trigger activates the INVCTRL register synchronization."] _1,
}
impl SWINVCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -466,10 +456,8 @@ impl SWINVCR {
#[doc = "Possible values of the field `SWSOC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWSOCR {
#[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
_0,
#[doc = "The software trigger activates the SWOCTRL register synchronization."]
_1,
#[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0,
#[doc = "The software trigger activates the SWOCTRL register synchronization."] _1,
}
impl SWSOCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -513,10 +501,8 @@ impl SWSOCR {
#[doc = "Possible values of the field `HWRSTCNT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HWRSTCNTR {
#[doc = "A hardware trigger does not activate the FTM counter synchronization."]
_0,
#[doc = "A hardware trigger activates the FTM counter synchronization."]
_1,
#[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0,
#[doc = "A hardware trigger activates the FTM counter synchronization."] _1,
}
impl HWRSTCNTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -562,8 +548,7 @@ impl HWRSTCNTR {
pub enum HWWRBUFR {
#[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
_0,
#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
_1,
#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
}
impl HWWRBUFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -607,10 +592,8 @@ impl HWWRBUFR {
#[doc = "Possible values of the field `HWOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HWOMR {
#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
_0,
#[doc = "A hardware trigger activates the OUTMASK register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0,
#[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1,
}
impl HWOMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -654,10 +637,8 @@ impl HWOMR {
#[doc = "Possible values of the field `HWINVC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HWINVCR {
#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
_0,
#[doc = "A hardware trigger activates the INVCTRL register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0,
#[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1,
}
impl HWINVCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -701,10 +682,8 @@ impl HWINVCR {
#[doc = "Possible values of the field `HWSOC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HWSOCR {
#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
_0,
#[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0,
#[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1,
}
impl HWSOCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -807,8 +786,7 @@ impl<'a> _HWTRIGMODEW<'a> {
pub enum CNTINCW {
#[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."] _1,
}
impl CNTINCW {
#[allow(missing_docs)]
@ -865,8 +843,7 @@ impl<'a> _CNTINCW<'a> {
pub enum INVCW {
#[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."] _1,
}
impl INVCW {
#[allow(missing_docs)]
@ -923,8 +900,7 @@ impl<'a> _INVCW<'a> {
pub enum SWOCW {
#[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
_0,
#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
_1,
#[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."] _1,
}
impl SWOCW {
#[allow(missing_docs)]
@ -979,10 +955,8 @@ impl<'a> _SWOCW<'a> {
}
#[doc = "Values that can be written to the field `SYNCMODE`"]
pub enum SYNCMODEW {
#[doc = "Legacy PWM synchronization is selected."]
_0,
#[doc = "Enhanced PWM synchronization is selected."]
_1,
#[doc = "Legacy PWM synchronization is selected."] _0,
#[doc = "Enhanced PWM synchronization is selected."] _1,
}
impl SYNCMODEW {
#[allow(missing_docs)]
@ -1037,10 +1011,8 @@ impl<'a> _SYNCMODEW<'a> {
}
#[doc = "Values that can be written to the field `SWRSTCNT`"]
pub enum SWRSTCNTW {
#[doc = "The software trigger does not activate the FTM counter synchronization."]
_0,
#[doc = "The software trigger activates the FTM counter synchronization."]
_1,
#[doc = "The software trigger does not activate the FTM counter synchronization."] _0,
#[doc = "The software trigger activates the FTM counter synchronization."] _1,
}
impl SWRSTCNTW {
#[allow(missing_docs)]
@ -1097,8 +1069,7 @@ impl<'a> _SWRSTCNTW<'a> {
pub enum SWWRBUFW {
#[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
_0,
#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
_1,
#[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
}
impl SWWRBUFW {
#[allow(missing_docs)]
@ -1153,10 +1124,8 @@ impl<'a> _SWWRBUFW<'a> {
}
#[doc = "Values that can be written to the field `SWOM`"]
pub enum SWOMW {
#[doc = "The software trigger does not activate the OUTMASK register synchronization."]
_0,
#[doc = "The software trigger activates the OUTMASK register synchronization."]
_1,
#[doc = "The software trigger does not activate the OUTMASK register synchronization."] _0,
#[doc = "The software trigger activates the OUTMASK register synchronization."] _1,
}
impl SWOMW {
#[allow(missing_docs)]
@ -1211,10 +1180,8 @@ impl<'a> _SWOMW<'a> {
}
#[doc = "Values that can be written to the field `SWINVC`"]
pub enum SWINVCW {
#[doc = "The software trigger does not activate the INVCTRL register synchronization."]
_0,
#[doc = "The software trigger activates the INVCTRL register synchronization."]
_1,
#[doc = "The software trigger does not activate the INVCTRL register synchronization."] _0,
#[doc = "The software trigger activates the INVCTRL register synchronization."] _1,
}
impl SWINVCW {
#[allow(missing_docs)]
@ -1269,10 +1236,8 @@ impl<'a> _SWINVCW<'a> {
}
#[doc = "Values that can be written to the field `SWSOC`"]
pub enum SWSOCW {
#[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
_0,
#[doc = "The software trigger activates the SWOCTRL register synchronization."]
_1,
#[doc = "The software trigger does not activate the SWOCTRL register synchronization."] _0,
#[doc = "The software trigger activates the SWOCTRL register synchronization."] _1,
}
impl SWSOCW {
#[allow(missing_docs)]
@ -1327,10 +1292,8 @@ impl<'a> _SWSOCW<'a> {
}
#[doc = "Values that can be written to the field `HWRSTCNT`"]
pub enum HWRSTCNTW {
#[doc = "A hardware trigger does not activate the FTM counter synchronization."]
_0,
#[doc = "A hardware trigger activates the FTM counter synchronization."]
_1,
#[doc = "A hardware trigger does not activate the FTM counter synchronization."] _0,
#[doc = "A hardware trigger activates the FTM counter synchronization."] _1,
}
impl HWRSTCNTW {
#[allow(missing_docs)]
@ -1387,8 +1350,7 @@ impl<'a> _HWRSTCNTW<'a> {
pub enum HWWRBUFW {
#[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
_0,
#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
_1,
#[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."] _1,
}
impl HWWRBUFW {
#[allow(missing_docs)]
@ -1443,10 +1405,8 @@ impl<'a> _HWWRBUFW<'a> {
}
#[doc = "Values that can be written to the field `HWOM`"]
pub enum HWOMW {
#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
_0,
#[doc = "A hardware trigger activates the OUTMASK register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the OUTMASK register synchronization."] _0,
#[doc = "A hardware trigger activates the OUTMASK register synchronization."] _1,
}
impl HWOMW {
#[allow(missing_docs)]
@ -1501,10 +1461,8 @@ impl<'a> _HWOMW<'a> {
}
#[doc = "Values that can be written to the field `HWINVC`"]
pub enum HWINVCW {
#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
_0,
#[doc = "A hardware trigger activates the INVCTRL register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the INVCTRL register synchronization."] _0,
#[doc = "A hardware trigger activates the INVCTRL register synchronization."] _1,
}
impl HWINVCW {
#[allow(missing_docs)]
@ -1559,10 +1517,8 @@ impl<'a> _HWINVCW<'a> {
}
#[doc = "Values that can be written to the field `HWSOC`"]
pub enum HWSOCW {
#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
_0,
#[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
_1,
#[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."] _0,
#[doc = "A hardware trigger activates the SWOCTRL register synchronization."] _1,
}
impl HWSOCW {
#[allow(missing_docs)]