Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::CTRL {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,10 +45,8 @@ impl super::CTRL {
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#[doc = "Possible values of the field `FLEXEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FLEXENR {
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#[doc = "FlexIO module is disabled."]
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_0,
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#[doc = "FlexIO module is enabled."]
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_1,
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#[doc = "FlexIO module is disabled."] _0,
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#[doc = "FlexIO module is enabled."] _1,
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}
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impl FLEXENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -90,8 +90,7 @@ impl FLEXENR {
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#[doc = "Possible values of the field `SWRST`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWRSTR {
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#[doc = "Software reset is disabled"]
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_0,
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#[doc = "Software reset is disabled"] _0,
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#[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
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_1,
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}
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@ -137,10 +136,8 @@ impl SWRSTR {
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#[doc = "Possible values of the field `FASTACC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FASTACCR {
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#[doc = "Configures for normal register accesses to FlexIO"]
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_0,
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#[doc = "Configures for fast register accesses to FlexIO"]
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_1,
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#[doc = "Configures for normal register accesses to FlexIO"] _0,
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#[doc = "Configures for fast register accesses to FlexIO"] _1,
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}
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impl FASTACCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -184,10 +181,8 @@ impl FASTACCR {
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#[doc = "Possible values of the field `DBGE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DBGER {
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#[doc = "FlexIO is disabled in debug modes."]
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_0,
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#[doc = "FlexIO is enabled in debug modes"]
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_1,
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#[doc = "FlexIO is disabled in debug modes."] _0,
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#[doc = "FlexIO is enabled in debug modes"] _1,
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}
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impl DBGER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -231,10 +226,8 @@ impl DBGER {
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#[doc = "Possible values of the field `DOZEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DOZENR {
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#[doc = "FlexIO enabled in Doze modes."]
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_0,
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#[doc = "FlexIO disabled in Doze modes."]
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_1,
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#[doc = "FlexIO enabled in Doze modes."] _0,
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#[doc = "FlexIO disabled in Doze modes."] _1,
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}
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impl DOZENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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@ -277,10 +270,8 @@ impl DOZENR {
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}
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#[doc = "Values that can be written to the field `FLEXEN`"]
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pub enum FLEXENW {
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#[doc = "FlexIO module is disabled."]
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_0,
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#[doc = "FlexIO module is enabled."]
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_1,
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#[doc = "FlexIO module is disabled."] _0,
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#[doc = "FlexIO module is enabled."] _1,
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}
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impl FLEXENW {
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#[allow(missing_docs)]
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@ -335,8 +326,7 @@ impl<'a> _FLEXENW<'a> {
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}
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#[doc = "Values that can be written to the field `SWRST`"]
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pub enum SWRSTW {
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#[doc = "Software reset is disabled"]
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_0,
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#[doc = "Software reset is disabled"] _0,
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#[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
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_1,
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}
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@ -393,10 +383,8 @@ impl<'a> _SWRSTW<'a> {
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}
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#[doc = "Values that can be written to the field `FASTACC`"]
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pub enum FASTACCW {
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#[doc = "Configures for normal register accesses to FlexIO"]
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_0,
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#[doc = "Configures for fast register accesses to FlexIO"]
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_1,
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#[doc = "Configures for normal register accesses to FlexIO"] _0,
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#[doc = "Configures for fast register accesses to FlexIO"] _1,
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}
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impl FASTACCW {
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#[allow(missing_docs)]
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@ -451,10 +439,8 @@ impl<'a> _FASTACCW<'a> {
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}
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#[doc = "Values that can be written to the field `DBGE`"]
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pub enum DBGEW {
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#[doc = "FlexIO is disabled in debug modes."]
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_0,
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#[doc = "FlexIO is enabled in debug modes"]
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_1,
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#[doc = "FlexIO is disabled in debug modes."] _0,
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#[doc = "FlexIO is enabled in debug modes"] _1,
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}
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impl DBGEW {
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#[allow(missing_docs)]
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@ -509,10 +495,8 @@ impl<'a> _DBGEW<'a> {
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}
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#[doc = "Values that can be written to the field `DOZEN`"]
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pub enum DOZENW {
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#[doc = "FlexIO enabled in Doze modes."]
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_0,
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#[doc = "FlexIO disabled in Doze modes."]
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_1,
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#[doc = "FlexIO enabled in Doze modes."] _0,
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#[doc = "FlexIO disabled in Doze modes."] _1,
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}
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impl DOZENW {
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#[allow(missing_docs)]
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@ -2,111 +2,64 @@ use vcell::VolatileCell;
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - Version ID Register"]
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pub verid: VERID,
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#[doc = "0x04 - Parameter Register"]
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pub param: PARAM,
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#[doc = "0x08 - FlexIO Control Register"]
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pub ctrl: CTRL,
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#[doc = "0x0c - Pin State Register"]
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pub pin: PIN,
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#[doc = "0x10 - Shifter Status Register"]
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pub shiftstat: SHIFTSTAT,
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#[doc = "0x14 - Shifter Error Register"]
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pub shifterr: SHIFTERR,
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#[doc = "0x18 - Timer Status Register"]
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pub timstat: TIMSTAT,
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#[doc = "0x00 - Version ID Register"] pub verid: VERID,
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#[doc = "0x04 - Parameter Register"] pub param: PARAM,
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#[doc = "0x08 - FlexIO Control Register"] pub ctrl: CTRL,
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#[doc = "0x0c - Pin State Register"] pub pin: PIN,
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#[doc = "0x10 - Shifter Status Register"] pub shiftstat: SHIFTSTAT,
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#[doc = "0x14 - Shifter Error Register"] pub shifterr: SHIFTERR,
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#[doc = "0x18 - Timer Status Register"] pub timstat: TIMSTAT,
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_reserved0: [u8; 4usize],
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#[doc = "0x20 - Shifter Status Interrupt Enable"]
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pub shiftsien: SHIFTSIEN,
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#[doc = "0x24 - Shifter Error Interrupt Enable"]
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pub shifteien: SHIFTEIEN,
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#[doc = "0x28 - Timer Interrupt Enable Register"]
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pub timien: TIMIEN,
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#[doc = "0x20 - Shifter Status Interrupt Enable"] pub shiftsien: SHIFTSIEN,
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#[doc = "0x24 - Shifter Error Interrupt Enable"] pub shifteien: SHIFTEIEN,
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#[doc = "0x28 - Timer Interrupt Enable Register"] pub timien: TIMIEN,
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_reserved1: [u8; 4usize],
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#[doc = "0x30 - Shifter Status DMA Enable"]
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pub shiftsden: SHIFTSDEN,
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#[doc = "0x30 - Shifter Status DMA Enable"] pub shiftsden: SHIFTSDEN,
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_reserved2: [u8; 76usize],
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#[doc = "0x80 - Shifter Control N Register"]
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pub shiftctl0: SHIFTCTL0,
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#[doc = "0x84 - Shifter Control N Register"]
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pub shiftctl1: SHIFTCTL1,
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#[doc = "0x88 - Shifter Control N Register"]
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pub shiftctl2: SHIFTCTL2,
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#[doc = "0x8c - Shifter Control N Register"]
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pub shiftctl3: SHIFTCTL3,
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#[doc = "0x80 - Shifter Control N Register"] pub shiftctl0: SHIFTCTL0,
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#[doc = "0x84 - Shifter Control N Register"] pub shiftctl1: SHIFTCTL1,
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#[doc = "0x88 - Shifter Control N Register"] pub shiftctl2: SHIFTCTL2,
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#[doc = "0x8c - Shifter Control N Register"] pub shiftctl3: SHIFTCTL3,
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_reserved3: [u8; 112usize],
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#[doc = "0x100 - Shifter Configuration N Register"]
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pub shiftcfg0: SHIFTCFG0,
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#[doc = "0x104 - Shifter Configuration N Register"]
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pub shiftcfg1: SHIFTCFG1,
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#[doc = "0x108 - Shifter Configuration N Register"]
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pub shiftcfg2: SHIFTCFG2,
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#[doc = "0x10c - Shifter Configuration N Register"]
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pub shiftcfg3: SHIFTCFG3,
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#[doc = "0x100 - Shifter Configuration N Register"] pub shiftcfg0: SHIFTCFG0,
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#[doc = "0x104 - Shifter Configuration N Register"] pub shiftcfg1: SHIFTCFG1,
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#[doc = "0x108 - Shifter Configuration N Register"] pub shiftcfg2: SHIFTCFG2,
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#[doc = "0x10c - Shifter Configuration N Register"] pub shiftcfg3: SHIFTCFG3,
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_reserved4: [u8; 240usize],
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#[doc = "0x200 - Shifter Buffer N Register"]
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pub shiftbuf0: SHIFTBUF0,
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#[doc = "0x204 - Shifter Buffer N Register"]
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pub shiftbuf1: SHIFTBUF1,
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#[doc = "0x208 - Shifter Buffer N Register"]
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pub shiftbuf2: SHIFTBUF2,
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#[doc = "0x20c - Shifter Buffer N Register"]
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pub shiftbuf3: SHIFTBUF3,
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#[doc = "0x200 - Shifter Buffer N Register"] pub shiftbuf0: SHIFTBUF0,
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#[doc = "0x204 - Shifter Buffer N Register"] pub shiftbuf1: SHIFTBUF1,
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#[doc = "0x208 - Shifter Buffer N Register"] pub shiftbuf2: SHIFTBUF2,
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#[doc = "0x20c - Shifter Buffer N Register"] pub shiftbuf3: SHIFTBUF3,
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_reserved5: [u8; 112usize],
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#[doc = "0x280 - Shifter Buffer N Bit Swapped Register"]
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pub shiftbufbis0: SHIFTBUFBIS0,
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#[doc = "0x284 - Shifter Buffer N Bit Swapped Register"]
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pub shiftbufbis1: SHIFTBUFBIS1,
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#[doc = "0x288 - Shifter Buffer N Bit Swapped Register"]
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pub shiftbufbis2: SHIFTBUFBIS2,
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#[doc = "0x28c - Shifter Buffer N Bit Swapped Register"]
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pub shiftbufbis3: SHIFTBUFBIS3,
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#[doc = "0x280 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis0: SHIFTBUFBIS0,
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#[doc = "0x284 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis1: SHIFTBUFBIS1,
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#[doc = "0x288 - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis2: SHIFTBUFBIS2,
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#[doc = "0x28c - Shifter Buffer N Bit Swapped Register"] pub shiftbufbis3: SHIFTBUFBIS3,
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_reserved6: [u8; 112usize],
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#[doc = "0x300 - Shifter Buffer N Byte Swapped Register"]
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pub shiftbufbys0: SHIFTBUFBYS0,
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#[doc = "0x304 - Shifter Buffer N Byte Swapped Register"]
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pub shiftbufbys1: SHIFTBUFBYS1,
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#[doc = "0x308 - Shifter Buffer N Byte Swapped Register"]
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pub shiftbufbys2: SHIFTBUFBYS2,
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#[doc = "0x30c - Shifter Buffer N Byte Swapped Register"]
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pub shiftbufbys3: SHIFTBUFBYS3,
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#[doc = "0x300 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys0: SHIFTBUFBYS0,
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#[doc = "0x304 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys1: SHIFTBUFBYS1,
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#[doc = "0x308 - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys2: SHIFTBUFBYS2,
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#[doc = "0x30c - Shifter Buffer N Byte Swapped Register"] pub shiftbufbys3: SHIFTBUFBYS3,
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_reserved7: [u8; 112usize],
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#[doc = "0x380 - Shifter Buffer N Bit Byte Swapped Register"]
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pub shiftbufbbs0: SHIFTBUFBBS0,
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#[doc = "0x384 - Shifter Buffer N Bit Byte Swapped Register"]
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pub shiftbufbbs1: SHIFTBUFBBS1,
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#[doc = "0x388 - Shifter Buffer N Bit Byte Swapped Register"]
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pub shiftbufbbs2: SHIFTBUFBBS2,
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#[doc = "0x38c - Shifter Buffer N Bit Byte Swapped Register"]
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pub shiftbufbbs3: SHIFTBUFBBS3,
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#[doc = "0x380 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs0: SHIFTBUFBBS0,
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#[doc = "0x384 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs1: SHIFTBUFBBS1,
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#[doc = "0x388 - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs2: SHIFTBUFBBS2,
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#[doc = "0x38c - Shifter Buffer N Bit Byte Swapped Register"] pub shiftbufbbs3: SHIFTBUFBBS3,
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_reserved8: [u8; 112usize],
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#[doc = "0x400 - Timer Control N Register"]
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pub timctl0: TIMCTL0,
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#[doc = "0x404 - Timer Control N Register"]
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pub timctl1: TIMCTL1,
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#[doc = "0x408 - Timer Control N Register"]
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pub timctl2: TIMCTL2,
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#[doc = "0x40c - Timer Control N Register"]
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pub timctl3: TIMCTL3,
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#[doc = "0x400 - Timer Control N Register"] pub timctl0: TIMCTL0,
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#[doc = "0x404 - Timer Control N Register"] pub timctl1: TIMCTL1,
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#[doc = "0x408 - Timer Control N Register"] pub timctl2: TIMCTL2,
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#[doc = "0x40c - Timer Control N Register"] pub timctl3: TIMCTL3,
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_reserved9: [u8; 112usize],
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#[doc = "0x480 - Timer Configuration N Register"]
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pub timcfg0: TIMCFG0,
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#[doc = "0x484 - Timer Configuration N Register"]
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pub timcfg1: TIMCFG1,
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#[doc = "0x488 - Timer Configuration N Register"]
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pub timcfg2: TIMCFG2,
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#[doc = "0x48c - Timer Configuration N Register"]
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pub timcfg3: TIMCFG3,
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#[doc = "0x480 - Timer Configuration N Register"] pub timcfg0: TIMCFG0,
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#[doc = "0x484 - Timer Configuration N Register"] pub timcfg1: TIMCFG1,
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#[doc = "0x488 - Timer Configuration N Register"] pub timcfg2: TIMCFG2,
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#[doc = "0x48c - Timer Configuration N Register"] pub timcfg3: TIMCFG3,
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_reserved10: [u8; 112usize],
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#[doc = "0x500 - Timer Compare N Register"]
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pub timcmp0: TIMCMP0,
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#[doc = "0x504 - Timer Compare N Register"]
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pub timcmp1: TIMCMP1,
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#[doc = "0x508 - Timer Compare N Register"]
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pub timcmp2: TIMCMP2,
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#[doc = "0x50c - Timer Compare N Register"]
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pub timcmp3: TIMCMP3,
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#[doc = "0x500 - Timer Compare N Register"] pub timcmp0: TIMCMP0,
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#[doc = "0x504 - Timer Compare N Register"] pub timcmp1: TIMCMP1,
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#[doc = "0x508 - Timer Compare N Register"] pub timcmp2: TIMCMP2,
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#[doc = "0x50c - Timer Compare N Register"] pub timcmp3: TIMCMP3,
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}
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#[doc = "Version ID Register"]
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pub struct VERID {
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@ -6,7 +6,9 @@ impl super::PARAM {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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}
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#[doc = r" Value of the field"]
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@ -6,7 +6,9 @@ impl super::PIN {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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}
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#[doc = r" Value of the field"]
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@ -22,7 +22,9 @@ impl super::SHIFTBUF0 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::SHIFTBUF1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::SHIFTBUF2 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::SHIFTBUF3 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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||||
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@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
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#[inline]
|
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pub fn read(&self) -> R {
|
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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||||
#[doc = r" Writes to the register"]
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||||
#[inline]
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||||
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||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
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||||
}
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||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBBS3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBIS3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTBUFBYS3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCFG0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -99,10 +101,8 @@ impl SSTARTR {
|
||||
#[doc = "Possible values of the field `SSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SSTOPR {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -155,10 +155,8 @@ impl SSTOPR {
|
||||
#[doc = "Possible values of the field `INSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INSRCR {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SSTOP`"]
|
||||
pub enum SSTOPW {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INSRC`"]
|
||||
pub enum INSRCW {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCFG1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -99,10 +101,8 @@ impl SSTARTR {
|
||||
#[doc = "Possible values of the field `SSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SSTOPR {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -155,10 +155,8 @@ impl SSTOPR {
|
||||
#[doc = "Possible values of the field `INSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INSRCR {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SSTOP`"]
|
||||
pub enum SSTOPW {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INSRC`"]
|
||||
pub enum INSRCW {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCFG2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -99,10 +101,8 @@ impl SSTARTR {
|
||||
#[doc = "Possible values of the field `SSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SSTOPR {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -155,10 +155,8 @@ impl SSTOPR {
|
||||
#[doc = "Possible values of the field `INSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INSRCR {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SSTOP`"]
|
||||
pub enum SSTOPW {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INSRC`"]
|
||||
pub enum INSRCW {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCFG3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -99,10 +101,8 @@ impl SSTARTR {
|
||||
#[doc = "Possible values of the field `SSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SSTOPR {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -155,10 +155,8 @@ impl SSTOPR {
|
||||
#[doc = "Possible values of the field `INSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INSRCR {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -267,10 +265,8 @@ impl<'a> _SSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SSTOP`"]
|
||||
pub enum SSTOPW {
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"]
|
||||
_0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"]
|
||||
_1,
|
||||
#[doc = "Stop bit disabled for transmitter/receiver/match store"] _0,
|
||||
#[doc = "Reserved for transmitter/receiver/match store"] _1,
|
||||
#[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
|
||||
_10,
|
||||
#[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
|
||||
@ -333,10 +329,8 @@ impl<'a> _SSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INSRC`"]
|
||||
pub enum INSRCW {
|
||||
#[doc = "Pin"]
|
||||
_0,
|
||||
#[doc = "Shifter N+1 Output"]
|
||||
_1,
|
||||
#[doc = "Pin"] _0,
|
||||
#[doc = "Shifter N+1 Output"] _1,
|
||||
}
|
||||
impl INSRCW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCTL0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,8 +45,7 @@ impl super::SHIFTCTL0 {
|
||||
#[doc = "Possible values of the field `SMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SMODR {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -53,8 +54,7 @@ pub enum SMODR {
|
||||
_100,
|
||||
#[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
|
||||
_101,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl SMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -111,10 +111,8 @@ impl SMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -169,14 +167,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -225,10 +219,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TIMPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMPOLR {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -282,8 +274,7 @@ impl TIMSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SMOD`"]
|
||||
pub enum SMODW {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMPOL`"]
|
||||
pub enum TIMPOLW {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCTL1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,8 +45,7 @@ impl super::SHIFTCTL1 {
|
||||
#[doc = "Possible values of the field `SMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SMODR {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -53,8 +54,7 @@ pub enum SMODR {
|
||||
_100,
|
||||
#[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
|
||||
_101,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl SMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -111,10 +111,8 @@ impl SMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -169,14 +167,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -225,10 +219,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TIMPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMPOLR {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -282,8 +274,7 @@ impl TIMSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SMOD`"]
|
||||
pub enum SMODW {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMPOL`"]
|
||||
pub enum TIMPOLW {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCTL2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,8 +45,7 @@ impl super::SHIFTCTL2 {
|
||||
#[doc = "Possible values of the field `SMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SMODR {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -53,8 +54,7 @@ pub enum SMODR {
|
||||
_100,
|
||||
#[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
|
||||
_101,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl SMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -111,10 +111,8 @@ impl SMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -169,14 +167,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -225,10 +219,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TIMPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMPOLR {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -282,8 +274,7 @@ impl TIMSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SMOD`"]
|
||||
pub enum SMODW {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMPOL`"]
|
||||
pub enum TIMPOLW {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTCTL3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,8 +45,7 @@ impl super::SHIFTCTL3 {
|
||||
#[doc = "Possible values of the field `SMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SMODR {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -53,8 +54,7 @@ pub enum SMODR {
|
||||
_100,
|
||||
#[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
|
||||
_101,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl SMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -111,10 +111,8 @@ impl SMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -169,14 +167,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -225,10 +219,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TIMPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMPOLR {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -282,8 +274,7 @@ impl TIMSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SMOD`"]
|
||||
pub enum SMODW {
|
||||
#[doc = "Disabled."]
|
||||
_0,
|
||||
#[doc = "Disabled."] _0,
|
||||
#[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
|
||||
_1,
|
||||
#[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
|
||||
@ -354,10 +345,8 @@ impl<'a> _SMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -427,14 +416,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Shifter pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Shifter pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Shifter pin output"]
|
||||
_11,
|
||||
#[doc = "Shifter pin output disabled"] _0,
|
||||
#[doc = "Shifter pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Shifter pin bidirectional output data"] _10,
|
||||
#[doc = "Shifter pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -493,10 +478,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMPOL`"]
|
||||
pub enum TIMPOLW {
|
||||
#[doc = "Shift on posedge of Shift clock"]
|
||||
_0,
|
||||
#[doc = "Shift on negedge of Shift clock"]
|
||||
_1,
|
||||
#[doc = "Shift on posedge of Shift clock"] _0,
|
||||
#[doc = "Shift on negedge of Shift clock"] _1,
|
||||
}
|
||||
impl TIMPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTEIEN {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTERR {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTSDEN {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTSIEN {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SHIFTSTAT {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCFG0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::TIMCFG0 {
|
||||
#[doc = "Possible values of the field `TSTART`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTARTR {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,14 +90,10 @@ impl TSTARTR {
|
||||
#[doc = "Possible values of the field `TSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTOPR {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -146,22 +142,14 @@ impl TSTOPR {
|
||||
#[doc = "Possible values of the field `TIMENA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMENAR {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,22 +226,14 @@ impl TIMENAR {
|
||||
#[doc = "Possible values of the field `TIMDIS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDISR {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMDISR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -324,20 +304,13 @@ impl TIMDISR {
|
||||
#[doc = "Possible values of the field `TIMRST`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMRSTR {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMRSTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -401,12 +374,9 @@ impl TIMRSTR {
|
||||
#[doc = "Possible values of the field `TIMDEC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDECR {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -457,14 +427,10 @@ impl TIMDECR {
|
||||
#[doc = "Possible values of the field `TIMOUT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMOUTR {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -512,10 +478,8 @@ impl TIMOUTR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTART`"]
|
||||
pub enum TSTARTW {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTOP`"]
|
||||
pub enum TSTOPW {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPW {
|
||||
#[allow(missing_docs)]
|
||||
@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMENA`"]
|
||||
pub enum TIMENAW {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDIS`"]
|
||||
pub enum TIMDISW {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
}
|
||||
impl TIMDISW {
|
||||
#[allow(missing_docs)]
|
||||
@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMRST`"]
|
||||
pub enum TIMRSTW {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMRSTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDEC`"]
|
||||
pub enum TIMDECW {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOUT`"]
|
||||
pub enum TIMOUTW {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCFG1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::TIMCFG1 {
|
||||
#[doc = "Possible values of the field `TSTART`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTARTR {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,14 +90,10 @@ impl TSTARTR {
|
||||
#[doc = "Possible values of the field `TSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTOPR {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -146,22 +142,14 @@ impl TSTOPR {
|
||||
#[doc = "Possible values of the field `TIMENA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMENAR {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,22 +226,14 @@ impl TIMENAR {
|
||||
#[doc = "Possible values of the field `TIMDIS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDISR {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMDISR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -324,20 +304,13 @@ impl TIMDISR {
|
||||
#[doc = "Possible values of the field `TIMRST`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMRSTR {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMRSTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -401,12 +374,9 @@ impl TIMRSTR {
|
||||
#[doc = "Possible values of the field `TIMDEC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDECR {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -457,14 +427,10 @@ impl TIMDECR {
|
||||
#[doc = "Possible values of the field `TIMOUT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMOUTR {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -512,10 +478,8 @@ impl TIMOUTR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTART`"]
|
||||
pub enum TSTARTW {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTOP`"]
|
||||
pub enum TSTOPW {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPW {
|
||||
#[allow(missing_docs)]
|
||||
@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMENA`"]
|
||||
pub enum TIMENAW {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDIS`"]
|
||||
pub enum TIMDISW {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
}
|
||||
impl TIMDISW {
|
||||
#[allow(missing_docs)]
|
||||
@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMRST`"]
|
||||
pub enum TIMRSTW {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMRSTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDEC`"]
|
||||
pub enum TIMDECW {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOUT`"]
|
||||
pub enum TIMOUTW {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCFG2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::TIMCFG2 {
|
||||
#[doc = "Possible values of the field `TSTART`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTARTR {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,14 +90,10 @@ impl TSTARTR {
|
||||
#[doc = "Possible values of the field `TSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTOPR {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -146,22 +142,14 @@ impl TSTOPR {
|
||||
#[doc = "Possible values of the field `TIMENA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMENAR {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,22 +226,14 @@ impl TIMENAR {
|
||||
#[doc = "Possible values of the field `TIMDIS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDISR {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMDISR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -324,20 +304,13 @@ impl TIMDISR {
|
||||
#[doc = "Possible values of the field `TIMRST`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMRSTR {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMRSTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -401,12 +374,9 @@ impl TIMRSTR {
|
||||
#[doc = "Possible values of the field `TIMDEC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDECR {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -457,14 +427,10 @@ impl TIMDECR {
|
||||
#[doc = "Possible values of the field `TIMOUT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMOUTR {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -512,10 +478,8 @@ impl TIMOUTR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTART`"]
|
||||
pub enum TSTARTW {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTOP`"]
|
||||
pub enum TSTOPW {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPW {
|
||||
#[allow(missing_docs)]
|
||||
@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMENA`"]
|
||||
pub enum TIMENAW {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDIS`"]
|
||||
pub enum TIMDISW {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
}
|
||||
impl TIMDISW {
|
||||
#[allow(missing_docs)]
|
||||
@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMRST`"]
|
||||
pub enum TIMRSTW {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMRSTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDEC`"]
|
||||
pub enum TIMDECW {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOUT`"]
|
||||
pub enum TIMOUTW {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCFG3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,10 +45,8 @@ impl super::TIMCFG3 {
|
||||
#[doc = "Possible values of the field `TSTART`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTARTR {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -90,14 +90,10 @@ impl TSTARTR {
|
||||
#[doc = "Possible values of the field `TSTOP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TSTOPR {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -146,22 +142,14 @@ impl TSTOPR {
|
||||
#[doc = "Possible values of the field `TIMENA`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMENAR {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,22 +226,14 @@ impl TIMENAR {
|
||||
#[doc = "Possible values of the field `TIMDIS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDISR {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMDISR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -324,20 +304,13 @@ impl TIMDISR {
|
||||
#[doc = "Possible values of the field `TIMRST`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMRSTR {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TIMRSTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -401,12 +374,9 @@ impl TIMRSTR {
|
||||
#[doc = "Possible values of the field `TIMDEC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMDECR {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -457,14 +427,10 @@ impl TIMDECR {
|
||||
#[doc = "Possible values of the field `TIMOUT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMOUTR {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -512,10 +478,8 @@ impl TIMOUTR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTART`"]
|
||||
pub enum TSTARTW {
|
||||
#[doc = "Start bit disabled"]
|
||||
_0,
|
||||
#[doc = "Start bit enabled"]
|
||||
_1,
|
||||
#[doc = "Start bit disabled"] _0,
|
||||
#[doc = "Start bit enabled"] _1,
|
||||
}
|
||||
impl TSTARTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -570,14 +534,10 @@ impl<'a> _TSTARTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TSTOP`"]
|
||||
pub enum TSTOPW {
|
||||
#[doc = "Stop bit disabled"]
|
||||
_0,
|
||||
#[doc = "Stop bit is enabled on timer compare"]
|
||||
_1,
|
||||
#[doc = "Stop bit is enabled on timer disable"]
|
||||
_10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"]
|
||||
_11,
|
||||
#[doc = "Stop bit disabled"] _0,
|
||||
#[doc = "Stop bit is enabled on timer compare"] _1,
|
||||
#[doc = "Stop bit is enabled on timer disable"] _10,
|
||||
#[doc = "Stop bit is enabled on timer compare and timer disable"] _11,
|
||||
}
|
||||
impl TSTOPW {
|
||||
#[allow(missing_docs)]
|
||||
@ -636,22 +596,14 @@ impl<'a> _TSTOPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMENA`"]
|
||||
pub enum TIMENAW {
|
||||
#[doc = "Timer always enabled"]
|
||||
_0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"]
|
||||
_1,
|
||||
#[doc = "Timer enabled on Trigger high"]
|
||||
_10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"]
|
||||
_11,
|
||||
#[doc = "Timer enabled on Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"]
|
||||
_101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer always enabled"] _0,
|
||||
#[doc = "Timer enabled on Timer N-1 enable"] _1,
|
||||
#[doc = "Timer enabled on Trigger high"] _10,
|
||||
#[doc = "Timer enabled on Trigger high and Pin high"] _11,
|
||||
#[doc = "Timer enabled on Pin rising edge"] _100,
|
||||
#[doc = "Timer enabled on Pin rising edge and Trigger high"] _101,
|
||||
#[doc = "Timer enabled on Trigger rising edge"] _110,
|
||||
#[doc = "Timer enabled on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMENAW {
|
||||
#[allow(missing_docs)]
|
||||
@ -734,20 +686,13 @@ impl<'a> _TIMENAW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDIS`"]
|
||||
pub enum TIMDISW {
|
||||
#[doc = "Timer never disabled"]
|
||||
_0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"]
|
||||
_1,
|
||||
#[doc = "Timer disabled on Timer compare"]
|
||||
_10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"]
|
||||
_11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"]
|
||||
_100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
|
||||
_101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"]
|
||||
_110,
|
||||
#[doc = "Timer never disabled"] _0,
|
||||
#[doc = "Timer disabled on Timer N-1 disable"] _1,
|
||||
#[doc = "Timer disabled on Timer compare"] _10,
|
||||
#[doc = "Timer disabled on Timer compare and Trigger Low"] _11,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge"] _100,
|
||||
#[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"] _101,
|
||||
#[doc = "Timer disabled on Trigger falling edge"] _110,
|
||||
}
|
||||
impl TIMDISW {
|
||||
#[allow(missing_docs)]
|
||||
@ -822,18 +767,12 @@ impl<'a> _TIMDISW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMRST`"]
|
||||
pub enum TIMRSTW {
|
||||
#[doc = "Timer never reset"]
|
||||
_0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"]
|
||||
_10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"]
|
||||
_11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"]
|
||||
_100,
|
||||
#[doc = "Timer reset on Trigger rising edge"]
|
||||
_110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"]
|
||||
_111,
|
||||
#[doc = "Timer never reset"] _0,
|
||||
#[doc = "Timer reset on Timer Pin equal to Timer Output"] _10,
|
||||
#[doc = "Timer reset on Timer Trigger equal to Timer Output"] _11,
|
||||
#[doc = "Timer reset on Timer Pin rising edge"] _100,
|
||||
#[doc = "Timer reset on Trigger rising edge"] _110,
|
||||
#[doc = "Timer reset on Trigger rising or falling edge"] _111,
|
||||
}
|
||||
impl TIMRSTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -902,12 +841,9 @@ impl<'a> _TIMRSTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMDEC`"]
|
||||
pub enum TIMDECW {
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
|
||||
_0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
|
||||
_1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
|
||||
_10,
|
||||
#[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."] _0,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."] _1,
|
||||
#[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."] _10,
|
||||
#[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
|
||||
_11,
|
||||
}
|
||||
@ -968,14 +904,10 @@ impl<'a> _TIMDECW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOUT`"]
|
||||
pub enum TIMOUTW {
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
|
||||
_0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
|
||||
_1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"]
|
||||
_10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"]
|
||||
_11,
|
||||
#[doc = "Timer output is logic one when enabled and is not affected by timer reset"] _0,
|
||||
#[doc = "Timer output is logic zero when enabled and is not affected by timer reset"] _1,
|
||||
#[doc = "Timer output is logic one when enabled and on timer reset"] _10,
|
||||
#[doc = "Timer output is logic zero when enabled and on timer reset"] _11,
|
||||
}
|
||||
impl TIMOUTW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCMP0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCMP1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCMP2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCMP3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCTL0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::TIMCTL0 {
|
||||
#[doc = "Possible values of the field `TIMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMODR {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl TIMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -157,14 +153,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -213,10 +205,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TRGSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSRCR {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -260,10 +250,8 @@ impl TRGSRCR {
|
||||
#[doc = "Possible values of the field `TRGPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGPOLR {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -317,14 +305,10 @@ impl TRGSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOD`"]
|
||||
pub enum TIMODW {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODW {
|
||||
#[allow(missing_docs)]
|
||||
@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGSRC`"]
|
||||
pub enum TRGSRCW {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCW {
|
||||
#[allow(missing_docs)]
|
||||
@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGPOL`"]
|
||||
pub enum TRGPOLW {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCTL1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::TIMCTL1 {
|
||||
#[doc = "Possible values of the field `TIMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMODR {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl TIMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -157,14 +153,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -213,10 +205,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TRGSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSRCR {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -260,10 +250,8 @@ impl TRGSRCR {
|
||||
#[doc = "Possible values of the field `TRGPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGPOLR {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -317,14 +305,10 @@ impl TRGSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOD`"]
|
||||
pub enum TIMODW {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODW {
|
||||
#[allow(missing_docs)]
|
||||
@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGSRC`"]
|
||||
pub enum TRGSRCW {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCW {
|
||||
#[allow(missing_docs)]
|
||||
@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGPOL`"]
|
||||
pub enum TRGPOLW {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCTL2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::TIMCTL2 {
|
||||
#[doc = "Possible values of the field `TIMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMODR {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl TIMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -157,14 +153,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -213,10 +205,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TRGSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSRCR {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -260,10 +250,8 @@ impl TRGSRCR {
|
||||
#[doc = "Possible values of the field `TRGPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGPOLR {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -317,14 +305,10 @@ impl TRGSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOD`"]
|
||||
pub enum TIMODW {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODW {
|
||||
#[allow(missing_docs)]
|
||||
@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGSRC`"]
|
||||
pub enum TRGSRCW {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCW {
|
||||
#[allow(missing_docs)]
|
||||
@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGPOL`"]
|
||||
pub enum TRGPOLW {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMCTL3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::TIMCTL3 {
|
||||
#[doc = "Possible values of the field `TIMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TIMODR {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl TIMODR {
|
||||
#[doc = "Possible values of the field `PINPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINPOLR {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -157,14 +153,10 @@ impl PINSELR {
|
||||
#[doc = "Possible values of the field `PINCFG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PINCFGR {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -213,10 +205,8 @@ impl PINCFGR {
|
||||
#[doc = "Possible values of the field `TRGSRC`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSRCR {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -260,10 +250,8 @@ impl TRGSRCR {
|
||||
#[doc = "Possible values of the field `TRGPOL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGPOLR {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -317,14 +305,10 @@ impl TRGSELR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TIMOD`"]
|
||||
pub enum TIMODW {
|
||||
#[doc = "Timer Disabled."]
|
||||
_0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."]
|
||||
_1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."]
|
||||
_10,
|
||||
#[doc = "Single 16-bit counter mode."]
|
||||
_11,
|
||||
#[doc = "Timer Disabled."] _0,
|
||||
#[doc = "Dual 8-bit counters baud/bit mode."] _1,
|
||||
#[doc = "Dual 8-bit counters PWM mode."] _10,
|
||||
#[doc = "Single 16-bit counter mode."] _11,
|
||||
}
|
||||
impl TIMODW {
|
||||
#[allow(missing_docs)]
|
||||
@ -383,10 +367,8 @@ impl<'a> _TIMODW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINPOL`"]
|
||||
pub enum PINPOLW {
|
||||
#[doc = "Pin is active high"]
|
||||
_0,
|
||||
#[doc = "Pin is active low"]
|
||||
_1,
|
||||
#[doc = "Pin is active high"] _0,
|
||||
#[doc = "Pin is active low"] _1,
|
||||
}
|
||||
impl PINPOLW {
|
||||
#[allow(missing_docs)]
|
||||
@ -456,14 +438,10 @@ impl<'a> _PINSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PINCFG`"]
|
||||
pub enum PINCFGW {
|
||||
#[doc = "Timer pin output disabled"]
|
||||
_0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||||
_1,
|
||||
#[doc = "Timer pin bidirectional output data"]
|
||||
_10,
|
||||
#[doc = "Timer pin output"]
|
||||
_11,
|
||||
#[doc = "Timer pin output disabled"] _0,
|
||||
#[doc = "Timer pin open drain or bidirectional output enable"] _1,
|
||||
#[doc = "Timer pin bidirectional output data"] _10,
|
||||
#[doc = "Timer pin output"] _11,
|
||||
}
|
||||
impl PINCFGW {
|
||||
#[allow(missing_docs)]
|
||||
@ -522,10 +500,8 @@ impl<'a> _PINCFGW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGSRC`"]
|
||||
pub enum TRGSRCW {
|
||||
#[doc = "External trigger selected"]
|
||||
_0,
|
||||
#[doc = "Internal trigger selected"]
|
||||
_1,
|
||||
#[doc = "External trigger selected"] _0,
|
||||
#[doc = "Internal trigger selected"] _1,
|
||||
}
|
||||
impl TRGSRCW {
|
||||
#[allow(missing_docs)]
|
||||
@ -580,10 +556,8 @@ impl<'a> _TRGSRCW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `TRGPOL`"]
|
||||
pub enum TRGPOLW {
|
||||
#[doc = "Trigger active high"]
|
||||
_0,
|
||||
#[doc = "Trigger active low"]
|
||||
_1,
|
||||
#[doc = "Trigger active high"] _0,
|
||||
#[doc = "Trigger active low"] _1,
|
||||
}
|
||||
impl TRGPOLW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMIEN {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::TIMSTAT {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -6,18 +6,17 @@ impl super::VERID {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FEATURE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FEATURER {
|
||||
#[doc = "Standard features implemented."]
|
||||
_0000000000000000,
|
||||
#[doc = "Supports state, logic and parallel modes."]
|
||||
_0000000000000001,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u16),
|
||||
#[doc = "Standard features implemented."] _0000000000000000,
|
||||
#[doc = "Supports state, logic and parallel modes."] _0000000000000001,
|
||||
#[doc = r" Reserved"] _Reserved(u16),
|
||||
}
|
||||
impl FEATURER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
|
||||
Reference in New Issue
Block a user