Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::C0 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::C0 {
|
||||
#[doc = "Possible values of the field `HYSTCTR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum HYSTCTRR {
|
||||
#[doc = "The hard block output has level 0 hysteresis internally."]
|
||||
_00,
|
||||
#[doc = "The hard block output has level 1 hysteresis internally."]
|
||||
_01,
|
||||
#[doc = "The hard block output has level 2 hysteresis internally."]
|
||||
_10,
|
||||
#[doc = "The hard block output has level 3 hysteresis internally."]
|
||||
_11,
|
||||
#[doc = "The hard block output has level 0 hysteresis internally."] _00,
|
||||
#[doc = "The hard block output has level 1 hysteresis internally."] _01,
|
||||
#[doc = "The hard block output has level 2 hysteresis internally."] _10,
|
||||
#[doc = "The hard block output has level 3 hysteresis internally."] _11,
|
||||
}
|
||||
impl HYSTCTRR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl HYSTCTRR {
|
||||
#[doc = "Possible values of the field `OFFSET`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum OFFSETR {
|
||||
#[doc = "The comparator hard block output has level 0 offset internally."]
|
||||
_0,
|
||||
#[doc = "The comparator hard block output has level 1 offset internally."]
|
||||
_1,
|
||||
#[doc = "The comparator hard block output has level 0 offset internally."] _0,
|
||||
#[doc = "The comparator hard block output has level 1 offset internally."] _1,
|
||||
}
|
||||
impl OFFSETR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -148,20 +144,13 @@ impl OFFSETR {
|
||||
pub enum FILTER_CNTR {
|
||||
#[doc = "Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA."]
|
||||
_000,
|
||||
#[doc = "1 consecutive sample must agree (comparator output is simply sampled)."]
|
||||
_001,
|
||||
#[doc = "2 consecutive samples must agree."]
|
||||
_010,
|
||||
#[doc = "3 consecutive samples must agree."]
|
||||
_011,
|
||||
#[doc = "4 consecutive samples must agree."]
|
||||
_100,
|
||||
#[doc = "5 consecutive samples must agree."]
|
||||
_101,
|
||||
#[doc = "6 consecutive samples must agree."]
|
||||
_110,
|
||||
#[doc = "7 consecutive samples must agree."]
|
||||
_111,
|
||||
#[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] _001,
|
||||
#[doc = "2 consecutive samples must agree."] _010,
|
||||
#[doc = "3 consecutive samples must agree."] _011,
|
||||
#[doc = "4 consecutive samples must agree."] _100,
|
||||
#[doc = "5 consecutive samples must agree."] _101,
|
||||
#[doc = "6 consecutive samples must agree."] _110,
|
||||
#[doc = "7 consecutive samples must agree."] _111,
|
||||
}
|
||||
impl FILTER_CNTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,10 +227,8 @@ impl FILTER_CNTR {
|
||||
#[doc = "Possible values of the field `EN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ENR {
|
||||
#[doc = "Analog Comparator is disabled."]
|
||||
_0,
|
||||
#[doc = "Analog Comparator is enabled."]
|
||||
_1,
|
||||
#[doc = "Analog Comparator is disabled."] _0,
|
||||
#[doc = "Analog Comparator is enabled."] _1,
|
||||
}
|
||||
impl ENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -332,10 +319,8 @@ impl OPER {
|
||||
#[doc = "Possible values of the field `COS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum COSR {
|
||||
#[doc = "Set CMPO to equal COUT (filtered comparator output)."]
|
||||
_0,
|
||||
#[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."]
|
||||
_1,
|
||||
#[doc = "Set CMPO to equal COUT (filtered comparator output)."] _0,
|
||||
#[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] _1,
|
||||
}
|
||||
impl COSR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -379,10 +364,8 @@ impl COSR {
|
||||
#[doc = "Possible values of the field `INVT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INVTR {
|
||||
#[doc = "Does not invert the comparator output."]
|
||||
_0,
|
||||
#[doc = "Inverts the comparator output."]
|
||||
_1,
|
||||
#[doc = "Does not invert the comparator output."] _0,
|
||||
#[doc = "Inverts the comparator output."] _1,
|
||||
}
|
||||
impl INVTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -426,8 +409,7 @@ impl INVTR {
|
||||
#[doc = "Possible values of the field `PMODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PMODER {
|
||||
#[doc = "Low Speed (LS) comparison mode is selected."]
|
||||
_0,
|
||||
#[doc = "Low Speed (LS) comparison mode is selected."] _0,
|
||||
#[doc = "High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode."]
|
||||
_1,
|
||||
}
|
||||
@ -473,10 +455,8 @@ impl PMODER {
|
||||
#[doc = "Possible values of the field `WE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum WER {
|
||||
#[doc = "Windowing mode is not selected."]
|
||||
_0,
|
||||
#[doc = "Windowing mode is selected."]
|
||||
_1,
|
||||
#[doc = "Windowing mode is not selected."] _0,
|
||||
#[doc = "Windowing mode is selected."] _1,
|
||||
}
|
||||
impl WER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -520,10 +500,8 @@ impl WER {
|
||||
#[doc = "Possible values of the field `SE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum SER {
|
||||
#[doc = "Sampling mode is not selected."]
|
||||
_0,
|
||||
#[doc = "Sampling mode is selected."]
|
||||
_1,
|
||||
#[doc = "Sampling mode is not selected."] _0,
|
||||
#[doc = "Sampling mode is selected."] _1,
|
||||
}
|
||||
impl SER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -599,10 +577,8 @@ impl COUTR {
|
||||
#[doc = "Possible values of the field `CFF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CFFR {
|
||||
#[doc = "A falling edge has not been detected on COUT."]
|
||||
_0,
|
||||
#[doc = "A falling edge on COUT has occurred."]
|
||||
_1,
|
||||
#[doc = "A falling edge has not been detected on COUT."] _0,
|
||||
#[doc = "A falling edge on COUT has occurred."] _1,
|
||||
}
|
||||
impl CFFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -646,10 +622,8 @@ impl CFFR {
|
||||
#[doc = "Possible values of the field `CFR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum CFRR {
|
||||
#[doc = "A rising edge has not been detected on COUT."]
|
||||
_0,
|
||||
#[doc = "A rising edge on COUT has occurred."]
|
||||
_1,
|
||||
#[doc = "A rising edge has not been detected on COUT."] _0,
|
||||
#[doc = "A rising edge on COUT has occurred."] _1,
|
||||
}
|
||||
impl CFRR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -693,10 +667,8 @@ impl CFRR {
|
||||
#[doc = "Possible values of the field `IEF`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum IEFR {
|
||||
#[doc = "Interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt is disabled."] _0,
|
||||
#[doc = "Interrupt is enabled."] _1,
|
||||
}
|
||||
impl IEFR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -740,10 +712,8 @@ impl IEFR {
|
||||
#[doc = "Possible values of the field `IER`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum IERR {
|
||||
#[doc = "Interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt is disabled."] _0,
|
||||
#[doc = "Interrupt is enabled."] _1,
|
||||
}
|
||||
impl IERR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -787,10 +757,8 @@ impl IERR {
|
||||
#[doc = "Possible values of the field `DMAEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DMAENR {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is enabled."]
|
||||
_1,
|
||||
#[doc = "DMA is disabled."] _0,
|
||||
#[doc = "DMA is enabled."] _1,
|
||||
}
|
||||
impl DMAENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -833,14 +801,10 @@ impl DMAENR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `HYSTCTR`"]
|
||||
pub enum HYSTCTRW {
|
||||
#[doc = "The hard block output has level 0 hysteresis internally."]
|
||||
_00,
|
||||
#[doc = "The hard block output has level 1 hysteresis internally."]
|
||||
_01,
|
||||
#[doc = "The hard block output has level 2 hysteresis internally."]
|
||||
_10,
|
||||
#[doc = "The hard block output has level 3 hysteresis internally."]
|
||||
_11,
|
||||
#[doc = "The hard block output has level 0 hysteresis internally."] _00,
|
||||
#[doc = "The hard block output has level 1 hysteresis internally."] _01,
|
||||
#[doc = "The hard block output has level 2 hysteresis internally."] _10,
|
||||
#[doc = "The hard block output has level 3 hysteresis internally."] _11,
|
||||
}
|
||||
impl HYSTCTRW {
|
||||
#[allow(missing_docs)]
|
||||
@ -899,10 +863,8 @@ impl<'a> _HYSTCTRW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `OFFSET`"]
|
||||
pub enum OFFSETW {
|
||||
#[doc = "The comparator hard block output has level 0 offset internally."]
|
||||
_0,
|
||||
#[doc = "The comparator hard block output has level 1 offset internally."]
|
||||
_1,
|
||||
#[doc = "The comparator hard block output has level 0 offset internally."] _0,
|
||||
#[doc = "The comparator hard block output has level 1 offset internally."] _1,
|
||||
}
|
||||
impl OFFSETW {
|
||||
#[allow(missing_docs)]
|
||||
@ -959,20 +921,13 @@ impl<'a> _OFFSETW<'a> {
|
||||
pub enum FILTER_CNTW {
|
||||
#[doc = "Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA."]
|
||||
_000,
|
||||
#[doc = "1 consecutive sample must agree (comparator output is simply sampled)."]
|
||||
_001,
|
||||
#[doc = "2 consecutive samples must agree."]
|
||||
_010,
|
||||
#[doc = "3 consecutive samples must agree."]
|
||||
_011,
|
||||
#[doc = "4 consecutive samples must agree."]
|
||||
_100,
|
||||
#[doc = "5 consecutive samples must agree."]
|
||||
_101,
|
||||
#[doc = "6 consecutive samples must agree."]
|
||||
_110,
|
||||
#[doc = "7 consecutive samples must agree."]
|
||||
_111,
|
||||
#[doc = "1 consecutive sample must agree (comparator output is simply sampled)."] _001,
|
||||
#[doc = "2 consecutive samples must agree."] _010,
|
||||
#[doc = "3 consecutive samples must agree."] _011,
|
||||
#[doc = "4 consecutive samples must agree."] _100,
|
||||
#[doc = "5 consecutive samples must agree."] _101,
|
||||
#[doc = "6 consecutive samples must agree."] _110,
|
||||
#[doc = "7 consecutive samples must agree."] _111,
|
||||
}
|
||||
impl FILTER_CNTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1055,10 +1010,8 @@ impl<'a> _FILTER_CNTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `EN`"]
|
||||
pub enum ENW {
|
||||
#[doc = "Analog Comparator is disabled."]
|
||||
_0,
|
||||
#[doc = "Analog Comparator is enabled."]
|
||||
_1,
|
||||
#[doc = "Analog Comparator is disabled."] _0,
|
||||
#[doc = "Analog Comparator is enabled."] _1,
|
||||
}
|
||||
impl ENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1171,10 +1124,8 @@ impl<'a> _OPEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `COS`"]
|
||||
pub enum COSW {
|
||||
#[doc = "Set CMPO to equal COUT (filtered comparator output)."]
|
||||
_0,
|
||||
#[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."]
|
||||
_1,
|
||||
#[doc = "Set CMPO to equal COUT (filtered comparator output)."] _0,
|
||||
#[doc = "Set CMPO to equal COUTA (unfiltered comparator output)."] _1,
|
||||
}
|
||||
impl COSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1229,10 +1180,8 @@ impl<'a> _COSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INVT`"]
|
||||
pub enum INVTW {
|
||||
#[doc = "Does not invert the comparator output."]
|
||||
_0,
|
||||
#[doc = "Inverts the comparator output."]
|
||||
_1,
|
||||
#[doc = "Does not invert the comparator output."] _0,
|
||||
#[doc = "Inverts the comparator output."] _1,
|
||||
}
|
||||
impl INVTW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1287,8 +1236,7 @@ impl<'a> _INVTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PMODE`"]
|
||||
pub enum PMODEW {
|
||||
#[doc = "Low Speed (LS) comparison mode is selected."]
|
||||
_0,
|
||||
#[doc = "Low Speed (LS) comparison mode is selected."] _0,
|
||||
#[doc = "High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode."]
|
||||
_1,
|
||||
}
|
||||
@ -1345,10 +1293,8 @@ impl<'a> _PMODEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `WE`"]
|
||||
pub enum WEW {
|
||||
#[doc = "Windowing mode is not selected."]
|
||||
_0,
|
||||
#[doc = "Windowing mode is selected."]
|
||||
_1,
|
||||
#[doc = "Windowing mode is not selected."] _0,
|
||||
#[doc = "Windowing mode is selected."] _1,
|
||||
}
|
||||
impl WEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1403,10 +1349,8 @@ impl<'a> _WEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SE`"]
|
||||
pub enum SEW {
|
||||
#[doc = "Sampling mode is not selected."]
|
||||
_0,
|
||||
#[doc = "Sampling mode is selected."]
|
||||
_1,
|
||||
#[doc = "Sampling mode is not selected."] _0,
|
||||
#[doc = "Sampling mode is selected."] _1,
|
||||
}
|
||||
impl SEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1476,10 +1420,8 @@ impl<'a> _FPRW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CFF`"]
|
||||
pub enum CFFW {
|
||||
#[doc = "A falling edge has not been detected on COUT."]
|
||||
_0,
|
||||
#[doc = "A falling edge on COUT has occurred."]
|
||||
_1,
|
||||
#[doc = "A falling edge has not been detected on COUT."] _0,
|
||||
#[doc = "A falling edge on COUT has occurred."] _1,
|
||||
}
|
||||
impl CFFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1534,10 +1476,8 @@ impl<'a> _CFFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `CFR`"]
|
||||
pub enum CFRW {
|
||||
#[doc = "A rising edge has not been detected on COUT."]
|
||||
_0,
|
||||
#[doc = "A rising edge on COUT has occurred."]
|
||||
_1,
|
||||
#[doc = "A rising edge has not been detected on COUT."] _0,
|
||||
#[doc = "A rising edge on COUT has occurred."] _1,
|
||||
}
|
||||
impl CFRW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1592,10 +1532,8 @@ impl<'a> _CFRW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `IEF`"]
|
||||
pub enum IEFW {
|
||||
#[doc = "Interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt is disabled."] _0,
|
||||
#[doc = "Interrupt is enabled."] _1,
|
||||
}
|
||||
impl IEFW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1650,10 +1588,8 @@ impl<'a> _IEFW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `IER`"]
|
||||
pub enum IERW {
|
||||
#[doc = "Interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Interrupt is disabled."] _0,
|
||||
#[doc = "Interrupt is enabled."] _1,
|
||||
}
|
||||
impl IERW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1708,10 +1644,8 @@ impl<'a> _IERW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DMAEN`"]
|
||||
pub enum DMAENW {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is enabled."]
|
||||
_1,
|
||||
#[doc = "DMA is disabled."] _0,
|
||||
#[doc = "DMA is enabled."] _1,
|
||||
}
|
||||
impl DMAENW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::C1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -54,22 +56,14 @@ impl VOSELR {
|
||||
#[doc = "Possible values of the field `MSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MSELR {
|
||||
#[doc = "IN0"]
|
||||
_000,
|
||||
#[doc = "IN1"]
|
||||
_001,
|
||||
#[doc = "IN2"]
|
||||
_010,
|
||||
#[doc = "IN3"]
|
||||
_011,
|
||||
#[doc = "IN4"]
|
||||
_100,
|
||||
#[doc = "IN5"]
|
||||
_101,
|
||||
#[doc = "IN6"]
|
||||
_110,
|
||||
#[doc = "IN7"]
|
||||
_111,
|
||||
#[doc = "IN0"] _000,
|
||||
#[doc = "IN1"] _001,
|
||||
#[doc = "IN2"] _010,
|
||||
#[doc = "IN3"] _011,
|
||||
#[doc = "IN4"] _100,
|
||||
#[doc = "IN5"] _101,
|
||||
#[doc = "IN6"] _110,
|
||||
#[doc = "IN7"] _111,
|
||||
}
|
||||
impl MSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -146,22 +140,14 @@ impl MSELR {
|
||||
#[doc = "Possible values of the field `PSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PSELR {
|
||||
#[doc = "IN0"]
|
||||
_000,
|
||||
#[doc = "IN1"]
|
||||
_001,
|
||||
#[doc = "IN2"]
|
||||
_010,
|
||||
#[doc = "IN3"]
|
||||
_011,
|
||||
#[doc = "IN4"]
|
||||
_100,
|
||||
#[doc = "IN5"]
|
||||
_101,
|
||||
#[doc = "IN6"]
|
||||
_110,
|
||||
#[doc = "IN7"]
|
||||
_111,
|
||||
#[doc = "IN0"] _000,
|
||||
#[doc = "IN1"] _001,
|
||||
#[doc = "IN2"] _010,
|
||||
#[doc = "IN3"] _011,
|
||||
#[doc = "IN4"] _100,
|
||||
#[doc = "IN5"] _101,
|
||||
#[doc = "IN6"] _110,
|
||||
#[doc = "IN7"] _111,
|
||||
}
|
||||
impl PSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -238,10 +224,8 @@ impl PSELR {
|
||||
#[doc = "Possible values of the field `VRSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum VRSELR {
|
||||
#[doc = "Vin1 is selected as resistor ladder network supply reference Vin."]
|
||||
_0,
|
||||
#[doc = "Vin2 is selected as resistor ladder network supply reference Vin."]
|
||||
_1,
|
||||
#[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] _0,
|
||||
#[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] _1,
|
||||
}
|
||||
impl VRSELR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -285,10 +269,8 @@ impl VRSELR {
|
||||
#[doc = "Possible values of the field `DACEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DACENR {
|
||||
#[doc = "DAC is disabled."]
|
||||
_0,
|
||||
#[doc = "DAC is enabled."]
|
||||
_1,
|
||||
#[doc = "DAC is disabled."] _0,
|
||||
#[doc = "DAC is enabled."] _1,
|
||||
}
|
||||
impl DACENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -500,12 +482,9 @@ impl CHN7R {
|
||||
#[doc = "Possible values of the field `INNSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INNSELR {
|
||||
#[doc = "IN0, from the 8-bit DAC output"]
|
||||
_00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"]
|
||||
_01,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "IN0, from the 8-bit DAC output"] _00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"] _01,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl INNSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -541,12 +520,9 @@ impl INNSELR {
|
||||
#[doc = "Possible values of the field `INPSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INPSELR {
|
||||
#[doc = "IN0, from the 8-bit DAC output"]
|
||||
_00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"]
|
||||
_01,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "IN0, from the 8-bit DAC output"] _00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"] _01,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl INPSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -596,22 +572,14 @@ impl<'a> _VOSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MSEL`"]
|
||||
pub enum MSELW {
|
||||
#[doc = "IN0"]
|
||||
_000,
|
||||
#[doc = "IN1"]
|
||||
_001,
|
||||
#[doc = "IN2"]
|
||||
_010,
|
||||
#[doc = "IN3"]
|
||||
_011,
|
||||
#[doc = "IN4"]
|
||||
_100,
|
||||
#[doc = "IN5"]
|
||||
_101,
|
||||
#[doc = "IN6"]
|
||||
_110,
|
||||
#[doc = "IN7"]
|
||||
_111,
|
||||
#[doc = "IN0"] _000,
|
||||
#[doc = "IN1"] _001,
|
||||
#[doc = "IN2"] _010,
|
||||
#[doc = "IN3"] _011,
|
||||
#[doc = "IN4"] _100,
|
||||
#[doc = "IN5"] _101,
|
||||
#[doc = "IN6"] _110,
|
||||
#[doc = "IN7"] _111,
|
||||
}
|
||||
impl MSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -694,22 +662,14 @@ impl<'a> _MSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `PSEL`"]
|
||||
pub enum PSELW {
|
||||
#[doc = "IN0"]
|
||||
_000,
|
||||
#[doc = "IN1"]
|
||||
_001,
|
||||
#[doc = "IN2"]
|
||||
_010,
|
||||
#[doc = "IN3"]
|
||||
_011,
|
||||
#[doc = "IN4"]
|
||||
_100,
|
||||
#[doc = "IN5"]
|
||||
_101,
|
||||
#[doc = "IN6"]
|
||||
_110,
|
||||
#[doc = "IN7"]
|
||||
_111,
|
||||
#[doc = "IN0"] _000,
|
||||
#[doc = "IN1"] _001,
|
||||
#[doc = "IN2"] _010,
|
||||
#[doc = "IN3"] _011,
|
||||
#[doc = "IN4"] _100,
|
||||
#[doc = "IN5"] _101,
|
||||
#[doc = "IN6"] _110,
|
||||
#[doc = "IN7"] _111,
|
||||
}
|
||||
impl PSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -792,10 +752,8 @@ impl<'a> _PSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `VRSEL`"]
|
||||
pub enum VRSELW {
|
||||
#[doc = "Vin1 is selected as resistor ladder network supply reference Vin."]
|
||||
_0,
|
||||
#[doc = "Vin2 is selected as resistor ladder network supply reference Vin."]
|
||||
_1,
|
||||
#[doc = "Vin1 is selected as resistor ladder network supply reference Vin."] _0,
|
||||
#[doc = "Vin2 is selected as resistor ladder network supply reference Vin."] _1,
|
||||
}
|
||||
impl VRSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -850,10 +808,8 @@ impl<'a> _VRSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DACEN`"]
|
||||
pub enum DACENW {
|
||||
#[doc = "DAC is disabled."]
|
||||
_0,
|
||||
#[doc = "DAC is enabled."]
|
||||
_1,
|
||||
#[doc = "DAC is disabled."] _0,
|
||||
#[doc = "DAC is enabled."] _1,
|
||||
}
|
||||
impl DACENW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1092,10 +1048,8 @@ impl<'a> _CHN7W<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INNSEL`"]
|
||||
pub enum INNSELW {
|
||||
#[doc = "IN0, from the 8-bit DAC output"]
|
||||
_00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"]
|
||||
_01,
|
||||
#[doc = "IN0, from the 8-bit DAC output"] _00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"] _01,
|
||||
}
|
||||
impl INNSELW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1140,10 +1094,8 @@ impl<'a> _INNSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INPSEL`"]
|
||||
pub enum INPSELW {
|
||||
#[doc = "IN0, from the 8-bit DAC output"]
|
||||
_00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"]
|
||||
_01,
|
||||
#[doc = "IN0, from the 8-bit DAC output"] _00,
|
||||
#[doc = "IN1, from the analog 8-1 mux"] _01,
|
||||
}
|
||||
impl INPSELW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::C2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -54,10 +56,8 @@ impl ACONR {
|
||||
#[doc = "Possible values of the field `INITMOD`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum INITMODR {
|
||||
#[doc = "The modulus is set to 64(same with 111111)."]
|
||||
_000000,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "The modulus is set to 64(same with 111111)."] _000000,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl INITMODR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -310,22 +310,14 @@ impl CH7FR {
|
||||
#[doc = "Possible values of the field `FXMXCH`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FXMXCHR {
|
||||
#[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."]
|
||||
_000,
|
||||
#[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."]
|
||||
_001,
|
||||
#[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."]
|
||||
_010,
|
||||
#[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."]
|
||||
_011,
|
||||
#[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."]
|
||||
_100,
|
||||
#[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."]
|
||||
_101,
|
||||
#[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."]
|
||||
_110,
|
||||
#[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."]
|
||||
_111,
|
||||
#[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] _000,
|
||||
#[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] _001,
|
||||
#[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] _010,
|
||||
#[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] _011,
|
||||
#[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] _100,
|
||||
#[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] _101,
|
||||
#[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] _110,
|
||||
#[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] _111,
|
||||
}
|
||||
impl FXMXCHR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -402,10 +394,8 @@ impl FXMXCHR {
|
||||
#[doc = "Possible values of the field `FXMP`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FXMPR {
|
||||
#[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."]
|
||||
_0,
|
||||
#[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."]
|
||||
_1,
|
||||
#[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] _0,
|
||||
#[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] _1,
|
||||
}
|
||||
impl FXMPR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -449,8 +439,7 @@ impl FXMPR {
|
||||
#[doc = "Possible values of the field `RRIE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RRIER {
|
||||
#[doc = "The round-robin interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "The round-robin interrupt is disabled."] _0,
|
||||
#[doc = "The round-robin interrupt is enabled when a comparison result changes from the last sample."]
|
||||
_1,
|
||||
}
|
||||
@ -496,10 +485,8 @@ impl RRIER {
|
||||
#[doc = "Possible values of the field `RRE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RRER {
|
||||
#[doc = "Round-robin operation is disabled."]
|
||||
_0,
|
||||
#[doc = "Round-robin operation is enabled."]
|
||||
_1,
|
||||
#[doc = "Round-robin operation is disabled."] _0,
|
||||
#[doc = "Round-robin operation is enabled."] _1,
|
||||
}
|
||||
impl RRER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -557,8 +544,7 @@ impl<'a> _ACONW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `INITMOD`"]
|
||||
pub enum INITMODW {
|
||||
#[doc = "The modulus is set to 64(same with 111111)."]
|
||||
_000000,
|
||||
#[doc = "The modulus is set to 64(same with 111111)."] _000000,
|
||||
}
|
||||
impl INITMODW {
|
||||
#[allow(missing_docs)]
|
||||
@ -847,22 +833,14 @@ impl<'a> _CH7FW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FXMXCH`"]
|
||||
pub enum FXMXCHW {
|
||||
#[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."]
|
||||
_000,
|
||||
#[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."]
|
||||
_001,
|
||||
#[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."]
|
||||
_010,
|
||||
#[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."]
|
||||
_011,
|
||||
#[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."]
|
||||
_100,
|
||||
#[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."]
|
||||
_101,
|
||||
#[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."]
|
||||
_110,
|
||||
#[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."]
|
||||
_111,
|
||||
#[doc = "Channel 0 is selected as the fixed reference input for the fixed mux port."] _000,
|
||||
#[doc = "Channel 1 is selected as the fixed reference input for the fixed mux port."] _001,
|
||||
#[doc = "Channel 2 is selected as the fixed reference input for the fixed mux port."] _010,
|
||||
#[doc = "Channel 3 is selected as the fixed reference input for the fixed mux port."] _011,
|
||||
#[doc = "Channel 4 is selected as the fixed reference input for the fixed mux port."] _100,
|
||||
#[doc = "Channel 5 is selected as the fixed reference input for the fixed mux port."] _101,
|
||||
#[doc = "Channel 6 is selected as the fixed reference input for the fixed mux port."] _110,
|
||||
#[doc = "Channel 7 is selected as the fixed reference input for the fixed mux port."] _111,
|
||||
}
|
||||
impl FXMXCHW {
|
||||
#[allow(missing_docs)]
|
||||
@ -945,10 +923,8 @@ impl<'a> _FXMXCHW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FXMP`"]
|
||||
pub enum FXMPW {
|
||||
#[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."]
|
||||
_0,
|
||||
#[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."]
|
||||
_1,
|
||||
#[doc = "The Plus port is fixed. Only the inputs to the Minus port are swept in each round."] _0,
|
||||
#[doc = "The Minus port is fixed. Only the inputs to the Plus port are swept in each round."] _1,
|
||||
}
|
||||
impl FXMPW {
|
||||
#[allow(missing_docs)]
|
||||
@ -1003,8 +979,7 @@ impl<'a> _FXMPW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RRIE`"]
|
||||
pub enum RRIEW {
|
||||
#[doc = "The round-robin interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "The round-robin interrupt is disabled."] _0,
|
||||
#[doc = "The round-robin interrupt is enabled when a comparison result changes from the last sample."]
|
||||
_1,
|
||||
}
|
||||
@ -1061,10 +1036,8 @@ impl<'a> _RRIEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RRE`"]
|
||||
pub enum RREW {
|
||||
#[doc = "Round-robin operation is disabled."]
|
||||
_0,
|
||||
#[doc = "Round-robin operation is enabled."]
|
||||
_1,
|
||||
#[doc = "Round-robin operation is disabled."] _0,
|
||||
#[doc = "Round-robin operation is enabled."] _1,
|
||||
}
|
||||
impl RREW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -2,12 +2,9 @@ use vcell::VolatileCell;
|
||||
#[doc = r" Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - CMP Control Register 0"]
|
||||
pub c0: C0,
|
||||
#[doc = "0x04 - CMP Control Register 1"]
|
||||
pub c1: C1,
|
||||
#[doc = "0x08 - CMP Control Register 2"]
|
||||
pub c2: C2,
|
||||
#[doc = "0x00 - CMP Control Register 0"] pub c0: C0,
|
||||
#[doc = "0x04 - CMP Control Register 1"] pub c1: C1,
|
||||
#[doc = "0x08 - CMP Control Register 2"] pub c2: C2,
|
||||
}
|
||||
#[doc = "CMP Control Register 0"]
|
||||
pub struct C0 {
|
||||
|
||||
Reference in New Issue
Block a user