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This commit is contained in:
Kjetil Kjeka
2017-09-23 20:31:10 +02:00
parent 7facea48b2
commit 2fc3ce22de
1658 changed files with 25191 additions and 42351 deletions
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16
src/can0/cbt/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CBT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -98,10 +100,8 @@ impl EPRESDIVR {
#[doc = "Possible values of the field `BTF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BTFR {
#[doc = "Extended bit time definitions disabled."]
_0,
#[doc = "Extended bit time definitions enabled."]
_1,
#[doc = "Extended bit time definitions disabled."] _0,
#[doc = "Extended bit time definitions enabled."] _1,
}
impl BTFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -219,10 +219,8 @@ impl<'a> _EPRESDIVW<'a> {
}
#[doc = "Values that can be written to the field `BTF`"]
pub enum BTFW {
#[doc = "Extended bit time definitions disabled."]
_0,
#[doc = "Extended bit time definitions enabled."]
_1,
#[doc = "Extended bit time definitions disabled."] _0,
#[doc = "Extended bit time definitions enabled."] _1,
}
impl BTFW {
#[allow(missing_docs)]

4
src/can0/crcr/mod.rs
View File

@ -6,7 +6,9 @@ impl super::CRCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

124
src/can0/ctrl1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CTRL1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,10 +56,8 @@ impl PROPSEGR {
#[doc = "Possible values of the field `LOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LOMR {
#[doc = "Listen-Only mode is deactivated."]
_0,
#[doc = "FlexCAN module operates in Listen-Only mode."]
_1,
#[doc = "Listen-Only mode is deactivated."] _0,
#[doc = "FlexCAN module operates in Listen-Only mode."] _1,
}
impl LOMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -101,10 +101,8 @@ impl LOMR {
#[doc = "Possible values of the field `LBUF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LBUFR {
#[doc = "Buffer with highest priority is transmitted first."]
_0,
#[doc = "Lowest number buffer is transmitted first."]
_1,
#[doc = "Buffer with highest priority is transmitted first."] _0,
#[doc = "Lowest number buffer is transmitted first."] _1,
}
impl LBUFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -148,10 +146,8 @@ impl LBUFR {
#[doc = "Possible values of the field `TSYN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TSYNR {
#[doc = "Timer Sync feature disabled"]
_0,
#[doc = "Timer Sync feature enabled"]
_1,
#[doc = "Timer Sync feature disabled"] _0,
#[doc = "Timer Sync feature enabled"] _1,
}
impl TSYNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -195,10 +191,8 @@ impl TSYNR {
#[doc = "Possible values of the field `BOFFREC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BOFFRECR {
#[doc = "Automatic recovering from Bus Off state enabled."]
_0,
#[doc = "Automatic recovering from Bus Off state disabled."]
_1,
#[doc = "Automatic recovering from Bus Off state enabled."] _0,
#[doc = "Automatic recovering from Bus Off state disabled."] _1,
}
impl BOFFRECR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -242,8 +236,7 @@ impl BOFFRECR {
#[doc = "Possible values of the field `SMP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMPR {
#[doc = "Just one sample is used to determine the bit value."]
_0,
#[doc = "Just one sample is used to determine the bit value."] _0,
#[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."]
_1,
}
@ -289,10 +282,8 @@ impl SMPR {
#[doc = "Possible values of the field `RWRNMSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RWRNMSKR {
#[doc = "Rx Warning Interrupt disabled."]
_0,
#[doc = "Rx Warning Interrupt enabled."]
_1,
#[doc = "Rx Warning Interrupt disabled."] _0,
#[doc = "Rx Warning Interrupt enabled."] _1,
}
impl RWRNMSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -336,10 +327,8 @@ impl RWRNMSKR {
#[doc = "Possible values of the field `TWRNMSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TWRNMSKR {
#[doc = "Tx Warning Interrupt disabled."]
_0,
#[doc = "Tx Warning Interrupt enabled."]
_1,
#[doc = "Tx Warning Interrupt disabled."] _0,
#[doc = "Tx Warning Interrupt enabled."] _1,
}
impl TWRNMSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -383,10 +372,8 @@ impl TWRNMSKR {
#[doc = "Possible values of the field `LPB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPBR {
#[doc = "Loop Back disabled."]
_0,
#[doc = "Loop Back enabled."]
_1,
#[doc = "Loop Back disabled."] _0,
#[doc = "Loop Back enabled."] _1,
}
impl LPBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -432,8 +419,7 @@ impl LPBR {
pub enum CLKSRCR {
#[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."]
_0,
#[doc = "The CAN engine clock source is the peripheral clock."]
_1,
#[doc = "The CAN engine clock source is the peripheral clock."] _1,
}
impl CLKSRCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -477,10 +463,8 @@ impl CLKSRCR {
#[doc = "Possible values of the field `ERRMSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRMSKR {
#[doc = "Error interrupt disabled."]
_0,
#[doc = "Error interrupt enabled."]
_1,
#[doc = "Error interrupt disabled."] _0,
#[doc = "Error interrupt enabled."] _1,
}
impl ERRMSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -524,10 +508,8 @@ impl ERRMSKR {
#[doc = "Possible values of the field `BOFFMSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BOFFMSKR {
#[doc = "Bus Off interrupt disabled."]
_0,
#[doc = "Bus Off interrupt enabled."]
_1,
#[doc = "Bus Off interrupt disabled."] _0,
#[doc = "Bus Off interrupt enabled."] _1,
}
impl BOFFMSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -629,10 +611,8 @@ impl<'a> _PROPSEGW<'a> {
}
#[doc = "Values that can be written to the field `LOM`"]
pub enum LOMW {
#[doc = "Listen-Only mode is deactivated."]
_0,
#[doc = "FlexCAN module operates in Listen-Only mode."]
_1,
#[doc = "Listen-Only mode is deactivated."] _0,
#[doc = "FlexCAN module operates in Listen-Only mode."] _1,
}
impl LOMW {
#[allow(missing_docs)]
@ -687,10 +667,8 @@ impl<'a> _LOMW<'a> {
}
#[doc = "Values that can be written to the field `LBUF`"]
pub enum LBUFW {
#[doc = "Buffer with highest priority is transmitted first."]
_0,
#[doc = "Lowest number buffer is transmitted first."]
_1,
#[doc = "Buffer with highest priority is transmitted first."] _0,
#[doc = "Lowest number buffer is transmitted first."] _1,
}
impl LBUFW {
#[allow(missing_docs)]
@ -745,10 +723,8 @@ impl<'a> _LBUFW<'a> {
}
#[doc = "Values that can be written to the field `TSYN`"]
pub enum TSYNW {
#[doc = "Timer Sync feature disabled"]
_0,
#[doc = "Timer Sync feature enabled"]
_1,
#[doc = "Timer Sync feature disabled"] _0,
#[doc = "Timer Sync feature enabled"] _1,
}
impl TSYNW {
#[allow(missing_docs)]
@ -803,10 +779,8 @@ impl<'a> _TSYNW<'a> {
}
#[doc = "Values that can be written to the field `BOFFREC`"]
pub enum BOFFRECW {
#[doc = "Automatic recovering from Bus Off state enabled."]
_0,
#[doc = "Automatic recovering from Bus Off state disabled."]
_1,
#[doc = "Automatic recovering from Bus Off state enabled."] _0,
#[doc = "Automatic recovering from Bus Off state disabled."] _1,
}
impl BOFFRECW {
#[allow(missing_docs)]
@ -861,8 +835,7 @@ impl<'a> _BOFFRECW<'a> {
}
#[doc = "Values that can be written to the field `SMP`"]
pub enum SMPW {
#[doc = "Just one sample is used to determine the bit value."]
_0,
#[doc = "Just one sample is used to determine the bit value."] _0,
#[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."]
_1,
}
@ -919,10 +892,8 @@ impl<'a> _SMPW<'a> {
}
#[doc = "Values that can be written to the field `RWRNMSK`"]
pub enum RWRNMSKW {
#[doc = "Rx Warning Interrupt disabled."]
_0,
#[doc = "Rx Warning Interrupt enabled."]
_1,
#[doc = "Rx Warning Interrupt disabled."] _0,
#[doc = "Rx Warning Interrupt enabled."] _1,
}
impl RWRNMSKW {
#[allow(missing_docs)]
@ -977,10 +948,8 @@ impl<'a> _RWRNMSKW<'a> {
}
#[doc = "Values that can be written to the field `TWRNMSK`"]
pub enum TWRNMSKW {
#[doc = "Tx Warning Interrupt disabled."]
_0,
#[doc = "Tx Warning Interrupt enabled."]
_1,
#[doc = "Tx Warning Interrupt disabled."] _0,
#[doc = "Tx Warning Interrupt enabled."] _1,
}
impl TWRNMSKW {
#[allow(missing_docs)]
@ -1035,10 +1004,8 @@ impl<'a> _TWRNMSKW<'a> {
}
#[doc = "Values that can be written to the field `LPB`"]
pub enum LPBW {
#[doc = "Loop Back disabled."]
_0,
#[doc = "Loop Back enabled."]
_1,
#[doc = "Loop Back disabled."] _0,
#[doc = "Loop Back enabled."] _1,
}
impl LPBW {
#[allow(missing_docs)]
@ -1095,8 +1062,7 @@ impl<'a> _LPBW<'a> {
pub enum CLKSRCW {
#[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."]
_0,
#[doc = "The CAN engine clock source is the peripheral clock."]
_1,
#[doc = "The CAN engine clock source is the peripheral clock."] _1,
}
impl CLKSRCW {
#[allow(missing_docs)]
@ -1151,10 +1117,8 @@ impl<'a> _CLKSRCW<'a> {
}
#[doc = "Values that can be written to the field `ERRMSK`"]
pub enum ERRMSKW {
#[doc = "Error interrupt disabled."]
_0,
#[doc = "Error interrupt enabled."]
_1,
#[doc = "Error interrupt disabled."] _0,
#[doc = "Error interrupt enabled."] _1,
}
impl ERRMSKW {
#[allow(missing_docs)]
@ -1209,10 +1173,8 @@ impl<'a> _ERRMSKW<'a> {
}
#[doc = "Values that can be written to the field `BOFFMSK`"]
pub enum BOFFMSKW {
#[doc = "Bus Off interrupt disabled."]
_0,
#[doc = "Bus Off interrupt enabled."]
_1,
#[doc = "Bus Off interrupt disabled."] _0,
#[doc = "Bus Off interrupt enabled."] _1,
}
impl BOFFMSKW {
#[allow(missing_docs)]

91
src/can0/ctrl1_pn/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CTRL1_PN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,14 +45,10 @@ impl super::CTRL1_PN {
#[doc = "Possible values of the field `FCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FCSR {
#[doc = "Message ID filtering only"]
_00,
#[doc = "Message ID filtering and payload filtering"]
_01,
#[doc = "Message ID filtering occurring a specified number of times."]
_10,
#[doc = "Message ID filtering and payload filtering a specified number of times"]
_11,
#[doc = "Message ID filtering only"] _00,
#[doc = "Message ID filtering and payload filtering"] _01,
#[doc = "Message ID filtering occurring a specified number of times."] _10,
#[doc = "Message ID filtering and payload filtering a specified number of times"] _11,
}
impl FCSR {
#[doc = r" Value of the field as raw bits"]
@ -99,12 +97,9 @@ impl FCSR {
#[doc = "Possible values of the field `IDFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDFSR {
#[doc = "Match upon a ID contents against an exact target value"]
_00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a ID contents against an exact target value"] _00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"] _01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10,
#[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
@ -155,12 +150,9 @@ impl IDFSR {
#[doc = "Possible values of the field `PLFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLFSR {
#[doc = "Match upon a payload contents against an exact target value"]
_00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a payload contents against an exact target value"] _00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"] _01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10,
#[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
@ -217,8 +209,7 @@ pub enum NMATCHR {
_00000010,
#[doc = "Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event."]
_11111111,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = r" Reserved"] _Reserved(u8),
}
impl NMATCHR {
#[doc = r" Value of the field as raw bits"]
@ -261,10 +252,8 @@ impl NMATCHR {
#[doc = "Possible values of the field `WUMF_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WUMF_MSKR {
#[doc = "Wake up match event is disabled"]
_0,
#[doc = "Wake up match event is enabled"]
_1,
#[doc = "Wake up match event is disabled"] _0,
#[doc = "Wake up match event is enabled"] _1,
}
impl WUMF_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -308,10 +297,8 @@ impl WUMF_MSKR {
#[doc = "Possible values of the field `WTOF_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WTOF_MSKR {
#[doc = "Timeout wake up event is disabled"]
_0,
#[doc = "Timeout wake up event is enabled"]
_1,
#[doc = "Timeout wake up event is disabled"] _0,
#[doc = "Timeout wake up event is enabled"] _1,
}
impl WTOF_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -354,14 +341,10 @@ impl WTOF_MSKR {
}
#[doc = "Values that can be written to the field `FCS`"]
pub enum FCSW {
#[doc = "Message ID filtering only"]
_00,
#[doc = "Message ID filtering and payload filtering"]
_01,
#[doc = "Message ID filtering occurring a specified number of times."]
_10,
#[doc = "Message ID filtering and payload filtering a specified number of times"]
_11,
#[doc = "Message ID filtering only"] _00,
#[doc = "Message ID filtering and payload filtering"] _01,
#[doc = "Message ID filtering occurring a specified number of times."] _10,
#[doc = "Message ID filtering and payload filtering a specified number of times"] _11,
}
impl FCSW {
#[allow(missing_docs)]
@ -420,12 +403,9 @@ impl<'a> _FCSW<'a> {
}
#[doc = "Values that can be written to the field `IDFS`"]
pub enum IDFSW {
#[doc = "Match upon a ID contents against an exact target value"]
_00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a ID contents against an exact target value"] _00,
#[doc = "Match upon a ID value greater than or equal to a specified target value"] _01,
#[doc = "Match upon a ID value smaller than or equal to a specified target value"] _10,
#[doc = "Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
@ -486,12 +466,9 @@ impl<'a> _IDFSW<'a> {
}
#[doc = "Values that can be written to the field `PLFS`"]
pub enum PLFSW {
#[doc = "Match upon a payload contents against an exact target value"]
_00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"]
_01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"]
_10,
#[doc = "Match upon a payload contents against an exact target value"] _00,
#[doc = "Match upon a payload value greater than or equal to a specified target value"] _01,
#[doc = "Match upon a payload value smaller than or equal to a specified target value"] _10,
#[doc = "Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit"]
_11,
}
@ -608,10 +585,8 @@ impl<'a> _NMATCHW<'a> {
}
#[doc = "Values that can be written to the field `WUMF_MSK`"]
pub enum WUMF_MSKW {
#[doc = "Wake up match event is disabled"]
_0,
#[doc = "Wake up match event is enabled"]
_1,
#[doc = "Wake up match event is disabled"] _0,
#[doc = "Wake up match event is enabled"] _1,
}
impl WUMF_MSKW {
#[allow(missing_docs)]
@ -666,10 +641,8 @@ impl<'a> _WUMF_MSKW<'a> {
}
#[doc = "Values that can be written to the field `WTOF_MSK`"]
pub enum WTOF_MSKW {
#[doc = "Timeout wake up event is disabled"]
_0,
#[doc = "Timeout wake up event is enabled"]
_1,
#[doc = "Timeout wake up event is disabled"] _0,
#[doc = "Timeout wake up event is enabled"] _1,
}
impl WTOF_MSKW {
#[allow(missing_docs)]

88
src/can0/ctrl2/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CTRL2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::CTRL2 {
#[doc = "Possible values of the field `EDFLTDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EDFLTDISR {
#[doc = "Edge Filter is enabled."]
_0,
#[doc = "Edge Filter is disabled."]
_1,
#[doc = "Edge Filter is enabled."] _0,
#[doc = "Edge Filter is disabled."] _1,
}
impl EDFLTDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl EDFLTDISR {
#[doc = "Possible values of the field `ISOCANFDEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISOCANFDENR {
#[doc = "FlexCAN operates using the non-ISO CAN FD protocol."]
_0,
#[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."]
_1,
#[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0,
#[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1,
}
impl ISOCANFDENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl ISOCANFDENR {
#[doc = "Possible values of the field `PREXCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PREXCENR {
#[doc = "Protocol Exception is disabled."]
_0,
#[doc = "Protocol Exception is enabled."]
_1,
#[doc = "Protocol Exception is disabled."] _0,
#[doc = "Protocol Exception is enabled."] _1,
}
impl PREXCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -278,10 +274,8 @@ impl EACENR {
#[doc = "Possible values of the field `RRS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RRSR {
#[doc = "Remote Response Frame is generated."]
_0,
#[doc = "Remote Request Frame is stored."]
_1,
#[doc = "Remote Response Frame is generated."] _0,
#[doc = "Remote Request Frame is stored."] _1,
}
impl RRSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -325,10 +319,8 @@ impl RRSR {
#[doc = "Possible values of the field `MRP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MRPR {
#[doc = "Matching starts from Rx FIFO and continues on Mailboxes."]
_0,
#[doc = "Matching starts from Mailboxes and continues on Rx FIFO."]
_1,
#[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0,
#[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1,
}
impl MRPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -394,10 +386,8 @@ impl RFFNR {
#[doc = "Possible values of the field `BOFFDONEMSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BOFFDONEMSKR {
#[doc = "Bus Off Done interrupt disabled."]
_0,
#[doc = "Bus Off Done interrupt enabled."]
_1,
#[doc = "Bus Off Done interrupt disabled."] _0,
#[doc = "Bus Off Done interrupt enabled."] _1,
}
impl BOFFDONEMSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -441,10 +431,8 @@ impl BOFFDONEMSKR {
#[doc = "Possible values of the field `ERRMSK_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRMSK_FASTR {
#[doc = "ERRINT_FAST Error interrupt disabled."]
_0,
#[doc = "ERRINT_FAST Error interrupt enabled."]
_1,
#[doc = "ERRINT_FAST Error interrupt disabled."] _0,
#[doc = "ERRINT_FAST Error interrupt enabled."] _1,
}
impl ERRMSK_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -487,10 +475,8 @@ impl ERRMSK_FASTR {
}
#[doc = "Values that can be written to the field `EDFLTDIS`"]
pub enum EDFLTDISW {
#[doc = "Edge Filter is enabled."]
_0,
#[doc = "Edge Filter is disabled."]
_1,
#[doc = "Edge Filter is enabled."] _0,
#[doc = "Edge Filter is disabled."] _1,
}
impl EDFLTDISW {
#[allow(missing_docs)]
@ -545,10 +531,8 @@ impl<'a> _EDFLTDISW<'a> {
}
#[doc = "Values that can be written to the field `ISOCANFDEN`"]
pub enum ISOCANFDENW {
#[doc = "FlexCAN operates using the non-ISO CAN FD protocol."]
_0,
#[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."]
_1,
#[doc = "FlexCAN operates using the non-ISO CAN FD protocol."] _0,
#[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."] _1,
}
impl ISOCANFDENW {
#[allow(missing_docs)]
@ -603,10 +587,8 @@ impl<'a> _ISOCANFDENW<'a> {
}
#[doc = "Values that can be written to the field `PREXCEN`"]
pub enum PREXCENW {
#[doc = "Protocol Exception is disabled."]
_0,
#[doc = "Protocol Exception is enabled."]
_1,
#[doc = "Protocol Exception is disabled."] _0,
#[doc = "Protocol Exception is enabled."] _1,
}
impl PREXCENW {
#[allow(missing_docs)]
@ -777,10 +759,8 @@ impl<'a> _EACENW<'a> {
}
#[doc = "Values that can be written to the field `RRS`"]
pub enum RRSW {
#[doc = "Remote Response Frame is generated."]
_0,
#[doc = "Remote Request Frame is stored."]
_1,
#[doc = "Remote Response Frame is generated."] _0,
#[doc = "Remote Request Frame is stored."] _1,
}
impl RRSW {
#[allow(missing_docs)]
@ -835,10 +815,8 @@ impl<'a> _RRSW<'a> {
}
#[doc = "Values that can be written to the field `MRP`"]
pub enum MRPW {
#[doc = "Matching starts from Rx FIFO and continues on Mailboxes."]
_0,
#[doc = "Matching starts from Mailboxes and continues on Rx FIFO."]
_1,
#[doc = "Matching starts from Rx FIFO and continues on Mailboxes."] _0,
#[doc = "Matching starts from Mailboxes and continues on Rx FIFO."] _1,
}
impl MRPW {
#[allow(missing_docs)]
@ -923,10 +901,8 @@ impl<'a> _RFFNW<'a> {
}
#[doc = "Values that can be written to the field `BOFFDONEMSK`"]
pub enum BOFFDONEMSKW {
#[doc = "Bus Off Done interrupt disabled."]
_0,
#[doc = "Bus Off Done interrupt enabled."]
_1,
#[doc = "Bus Off Done interrupt disabled."] _0,
#[doc = "Bus Off Done interrupt enabled."] _1,
}
impl BOFFDONEMSKW {
#[allow(missing_docs)]
@ -981,10 +957,8 @@ impl<'a> _BOFFDONEMSKW<'a> {
}
#[doc = "Values that can be written to the field `ERRMSK_FAST`"]
pub enum ERRMSK_FASTW {
#[doc = "ERRINT_FAST Error interrupt disabled."]
_0,
#[doc = "ERRINT_FAST Error interrupt enabled."]
_1,
#[doc = "ERRINT_FAST Error interrupt disabled."] _0,
#[doc = "ERRINT_FAST Error interrupt enabled."] _1,
}
impl ERRMSK_FASTW {
#[allow(missing_docs)]

4
src/can0/ctrl2_pn/mod.rs
View File

@ -22,7 +22,9 @@ impl super::CTRL2_PN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/ecr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::ECR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/embedded_ram/mod.rs
View File

@ -22,7 +22,9 @@ impl super::EMBEDDEDRAM {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

184
src/can0/esr1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::ESR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -43,10 +45,8 @@ impl super::ESR1 {
#[doc = "Possible values of the field `ERRINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRINTR {
#[doc = "No such occurrence."]
_0,
#[doc = "Indicates setting of any Error Bit in the Error and Status Register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1,
}
impl ERRINTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,10 +90,8 @@ impl ERRINTR {
#[doc = "Possible values of the field `BOFFINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BOFFINTR {
#[doc = "No such occurrence."]
_0,
#[doc = "FlexCAN module entered Bus Off state."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "FlexCAN module entered Bus Off state."] _1,
}
impl BOFFINTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -137,10 +135,8 @@ impl BOFFINTR {
#[doc = "Possible values of the field `RX`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXR {
#[doc = "FlexCAN is not receiving a message."]
_0,
#[doc = "FlexCAN is receiving a message."]
_1,
#[doc = "FlexCAN is not receiving a message."] _0,
#[doc = "FlexCAN is receiving a message."] _1,
}
impl RXR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -184,14 +180,10 @@ impl RXR {
#[doc = "Possible values of the field `FLTCONF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLTCONFR {
#[doc = "Error Active"]
_00,
#[doc = "Error Passive"]
_01,
#[doc = "Bus Off"]
_1X,
#[doc = r" Reserved"]
_Reserved(u8),
#[doc = "Error Active"] _00,
#[doc = "Error Passive"] _01,
#[doc = "Bus Off"] _1X,
#[doc = r" Reserved"] _Reserved(u8),
}
impl FLTCONFR {
#[doc = r" Value of the field as raw bits"]
@ -234,10 +226,8 @@ impl FLTCONFR {
#[doc = "Possible values of the field `TX`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXR {
#[doc = "FlexCAN is not transmitting a message."]
_0,
#[doc = "FlexCAN is transmitting a message."]
_1,
#[doc = "FlexCAN is not transmitting a message."] _0,
#[doc = "FlexCAN is transmitting a message."] _1,
}
impl TXR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -281,10 +271,8 @@ impl TXR {
#[doc = "Possible values of the field `IDLE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDLER {
#[doc = "No such occurrence."]
_0,
#[doc = "CAN bus is now IDLE."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "CAN bus is now IDLE."] _1,
}
impl IDLER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -328,10 +316,8 @@ impl IDLER {
#[doc = "Possible values of the field `RXWRN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXWRNR {
#[doc = "No such occurrence."]
_0,
#[doc = "RXERRCNT is greater than or equal to 96."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "RXERRCNT is greater than or equal to 96."] _1,
}
impl RXWRNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -375,10 +361,8 @@ impl RXWRNR {
#[doc = "Possible values of the field `TXWRN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXWRNR {
#[doc = "No such occurrence."]
_0,
#[doc = "TXERRCNT is greater than or equal to 96."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "TXERRCNT is greater than or equal to 96."] _1,
}
impl TXWRNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -422,10 +406,8 @@ impl TXWRNR {
#[doc = "Possible values of the field `STFERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STFERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "A Stuffing Error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A Stuffing Error occurred since last read of this register."] _1,
}
impl STFERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -469,10 +451,8 @@ impl STFERRR {
#[doc = "Possible values of the field `FRMERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRMERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "A Form Error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A Form Error occurred since last read of this register."] _1,
}
impl FRMERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -516,10 +496,8 @@ impl FRMERRR {
#[doc = "Possible values of the field `CRCERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRCERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "A CRC error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A CRC error occurred since last read of this register."] _1,
}
impl CRCERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -563,10 +541,8 @@ impl CRCERRR {
#[doc = "Possible values of the field `ACKERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACKERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "An ACK error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "An ACK error occurred since last read of this register."] _1,
}
impl ACKERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -610,10 +586,8 @@ impl ACKERRR {
#[doc = "Possible values of the field `BIT0ERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIT0ERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "At least one bit sent as dominant is received as recessive."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "At least one bit sent as dominant is received as recessive."] _1,
}
impl BIT0ERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -657,10 +631,8 @@ impl BIT0ERRR {
#[doc = "Possible values of the field `BIT1ERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIT1ERRR {
#[doc = "No such occurrence."]
_0,
#[doc = "At least one bit sent as recessive is received as dominant."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "At least one bit sent as recessive is received as dominant."] _1,
}
impl BIT1ERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -704,8 +676,7 @@ impl BIT1ERRR {
#[doc = "Possible values of the field `RWRNINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RWRNINTR {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."]
_1,
}
@ -751,8 +722,7 @@ impl RWRNINTR {
#[doc = "Possible values of the field `TWRNINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TWRNINTR {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."]
_1,
}
@ -798,10 +768,8 @@ impl TWRNINTR {
#[doc = "Possible values of the field `SYNCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNCHR {
#[doc = "FlexCAN is not synchronized to the CAN bus."]
_0,
#[doc = "FlexCAN is synchronized to the CAN bus."]
_1,
#[doc = "FlexCAN is not synchronized to the CAN bus."] _0,
#[doc = "FlexCAN is synchronized to the CAN bus."] _1,
}
impl SYNCHR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -845,10 +813,8 @@ impl SYNCHR {
#[doc = "Possible values of the field `BOFFDONEINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BOFFDONEINTR {
#[doc = "No such occurrence."]
_0,
#[doc = "FlexCAN module has completed Bus Off process."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "FlexCAN module has completed Bus Off process."] _1,
}
impl BOFFDONEINTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -892,8 +858,7 @@ impl BOFFDONEINTR {
#[doc = "Possible values of the field `ERRINT_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRINT_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."]
_1,
}
@ -939,10 +904,8 @@ impl ERRINT_FASTR {
#[doc = "Possible values of the field `ERROVR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERROVRR {
#[doc = "Overrun has not occurred."]
_0,
#[doc = "Overrun has occurred."]
_1,
#[doc = "Overrun has not occurred."] _0,
#[doc = "Overrun has occurred."] _1,
}
impl ERROVRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -986,10 +949,8 @@ impl ERROVRR {
#[doc = "Possible values of the field `STFERR_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STFERR_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "A Stuffing Error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A Stuffing Error occurred since last read of this register."] _1,
}
impl STFERR_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1033,10 +994,8 @@ impl STFERR_FASTR {
#[doc = "Possible values of the field `FRMERR_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRMERR_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "A Form Error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A Form Error occurred since last read of this register."] _1,
}
impl FRMERR_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1080,10 +1039,8 @@ impl FRMERR_FASTR {
#[doc = "Possible values of the field `CRCERR_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRCERR_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "A CRC error occurred since last read of this register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "A CRC error occurred since last read of this register."] _1,
}
impl CRCERR_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1127,10 +1084,8 @@ impl CRCERR_FASTR {
#[doc = "Possible values of the field `BIT0ERR_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIT0ERR_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "At least one bit sent as dominant is received as recessive."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "At least one bit sent as dominant is received as recessive."] _1,
}
impl BIT0ERR_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1174,10 +1129,8 @@ impl BIT0ERR_FASTR {
#[doc = "Possible values of the field `BIT1ERR_FAST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIT1ERR_FASTR {
#[doc = "No such occurrence."]
_0,
#[doc = "At least one bit sent as recessive is received as dominant."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "At least one bit sent as recessive is received as dominant."] _1,
}
impl BIT1ERR_FASTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -1220,10 +1173,8 @@ impl BIT1ERR_FASTR {
}
#[doc = "Values that can be written to the field `ERRINT`"]
pub enum ERRINTW {
#[doc = "No such occurrence."]
_0,
#[doc = "Indicates setting of any Error Bit in the Error and Status Register."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "Indicates setting of any Error Bit in the Error and Status Register."] _1,
}
impl ERRINTW {
#[allow(missing_docs)]
@ -1278,10 +1229,8 @@ impl<'a> _ERRINTW<'a> {
}
#[doc = "Values that can be written to the field `BOFFINT`"]
pub enum BOFFINTW {
#[doc = "No such occurrence."]
_0,
#[doc = "FlexCAN module entered Bus Off state."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "FlexCAN module entered Bus Off state."] _1,
}
impl BOFFINTW {
#[allow(missing_docs)]
@ -1336,8 +1285,7 @@ impl<'a> _BOFFINTW<'a> {
}
#[doc = "Values that can be written to the field `RWRNINT`"]
pub enum RWRNINTW {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."]
_1,
}
@ -1394,8 +1342,7 @@ impl<'a> _RWRNINTW<'a> {
}
#[doc = "Values that can be written to the field `TWRNINT`"]
pub enum TWRNINTW {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."]
_1,
}
@ -1452,10 +1399,8 @@ impl<'a> _TWRNINTW<'a> {
}
#[doc = "Values that can be written to the field `BOFFDONEINT`"]
pub enum BOFFDONEINTW {
#[doc = "No such occurrence."]
_0,
#[doc = "FlexCAN module has completed Bus Off process."]
_1,
#[doc = "No such occurrence."] _0,
#[doc = "FlexCAN module has completed Bus Off process."] _1,
}
impl BOFFDONEINTW {
#[allow(missing_docs)]
@ -1510,8 +1455,7 @@ impl<'a> _BOFFDONEINTW<'a> {
}
#[doc = "Values that can be written to the field `ERRINT_FAST`"]
pub enum ERRINT_FASTW {
#[doc = "No such occurrence."]
_0,
#[doc = "No such occurrence."] _0,
#[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."]
_1,
}
@ -1568,10 +1512,8 @@ impl<'a> _ERRINT_FASTW<'a> {
}
#[doc = "Values that can be written to the field `ERROVR`"]
pub enum ERROVRW {
#[doc = "Overrun has not occurred."]
_0,
#[doc = "Overrun has occurred."]
_1,
#[doc = "Overrun has not occurred."] _0,
#[doc = "Overrun has occurred."] _1,
}
impl ERROVRW {
#[allow(missing_docs)]

13
src/can0/esr2/mod.rs
View File

@ -6,14 +6,15 @@ impl super::ESR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `IMB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMBR {
#[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."]
_0,
#[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."] _0,
#[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
_1,
}
@ -59,10 +60,8 @@ impl IMBR {
#[doc = "Possible values of the field `VPS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum VPSR {
#[doc = "Contents of IMB and LPTM are invalid."]
_0,
#[doc = "Contents of IMB and LPTM are valid."]
_1,
#[doc = "Contents of IMB and LPTM are invalid."] _0,
#[doc = "Contents of IMB and LPTM are valid."] _1,
}
impl VPSR {
#[doc = r" Returns `true` if the bit is clear (0)"]

4
src/can0/fdcbt/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FDCBT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/fdcrc/mod.rs
View File

@ -6,7 +6,9 @@ impl super::FDCRC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

64
src/can0/fdctrl/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FDCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -65,10 +67,8 @@ impl TDCOFFR {
#[doc = "Possible values of the field `TDCFAIL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDCFAILR {
#[doc = "Measured loop delay is in range."]
_0,
#[doc = "Measured loop delay is out of range."]
_1,
#[doc = "Measured loop delay is in range."] _0,
#[doc = "Measured loop delay is out of range."] _1,
}
impl TDCFAILR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -112,10 +112,8 @@ impl TDCFAILR {
#[doc = "Possible values of the field `TDCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDCENR {
#[doc = "TDC is disabled"]
_0,
#[doc = "TDC is enabled"]
_1,
#[doc = "TDC is disabled"] _0,
#[doc = "TDC is enabled"] _1,
}
impl TDCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -159,14 +157,10 @@ impl TDCENR {
#[doc = "Possible values of the field `MBDSR0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MBDSR0R {
#[doc = "Selects 8 bytes per Message Buffer."]
_00,
#[doc = "Selects 16 bytes per Message Buffer."]
_01,
#[doc = "Selects 32 bytes per Message Buffer."]
_10,
#[doc = "Selects 64 bytes per Message Buffer."]
_11,
#[doc = "Selects 8 bytes per Message Buffer."] _00,
#[doc = "Selects 16 bytes per Message Buffer."] _01,
#[doc = "Selects 32 bytes per Message Buffer."] _10,
#[doc = "Selects 64 bytes per Message Buffer."] _11,
}
impl MBDSR0R {
#[doc = r" Value of the field as raw bits"]
@ -215,10 +209,8 @@ impl MBDSR0R {
#[doc = "Possible values of the field `FDRATE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FDRATER {
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
_0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
_1,
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1,
}
impl FDRATER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -276,10 +268,8 @@ impl<'a> _TDCOFFW<'a> {
}
#[doc = "Values that can be written to the field `TDCFAIL`"]
pub enum TDCFAILW {
#[doc = "Measured loop delay is in range."]
_0,
#[doc = "Measured loop delay is out of range."]
_1,
#[doc = "Measured loop delay is in range."] _0,
#[doc = "Measured loop delay is out of range."] _1,
}
impl TDCFAILW {
#[allow(missing_docs)]
@ -334,10 +324,8 @@ impl<'a> _TDCFAILW<'a> {
}
#[doc = "Values that can be written to the field `TDCEN`"]
pub enum TDCENW {
#[doc = "TDC is disabled"]
_0,
#[doc = "TDC is enabled"]
_1,
#[doc = "TDC is disabled"] _0,
#[doc = "TDC is enabled"] _1,
}
impl TDCENW {
#[allow(missing_docs)]
@ -392,14 +380,10 @@ impl<'a> _TDCENW<'a> {
}
#[doc = "Values that can be written to the field `MBDSR0`"]
pub enum MBDSR0W {
#[doc = "Selects 8 bytes per Message Buffer."]
_00,
#[doc = "Selects 16 bytes per Message Buffer."]
_01,
#[doc = "Selects 32 bytes per Message Buffer."]
_10,
#[doc = "Selects 64 bytes per Message Buffer."]
_11,
#[doc = "Selects 8 bytes per Message Buffer."] _00,
#[doc = "Selects 16 bytes per Message Buffer."] _01,
#[doc = "Selects 32 bytes per Message Buffer."] _10,
#[doc = "Selects 64 bytes per Message Buffer."] _11,
}
impl MBDSR0W {
#[allow(missing_docs)]
@ -458,10 +442,8 @@ impl<'a> _MBDSR0W<'a> {
}
#[doc = "Values that can be written to the field `FDRATE`"]
pub enum FDRATEW {
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
_0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
_1,
#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0,
#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1,
}
impl FDRATEW {
#[allow(missing_docs)]

4
src/can0/flt_dlc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FLT_DLC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

28
src/can0/flt_id1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FLT_ID1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,10 +56,8 @@ impl FLT_ID1R {
#[doc = "Possible values of the field `FLT_RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT_RTRR {
#[doc = "Reject remote frame (accept data frame)"]
_0,
#[doc = "Accept remote frame"]
_1,
#[doc = "Reject remote frame (accept data frame)"] _0,
#[doc = "Accept remote frame"] _1,
}
impl FLT_RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -101,10 +101,8 @@ impl FLT_RTRR {
#[doc = "Possible values of the field `FLT_IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLT_IDER {
#[doc = "Accept standard frame format"]
_0,
#[doc = "Accept extended frame format"]
_1,
#[doc = "Accept standard frame format"] _0,
#[doc = "Accept extended frame format"] _1,
}
impl FLT_IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -162,10 +160,8 @@ impl<'a> _FLT_ID1W<'a> {
}
#[doc = "Values that can be written to the field `FLT_RTR`"]
pub enum FLT_RTRW {
#[doc = "Reject remote frame (accept data frame)"]
_0,
#[doc = "Accept remote frame"]
_1,
#[doc = "Reject remote frame (accept data frame)"] _0,
#[doc = "Accept remote frame"] _1,
}
impl FLT_RTRW {
#[allow(missing_docs)]
@ -220,10 +216,8 @@ impl<'a> _FLT_RTRW<'a> {
}
#[doc = "Values that can be written to the field `FLT_IDE`"]
pub enum FLT_IDEW {
#[doc = "Accept standard frame format"]
_0,
#[doc = "Accept extended frame format"]
_1,
#[doc = "Accept standard frame format"] _0,
#[doc = "Accept extended frame format"] _1,
}
impl FLT_IDEW {
#[allow(missing_docs)]

28
src/can0/flt_id2_idmask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::FLT_ID2_IDMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,10 +56,8 @@ impl FLT_ID2_IDMASKR {
#[doc = "Possible values of the field `RTR_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTR_MSKR {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
#[doc = "The corresponding bit in the filter is \"don't care\""] _0,
#[doc = "The corresponding bit in the filter is checked"] _1,
}
impl RTR_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -101,10 +101,8 @@ impl RTR_MSKR {
#[doc = "Possible values of the field `IDE_MSK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDE_MSKR {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
#[doc = "The corresponding bit in the filter is \"don't care\""] _0,
#[doc = "The corresponding bit in the filter is checked"] _1,
}
impl IDE_MSKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -162,10 +160,8 @@ impl<'a> _FLT_ID2_IDMASKW<'a> {
}
#[doc = "Values that can be written to the field `RTR_MSK`"]
pub enum RTR_MSKW {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
#[doc = "The corresponding bit in the filter is \"don't care\""] _0,
#[doc = "The corresponding bit in the filter is checked"] _1,
}
impl RTR_MSKW {
#[allow(missing_docs)]
@ -220,10 +216,8 @@ impl<'a> _RTR_MSKW<'a> {
}
#[doc = "Values that can be written to the field `IDE_MSK`"]
pub enum IDE_MSKW {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
#[doc = "The corresponding bit in the filter is \"don't care\""] _0,
#[doc = "The corresponding bit in the filter is checked"] _1,
}
impl IDE_MSKW {
#[allow(missing_docs)]

4
src/can0/iflag1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::IFLAG1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/imask1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::IMASK1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

166
src/can0/mcr/mod.rs
View File

@ -22,7 +22,9 @@ impl super::MCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,14 +56,11 @@ impl MAXMBR {
#[doc = "Possible values of the field `IDAM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDAMR {
#[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."]
_00,
#[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00,
#[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."]
_01,
#[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."]
_10,
#[doc = "Format D: All frames rejected."]
_11,
#[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10,
#[doc = "Format D: All frames rejected."] _11,
}
impl IDAMR {
#[doc = r" Value of the field as raw bits"]
@ -157,10 +156,8 @@ impl FDENR {
#[doc = "Possible values of the field `AEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AENR {
#[doc = "Abort disabled."]
_0,
#[doc = "Abort enabled."]
_1,
#[doc = "Abort disabled."] _0,
#[doc = "Abort enabled."] _1,
}
impl AENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -204,10 +201,8 @@ impl AENR {
#[doc = "Possible values of the field `LPRIOEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPRIOENR {
#[doc = "Local Priority disabled."]
_0,
#[doc = "Local Priority enabled."]
_1,
#[doc = "Local Priority disabled."] _0,
#[doc = "Local Priority enabled."] _1,
}
impl LPRIOENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -251,10 +246,8 @@ impl LPRIOENR {
#[doc = "Possible values of the field `PNET_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PNET_ENR {
#[doc = "Pretended Networking mode is disabled."]
_0,
#[doc = "Pretended Networking mode is enabled."]
_1,
#[doc = "Pretended Networking mode is disabled."] _0,
#[doc = "Pretended Networking mode is enabled."] _1,
}
impl PNET_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -298,10 +291,8 @@ impl PNET_ENR {
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "DMA feature for RX FIFO disabled."]
_0,
#[doc = "DMA feature for RX FIFO enabled."]
_1,
#[doc = "DMA feature for RX FIFO disabled."] _0,
#[doc = "DMA feature for RX FIFO enabled."] _1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -347,8 +338,7 @@ impl DMAR {
pub enum IRMQR {
#[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."]
_0,
#[doc = "Individual Rx masking and queue feature are enabled."]
_1,
#[doc = "Individual Rx masking and queue feature are enabled."] _1,
}
impl IRMQR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -392,10 +382,8 @@ impl IRMQR {
#[doc = "Possible values of the field `SRXDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRXDISR {
#[doc = "Self reception enabled."]
_0,
#[doc = "Self reception disabled."]
_1,
#[doc = "Self reception enabled."] _0,
#[doc = "Self reception disabled."] _1,
}
impl SRXDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -439,10 +427,8 @@ impl SRXDISR {
#[doc = "Possible values of the field `LPMACK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPMACKR {
#[doc = "FlexCAN is not in a low-power mode."]
_0,
#[doc = "FlexCAN is in a low-power mode."]
_1,
#[doc = "FlexCAN is not in a low-power mode."] _0,
#[doc = "FlexCAN is in a low-power mode."] _1,
}
impl LPMACKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -554,10 +540,8 @@ impl SUPVR {
#[doc = "Possible values of the field `FRZACK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRZACKR {
#[doc = "FlexCAN not in Freeze mode, prescaler running."]
_0,
#[doc = "FlexCAN in Freeze mode, prescaler stopped."]
_1,
#[doc = "FlexCAN not in Freeze mode, prescaler running."] _0,
#[doc = "FlexCAN in Freeze mode, prescaler stopped."] _1,
}
impl FRZACKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -601,10 +585,8 @@ impl FRZACKR {
#[doc = "Possible values of the field `SOFTRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOFTRSTR {
#[doc = "No reset request."]
_0,
#[doc = "Resets the registers affected by soft reset."]
_1,
#[doc = "No reset request."] _0,
#[doc = "Resets the registers affected by soft reset."] _1,
}
impl SOFTRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -648,10 +630,8 @@ impl SOFTRSTR {
#[doc = "Possible values of the field `NOTRDY`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NOTRDYR {
#[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."]
_0,
#[doc = r" Reserved"]
_Reserved(bool),
#[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."] _0,
#[doc = r" Reserved"] _Reserved(bool),
}
impl NOTRDYR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -690,10 +670,8 @@ impl NOTRDYR {
#[doc = "Possible values of the field `HALT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HALTR {
#[doc = "No Freeze mode request."]
_0,
#[doc = "Enters Freeze mode if the FRZ bit is asserted."]
_1,
#[doc = "No Freeze mode request."] _0,
#[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1,
}
impl HALTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -737,10 +715,8 @@ impl HALTR {
#[doc = "Possible values of the field `RFEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RFENR {
#[doc = "Rx FIFO not enabled."]
_0,
#[doc = "Rx FIFO enabled."]
_1,
#[doc = "Rx FIFO not enabled."] _0,
#[doc = "Rx FIFO enabled."] _1,
}
impl RFENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -784,10 +760,8 @@ impl RFENR {
#[doc = "Possible values of the field `FRZ`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRZR {
#[doc = "Not enabled to enter Freeze mode."]
_0,
#[doc = "Enabled to enter Freeze mode."]
_1,
#[doc = "Not enabled to enter Freeze mode."] _0,
#[doc = "Enabled to enter Freeze mode."] _1,
}
impl FRZR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -831,10 +805,8 @@ impl FRZR {
#[doc = "Possible values of the field `MDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MDISR {
#[doc = "Enable the FlexCAN module."]
_0,
#[doc = "Disable the FlexCAN module."]
_1,
#[doc = "Enable the FlexCAN module."] _0,
#[doc = "Disable the FlexCAN module."] _1,
}
impl MDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -892,14 +864,11 @@ impl<'a> _MAXMBW<'a> {
}
#[doc = "Values that can be written to the field `IDAM`"]
pub enum IDAMW {
#[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."]
_00,
#[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."] _00,
#[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."]
_01,
#[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."]
_10,
#[doc = "Format D: All frames rejected."]
_11,
#[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."] _10,
#[doc = "Format D: All frames rejected."] _11,
}
impl IDAMW {
#[allow(missing_docs)]
@ -1016,10 +985,8 @@ impl<'a> _FDENW<'a> {
}
#[doc = "Values that can be written to the field `AEN`"]
pub enum AENW {
#[doc = "Abort disabled."]
_0,
#[doc = "Abort enabled."]
_1,
#[doc = "Abort disabled."] _0,
#[doc = "Abort enabled."] _1,
}
impl AENW {
#[allow(missing_docs)]
@ -1074,10 +1041,8 @@ impl<'a> _AENW<'a> {
}
#[doc = "Values that can be written to the field `LPRIOEN`"]
pub enum LPRIOENW {
#[doc = "Local Priority disabled."]
_0,
#[doc = "Local Priority enabled."]
_1,
#[doc = "Local Priority disabled."] _0,
#[doc = "Local Priority enabled."] _1,
}
impl LPRIOENW {
#[allow(missing_docs)]
@ -1132,10 +1097,8 @@ impl<'a> _LPRIOENW<'a> {
}
#[doc = "Values that can be written to the field `PNET_EN`"]
pub enum PNET_ENW {
#[doc = "Pretended Networking mode is disabled."]
_0,
#[doc = "Pretended Networking mode is enabled."]
_1,
#[doc = "Pretended Networking mode is disabled."] _0,
#[doc = "Pretended Networking mode is enabled."] _1,
}
impl PNET_ENW {
#[allow(missing_docs)]
@ -1190,10 +1153,8 @@ impl<'a> _PNET_ENW<'a> {
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "DMA feature for RX FIFO disabled."]
_0,
#[doc = "DMA feature for RX FIFO enabled."]
_1,
#[doc = "DMA feature for RX FIFO disabled."] _0,
#[doc = "DMA feature for RX FIFO enabled."] _1,
}
impl DMAW {
#[allow(missing_docs)]
@ -1250,8 +1211,7 @@ impl<'a> _DMAW<'a> {
pub enum IRMQW {
#[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."]
_0,
#[doc = "Individual Rx masking and queue feature are enabled."]
_1,
#[doc = "Individual Rx masking and queue feature are enabled."] _1,
}
impl IRMQW {
#[allow(missing_docs)]
@ -1306,10 +1266,8 @@ impl<'a> _IRMQW<'a> {
}
#[doc = "Values that can be written to the field `SRXDIS`"]
pub enum SRXDISW {
#[doc = "Self reception enabled."]
_0,
#[doc = "Self reception disabled."]
_1,
#[doc = "Self reception enabled."] _0,
#[doc = "Self reception disabled."] _1,
}
impl SRXDISW {
#[allow(missing_docs)]
@ -1445,10 +1403,8 @@ impl<'a> _SUPVW<'a> {
}
#[doc = "Values that can be written to the field `SOFTRST`"]
pub enum SOFTRSTW {
#[doc = "No reset request."]
_0,
#[doc = "Resets the registers affected by soft reset."]
_1,
#[doc = "No reset request."] _0,
#[doc = "Resets the registers affected by soft reset."] _1,
}
impl SOFTRSTW {
#[allow(missing_docs)]
@ -1503,10 +1459,8 @@ impl<'a> _SOFTRSTW<'a> {
}
#[doc = "Values that can be written to the field `HALT`"]
pub enum HALTW {
#[doc = "No Freeze mode request."]
_0,
#[doc = "Enters Freeze mode if the FRZ bit is asserted."]
_1,
#[doc = "No Freeze mode request."] _0,
#[doc = "Enters Freeze mode if the FRZ bit is asserted."] _1,
}
impl HALTW {
#[allow(missing_docs)]
@ -1561,10 +1515,8 @@ impl<'a> _HALTW<'a> {
}
#[doc = "Values that can be written to the field `RFEN`"]
pub enum RFENW {
#[doc = "Rx FIFO not enabled."]
_0,
#[doc = "Rx FIFO enabled."]
_1,
#[doc = "Rx FIFO not enabled."] _0,
#[doc = "Rx FIFO enabled."] _1,
}
impl RFENW {
#[allow(missing_docs)]
@ -1619,10 +1571,8 @@ impl<'a> _RFENW<'a> {
}
#[doc = "Values that can be written to the field `FRZ`"]
pub enum FRZW {
#[doc = "Not enabled to enter Freeze mode."]
_0,
#[doc = "Enabled to enter Freeze mode."]
_1,
#[doc = "Not enabled to enter Freeze mode."] _0,
#[doc = "Enabled to enter Freeze mode."] _1,
}
impl FRZW {
#[allow(missing_docs)]
@ -1677,10 +1627,8 @@ impl<'a> _FRZW<'a> {
}
#[doc = "Values that can be written to the field `MDIS`"]
pub enum MDISW {
#[doc = "Enable the FlexCAN module."]
_0,
#[doc = "Disable the FlexCAN module."]
_1,
#[doc = "Enable the FlexCAN module."] _0,
#[doc = "Disable the FlexCAN module."] _1,
}
impl MDISW {
#[allow(missing_docs)]

177
src/can0/mod.rs
View File

@ -2,93 +2,53 @@ use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Module Configuration Register"]
pub mcr: MCR,
#[doc = "0x04 - Control 1 register"]
pub ctrl1: CTRL1,
#[doc = "0x08 - Free Running Timer"]
pub timer: TIMER,
#[doc = "0x00 - Module Configuration Register"] pub mcr: MCR,
#[doc = "0x04 - Control 1 register"] pub ctrl1: CTRL1,
#[doc = "0x08 - Free Running Timer"] pub timer: TIMER,
_reserved0: [u8; 4usize],
#[doc = "0x10 - Rx Mailboxes Global Mask Register"]
pub rxmgmask: RXMGMASK,
#[doc = "0x14 - Rx 14 Mask register"]
pub rx14mask: RX14MASK,
#[doc = "0x18 - Rx 15 Mask register"]
pub rx15mask: RX15MASK,
#[doc = "0x1c - Error Counter"]
pub ecr: ECR,
#[doc = "0x20 - Error and Status 1 register"]
pub esr1: ESR1,
#[doc = "0x10 - Rx Mailboxes Global Mask Register"] pub rxmgmask: RXMGMASK,
#[doc = "0x14 - Rx 14 Mask register"] pub rx14mask: RX14MASK,
#[doc = "0x18 - Rx 15 Mask register"] pub rx15mask: RX15MASK,
#[doc = "0x1c - Error Counter"] pub ecr: ECR,
#[doc = "0x20 - Error and Status 1 register"] pub esr1: ESR1,
_reserved1: [u8; 4usize],
#[doc = "0x28 - Interrupt Masks 1 register"]
pub imask1: IMASK1,
#[doc = "0x28 - Interrupt Masks 1 register"] pub imask1: IMASK1,
_reserved2: [u8; 4usize],
#[doc = "0x30 - Interrupt Flags 1 register"]
pub iflag1: IFLAG1,
#[doc = "0x34 - Control 2 register"]
pub ctrl2: CTRL2,
#[doc = "0x38 - Error and Status 2 register"]
pub esr2: ESR2,
#[doc = "0x30 - Interrupt Flags 1 register"] pub iflag1: IFLAG1,
#[doc = "0x34 - Control 2 register"] pub ctrl2: CTRL2,
#[doc = "0x38 - Error and Status 2 register"] pub esr2: ESR2,
_reserved3: [u8; 8usize],
#[doc = "0x44 - CRC Register"]
pub crcr: CRCR,
#[doc = "0x48 - Rx FIFO Global Mask register"]
pub rxfgmask: RXFGMASK,
#[doc = "0x4c - Rx FIFO Information Register"]
pub rxfir: RXFIR,
#[doc = "0x50 - CAN Bit Timing Register"]
pub cbt: CBT,
#[doc = "0x44 - CRC Register"] pub crcr: CRCR,
#[doc = "0x48 - Rx FIFO Global Mask register"] pub rxfgmask: RXFGMASK,
#[doc = "0x4c - Rx FIFO Information Register"] pub rxfir: RXFIR,
#[doc = "0x50 - CAN Bit Timing Register"] pub cbt: CBT,
_reserved4: [u8; 44usize],
#[doc = "0x80 - Embedded RAM"]
pub embedded_ram: [EMBEDDEDRAM; 128],
#[doc = "0x80 - Embedded RAM"] pub embedded_ram: [EMBEDDEDRAM; 128],
_reserved5: [u8; 1536usize],
#[doc = "0x880 - Rx Individual Mask Registers"]
pub rximr0: RXIMR0,
#[doc = "0x884 - Rx Individual Mask Registers"]
pub rximr1: RXIMR1,
#[doc = "0x888 - Rx Individual Mask Registers"]
pub rximr2: RXIMR2,
#[doc = "0x88c - Rx Individual Mask Registers"]
pub rximr3: RXIMR3,
#[doc = "0x890 - Rx Individual Mask Registers"]
pub rximr4: RXIMR4,
#[doc = "0x894 - Rx Individual Mask Registers"]
pub rximr5: RXIMR5,
#[doc = "0x898 - Rx Individual Mask Registers"]
pub rximr6: RXIMR6,
#[doc = "0x89c - Rx Individual Mask Registers"]
pub rximr7: RXIMR7,
#[doc = "0x8a0 - Rx Individual Mask Registers"]
pub rximr8: RXIMR8,
#[doc = "0x8a4 - Rx Individual Mask Registers"]
pub rximr9: RXIMR9,
#[doc = "0x8a8 - Rx Individual Mask Registers"]
pub rximr10: RXIMR10,
#[doc = "0x8ac - Rx Individual Mask Registers"]
pub rximr11: RXIMR11,
#[doc = "0x8b0 - Rx Individual Mask Registers"]
pub rximr12: RXIMR12,
#[doc = "0x8b4 - Rx Individual Mask Registers"]
pub rximr13: RXIMR13,
#[doc = "0x8b8 - Rx Individual Mask Registers"]
pub rximr14: RXIMR14,
#[doc = "0x8bc - Rx Individual Mask Registers"]
pub rximr15: RXIMR15,
#[doc = "0x880 - Rx Individual Mask Registers"] pub rximr0: RXIMR0,
#[doc = "0x884 - Rx Individual Mask Registers"] pub rximr1: RXIMR1,
#[doc = "0x888 - Rx Individual Mask Registers"] pub rximr2: RXIMR2,
#[doc = "0x88c - Rx Individual Mask Registers"] pub rximr3: RXIMR3,
#[doc = "0x890 - Rx Individual Mask Registers"] pub rximr4: RXIMR4,
#[doc = "0x894 - Rx Individual Mask Registers"] pub rximr5: RXIMR5,
#[doc = "0x898 - Rx Individual Mask Registers"] pub rximr6: RXIMR6,
#[doc = "0x89c - Rx Individual Mask Registers"] pub rximr7: RXIMR7,
#[doc = "0x8a0 - Rx Individual Mask Registers"] pub rximr8: RXIMR8,
#[doc = "0x8a4 - Rx Individual Mask Registers"] pub rximr9: RXIMR9,
#[doc = "0x8a8 - Rx Individual Mask Registers"] pub rximr10: RXIMR10,
#[doc = "0x8ac - Rx Individual Mask Registers"] pub rximr11: RXIMR11,
#[doc = "0x8b0 - Rx Individual Mask Registers"] pub rximr12: RXIMR12,
#[doc = "0x8b4 - Rx Individual Mask Registers"] pub rximr13: RXIMR13,
#[doc = "0x8b8 - Rx Individual Mask Registers"] pub rximr14: RXIMR14,
#[doc = "0x8bc - Rx Individual Mask Registers"] pub rximr15: RXIMR15,
_reserved6: [u8; 576usize],
#[doc = "0xb00 - Pretended Networking Control 1 Register"]
pub ctrl1_pn: CTRL1_PN,
#[doc = "0xb04 - Pretended Networking Control 2 Register"]
pub ctrl2_pn: CTRL2_PN,
#[doc = "0xb08 - Pretended Networking Wake Up Match Register"]
pub wu_mtc: WU_MTC,
#[doc = "0xb0c - Pretended Networking ID Filter 1 Register"]
pub flt_id1: FLT_ID1,
#[doc = "0xb10 - Pretended Networking DLC Filter Register"]
pub flt_dlc: FLT_DLC,
#[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"]
pub pl1_lo: PL1_LO,
#[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"]
pub pl1_hi: PL1_HI,
#[doc = "0xb00 - Pretended Networking Control 1 Register"] pub ctrl1_pn: CTRL1_PN,
#[doc = "0xb04 - Pretended Networking Control 2 Register"] pub ctrl2_pn: CTRL2_PN,
#[doc = "0xb08 - Pretended Networking Wake Up Match Register"] pub wu_mtc: WU_MTC,
#[doc = "0xb0c - Pretended Networking ID Filter 1 Register"] pub flt_id1: FLT_ID1,
#[doc = "0xb10 - Pretended Networking DLC Filter Register"] pub flt_dlc: FLT_DLC,
#[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"] pub pl1_lo: PL1_LO,
#[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"] pub pl1_hi: PL1_HI,
#[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub flt_id2_idmask: FLT_ID2_IDMASK,
#[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
@ -96,45 +56,26 @@ pub struct RegisterBlock {
#[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub pl2_plmask_hi: PL2_PLMASK_HI,
_reserved7: [u8; 24usize],
#[doc = "0xb40 - Wake Up Message Buffer Register for C/S"]
pub wmb0_cs: WMB0_CS,
#[doc = "0xb44 - Wake Up Message Buffer Register for ID"]
pub wmb0_id: WMB0_ID,
#[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb0_d03: WMB0_D03,
#[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"]
pub wmb0_d47: WMB0_D47,
#[doc = "0xb50 - Wake Up Message Buffer Register for C/S"]
pub wmb1_cs: WMB1_CS,
#[doc = "0xb54 - Wake Up Message Buffer Register for ID"]
pub wmb1_id: WMB1_ID,
#[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb1_d03: WMB1_D03,
#[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"]
pub wmb1_d47: WMB1_D47,
#[doc = "0xb60 - Wake Up Message Buffer Register for C/S"]
pub wmb2_cs: WMB2_CS,
#[doc = "0xb64 - Wake Up Message Buffer Register for ID"]
pub wmb2_id: WMB2_ID,
#[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb2_d03: WMB2_D03,
#[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"]
pub wmb2_d47: WMB2_D47,
#[doc = "0xb70 - Wake Up Message Buffer Register for C/S"]
pub wmb3_cs: WMB3_CS,
#[doc = "0xb74 - Wake Up Message Buffer Register for ID"]
pub wmb3_id: WMB3_ID,
#[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb3_d03: WMB3_D03,
#[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"]
pub wmb3_d47: WMB3_D47,
#[doc = "0xb40 - Wake Up Message Buffer Register for C/S"] pub wmb0_cs: WMB0_CS,
#[doc = "0xb44 - Wake Up Message Buffer Register for ID"] pub wmb0_id: WMB0_ID,
#[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"] pub wmb0_d03: WMB0_D03,
#[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"] pub wmb0_d47: WMB0_D47,
#[doc = "0xb50 - Wake Up Message Buffer Register for C/S"] pub wmb1_cs: WMB1_CS,
#[doc = "0xb54 - Wake Up Message Buffer Register for ID"] pub wmb1_id: WMB1_ID,
#[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"] pub wmb1_d03: WMB1_D03,
#[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"] pub wmb1_d47: WMB1_D47,
#[doc = "0xb60 - Wake Up Message Buffer Register for C/S"] pub wmb2_cs: WMB2_CS,
#[doc = "0xb64 - Wake Up Message Buffer Register for ID"] pub wmb2_id: WMB2_ID,
#[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"] pub wmb2_d03: WMB2_D03,
#[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"] pub wmb2_d47: WMB2_D47,
#[doc = "0xb70 - Wake Up Message Buffer Register for C/S"] pub wmb3_cs: WMB3_CS,
#[doc = "0xb74 - Wake Up Message Buffer Register for ID"] pub wmb3_id: WMB3_ID,
#[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"] pub wmb3_d03: WMB3_D03,
#[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"] pub wmb3_d47: WMB3_D47,
_reserved8: [u8; 128usize],
#[doc = "0xc00 - CAN FD Control Register"]
pub fdctrl: FDCTRL,
#[doc = "0xc04 - CAN FD Bit Timing Register"]
pub fdcbt: FDCBT,
#[doc = "0xc08 - CAN FD CRC Register"]
pub fdcrc: FDCRC,
#[doc = "0xc00 - CAN FD Control Register"] pub fdctrl: FDCTRL,
#[doc = "0xc04 - CAN FD Bit Timing Register"] pub fdcbt: FDCBT,
#[doc = "0xc08 - CAN FD CRC Register"] pub fdcrc: FDCRC,
}
#[doc = "Module Configuration Register"]
pub struct MCR {

4
src/can0/pl1_hi/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PL1_HI {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl1_lo/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PL1_LO {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl2_plmask_hi/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PL2_PLMASK_HI {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl2_plmask_lo/mod.rs
View File

@ -22,7 +22,9 @@ impl super::PL2_PLMASK_LO {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rx14mask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RX14MASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rx15mask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RX15MASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxfgmask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXFGMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxfir/mod.rs
View File

@ -6,7 +6,9 @@ impl super::RXFIR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/rximr0/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr1/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr10/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR10 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr11/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR11 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr12/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR12 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr13/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR13 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr14/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR14 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr15/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR15 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr2/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr3/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR3 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr4/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR4 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr5/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR5 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr6/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR6 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr7/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR7 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr8/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR8 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rximr9/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXIMR9 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxmgmask/mod.rs
View File

@ -22,7 +22,9 @@ impl super::RXMGMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/timer/mod.rs
View File

@ -22,7 +22,9 @@ impl super::TIMER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]

16
src/can0/wmb0_cs/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB0_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
@ -23,10 +25,8 @@ impl DLCR {
#[doc = "Possible values of the field `RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTRR {
#[doc = "Frame is data one (not remote)"]
_0,
#[doc = "Frame is a remote one"]
_1,
#[doc = "Frame is data one (not remote)"] _0,
#[doc = "Frame is a remote one"] _1,
}
impl RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -70,10 +70,8 @@ impl RTRR {
#[doc = "Possible values of the field `IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDER {
#[doc = "Frame format is standard"]
_0,
#[doc = "Frame format is extended"]
_1,
#[doc = "Frame format is standard"] _0,
#[doc = "Frame format is extended"] _1,
}
impl IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]

4
src/can0/wmb0_d03/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB0_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb0_d47/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB0_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb0_id/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB0_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

16
src/can0/wmb1_cs/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB1_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
@ -23,10 +25,8 @@ impl DLCR {
#[doc = "Possible values of the field `RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTRR {
#[doc = "Frame is data one (not remote)"]
_0,
#[doc = "Frame is a remote one"]
_1,
#[doc = "Frame is data one (not remote)"] _0,
#[doc = "Frame is a remote one"] _1,
}
impl RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -70,10 +70,8 @@ impl RTRR {
#[doc = "Possible values of the field `IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDER {
#[doc = "Frame format is standard"]
_0,
#[doc = "Frame format is extended"]
_1,
#[doc = "Frame format is standard"] _0,
#[doc = "Frame format is extended"] _1,
}
impl IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]

4
src/can0/wmb1_d03/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB1_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_d47/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB1_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_id/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB1_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

16
src/can0/wmb2_cs/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB2_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
@ -23,10 +25,8 @@ impl DLCR {
#[doc = "Possible values of the field `RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTRR {
#[doc = "Frame is data one (not remote)"]
_0,
#[doc = "Frame is a remote one"]
_1,
#[doc = "Frame is data one (not remote)"] _0,
#[doc = "Frame is a remote one"] _1,
}
impl RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -70,10 +70,8 @@ impl RTRR {
#[doc = "Possible values of the field `IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDER {
#[doc = "Frame format is standard"]
_0,
#[doc = "Frame format is extended"]
_1,
#[doc = "Frame format is standard"] _0,
#[doc = "Frame format is extended"] _1,
}
impl IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]

4
src/can0/wmb2_d03/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB2_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_d47/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB2_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_id/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB2_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

16
src/can0/wmb3_cs/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB3_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
@ -23,10 +25,8 @@ impl DLCR {
#[doc = "Possible values of the field `RTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTRR {
#[doc = "Frame is data one (not remote)"]
_0,
#[doc = "Frame is a remote one"]
_1,
#[doc = "Frame is data one (not remote)"] _0,
#[doc = "Frame is a remote one"] _1,
}
impl RTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -70,10 +70,8 @@ impl RTRR {
#[doc = "Possible values of the field `IDE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDER {
#[doc = "Frame format is standard"]
_0,
#[doc = "Frame format is extended"]
_1,
#[doc = "Frame format is standard"] _0,
#[doc = "Frame format is extended"] _1,
}
impl IDER {
#[doc = r" Returns `true` if the bit is clear (0)"]

4
src/can0/wmb3_d03/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB3_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_d47/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB3_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_id/mod.rs
View File

@ -6,7 +6,9 @@ impl super::WMB3_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]

28
src/can0/wu_mtc/mod.rs
View File

@ -22,7 +22,9 @@ impl super::WU_MTC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
@ -54,10 +56,8 @@ impl MCOUNTERR {
#[doc = "Possible values of the field `WUMF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WUMFR {
#[doc = "No wake up by match event detected"]
_0,
#[doc = "Wake up by match event detected"]
_1,
#[doc = "No wake up by match event detected"] _0,
#[doc = "Wake up by match event detected"] _1,
}
impl WUMFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -101,10 +101,8 @@ impl WUMFR {
#[doc = "Possible values of the field `WTOF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WTOFR {
#[doc = "No wake up by timeout event detected"]
_0,
#[doc = "Wake up by timeout event detected"]
_1,
#[doc = "No wake up by timeout event detected"] _0,
#[doc = "Wake up by timeout event detected"] _1,
}
impl WTOFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -147,10 +145,8 @@ impl WTOFR {
}
#[doc = "Values that can be written to the field `WUMF`"]
pub enum WUMFW {
#[doc = "No wake up by match event detected"]
_0,
#[doc = "Wake up by match event detected"]
_1,
#[doc = "No wake up by match event detected"] _0,
#[doc = "Wake up by match event detected"] _1,
}
impl WUMFW {
#[allow(missing_docs)]
@ -205,10 +201,8 @@ impl<'a> _WUMFW<'a> {
}
#[doc = "Values that can be written to the field `WTOF`"]
pub enum WTOFW {
#[doc = "No wake up by timeout event detected"]
_0,
#[doc = "Wake up by timeout event detected"]
_1,
#[doc = "No wake up by timeout event detected"] _0,
#[doc = "Wake up by timeout event detected"] _1,
}
impl WTOFW {
#[allow(missing_docs)]