Run with updated version of rustfmt
This commit is contained in:
Kjetil Kjeka
@ -22,7 +22,9 @@ impl super::BASE_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CFG1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -43,14 +45,10 @@ impl super::CFG1 {
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#[doc = "Possible values of the field `ADICLK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADICLKR {
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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_00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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_01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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_10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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_11,
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11,
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}
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impl ADICLKR {
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#[doc = r" Value of the field as raw bits"]
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@ -99,14 +97,10 @@ impl ADICLKR {
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#[doc = "Possible values of the field `MODE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MODER {
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#[doc = "8-bit conversion."]
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_00,
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#[doc = "12-bit conversion."]
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_01,
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#[doc = "10-bit conversion."]
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_10,
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#[doc = r" Reserved"]
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_Reserved(u8),
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#[doc = "8-bit conversion."] _00,
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#[doc = "12-bit conversion."] _01,
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#[doc = "10-bit conversion."] _10,
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#[doc = r" Reserved"] _Reserved(u8),
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}
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impl MODER {
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#[doc = r" Value of the field as raw bits"]
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@ -149,14 +143,10 @@ impl MODER {
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#[doc = "Possible values of the field `ADIV`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ADIVR {
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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_00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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_01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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_10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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_11,
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#[doc = "The divide ratio is 1 and the clock rate is input clock."] _00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11,
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}
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impl ADIVR {
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#[doc = r" Value of the field as raw bits"]
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@ -204,14 +194,10 @@ impl ADIVR {
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}
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#[doc = "Values that can be written to the field `ADICLK`"]
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pub enum ADICLKW {
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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_00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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_01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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_10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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_11,
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"] _00,
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"] _01,
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"] _10,
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"] _11,
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}
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impl ADICLKW {
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#[allow(missing_docs)]
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@ -270,12 +256,9 @@ impl<'a> _ADICLKW<'a> {
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}
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#[doc = "Values that can be written to the field `MODE`"]
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pub enum MODEW {
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#[doc = "8-bit conversion."]
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_00,
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#[doc = "12-bit conversion."]
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_01,
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#[doc = "10-bit conversion."]
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_10,
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#[doc = "8-bit conversion."] _00,
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#[doc = "12-bit conversion."] _01,
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#[doc = "10-bit conversion."] _10,
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}
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impl MODEW {
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#[allow(missing_docs)]
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@ -326,14 +309,10 @@ impl<'a> _MODEW<'a> {
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}
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#[doc = "Values that can be written to the field `ADIV`"]
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pub enum ADIVW {
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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_00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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_01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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_10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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_11,
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#[doc = "The divide ratio is 1 and the clock rate is input clock."] _00,
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] _01,
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] _10,
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] _11,
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}
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impl ADIVW {
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#[allow(missing_docs)]
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@ -22,7 +22,9 @@ impl super::CFG2 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP0 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP0_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP1_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP2 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP2_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP3 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP3_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP9 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLP9_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLPS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLPS_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLPX {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CLPX_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::CV {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,7 +22,9 @@ impl super::G {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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177
src/adc0/mod.rs
177
src/adc0/mod.rs
@ -2,124 +2,77 @@ use vcell::VolatileCell;
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - ADC Status and Control Register 1"]
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pub sc1a: SC1,
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#[doc = "0x04 - ADC Status and Control Register 1"]
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pub sc1b: SC1,
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#[doc = "0x08 - ADC Status and Control Register 1"]
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pub sc1c: SC1,
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#[doc = "0x0c - ADC Status and Control Register 1"]
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pub sc1d: SC1,
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#[doc = "0x10 - ADC Status and Control Register 1"]
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pub sc1e: SC1,
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#[doc = "0x14 - ADC Status and Control Register 1"]
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pub sc1f: SC1,
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#[doc = "0x18 - ADC Status and Control Register 1"]
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pub sc1g: SC1,
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#[doc = "0x1c - ADC Status and Control Register 1"]
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pub sc1h: SC1,
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#[doc = "0x20 - ADC Status and Control Register 1"]
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pub sc1i: SC1,
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#[doc = "0x24 - ADC Status and Control Register 1"]
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pub sc1j: SC1,
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#[doc = "0x28 - ADC Status and Control Register 1"]
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pub sc1k: SC1,
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#[doc = "0x2c - ADC Status and Control Register 1"]
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pub sc1l: SC1,
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#[doc = "0x30 - ADC Status and Control Register 1"]
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pub sc1m: SC1,
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#[doc = "0x34 - ADC Status and Control Register 1"]
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pub sc1n: SC1,
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#[doc = "0x38 - ADC Status and Control Register 1"]
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pub sc1o: SC1,
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#[doc = "0x3c - ADC Status and Control Register 1"]
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pub sc1p: SC1,
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#[doc = "0x40 - ADC Configuration Register 1"]
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pub cfg1: CFG1,
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#[doc = "0x44 - ADC Configuration Register 2"]
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pub cfg2: CFG2,
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#[doc = "0x48 - ADC Data Result Registers"]
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pub ra: R,
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#[doc = "0x4c - ADC Data Result Registers"]
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pub rb: R,
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#[doc = "0x50 - ADC Data Result Registers"]
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pub rc: R,
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#[doc = "0x54 - ADC Data Result Registers"]
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pub rd: R,
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#[doc = "0x58 - ADC Data Result Registers"]
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pub re: R,
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#[doc = "0x5c - ADC Data Result Registers"]
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pub rf: R,
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#[doc = "0x60 - ADC Data Result Registers"]
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pub rg: R,
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#[doc = "0x64 - ADC Data Result Registers"]
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pub rh: R,
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#[doc = "0x68 - ADC Data Result Registers"]
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pub ri: R,
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#[doc = "0x6c - ADC Data Result Registers"]
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pub rj: R,
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#[doc = "0x70 - ADC Data Result Registers"]
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pub rk: R,
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#[doc = "0x74 - ADC Data Result Registers"]
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pub rl: R,
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#[doc = "0x78 - ADC Data Result Registers"]
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pub rm: R,
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#[doc = "0x7c - ADC Data Result Registers"]
|
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pub rn: R,
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#[doc = "0x80 - ADC Data Result Registers"]
|
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pub ro: R,
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#[doc = "0x84 - ADC Data Result Registers"]
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pub rp: R,
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#[doc = "0x88 - Compare Value Registers"]
|
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pub cv1: CV,
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#[doc = "0x8c - Compare Value Registers"]
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pub cv2: CV,
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#[doc = "0x90 - Status and Control Register 2"]
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pub sc2: SC2,
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#[doc = "0x94 - Status and Control Register 3"]
|
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pub sc3: SC3,
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#[doc = "0x98 - BASE Offset Register"]
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pub base_ofs: BASE_OFS,
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#[doc = "0x9c - ADC Offset Correction Register"]
|
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pub ofs: OFS,
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#[doc = "0xa0 - USER Offset Correction Register"]
|
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pub usr_ofs: USR_OFS,
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#[doc = "0xa4 - ADC X Offset Correction Register"]
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pub xofs: XOFS,
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#[doc = "0xa8 - ADC Y Offset Correction Register"]
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pub yofs: YOFS,
|
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#[doc = "0xac - ADC Gain Register"]
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pub g: G,
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#[doc = "0xb0 - ADC User Gain Register"]
|
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pub ug: UG,
|
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#[doc = "0xb4 - ADC General Calibration Value Register S"]
|
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pub clps: CLPS,
|
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#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
|
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pub clp3: CLP3,
|
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#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
|
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pub clp2: CLP2,
|
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#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
|
||||
pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
|
||||
pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0x00 - ADC Status and Control Register 1"] pub sc1a: SC1,
|
||||
#[doc = "0x04 - ADC Status and Control Register 1"] pub sc1b: SC1,
|
||||
#[doc = "0x08 - ADC Status and Control Register 1"] pub sc1c: SC1,
|
||||
#[doc = "0x0c - ADC Status and Control Register 1"] pub sc1d: SC1,
|
||||
#[doc = "0x10 - ADC Status and Control Register 1"] pub sc1e: SC1,
|
||||
#[doc = "0x14 - ADC Status and Control Register 1"] pub sc1f: SC1,
|
||||
#[doc = "0x18 - ADC Status and Control Register 1"] pub sc1g: SC1,
|
||||
#[doc = "0x1c - ADC Status and Control Register 1"] pub sc1h: SC1,
|
||||
#[doc = "0x20 - ADC Status and Control Register 1"] pub sc1i: SC1,
|
||||
#[doc = "0x24 - ADC Status and Control Register 1"] pub sc1j: SC1,
|
||||
#[doc = "0x28 - ADC Status and Control Register 1"] pub sc1k: SC1,
|
||||
#[doc = "0x2c - ADC Status and Control Register 1"] pub sc1l: SC1,
|
||||
#[doc = "0x30 - ADC Status and Control Register 1"] pub sc1m: SC1,
|
||||
#[doc = "0x34 - ADC Status and Control Register 1"] pub sc1n: SC1,
|
||||
#[doc = "0x38 - ADC Status and Control Register 1"] pub sc1o: SC1,
|
||||
#[doc = "0x3c - ADC Status and Control Register 1"] pub sc1p: SC1,
|
||||
#[doc = "0x40 - ADC Configuration Register 1"] pub cfg1: CFG1,
|
||||
#[doc = "0x44 - ADC Configuration Register 2"] pub cfg2: CFG2,
|
||||
#[doc = "0x48 - ADC Data Result Registers"] pub ra: R,
|
||||
#[doc = "0x4c - ADC Data Result Registers"] pub rb: R,
|
||||
#[doc = "0x50 - ADC Data Result Registers"] pub rc: R,
|
||||
#[doc = "0x54 - ADC Data Result Registers"] pub rd: R,
|
||||
#[doc = "0x58 - ADC Data Result Registers"] pub re: R,
|
||||
#[doc = "0x5c - ADC Data Result Registers"] pub rf: R,
|
||||
#[doc = "0x60 - ADC Data Result Registers"] pub rg: R,
|
||||
#[doc = "0x64 - ADC Data Result Registers"] pub rh: R,
|
||||
#[doc = "0x68 - ADC Data Result Registers"] pub ri: R,
|
||||
#[doc = "0x6c - ADC Data Result Registers"] pub rj: R,
|
||||
#[doc = "0x70 - ADC Data Result Registers"] pub rk: R,
|
||||
#[doc = "0x74 - ADC Data Result Registers"] pub rl: R,
|
||||
#[doc = "0x78 - ADC Data Result Registers"] pub rm: R,
|
||||
#[doc = "0x7c - ADC Data Result Registers"] pub rn: R,
|
||||
#[doc = "0x80 - ADC Data Result Registers"] pub ro: R,
|
||||
#[doc = "0x84 - ADC Data Result Registers"] pub rp: R,
|
||||
#[doc = "0x88 - Compare Value Registers"] pub cv1: CV,
|
||||
#[doc = "0x8c - Compare Value Registers"] pub cv2: CV,
|
||||
#[doc = "0x90 - Status and Control Register 2"] pub sc2: SC2,
|
||||
#[doc = "0x94 - Status and Control Register 3"] pub sc3: SC3,
|
||||
#[doc = "0x98 - BASE Offset Register"] pub base_ofs: BASE_OFS,
|
||||
#[doc = "0x9c - ADC Offset Correction Register"] pub ofs: OFS,
|
||||
#[doc = "0xa0 - USER Offset Correction Register"] pub usr_ofs: USR_OFS,
|
||||
#[doc = "0xa4 - ADC X Offset Correction Register"] pub xofs: XOFS,
|
||||
#[doc = "0xa8 - ADC Y Offset Correction Register"] pub yofs: YOFS,
|
||||
#[doc = "0xac - ADC Gain Register"] pub g: G,
|
||||
#[doc = "0xb0 - ADC User Gain Register"] pub ug: UG,
|
||||
#[doc = "0xb4 - ADC General Calibration Value Register S"] pub clps: CLPS,
|
||||
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] pub clp3: CLP3,
|
||||
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] pub clp2: CLP2,
|
||||
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"] pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub clp3_ofs: CLP3_OFS,
|
||||
pub clp3_ofs:
|
||||
CLP3_OFS,
|
||||
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub clp2_ofs: CLP2_OFS,
|
||||
pub clp2_ofs:
|
||||
CLP2_OFS,
|
||||
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub clp1_ofs: CLP1_OFS,
|
||||
pub clp1_ofs:
|
||||
CLP1_OFS,
|
||||
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub clp0_ofs: CLP0_OFS,
|
||||
pub clp0_ofs:
|
||||
CLP0_OFS,
|
||||
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub clpx_ofs: CLPX_OFS,
|
||||
pub clpx_ofs:
|
||||
CLPX_OFS,
|
||||
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub clp9_ofs: CLP9_OFS,
|
||||
pub clp9_ofs:
|
||||
CLP9_OFS,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub struct SC1 {
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::OFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -6,7 +6,9 @@ impl super::R {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SC1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,62 +45,36 @@ impl super::SC1 {
|
||||
#[doc = "Possible values of the field `ADCH`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADCHR {
|
||||
#[doc = "Exernal channel 0 is selected as input."]
|
||||
_00000,
|
||||
#[doc = "Exernal channel 1 is selected as input."]
|
||||
_00001,
|
||||
#[doc = "Exernal channel 2 is selected as input."]
|
||||
_00010,
|
||||
#[doc = "Exernal channel 3 is selected as input."]
|
||||
_00011,
|
||||
#[doc = "Exernal channel 4 is selected as input."]
|
||||
_00100,
|
||||
#[doc = "Exernal channel 5 is selected as input."]
|
||||
_00101,
|
||||
#[doc = "Exernal channel 6 is selected as input."]
|
||||
_00110,
|
||||
#[doc = "Exernal channel 7 is selected as input."]
|
||||
_00111,
|
||||
#[doc = "Exernal channel 8 is selected as input."]
|
||||
_01000,
|
||||
#[doc = "Exernal channel 9 is selected as input."]
|
||||
_01001,
|
||||
#[doc = "Exernal channel 10 is selected as input."]
|
||||
_01010,
|
||||
#[doc = "Exernal channel 11 is selected as input."]
|
||||
_01011,
|
||||
#[doc = "Exernal channel 12 is selected as input."]
|
||||
_01100,
|
||||
#[doc = "Exernal channel 13 is selected as input."]
|
||||
_01101,
|
||||
#[doc = "Exernal channel 14 is selected as input."]
|
||||
_01110,
|
||||
#[doc = "Exernal channel 15 is selected as input."]
|
||||
_01111,
|
||||
#[doc = "Exernal channel 18 is selected as input."]
|
||||
_10010,
|
||||
#[doc = "Exernal channel 19 is selected as input."]
|
||||
_10011,
|
||||
#[doc = "Internal channel 0 is selected as input."]
|
||||
_10101,
|
||||
#[doc = "Internal channel 1 is selected as input."]
|
||||
_10110,
|
||||
#[doc = "Internal channel 2 is selected as input."]
|
||||
_10111,
|
||||
#[doc = "Temp Sensor"]
|
||||
_11010,
|
||||
#[doc = "Band Gap"]
|
||||
_11011,
|
||||
#[doc = "Internal channel 3 is selected as input."]
|
||||
_11100,
|
||||
#[doc = "Exernal channel 0 is selected as input."] _00000,
|
||||
#[doc = "Exernal channel 1 is selected as input."] _00001,
|
||||
#[doc = "Exernal channel 2 is selected as input."] _00010,
|
||||
#[doc = "Exernal channel 3 is selected as input."] _00011,
|
||||
#[doc = "Exernal channel 4 is selected as input."] _00100,
|
||||
#[doc = "Exernal channel 5 is selected as input."] _00101,
|
||||
#[doc = "Exernal channel 6 is selected as input."] _00110,
|
||||
#[doc = "Exernal channel 7 is selected as input."] _00111,
|
||||
#[doc = "Exernal channel 8 is selected as input."] _01000,
|
||||
#[doc = "Exernal channel 9 is selected as input."] _01001,
|
||||
#[doc = "Exernal channel 10 is selected as input."] _01010,
|
||||
#[doc = "Exernal channel 11 is selected as input."] _01011,
|
||||
#[doc = "Exernal channel 12 is selected as input."] _01100,
|
||||
#[doc = "Exernal channel 13 is selected as input."] _01101,
|
||||
#[doc = "Exernal channel 14 is selected as input."] _01110,
|
||||
#[doc = "Exernal channel 15 is selected as input."] _01111,
|
||||
#[doc = "Exernal channel 18 is selected as input."] _10010,
|
||||
#[doc = "Exernal channel 19 is selected as input."] _10011,
|
||||
#[doc = "Internal channel 0 is selected as input."] _10101,
|
||||
#[doc = "Internal channel 1 is selected as input."] _10110,
|
||||
#[doc = "Internal channel 2 is selected as input."] _10111,
|
||||
#[doc = "Temp Sensor"] _11010,
|
||||
#[doc = "Band Gap"] _11011,
|
||||
#[doc = "Internal channel 3 is selected as input."] _11100,
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
_11101,
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
_11110,
|
||||
#[doc = "Module is disabled"]
|
||||
_11111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "Module is disabled"] _11111,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl ADCHR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -309,10 +285,8 @@ impl ADCHR {
|
||||
#[doc = "Possible values of the field `AIEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AIENR {
|
||||
#[doc = "Conversion complete interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Conversion complete interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Conversion complete interrupt is disabled."] _0,
|
||||
#[doc = "Conversion complete interrupt is enabled."] _1,
|
||||
}
|
||||
impl AIENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -356,10 +330,8 @@ impl AIENR {
|
||||
#[doc = "Possible values of the field `COCO`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum COCOR {
|
||||
#[doc = "Conversion is not completed."]
|
||||
_0,
|
||||
#[doc = "Conversion is completed."]
|
||||
_1,
|
||||
#[doc = "Conversion is not completed."] _0,
|
||||
#[doc = "Conversion is completed."] _1,
|
||||
}
|
||||
impl COCOR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -402,60 +374,35 @@ impl COCOR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADCH`"]
|
||||
pub enum ADCHW {
|
||||
#[doc = "Exernal channel 0 is selected as input."]
|
||||
_00000,
|
||||
#[doc = "Exernal channel 1 is selected as input."]
|
||||
_00001,
|
||||
#[doc = "Exernal channel 2 is selected as input."]
|
||||
_00010,
|
||||
#[doc = "Exernal channel 3 is selected as input."]
|
||||
_00011,
|
||||
#[doc = "Exernal channel 4 is selected as input."]
|
||||
_00100,
|
||||
#[doc = "Exernal channel 5 is selected as input."]
|
||||
_00101,
|
||||
#[doc = "Exernal channel 6 is selected as input."]
|
||||
_00110,
|
||||
#[doc = "Exernal channel 7 is selected as input."]
|
||||
_00111,
|
||||
#[doc = "Exernal channel 8 is selected as input."]
|
||||
_01000,
|
||||
#[doc = "Exernal channel 9 is selected as input."]
|
||||
_01001,
|
||||
#[doc = "Exernal channel 10 is selected as input."]
|
||||
_01010,
|
||||
#[doc = "Exernal channel 11 is selected as input."]
|
||||
_01011,
|
||||
#[doc = "Exernal channel 12 is selected as input."]
|
||||
_01100,
|
||||
#[doc = "Exernal channel 13 is selected as input."]
|
||||
_01101,
|
||||
#[doc = "Exernal channel 14 is selected as input."]
|
||||
_01110,
|
||||
#[doc = "Exernal channel 15 is selected as input."]
|
||||
_01111,
|
||||
#[doc = "Exernal channel 18 is selected as input."]
|
||||
_10010,
|
||||
#[doc = "Exernal channel 19 is selected as input."]
|
||||
_10011,
|
||||
#[doc = "Internal channel 0 is selected as input."]
|
||||
_10101,
|
||||
#[doc = "Internal channel 1 is selected as input."]
|
||||
_10110,
|
||||
#[doc = "Internal channel 2 is selected as input."]
|
||||
_10111,
|
||||
#[doc = "Temp Sensor"]
|
||||
_11010,
|
||||
#[doc = "Band Gap"]
|
||||
_11011,
|
||||
#[doc = "Internal channel 3 is selected as input."]
|
||||
_11100,
|
||||
#[doc = "Exernal channel 0 is selected as input."] _00000,
|
||||
#[doc = "Exernal channel 1 is selected as input."] _00001,
|
||||
#[doc = "Exernal channel 2 is selected as input."] _00010,
|
||||
#[doc = "Exernal channel 3 is selected as input."] _00011,
|
||||
#[doc = "Exernal channel 4 is selected as input."] _00100,
|
||||
#[doc = "Exernal channel 5 is selected as input."] _00101,
|
||||
#[doc = "Exernal channel 6 is selected as input."] _00110,
|
||||
#[doc = "Exernal channel 7 is selected as input."] _00111,
|
||||
#[doc = "Exernal channel 8 is selected as input."] _01000,
|
||||
#[doc = "Exernal channel 9 is selected as input."] _01001,
|
||||
#[doc = "Exernal channel 10 is selected as input."] _01010,
|
||||
#[doc = "Exernal channel 11 is selected as input."] _01011,
|
||||
#[doc = "Exernal channel 12 is selected as input."] _01100,
|
||||
#[doc = "Exernal channel 13 is selected as input."] _01101,
|
||||
#[doc = "Exernal channel 14 is selected as input."] _01110,
|
||||
#[doc = "Exernal channel 15 is selected as input."] _01111,
|
||||
#[doc = "Exernal channel 18 is selected as input."] _10010,
|
||||
#[doc = "Exernal channel 19 is selected as input."] _10011,
|
||||
#[doc = "Internal channel 0 is selected as input."] _10101,
|
||||
#[doc = "Internal channel 1 is selected as input."] _10110,
|
||||
#[doc = "Internal channel 2 is selected as input."] _10111,
|
||||
#[doc = "Temp Sensor"] _11010,
|
||||
#[doc = "Band Gap"] _11011,
|
||||
#[doc = "Internal channel 3 is selected as input."] _11100,
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
_11101,
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
_11110,
|
||||
#[doc = "Module is disabled"]
|
||||
_11111,
|
||||
#[doc = "Module is disabled"] _11111,
|
||||
}
|
||||
impl ADCHW {
|
||||
#[allow(missing_docs)]
|
||||
@ -650,10 +597,8 @@ impl<'a> _ADCHW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `AIEN`"]
|
||||
pub enum AIENW {
|
||||
#[doc = "Conversion complete interrupt is disabled."]
|
||||
_0,
|
||||
#[doc = "Conversion complete interrupt is enabled."]
|
||||
_1,
|
||||
#[doc = "Conversion complete interrupt is disabled."] _0,
|
||||
#[doc = "Conversion complete interrupt is enabled."] _1,
|
||||
}
|
||||
impl AIENW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SC2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,12 +45,10 @@ impl super::SC2 {
|
||||
#[doc = "Possible values of the field `REFSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum REFSELR {
|
||||
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
|
||||
_00,
|
||||
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00,
|
||||
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
|
||||
_01,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl REFSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -84,8 +84,7 @@ impl REFSELR {
|
||||
#[doc = "Possible values of the field `DMAEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum DMAENR {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is disabled."] _0,
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
|
||||
_1,
|
||||
}
|
||||
@ -173,10 +172,8 @@ impl ACFGTR {
|
||||
#[doc = "Possible values of the field `ACFE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ACFER {
|
||||
#[doc = "Compare function disabled."]
|
||||
_0,
|
||||
#[doc = "Compare function enabled."]
|
||||
_1,
|
||||
#[doc = "Compare function disabled."] _0,
|
||||
#[doc = "Compare function enabled."] _1,
|
||||
}
|
||||
impl ACFER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -220,10 +217,8 @@ impl ACFER {
|
||||
#[doc = "Possible values of the field `ADTRG`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADTRGR {
|
||||
#[doc = "Software trigger selected."]
|
||||
_0,
|
||||
#[doc = "Hardware trigger selected."]
|
||||
_1,
|
||||
#[doc = "Software trigger selected."] _0,
|
||||
#[doc = "Hardware trigger selected."] _1,
|
||||
}
|
||||
impl ADTRGR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -267,10 +262,8 @@ impl ADTRGR {
|
||||
#[doc = "Possible values of the field `ADACT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADACTR {
|
||||
#[doc = "Conversion not in progress."]
|
||||
_0,
|
||||
#[doc = "Conversion in progress."]
|
||||
_1,
|
||||
#[doc = "Conversion not in progress."] _0,
|
||||
#[doc = "Conversion in progress."] _1,
|
||||
}
|
||||
impl ADACTR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -325,12 +318,9 @@ impl TRGPRNUMR {
|
||||
#[doc = "Possible values of the field `TRGSTLAT`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSTLATR {
|
||||
#[doc = "No trigger request has been latched"]
|
||||
_0,
|
||||
#[doc = "A trigger request has been latched"]
|
||||
_1,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "No trigger request has been latched"] _0,
|
||||
#[doc = "A trigger request has been latched"] _1,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TRGSTLATR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -366,12 +356,9 @@ impl TRGSTLATR {
|
||||
#[doc = "Possible values of the field `TRGSTERR`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum TRGSTERRR {
|
||||
#[doc = "No error has occurred"]
|
||||
_0,
|
||||
#[doc = "An error has occurred"]
|
||||
_1,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
#[doc = "No error has occurred"] _0,
|
||||
#[doc = "An error has occurred"] _1,
|
||||
#[doc = r" Reserved"] _Reserved(u8),
|
||||
}
|
||||
impl TRGSTERRR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -406,8 +393,7 @@ impl TRGSTERRR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `REFSEL`"]
|
||||
pub enum REFSELW {
|
||||
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
|
||||
_00,
|
||||
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"] _00,
|
||||
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
|
||||
_01,
|
||||
}
|
||||
@ -454,8 +440,7 @@ impl<'a> _REFSELW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DMAEN`"]
|
||||
pub enum DMAENW {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is disabled."] _0,
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
|
||||
_1,
|
||||
}
|
||||
@ -558,10 +543,8 @@ impl<'a> _ACFGTW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ACFE`"]
|
||||
pub enum ACFEW {
|
||||
#[doc = "Compare function disabled."]
|
||||
_0,
|
||||
#[doc = "Compare function enabled."]
|
||||
_1,
|
||||
#[doc = "Compare function disabled."] _0,
|
||||
#[doc = "Compare function enabled."] _1,
|
||||
}
|
||||
impl ACFEW {
|
||||
#[allow(missing_docs)]
|
||||
@ -616,10 +599,8 @@ impl<'a> _ACFEW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADTRG`"]
|
||||
pub enum ADTRGW {
|
||||
#[doc = "Software trigger selected."]
|
||||
_0,
|
||||
#[doc = "Hardware trigger selected."]
|
||||
_1,
|
||||
#[doc = "Software trigger selected."] _0,
|
||||
#[doc = "Hardware trigger selected."] _1,
|
||||
}
|
||||
impl ADTRGW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::SC3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -43,14 +45,10 @@ impl super::SC3 {
|
||||
#[doc = "Possible values of the field `AVGS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AVGSR {
|
||||
#[doc = "4 samples averaged."]
|
||||
_00,
|
||||
#[doc = "8 samples averaged."]
|
||||
_01,
|
||||
#[doc = "16 samples averaged."]
|
||||
_10,
|
||||
#[doc = "32 samples averaged."]
|
||||
_11,
|
||||
#[doc = "4 samples averaged."] _00,
|
||||
#[doc = "8 samples averaged."] _01,
|
||||
#[doc = "16 samples averaged."] _10,
|
||||
#[doc = "32 samples averaged."] _11,
|
||||
}
|
||||
impl AVGSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
@ -99,10 +97,8 @@ impl AVGSR {
|
||||
#[doc = "Possible values of the field `AVGE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AVGER {
|
||||
#[doc = "Hardware average function disabled."]
|
||||
_0,
|
||||
#[doc = "Hardware average function enabled."]
|
||||
_1,
|
||||
#[doc = "Hardware average function disabled."] _0,
|
||||
#[doc = "Hardware average function enabled."] _1,
|
||||
}
|
||||
impl AVGER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
@ -213,14 +209,10 @@ impl CALR {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `AVGS`"]
|
||||
pub enum AVGSW {
|
||||
#[doc = "4 samples averaged."]
|
||||
_00,
|
||||
#[doc = "8 samples averaged."]
|
||||
_01,
|
||||
#[doc = "16 samples averaged."]
|
||||
_10,
|
||||
#[doc = "32 samples averaged."]
|
||||
_11,
|
||||
#[doc = "4 samples averaged."] _00,
|
||||
#[doc = "8 samples averaged."] _01,
|
||||
#[doc = "16 samples averaged."] _10,
|
||||
#[doc = "32 samples averaged."] _11,
|
||||
}
|
||||
impl AVGSW {
|
||||
#[allow(missing_docs)]
|
||||
@ -279,10 +271,8 @@ impl<'a> _AVGSW<'a> {
|
||||
}
|
||||
#[doc = "Values that can be written to the field `AVGE`"]
|
||||
pub enum AVGEW {
|
||||
#[doc = "Hardware average function disabled."]
|
||||
_0,
|
||||
#[doc = "Hardware average function enabled."]
|
||||
_1,
|
||||
#[doc = "Hardware average function disabled."] _0,
|
||||
#[doc = "Hardware average function enabled."] _1,
|
||||
}
|
||||
impl AVGEW {
|
||||
#[allow(missing_docs)]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::UG {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::USR_OFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::XOFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
@ -22,7 +22,9 @@ impl super::YOFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
|
||||
Reference in New Issue
Block a user