2017-09-23 18:09:53 +00:00
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::VCCR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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2017-09-23 18:31:10 +00:00
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R {
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bits: self.register.get(),
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}
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2017-09-23 18:09:53 +00:00
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `DIVSLOW`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DIVSLOWR {
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2018-02-06 14:15:10 +00:00
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#[doc = "Divide-by-1"]
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_0000,
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#[doc = "Divide-by-2"]
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_0001,
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#[doc = "Divide-by-3"]
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_0010,
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#[doc = "Divide-by-4"]
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_0011,
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#[doc = "Divide-by-5"]
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_0100,
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#[doc = "Divide-by-6"]
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_0101,
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#[doc = "Divide-by-7"]
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_0110,
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#[doc = "Divide-by-8"]
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_0111,
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#[doc = r" Reserved"]
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_Reserved(u8),
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2017-09-23 18:09:53 +00:00
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}
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impl DIVSLOWR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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DIVSLOWR::_0000 => 0,
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DIVSLOWR::_0001 => 1,
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DIVSLOWR::_0010 => 2,
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DIVSLOWR::_0011 => 3,
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DIVSLOWR::_0100 => 4,
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DIVSLOWR::_0101 => 5,
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DIVSLOWR::_0110 => 6,
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DIVSLOWR::_0111 => 7,
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DIVSLOWR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> DIVSLOWR {
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match value {
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0 => DIVSLOWR::_0000,
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1 => DIVSLOWR::_0001,
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2 => DIVSLOWR::_0010,
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3 => DIVSLOWR::_0011,
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4 => DIVSLOWR::_0100,
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5 => DIVSLOWR::_0101,
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6 => DIVSLOWR::_0110,
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7 => DIVSLOWR::_0111,
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i => DIVSLOWR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0000`"]
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#[inline]
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pub fn is_0000(&self) -> bool {
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*self == DIVSLOWR::_0000
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}
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#[doc = "Checks if the value of the field is `_0001`"]
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#[inline]
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pub fn is_0001(&self) -> bool {
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*self == DIVSLOWR::_0001
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}
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#[doc = "Checks if the value of the field is `_0010`"]
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#[inline]
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pub fn is_0010(&self) -> bool {
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*self == DIVSLOWR::_0010
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}
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#[doc = "Checks if the value of the field is `_0011`"]
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#[inline]
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pub fn is_0011(&self) -> bool {
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*self == DIVSLOWR::_0011
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}
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#[doc = "Checks if the value of the field is `_0100`"]
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#[inline]
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pub fn is_0100(&self) -> bool {
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*self == DIVSLOWR::_0100
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}
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#[doc = "Checks if the value of the field is `_0101`"]
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#[inline]
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pub fn is_0101(&self) -> bool {
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*self == DIVSLOWR::_0101
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}
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#[doc = "Checks if the value of the field is `_0110`"]
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#[inline]
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pub fn is_0110(&self) -> bool {
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*self == DIVSLOWR::_0110
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}
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#[doc = "Checks if the value of the field is `_0111`"]
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#[inline]
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pub fn is_0111(&self) -> bool {
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*self == DIVSLOWR::_0111
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}
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}
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#[doc = "Possible values of the field `DIVBUS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DIVBUSR {
|
2018-02-06 14:15:10 +00:00
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#[doc = "Divide-by-1"]
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_0000,
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#[doc = "Divide-by-2"]
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_0001,
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#[doc = "Divide-by-3"]
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_0010,
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#[doc = "Divide-by-4"]
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_0011,
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#[doc = "Divide-by-5"]
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_0100,
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#[doc = "Divide-by-6"]
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_0101,
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#[doc = "Divide-by-7"]
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_0110,
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#[doc = "Divide-by-8"]
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_0111,
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#[doc = "Divide-by-9"]
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_1000,
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#[doc = "Divide-by-10"]
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_1001,
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#[doc = "Divide-by-11"]
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_1010,
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#[doc = "Divide-by-12"]
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_1011,
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#[doc = "Divide-by-13"]
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_1100,
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#[doc = "Divide-by-14"]
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_1101,
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#[doc = "Divide-by-15"]
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_1110,
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#[doc = "Divide-by-16"]
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_1111,
|
2017-09-23 18:09:53 +00:00
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}
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impl DIVBUSR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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DIVBUSR::_0000 => 0,
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DIVBUSR::_0001 => 1,
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DIVBUSR::_0010 => 2,
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DIVBUSR::_0011 => 3,
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DIVBUSR::_0100 => 4,
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DIVBUSR::_0101 => 5,
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DIVBUSR::_0110 => 6,
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DIVBUSR::_0111 => 7,
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DIVBUSR::_1000 => 8,
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DIVBUSR::_1001 => 9,
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DIVBUSR::_1010 => 10,
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DIVBUSR::_1011 => 11,
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DIVBUSR::_1100 => 12,
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DIVBUSR::_1101 => 13,
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DIVBUSR::_1110 => 14,
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DIVBUSR::_1111 => 15,
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}
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}
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|
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> DIVBUSR {
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match value {
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0 => DIVBUSR::_0000,
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1 => DIVBUSR::_0001,
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2 => DIVBUSR::_0010,
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3 => DIVBUSR::_0011,
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4 => DIVBUSR::_0100,
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5 => DIVBUSR::_0101,
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6 => DIVBUSR::_0110,
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7 => DIVBUSR::_0111,
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8 => DIVBUSR::_1000,
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9 => DIVBUSR::_1001,
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10 => DIVBUSR::_1010,
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11 => DIVBUSR::_1011,
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12 => DIVBUSR::_1100,
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13 => DIVBUSR::_1101,
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14 => DIVBUSR::_1110,
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15 => DIVBUSR::_1111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_0000`"]
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#[inline]
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pub fn is_0000(&self) -> bool {
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*self == DIVBUSR::_0000
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}
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#[doc = "Checks if the value of the field is `_0001`"]
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#[inline]
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pub fn is_0001(&self) -> bool {
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*self == DIVBUSR::_0001
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}
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#[doc = "Checks if the value of the field is `_0010`"]
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#[inline]
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pub fn is_0010(&self) -> bool {
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*self == DIVBUSR::_0010
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}
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#[doc = "Checks if the value of the field is `_0011`"]
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#[inline]
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pub fn is_0011(&self) -> bool {
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*self == DIVBUSR::_0011
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}
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#[doc = "Checks if the value of the field is `_0100`"]
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#[inline]
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pub fn is_0100(&self) -> bool {
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*self == DIVBUSR::_0100
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}
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#[doc = "Checks if the value of the field is `_0101`"]
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#[inline]
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pub fn is_0101(&self) -> bool {
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*self == DIVBUSR::_0101
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}
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#[doc = "Checks if the value of the field is `_0110`"]
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#[inline]
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pub fn is_0110(&self) -> bool {
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*self == DIVBUSR::_0110
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}
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#[doc = "Checks if the value of the field is `_0111`"]
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#[inline]
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pub fn is_0111(&self) -> bool {
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*self == DIVBUSR::_0111
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}
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#[doc = "Checks if the value of the field is `_1000`"]
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#[inline]
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pub fn is_1000(&self) -> bool {
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*self == DIVBUSR::_1000
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}
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#[doc = "Checks if the value of the field is `_1001`"]
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#[inline]
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pub fn is_1001(&self) -> bool {
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*self == DIVBUSR::_1001
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}
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#[doc = "Checks if the value of the field is `_1010`"]
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#[inline]
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pub fn is_1010(&self) -> bool {
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*self == DIVBUSR::_1010
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}
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#[doc = "Checks if the value of the field is `_1011`"]
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#[inline]
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pub fn is_1011(&self) -> bool {
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*self == DIVBUSR::_1011
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}
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#[doc = "Checks if the value of the field is `_1100`"]
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|
|
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#[inline]
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|
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pub fn is_1100(&self) -> bool {
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|
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*self == DIVBUSR::_1100
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}
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|
|
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#[doc = "Checks if the value of the field is `_1101`"]
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|
|
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#[inline]
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|
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pub fn is_1101(&self) -> bool {
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|
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*self == DIVBUSR::_1101
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|
|
}
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|
|
|
#[doc = "Checks if the value of the field is `_1110`"]
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|
|
|
#[inline]
|
|
|
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pub fn is_1110(&self) -> bool {
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|
|
|
*self == DIVBUSR::_1110
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1111`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1111(&self) -> bool {
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|
|
|
*self == DIVBUSR::_1111
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Possible values of the field `DIVCORE`"]
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|
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
|
|
pub enum DIVCORER {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
_0000,
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
_0001,
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
_0010,
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
_0011,
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
_0100,
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
_0101,
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
_0110,
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
_0111,
|
|
|
|
#[doc = "Divide-by-9"]
|
|
|
|
_1000,
|
|
|
|
#[doc = "Divide-by-10"]
|
|
|
|
_1001,
|
|
|
|
#[doc = "Divide-by-11"]
|
|
|
|
_1010,
|
|
|
|
#[doc = "Divide-by-12"]
|
|
|
|
_1011,
|
|
|
|
#[doc = "Divide-by-13"]
|
|
|
|
_1100,
|
|
|
|
#[doc = "Divide-by-14"]
|
|
|
|
_1101,
|
|
|
|
#[doc = "Divide-by-15"]
|
|
|
|
_1110,
|
|
|
|
#[doc = "Divide-by-16"]
|
|
|
|
_1111,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DIVCORER {
|
|
|
|
#[doc = r" Value of the field as raw bits"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
DIVCORER::_0000 => 0,
|
|
|
|
DIVCORER::_0001 => 1,
|
|
|
|
DIVCORER::_0010 => 2,
|
|
|
|
DIVCORER::_0011 => 3,
|
|
|
|
DIVCORER::_0100 => 4,
|
|
|
|
DIVCORER::_0101 => 5,
|
|
|
|
DIVCORER::_0110 => 6,
|
|
|
|
DIVCORER::_0111 => 7,
|
|
|
|
DIVCORER::_1000 => 8,
|
|
|
|
DIVCORER::_1001 => 9,
|
|
|
|
DIVCORER::_1010 => 10,
|
|
|
|
DIVCORER::_1011 => 11,
|
|
|
|
DIVCORER::_1100 => 12,
|
|
|
|
DIVCORER::_1101 => 13,
|
|
|
|
DIVCORER::_1110 => 14,
|
|
|
|
DIVCORER::_1111 => 15,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _from(value: u8) -> DIVCORER {
|
|
|
|
match value {
|
|
|
|
0 => DIVCORER::_0000,
|
|
|
|
1 => DIVCORER::_0001,
|
|
|
|
2 => DIVCORER::_0010,
|
|
|
|
3 => DIVCORER::_0011,
|
|
|
|
4 => DIVCORER::_0100,
|
|
|
|
5 => DIVCORER::_0101,
|
|
|
|
6 => DIVCORER::_0110,
|
|
|
|
7 => DIVCORER::_0111,
|
|
|
|
8 => DIVCORER::_1000,
|
|
|
|
9 => DIVCORER::_1001,
|
|
|
|
10 => DIVCORER::_1010,
|
|
|
|
11 => DIVCORER::_1011,
|
|
|
|
12 => DIVCORER::_1100,
|
|
|
|
13 => DIVCORER::_1101,
|
|
|
|
14 => DIVCORER::_1110,
|
|
|
|
15 => DIVCORER::_1111,
|
|
|
|
_ => unreachable!(),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0000`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0000(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0000
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0001`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0001(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0001
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0010`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0010(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0010
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0011`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0011(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0011
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0100`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0100(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0100
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0101`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0101(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0101
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0110`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0110(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0110
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0111`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0111(&self) -> bool {
|
|
|
|
*self == DIVCORER::_0111
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1000`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1000(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1000
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1001`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1001(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1001
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1010`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1010(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1010
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1011`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1011(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1011
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1100`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1100(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1100
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1101`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1101(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1101
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1110`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1110(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1110
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_1111`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_1111(&self) -> bool {
|
|
|
|
*self == DIVCORER::_1111
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Possible values of the field `SCS`"]
|
|
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
|
|
pub enum SCSR {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Slow IRC (SIRC_CLK)"]
|
|
|
|
_0010,
|
|
|
|
#[doc = r" Reserved"]
|
|
|
|
_Reserved(u8),
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl SCSR {
|
|
|
|
#[doc = r" Value of the field as raw bits"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
SCSR::_0010 => 2,
|
|
|
|
SCSR::_Reserved(bits) => bits,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _from(value: u8) -> SCSR {
|
|
|
|
match value {
|
|
|
|
2 => SCSR::_0010,
|
|
|
|
i => SCSR::_Reserved(i),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Checks if the value of the field is `_0010`"]
|
|
|
|
#[inline]
|
|
|
|
pub fn is_0010(&self) -> bool {
|
|
|
|
*self == SCSR::_0010
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `DIVSLOW`"]
|
|
|
|
pub enum DIVSLOWW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
_0000,
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
_0001,
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
_0010,
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
_0011,
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
_0100,
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
_0101,
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
_0110,
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
_0111,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DIVSLOWW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
DIVSLOWW::_0000 => 0,
|
|
|
|
DIVSLOWW::_0001 => 1,
|
|
|
|
DIVSLOWW::_0010 => 2,
|
|
|
|
DIVSLOWW::_0011 => 3,
|
|
|
|
DIVSLOWW::_0100 => 4,
|
|
|
|
DIVSLOWW::_0101 => 5,
|
|
|
|
DIVSLOWW::_0110 => 6,
|
|
|
|
DIVSLOWW::_0111 => 7,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _DIVSLOWW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _DIVSLOWW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: DIVSLOWW) -> &'a mut W {
|
|
|
|
unsafe { self.bits(variant._bits()) }
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0000(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0000)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0001(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0001)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0010(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0010)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0011(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0011)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0100(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0100)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0101(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0101)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0110(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0110)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0111(self) -> &'a mut W {
|
|
|
|
self.variant(DIVSLOWW::_0111)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 0;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `DIVBUS`"]
|
|
|
|
pub enum DIVBUSW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
_0000,
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
_0001,
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
_0010,
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
_0011,
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
_0100,
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
_0101,
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
_0110,
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
_0111,
|
|
|
|
#[doc = "Divide-by-9"]
|
|
|
|
_1000,
|
|
|
|
#[doc = "Divide-by-10"]
|
|
|
|
_1001,
|
|
|
|
#[doc = "Divide-by-11"]
|
|
|
|
_1010,
|
|
|
|
#[doc = "Divide-by-12"]
|
|
|
|
_1011,
|
|
|
|
#[doc = "Divide-by-13"]
|
|
|
|
_1100,
|
|
|
|
#[doc = "Divide-by-14"]
|
|
|
|
_1101,
|
|
|
|
#[doc = "Divide-by-15"]
|
|
|
|
_1110,
|
|
|
|
#[doc = "Divide-by-16"]
|
|
|
|
_1111,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DIVBUSW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
DIVBUSW::_0000 => 0,
|
|
|
|
DIVBUSW::_0001 => 1,
|
|
|
|
DIVBUSW::_0010 => 2,
|
|
|
|
DIVBUSW::_0011 => 3,
|
|
|
|
DIVBUSW::_0100 => 4,
|
|
|
|
DIVBUSW::_0101 => 5,
|
|
|
|
DIVBUSW::_0110 => 6,
|
|
|
|
DIVBUSW::_0111 => 7,
|
|
|
|
DIVBUSW::_1000 => 8,
|
|
|
|
DIVBUSW::_1001 => 9,
|
|
|
|
DIVBUSW::_1010 => 10,
|
|
|
|
DIVBUSW::_1011 => 11,
|
|
|
|
DIVBUSW::_1100 => 12,
|
|
|
|
DIVBUSW::_1101 => 13,
|
|
|
|
DIVBUSW::_1110 => 14,
|
|
|
|
DIVBUSW::_1111 => 15,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _DIVBUSW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _DIVBUSW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: DIVBUSW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bits(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0000(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0000)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0001(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0001)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0010(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0010)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0011(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0011)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0100(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0100)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0101(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0101)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0110(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0110)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0111(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_0111)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-9"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1000(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1000)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-10"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1001(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1001)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-11"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1010(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1010)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-12"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1011(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1011)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-13"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1100(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1100)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-14"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1101(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1101)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-15"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1110(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1110)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-16"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1111(self) -> &'a mut W {
|
|
|
|
self.variant(DIVBUSW::_1111)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 4;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `DIVCORE`"]
|
|
|
|
pub enum DIVCOREW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
_0000,
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
_0001,
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
_0010,
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
_0011,
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
_0100,
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
_0101,
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
_0110,
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
_0111,
|
|
|
|
#[doc = "Divide-by-9"]
|
|
|
|
_1000,
|
|
|
|
#[doc = "Divide-by-10"]
|
|
|
|
_1001,
|
|
|
|
#[doc = "Divide-by-11"]
|
|
|
|
_1010,
|
|
|
|
#[doc = "Divide-by-12"]
|
|
|
|
_1011,
|
|
|
|
#[doc = "Divide-by-13"]
|
|
|
|
_1100,
|
|
|
|
#[doc = "Divide-by-14"]
|
|
|
|
_1101,
|
|
|
|
#[doc = "Divide-by-15"]
|
|
|
|
_1110,
|
|
|
|
#[doc = "Divide-by-16"]
|
|
|
|
_1111,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DIVCOREW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
DIVCOREW::_0000 => 0,
|
|
|
|
DIVCOREW::_0001 => 1,
|
|
|
|
DIVCOREW::_0010 => 2,
|
|
|
|
DIVCOREW::_0011 => 3,
|
|
|
|
DIVCOREW::_0100 => 4,
|
|
|
|
DIVCOREW::_0101 => 5,
|
|
|
|
DIVCOREW::_0110 => 6,
|
|
|
|
DIVCOREW::_0111 => 7,
|
|
|
|
DIVCOREW::_1000 => 8,
|
|
|
|
DIVCOREW::_1001 => 9,
|
|
|
|
DIVCOREW::_1010 => 10,
|
|
|
|
DIVCOREW::_1011 => 11,
|
|
|
|
DIVCOREW::_1100 => 12,
|
|
|
|
DIVCOREW::_1101 => 13,
|
|
|
|
DIVCOREW::_1110 => 14,
|
|
|
|
DIVCOREW::_1111 => 15,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _DIVCOREW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _DIVCOREW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: DIVCOREW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bits(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-1"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0000(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0000)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-2"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0001(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0001)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-3"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0010(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0010)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-4"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0011(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0011)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-5"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0100(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0100)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-6"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0101(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0101)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-7"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0110(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0110)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-8"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0111(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_0111)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-9"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1000(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1000)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-10"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1001(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1001)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-11"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1010(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1010)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-12"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1011(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1011)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-13"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1100(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1100)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-14"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1101(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1101)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-15"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1110(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1110)
|
|
|
|
}
|
|
|
|
#[doc = "Divide-by-16"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1111(self) -> &'a mut W {
|
|
|
|
self.variant(DIVCOREW::_1111)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 16;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `SCS`"]
|
|
|
|
pub enum SCSW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Slow IRC (SIRC_CLK)"]
|
|
|
|
_0010,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl SCSW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> u8 {
|
|
|
|
match *self {
|
|
|
|
SCSW::_0010 => 2,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _SCSW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _SCSW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: SCSW) -> &'a mut W {
|
|
|
|
unsafe { self.bits(variant._bits()) }
|
|
|
|
}
|
|
|
|
#[doc = "Slow IRC (SIRC_CLK)"]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0010(self) -> &'a mut W {
|
|
|
|
self.variant(SCSW::_0010)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 24;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
impl R {
|
|
|
|
#[doc = r" Value of the register as raw bits"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(&self) -> u32 {
|
|
|
|
self.bits
|
|
|
|
}
|
|
|
|
#[doc = "Bits 0:3 - Slow Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divslow(&self) -> DIVSLOWR {
|
|
|
|
DIVSLOWR::_from({
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 0;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bits 4:7 - Bus Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divbus(&self) -> DIVBUSR {
|
|
|
|
DIVBUSR::_from({
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 4;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bits 16:19 - Core Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divcore(&self) -> DIVCORER {
|
|
|
|
DIVCORER::_from({
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 16;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bits 24:27 - System Clock Source"]
|
|
|
|
#[inline]
|
|
|
|
pub fn scs(&self) -> SCSR {
|
|
|
|
SCSR::_from({
|
|
|
|
const MASK: u8 = 15;
|
|
|
|
const OFFSET: u8 = 24;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
|
|
})
|
|
|
|
}
|
|
|
|
}
|
|
|
|
impl W {
|
|
|
|
#[doc = r" Reset value of the register"]
|
|
|
|
#[inline]
|
|
|
|
pub fn reset_value() -> W {
|
|
|
|
W { bits: 33554433 }
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the register"]
|
|
|
|
#[inline]
|
|
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
|
|
self.bits = bits;
|
|
|
|
self
|
|
|
|
}
|
|
|
|
#[doc = "Bits 0:3 - Slow Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divslow(&mut self) -> _DIVSLOWW {
|
|
|
|
_DIVSLOWW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bits 4:7 - Bus Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divbus(&mut self) -> _DIVBUSW {
|
|
|
|
_DIVBUSW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bits 16:19 - Core Clock Divide Ratio"]
|
|
|
|
#[inline]
|
|
|
|
pub fn divcore(&mut self) -> _DIVCOREW {
|
|
|
|
_DIVCOREW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bits 24:27 - System Clock Source"]
|
|
|
|
#[inline]
|
|
|
|
pub fn scs(&mut self) -> _SCSW {
|
|
|
|
_SCSW { w: self }
|
|
|
|
}
|
|
|
|
}
|