2017-09-23 18:09:53 +00:00
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::CR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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2019-01-16 14:39:25 +00:00
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R { bits: self.register.get() }
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2017-09-23 18:09:53 +00:00
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `MEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MENR {
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2018-02-06 14:15:10 +00:00
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#[doc = "Module is disabled."]
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_0,
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#[doc = "Module is enabled."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl MENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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MENR::_0 => false,
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MENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> MENR {
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match value {
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false => MENR::_0,
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true => MENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == MENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == MENR::_1
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}
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}
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#[doc = "Possible values of the field `RST`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum RSTR {
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2018-02-06 14:15:10 +00:00
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#[doc = "Master logic is not reset."]
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_0,
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#[doc = "Master logic is reset."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl RSTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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RSTR::_0 => false,
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RSTR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> RSTR {
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match value {
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false => RSTR::_0,
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true => RSTR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == RSTR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == RSTR::_1
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}
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}
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#[doc = "Possible values of the field `DOZEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DOZENR {
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2018-02-06 14:15:10 +00:00
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#[doc = "Module is enabled in Doze mode."]
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_0,
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#[doc = "Module is disabled in Doze mode."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl DOZENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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DOZENR::_0 => false,
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DOZENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> DOZENR {
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match value {
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false => DOZENR::_0,
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true => DOZENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == DOZENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == DOZENR::_1
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}
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}
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#[doc = "Possible values of the field `DBGEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DBGENR {
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2018-02-06 14:15:10 +00:00
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#[doc = "Module is disabled in debug mode."]
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_0,
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#[doc = "Module is enabled in debug mode."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl DBGENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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DBGENR::_0 => false,
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DBGENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> DBGENR {
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match value {
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false => DBGENR::_0,
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true => DBGENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == DBGENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == DBGENR::_1
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}
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}
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#[doc = "Values that can be written to the field `MEN`"]
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pub enum MENW {
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2018-02-06 14:15:10 +00:00
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#[doc = "Module is disabled."]
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_0,
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#[doc = "Module is enabled."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl MENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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MENW::_0 => false,
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MENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _MENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _MENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: MENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Module is disabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(MENW::_0)
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}
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#[doc = "Module is enabled."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(MENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `RST`"]
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pub enum RSTW {
|
2018-02-06 14:15:10 +00:00
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#[doc = "Master logic is not reset."]
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_0,
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#[doc = "Master logic is reset."]
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_1,
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2017-09-23 18:09:53 +00:00
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}
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impl RSTW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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RSTW::_0 => false,
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RSTW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _RSTW<'a> {
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w: &'a mut W,
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}
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impl<'a> _RSTW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: RSTW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Master logic is not reset."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(RSTW::_0)
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}
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#[doc = "Master logic is reset."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(RSTW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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|
#[doc = r" Writes raw bits to the field"]
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#[inline]
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|
pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 1;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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|
#[doc = "Values that can be written to the field `DOZEN`"]
|
|
|
|
pub enum DOZENW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Module is enabled in Doze mode."]
|
|
|
|
_0,
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|
#[doc = "Module is disabled in Doze mode."]
|
|
|
|
_1,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DOZENW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> bool {
|
|
|
|
match *self {
|
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|
|
DOZENW::_0 => false,
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|
|
|
DOZENW::_1 => true,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _DOZENW<'a> {
|
|
|
|
w: &'a mut W,
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|
|
|
}
|
|
|
|
impl<'a> _DOZENW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: DOZENW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bit(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Module is enabled in Doze mode."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0(self) -> &'a mut W {
|
|
|
|
self.variant(DOZENW::_0)
|
|
|
|
}
|
|
|
|
#[doc = "Module is disabled in Doze mode."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1(self) -> &'a mut W {
|
|
|
|
self.variant(DOZENW::_1)
|
|
|
|
}
|
|
|
|
#[doc = r" Sets the field bit"]
|
|
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
|
|
self.bit(true)
|
|
|
|
}
|
|
|
|
#[doc = r" Clears the field bit"]
|
|
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
|
|
self.bit(false)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 2;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `DBGEN`"]
|
|
|
|
pub enum DBGENW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "Module is disabled in debug mode."]
|
|
|
|
_0,
|
|
|
|
#[doc = "Module is enabled in debug mode."]
|
|
|
|
_1,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl DBGENW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> bool {
|
|
|
|
match *self {
|
|
|
|
DBGENW::_0 => false,
|
|
|
|
DBGENW::_1 => true,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _DBGENW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _DBGENW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: DBGENW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bit(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Module is disabled in debug mode."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0(self) -> &'a mut W {
|
|
|
|
self.variant(DBGENW::_0)
|
|
|
|
}
|
|
|
|
#[doc = "Module is enabled in debug mode."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1(self) -> &'a mut W {
|
|
|
|
self.variant(DBGENW::_1)
|
|
|
|
}
|
|
|
|
#[doc = r" Sets the field bit"]
|
|
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
|
|
self.bit(true)
|
|
|
|
}
|
|
|
|
#[doc = r" Clears the field bit"]
|
|
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
|
|
self.bit(false)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 3;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `RTF`"]
|
|
|
|
pub enum RTFW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "No effect."]
|
|
|
|
_0,
|
|
|
|
#[doc = "Transmit FIFO is reset."]
|
|
|
|
_1,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl RTFW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> bool {
|
|
|
|
match *self {
|
|
|
|
RTFW::_0 => false,
|
|
|
|
RTFW::_1 => true,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _RTFW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _RTFW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: RTFW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bit(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "No effect."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0(self) -> &'a mut W {
|
|
|
|
self.variant(RTFW::_0)
|
|
|
|
}
|
|
|
|
#[doc = "Transmit FIFO is reset."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1(self) -> &'a mut W {
|
|
|
|
self.variant(RTFW::_1)
|
|
|
|
}
|
|
|
|
#[doc = r" Sets the field bit"]
|
|
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
|
|
self.bit(true)
|
|
|
|
}
|
|
|
|
#[doc = r" Clears the field bit"]
|
|
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
|
|
self.bit(false)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 8;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "Values that can be written to the field `RRF`"]
|
|
|
|
pub enum RRFW {
|
2018-02-06 14:15:10 +00:00
|
|
|
#[doc = "No effect."]
|
|
|
|
_0,
|
|
|
|
#[doc = "Receive FIFO is reset."]
|
|
|
|
_1,
|
2017-09-23 18:09:53 +00:00
|
|
|
}
|
|
|
|
impl RRFW {
|
|
|
|
#[allow(missing_docs)]
|
|
|
|
#[doc(hidden)]
|
|
|
|
#[inline]
|
|
|
|
pub fn _bits(&self) -> bool {
|
|
|
|
match *self {
|
|
|
|
RRFW::_0 => false,
|
|
|
|
RRFW::_1 => true,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = r" Proxy"]
|
|
|
|
pub struct _RRFW<'a> {
|
|
|
|
w: &'a mut W,
|
|
|
|
}
|
|
|
|
impl<'a> _RRFW<'a> {
|
|
|
|
#[doc = r" Writes `variant` to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn variant(self, variant: RRFW) -> &'a mut W {
|
|
|
|
{
|
|
|
|
self.bit(variant._bits())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#[doc = "No effect."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _0(self) -> &'a mut W {
|
|
|
|
self.variant(RRFW::_0)
|
|
|
|
}
|
|
|
|
#[doc = "Receive FIFO is reset."]
|
|
|
|
#[inline]
|
|
|
|
pub fn _1(self) -> &'a mut W {
|
|
|
|
self.variant(RRFW::_1)
|
|
|
|
}
|
|
|
|
#[doc = r" Sets the field bit"]
|
|
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
|
|
self.bit(true)
|
|
|
|
}
|
|
|
|
#[doc = r" Clears the field bit"]
|
|
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
|
|
self.bit(false)
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the field"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 9;
|
|
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
|
|
self.w
|
|
|
|
}
|
|
|
|
}
|
|
|
|
impl R {
|
|
|
|
#[doc = r" Value of the register as raw bits"]
|
|
|
|
#[inline]
|
|
|
|
pub fn bits(&self) -> u32 {
|
|
|
|
self.bits
|
|
|
|
}
|
|
|
|
#[doc = "Bit 0 - Module Enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn men(&self) -> MENR {
|
|
|
|
MENR::_from({
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 0;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bit 1 - Software Reset"]
|
|
|
|
#[inline]
|
|
|
|
pub fn rst(&self) -> RSTR {
|
|
|
|
RSTR::_from({
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 1;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bit 2 - Doze mode enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn dozen(&self) -> DOZENR {
|
|
|
|
DOZENR::_from({
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 2;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
|
|
})
|
|
|
|
}
|
|
|
|
#[doc = "Bit 3 - Debug Enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn dbgen(&self) -> DBGENR {
|
|
|
|
DBGENR::_from({
|
|
|
|
const MASK: bool = true;
|
|
|
|
const OFFSET: u8 = 3;
|
|
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
|
|
})
|
|
|
|
}
|
|
|
|
}
|
|
|
|
impl W {
|
|
|
|
#[doc = r" Reset value of the register"]
|
|
|
|
#[inline]
|
|
|
|
pub fn reset_value() -> W {
|
|
|
|
W { bits: 0 }
|
|
|
|
}
|
|
|
|
#[doc = r" Writes raw bits to the register"]
|
|
|
|
#[inline]
|
|
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
|
|
self.bits = bits;
|
|
|
|
self
|
|
|
|
}
|
|
|
|
#[doc = "Bit 0 - Module Enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn men(&mut self) -> _MENW {
|
|
|
|
_MENW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bit 1 - Software Reset"]
|
|
|
|
#[inline]
|
|
|
|
pub fn rst(&mut self) -> _RSTW {
|
|
|
|
_RSTW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bit 2 - Doze mode enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn dozen(&mut self) -> _DOZENW {
|
|
|
|
_DOZENW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bit 3 - Debug Enable"]
|
|
|
|
#[inline]
|
|
|
|
pub fn dbgen(&mut self) -> _DBGENW {
|
|
|
|
_DBGENW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bit 8 - Reset Transmit FIFO"]
|
|
|
|
#[inline]
|
|
|
|
pub fn rtf(&mut self) -> _RTFW {
|
|
|
|
_RTFW { w: self }
|
|
|
|
}
|
|
|
|
#[doc = "Bit 9 - Reset Receive FIFO"]
|
|
|
|
#[inline]
|
|
|
|
pub fn rrf(&mut self) -> _RRFW {
|
|
|
|
_RRFW { w: self }
|
|
|
|
}
|
|
|
|
}
|