2017-09-23 18:09:53 +00:00
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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_reserved0: [u8; 8usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x08 - Crossbar Switch (AXBS) Slave Configuration"]
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pub plasc: PLASC,
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#[doc = "0x0a - Crossbar Switch (AXBS) Master Configuration"]
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pub plamc: PLAMC,
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#[doc = "0x0c - Core Platform Control Register"]
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pub cpcr: CPCR,
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#[doc = "0x10 - Interrupt Status and Control Register"]
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pub iscr: ISCR,
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2017-09-23 18:09:53 +00:00
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_reserved1: [u8; 28usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x30 - Process ID Register"]
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pub pid: PID,
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2017-09-23 18:09:53 +00:00
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_reserved2: [u8; 12usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x40 - Compute Operation Control Register"]
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pub cpo: CPO,
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2017-09-23 18:09:53 +00:00
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_reserved3: [u8; 956usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x400 - Local Memory Descriptor Register"]
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pub lmdr0: LMDR0,
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#[doc = "0x404 - Local Memory Descriptor Register"]
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pub lmdr1: LMDR1,
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#[doc = "0x408 - Local Memory Descriptor Register2"]
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pub lmdr2: LMDR2,
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2017-09-23 18:09:53 +00:00
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_reserved4: [u8; 116usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x480 - LMEM Parity and ECC Control Register"]
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pub lmpecr: LMPECR,
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2017-09-23 18:09:53 +00:00
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_reserved5: [u8; 4usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x488 - LMEM Parity and ECC Interrupt Register"]
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pub lmpeir: LMPEIR,
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2017-09-23 18:09:53 +00:00
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_reserved6: [u8; 4usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x490 - LMEM Fault Address Register"]
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pub lmfar: LMFAR,
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#[doc = "0x494 - LMEM Fault Attribute Register"]
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pub lmfatr: LMFATR,
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2017-09-23 18:09:53 +00:00
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_reserved7: [u8; 8usize],
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2018-02-06 14:15:10 +00:00
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#[doc = "0x4a0 - LMEM Fault Data High Register"]
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pub lmfdhr: LMFDHR,
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#[doc = "0x4a4 - LMEM Fault Data Low Register"]
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pub lmfdlr: LMFDLR,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Crossbar Switch (AXBS) Slave Configuration"]
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pub struct PLASC {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u16>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Crossbar Switch (AXBS) Slave Configuration"]
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pub mod plasc;
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#[doc = "Crossbar Switch (AXBS) Master Configuration"]
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pub struct PLAMC {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u16>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Crossbar Switch (AXBS) Master Configuration"]
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pub mod plamc;
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#[doc = "Core Platform Control Register"]
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pub struct CPCR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Core Platform Control Register"]
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pub mod cpcr;
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#[doc = "Interrupt Status and Control Register"]
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pub struct ISCR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Interrupt Status and Control Register"]
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pub mod iscr;
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#[doc = "Process ID Register"]
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pub struct PID {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Process ID Register"]
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pub mod pid;
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#[doc = "Compute Operation Control Register"]
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pub struct CPO {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Compute Operation Control Register"]
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pub mod cpo;
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#[doc = "Local Memory Descriptor Register"]
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pub struct LMDR0 {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Local Memory Descriptor Register"]
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pub mod lmdr0;
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#[doc = "Local Memory Descriptor Register"]
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pub struct LMDR1 {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Local Memory Descriptor Register"]
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pub mod lmdr1;
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#[doc = "Local Memory Descriptor Register2"]
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pub struct LMDR2 {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "Local Memory Descriptor Register2"]
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pub mod lmdr2;
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#[doc = "LMEM Parity and ECC Control Register"]
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pub struct LMPECR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Parity and ECC Control Register"]
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pub mod lmpecr;
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#[doc = "LMEM Parity and ECC Interrupt Register"]
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pub struct LMPEIR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Parity and ECC Interrupt Register"]
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pub mod lmpeir;
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#[doc = "LMEM Fault Address Register"]
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pub struct LMFAR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Fault Address Register"]
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pub mod lmfar;
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#[doc = "LMEM Fault Attribute Register"]
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pub struct LMFATR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Fault Attribute Register"]
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pub mod lmfatr;
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#[doc = "LMEM Fault Data High Register"]
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pub struct LMFDHR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Fault Data High Register"]
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pub mod lmfdhr;
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#[doc = "LMEM Fault Data Low Register"]
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pub struct LMFDLR {
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2019-01-16 14:39:25 +00:00
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register: ::vcell::VolatileCell<u32>,
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2017-09-23 18:09:53 +00:00
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}
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#[doc = "LMEM Fault Data Low Register"]
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pub mod lmfdlr;
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