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sw: first software commit

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The software is untested, but it builds.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
2019-05-22 15:02:00 +08:00
parent dd14bb4d29
commit e8aaac5cfe
57 changed files with 36778 additions and 43 deletions
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903
sw/include/fomu/csr.h Normal file
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#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#ifdef CSR_ACCESSORS_DEFINED
extern void csr_writeb(uint8_t value, uint32_t addr);
extern uint8_t csr_readb(uint32_t addr);
extern void csr_writew(uint16_t value, uint32_t addr);
extern uint16_t csr_readw(uint32_t addr);
extern void csr_writel(uint32_t value, uint32_t addr);
extern uint32_t csr_readl(uint32_t addr);
#else /* ! CSR_ACCESSORS_DEFINED */
static inline void csr_writeb(uint8_t value, uint32_t addr)
{
*((volatile uint8_t *)addr) = value;
}
static inline uint8_t csr_readb(uint32_t addr)
{
return *(volatile uint8_t *)addr;
}
static inline void csr_writew(uint16_t value, uint32_t addr)
{
*((volatile uint16_t *)addr) = value;
}
static inline uint16_t csr_readw(uint32_t addr)
{
return *(volatile uint16_t *)addr;
}
static inline void csr_writel(uint32_t value, uint32_t addr)
{
*((volatile uint32_t *)addr) = value;
}
static inline uint32_t csr_readl(uint32_t addr)
{
return *(volatile uint32_t *)addr;
}
#endif /* ! CSR_ACCESSORS_DEFINED */
/* ctrl */
#define CSR_CTRL_BASE 0xe0000000
#define CSR_CTRL_RESET_ADDR 0xe0000000
#define CSR_CTRL_RESET_SIZE 1
static inline unsigned char
ctrl_reset_read(void)
{
unsigned char r = csr_readl(0xe0000000);
return r;
}
static inline void ctrl_reset_write(unsigned char value)
{
csr_writel(value, 0xe0000000);
}
#define CSR_CTRL_SCRATCH_ADDR 0xe0000004
#define CSR_CTRL_SCRATCH_SIZE 4
static inline unsigned int ctrl_scratch_read(void)
{
unsigned int r = csr_readl(0xe0000004);
r <<= 8;
r |= csr_readl(0xe0000008);
r <<= 8;
r |= csr_readl(0xe000000c);
r <<= 8;
r |= csr_readl(0xe0000010);
return r;
}
static inline void ctrl_scratch_write(unsigned int value)
{
csr_writel(value >> 24, 0xe0000004);
csr_writel(value >> 16, 0xe0000008);
csr_writel(value >> 8, 0xe000000c);
csr_writel(value, 0xe0000010);
}
#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014
#define CSR_CTRL_BUS_ERRORS_SIZE 4
static inline unsigned int ctrl_bus_errors_read(void)
{
unsigned int r = csr_readl(0xe0000014);
r <<= 8;
r |= csr_readl(0xe0000018);
r <<= 8;
r |= csr_readl(0xe000001c);
r <<= 8;
r |= csr_readl(0xe0000020);
return r;
}
/* picorvspi */
#define CSR_PICORVSPI_BASE 0xe0005000
#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000
#define CSR_PICORVSPI_CFG1_SIZE 1
static inline unsigned char picorvspi_cfg1_read(void)
{
unsigned char r = csr_readl(0xe0005000);
return r;
}
static inline void picorvspi_cfg1_write(unsigned char value)
{
csr_writel(value, 0xe0005000);
}
#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004
#define CSR_PICORVSPI_CFG2_SIZE 1
static inline unsigned char picorvspi_cfg2_read(void)
{
unsigned char r = csr_readl(0xe0005004);
return r;
}
static inline void picorvspi_cfg2_write(unsigned char value)
{
csr_writel(value, 0xe0005004);
}
#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008
#define CSR_PICORVSPI_CFG3_SIZE 1
static inline unsigned char picorvspi_cfg3_read(void)
{
unsigned char r = csr_readl(0xe0005008);
return r;
}
static inline void picorvspi_cfg3_write(unsigned char value)
{
csr_writel(value, 0xe0005008);
}
#define CSR_PICORVSPI_CFG4_ADDR 0xe000500c
#define CSR_PICORVSPI_CFG4_SIZE 1
static inline unsigned char picorvspi_cfg4_read(void)
{
unsigned char r = csr_readl(0xe000500c);
return r;
}
static inline void picorvspi_cfg4_write(unsigned char value)
{
csr_writel(value, 0xe000500c);
}
#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010
#define CSR_PICORVSPI_STAT1_SIZE 1
static inline unsigned char picorvspi_stat1_read(void)
{
unsigned char r = csr_readl(0xe0005010);
return r;
}
#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014
#define CSR_PICORVSPI_STAT2_SIZE 1
static inline unsigned char picorvspi_stat2_read(void)
{
unsigned char r = csr_readl(0xe0005014);
return r;
}
#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018
#define CSR_PICORVSPI_STAT3_SIZE 1
static inline unsigned char picorvspi_stat3_read(void)
{
unsigned char r = csr_readl(0xe0005018);
return r;
}
#define CSR_PICORVSPI_STAT4_ADDR 0xe000501c
#define CSR_PICORVSPI_STAT4_SIZE 1
static inline unsigned char picorvspi_stat4_read(void)
{
unsigned char r = csr_readl(0xe000501c);
return r;
}
/* reboot */
#define CSR_REBOOT_BASE 0xe0006000
#define CSR_REBOOT_CTRL_ADDR 0xe0006000
#define CSR_REBOOT_CTRL_SIZE 1
static inline unsigned char reboot_ctrl_read(void)
{
unsigned char r = csr_readl(0xe0006000);
return r;
}
static inline void reboot_ctrl_write(unsigned char value)
{
csr_writel(value, 0xe0006000);
}
#define CSR_REBOOT_ADDR_ADDR 0xe0006004
#define CSR_REBOOT_ADDR_SIZE 4
static inline unsigned int reboot_addr_read(void)
{
unsigned int r = csr_readl(0xe0006004);
r <<= 8;
r |= csr_readl(0xe0006008);
r <<= 8;
r |= csr_readl(0xe000600c);
r <<= 8;
r |= csr_readl(0xe0006010);
return r;
}
static inline void reboot_addr_write(unsigned int value)
{
csr_writel(value >> 24, 0xe0006004);
csr_writel(value >> 16, 0xe0006008);
csr_writel(value >> 8, 0xe000600c);
csr_writel(value, 0xe0006010);
}
/* rgb */
#define CSR_RGB_BASE 0xe0006800
#define CSR_RGB_DAT_ADDR 0xe0006800
#define CSR_RGB_DAT_SIZE 1
static inline unsigned char rgb_dat_read(void)
{
unsigned char r = csr_readl(0xe0006800);
return r;
}
static inline void rgb_dat_write(unsigned char value)
{
csr_writel(value, 0xe0006800);
}
#define CSR_RGB_ADDR_ADDR 0xe0006804
#define CSR_RGB_ADDR_SIZE 1
static inline unsigned char rgb_addr_read(void)
{
unsigned char r = csr_readl(0xe0006804);
return r;
}
static inline void rgb_addr_write(unsigned char value)
{
csr_writel(value, 0xe0006804);
}
#define CSR_RGB_CTRL_ADDR 0xe0006808
#define CSR_RGB_CTRL_SIZE 1
static inline unsigned char rgb_ctrl_read(void)
{
unsigned char r = csr_readl(0xe0006808);
return r;
}
static inline void rgb_ctrl_write(unsigned char value)
{
csr_writel(value, 0xe0006808);
}
/* timer0 */
#define CSR_TIMER0_BASE 0xe0002800
#define CSR_TIMER0_LOAD_ADDR 0xe0002800
#define CSR_TIMER0_LOAD_SIZE 4
static inline unsigned int timer0_load_read(void)
{
unsigned int r = csr_readl(0xe0002800);
r <<= 8;
r |= csr_readl(0xe0002804);
r <<= 8;
r |= csr_readl(0xe0002808);
r <<= 8;
r |= csr_readl(0xe000280c);
return r;
}
static inline void timer0_load_write(unsigned int value)
{
csr_writel(value >> 24, 0xe0002800);
csr_writel(value >> 16, 0xe0002804);
csr_writel(value >> 8, 0xe0002808);
csr_writel(value, 0xe000280c);
}
#define CSR_TIMER0_RELOAD_ADDR 0xe0002810
#define CSR_TIMER0_RELOAD_SIZE 4
static inline unsigned int timer0_reload_read(void)
{
unsigned int r = csr_readl(0xe0002810);
r <<= 8;
r |= csr_readl(0xe0002814);
r <<= 8;
r |= csr_readl(0xe0002818);
r <<= 8;
r |= csr_readl(0xe000281c);
return r;
}
static inline void timer0_reload_write(unsigned int value)
{
csr_writel(value >> 24, 0xe0002810);
csr_writel(value >> 16, 0xe0002814);
csr_writel(value >> 8, 0xe0002818);
csr_writel(value, 0xe000281c);
}
#define CSR_TIMER0_EN_ADDR 0xe0002820
#define CSR_TIMER0_EN_SIZE 1
static inline unsigned char timer0_en_read(void)
{
unsigned char r = csr_readl(0xe0002820);
return r;
}
static inline void timer0_en_write(unsigned char value)
{
csr_writel(value, 0xe0002820);
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline unsigned char timer0_update_value_read(void)
{
unsigned char r = csr_readl(0xe0002824);
return r;
}
static inline void timer0_update_value_write(unsigned char value)
{
csr_writel(value, 0xe0002824);
}
#define CSR_TIMER0_VALUE_ADDR 0xe0002828
#define CSR_TIMER0_VALUE_SIZE 4
static inline unsigned int timer0_value_read(void)
{
unsigned int r = csr_readl(0xe0002828);
r <<= 8;
r |= csr_readl(0xe000282c);
r <<= 8;
r |= csr_readl(0xe0002830);
r <<= 8;
r |= csr_readl(0xe0002834);
return r;
}
#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline unsigned char timer0_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0002838);
return r;
}
static inline void timer0_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0002838);
}
#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283c
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline unsigned char timer0_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe000283c);
return r;
}
static inline void timer0_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe000283c);
}
#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline unsigned char timer0_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe0002840);
return r;
}
static inline void timer0_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe0002840);
}
/* touch */
#define CSR_TOUCH_BASE 0xe0005800
#define CSR_TOUCH_O_ADDR 0xe0005800
#define CSR_TOUCH_O_SIZE 1
static inline unsigned char touch_o_read(void)
{
unsigned char r = csr_readl(0xe0005800);
return r;
}
static inline void touch_o_write(unsigned char value)
{
csr_writel(value, 0xe0005800);
}
#define CSR_TOUCH_OE_ADDR 0xe0005804
#define CSR_TOUCH_OE_SIZE 1
static inline unsigned char touch_oe_read(void)
{
unsigned char r = csr_readl(0xe0005804);
return r;
}
static inline void touch_oe_write(unsigned char value)
{
csr_writel(value, 0xe0005804);
}
#define CSR_TOUCH_I_ADDR 0xe0005808
#define CSR_TOUCH_I_SIZE 1
static inline unsigned char touch_i_read(void)
{
unsigned char r = csr_readl(0xe0005808);
return r;
}
/* usb */
#define CSR_USB_BASE 0xe0004800
#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800
#define CSR_USB_PULLUP_OUT_SIZE 1
static inline unsigned char usb_pullup_out_read(void)
{
unsigned char r = csr_readl(0xe0004800);
return r;
}
static inline void usb_pullup_out_write(unsigned char value)
{
csr_writel(value, 0xe0004800);
}
#define CSR_USB_EP_0_OUT_EV_STATUS_ADDR 0xe0004804
#define CSR_USB_EP_0_OUT_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_0_out_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0004804);
return r;
}
static inline void usb_ep_0_out_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0004804);
}
#define CSR_USB_EP_0_OUT_EV_PENDING_ADDR 0xe0004808
#define CSR_USB_EP_0_OUT_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_0_out_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe0004808);
return r;
}
static inline void usb_ep_0_out_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe0004808);
}
#define CSR_USB_EP_0_OUT_EV_ENABLE_ADDR 0xe000480c
#define CSR_USB_EP_0_OUT_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_0_out_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe000480c);
return r;
}
static inline void usb_ep_0_out_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe000480c);
}
#define CSR_USB_EP_0_OUT_LAST_TOK_ADDR 0xe0004810
#define CSR_USB_EP_0_OUT_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_0_out_last_tok_read(void)
{
unsigned char r = csr_readl(0xe0004810);
return r;
}
#define CSR_USB_EP_0_OUT_RESPOND_ADDR 0xe0004814
#define CSR_USB_EP_0_OUT_RESPOND_SIZE 1
static inline unsigned char usb_ep_0_out_respond_read(void)
{
unsigned char r = csr_readl(0xe0004814);
return r;
}
static inline void usb_ep_0_out_respond_write(unsigned char value)
{
csr_writel(value, 0xe0004814);
}
#define CSR_USB_EP_0_OUT_DTB_ADDR 0xe0004818
#define CSR_USB_EP_0_OUT_DTB_SIZE 1
static inline unsigned char usb_ep_0_out_dtb_read(void)
{
unsigned char r = csr_readl(0xe0004818);
return r;
}
static inline void usb_ep_0_out_dtb_write(unsigned char value)
{
csr_writel(value, 0xe0004818);
}
#define CSR_USB_EP_0_OUT_OBUF_HEAD_ADDR 0xe000481c
#define CSR_USB_EP_0_OUT_OBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_0_out_obuf_head_read(void)
{
unsigned char r = csr_readl(0xe000481c);
return r;
}
static inline void usb_ep_0_out_obuf_head_write(unsigned char value)
{
csr_writel(value, 0xe000481c);
}
#define CSR_USB_EP_0_OUT_OBUF_EMPTY_ADDR 0xe0004820
#define CSR_USB_EP_0_OUT_OBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_0_out_obuf_empty_read(void)
{
unsigned char r = csr_readl(0xe0004820);
return r;
}
#define CSR_USB_EP_0_IN_EV_STATUS_ADDR 0xe0004824
#define CSR_USB_EP_0_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_0_in_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0004824);
return r;
}
static inline void usb_ep_0_in_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0004824);
}
#define CSR_USB_EP_0_IN_EV_PENDING_ADDR 0xe0004828
#define CSR_USB_EP_0_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_0_in_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe0004828);
return r;
}
static inline void usb_ep_0_in_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe0004828);
}
#define CSR_USB_EP_0_IN_EV_ENABLE_ADDR 0xe000482c
#define CSR_USB_EP_0_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_0_in_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe000482c);
return r;
}
static inline void usb_ep_0_in_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe000482c);
}
#define CSR_USB_EP_0_IN_LAST_TOK_ADDR 0xe0004830
#define CSR_USB_EP_0_IN_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_0_in_last_tok_read(void)
{
unsigned char r = csr_readl(0xe0004830);
return r;
}
#define CSR_USB_EP_0_IN_RESPOND_ADDR 0xe0004834
#define CSR_USB_EP_0_IN_RESPOND_SIZE 1
static inline unsigned char usb_ep_0_in_respond_read(void)
{
unsigned char r = csr_readl(0xe0004834);
return r;
}
static inline void usb_ep_0_in_respond_write(unsigned char value)
{
csr_writel(value, 0xe0004834);
}
#define CSR_USB_EP_0_IN_DTB_ADDR 0xe0004838
#define CSR_USB_EP_0_IN_DTB_SIZE 1
static inline unsigned char usb_ep_0_in_dtb_read(void)
{
unsigned char r = csr_readl(0xe0004838);
return r;
}
static inline void usb_ep_0_in_dtb_write(unsigned char value)
{
csr_writel(value, 0xe0004838);
}
#define CSR_USB_EP_0_IN_IBUF_HEAD_ADDR 0xe000483c
#define CSR_USB_EP_0_IN_IBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_0_in_ibuf_head_read(void)
{
unsigned char r = csr_readl(0xe000483c);
return r;
}
static inline void usb_ep_0_in_ibuf_head_write(unsigned char value)
{
csr_writel(value, 0xe000483c);
}
#define CSR_USB_EP_0_IN_IBUF_EMPTY_ADDR 0xe0004840
#define CSR_USB_EP_0_IN_IBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_0_in_ibuf_empty_read(void)
{
unsigned char r = csr_readl(0xe0004840);
return r;
}
#define CSR_USB_EP_1_IN_EV_STATUS_ADDR 0xe0004844
#define CSR_USB_EP_1_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_1_in_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0004844);
return r;
}
static inline void usb_ep_1_in_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0004844);
}
#define CSR_USB_EP_1_IN_EV_PENDING_ADDR 0xe0004848
#define CSR_USB_EP_1_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_1_in_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe0004848);
return r;
}
static inline void usb_ep_1_in_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe0004848);
}
#define CSR_USB_EP_1_IN_EV_ENABLE_ADDR 0xe000484c
#define CSR_USB_EP_1_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_1_in_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe000484c);
return r;
}
static inline void usb_ep_1_in_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe000484c);
}
#define CSR_USB_EP_1_IN_LAST_TOK_ADDR 0xe0004850
#define CSR_USB_EP_1_IN_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_1_in_last_tok_read(void)
{
unsigned char r = csr_readl(0xe0004850);
return r;
}
#define CSR_USB_EP_1_IN_RESPOND_ADDR 0xe0004854
#define CSR_USB_EP_1_IN_RESPOND_SIZE 1
static inline unsigned char usb_ep_1_in_respond_read(void)
{
unsigned char r = csr_readl(0xe0004854);
return r;
}
static inline void usb_ep_1_in_respond_write(unsigned char value)
{
csr_writel(value, 0xe0004854);
}
#define CSR_USB_EP_1_IN_DTB_ADDR 0xe0004858
#define CSR_USB_EP_1_IN_DTB_SIZE 1
static inline unsigned char usb_ep_1_in_dtb_read(void)
{
unsigned char r = csr_readl(0xe0004858);
return r;
}
static inline void usb_ep_1_in_dtb_write(unsigned char value)
{
csr_writel(value, 0xe0004858);
}
#define CSR_USB_EP_1_IN_IBUF_HEAD_ADDR 0xe000485c
#define CSR_USB_EP_1_IN_IBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_1_in_ibuf_head_read(void)
{
unsigned char r = csr_readl(0xe000485c);
return r;
}
static inline void usb_ep_1_in_ibuf_head_write(unsigned char value)
{
csr_writel(value, 0xe000485c);
}
#define CSR_USB_EP_1_IN_IBUF_EMPTY_ADDR 0xe0004860
#define CSR_USB_EP_1_IN_IBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_1_in_ibuf_empty_read(void)
{
unsigned char r = csr_readl(0xe0004860);
return r;
}
#define CSR_USB_EP_2_OUT_EV_STATUS_ADDR 0xe0004864
#define CSR_USB_EP_2_OUT_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_2_out_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0004864);
return r;
}
static inline void usb_ep_2_out_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0004864);
}
#define CSR_USB_EP_2_OUT_EV_PENDING_ADDR 0xe0004868
#define CSR_USB_EP_2_OUT_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_2_out_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe0004868);
return r;
}
static inline void usb_ep_2_out_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe0004868);
}
#define CSR_USB_EP_2_OUT_EV_ENABLE_ADDR 0xe000486c
#define CSR_USB_EP_2_OUT_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_2_out_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe000486c);
return r;
}
static inline void usb_ep_2_out_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe000486c);
}
#define CSR_USB_EP_2_OUT_LAST_TOK_ADDR 0xe0004870
#define CSR_USB_EP_2_OUT_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_2_out_last_tok_read(void)
{
unsigned char r = csr_readl(0xe0004870);
return r;
}
#define CSR_USB_EP_2_OUT_RESPOND_ADDR 0xe0004874
#define CSR_USB_EP_2_OUT_RESPOND_SIZE 1
static inline unsigned char usb_ep_2_out_respond_read(void)
{
unsigned char r = csr_readl(0xe0004874);
return r;
}
static inline void usb_ep_2_out_respond_write(unsigned char value)
{
csr_writel(value, 0xe0004874);
}
#define CSR_USB_EP_2_OUT_DTB_ADDR 0xe0004878
#define CSR_USB_EP_2_OUT_DTB_SIZE 1
static inline unsigned char usb_ep_2_out_dtb_read(void)
{
unsigned char r = csr_readl(0xe0004878);
return r;
}
static inline void usb_ep_2_out_dtb_write(unsigned char value)
{
csr_writel(value, 0xe0004878);
}
#define CSR_USB_EP_2_OUT_OBUF_HEAD_ADDR 0xe000487c
#define CSR_USB_EP_2_OUT_OBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_2_out_obuf_head_read(void)
{
unsigned char r = csr_readl(0xe000487c);
return r;
}
static inline void usb_ep_2_out_obuf_head_write(unsigned char value)
{
csr_writel(value, 0xe000487c);
}
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_ADDR 0xe0004880
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_2_out_obuf_empty_read(void)
{
unsigned char r = csr_readl(0xe0004880);
return r;
}
#define CSR_USB_EP_2_IN_EV_STATUS_ADDR 0xe0004884
#define CSR_USB_EP_2_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_2_in_ev_status_read(void)
{
unsigned char r = csr_readl(0xe0004884);
return r;
}
static inline void usb_ep_2_in_ev_status_write(unsigned char value)
{
csr_writel(value, 0xe0004884);
}
#define CSR_USB_EP_2_IN_EV_PENDING_ADDR 0xe0004888
#define CSR_USB_EP_2_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_2_in_ev_pending_read(void)
{
unsigned char r = csr_readl(0xe0004888);
return r;
}
static inline void usb_ep_2_in_ev_pending_write(unsigned char value)
{
csr_writel(value, 0xe0004888);
}
#define CSR_USB_EP_2_IN_EV_ENABLE_ADDR 0xe000488c
#define CSR_USB_EP_2_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_2_in_ev_enable_read(void)
{
unsigned char r = csr_readl(0xe000488c);
return r;
}
static inline void usb_ep_2_in_ev_enable_write(unsigned char value)
{
csr_writel(value, 0xe000488c);
}
#define CSR_USB_EP_2_IN_LAST_TOK_ADDR 0xe0004890
#define CSR_USB_EP_2_IN_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_2_in_last_tok_read(void)
{
unsigned char r = csr_readl(0xe0004890);
return r;
}
#define CSR_USB_EP_2_IN_RESPOND_ADDR 0xe0004894
#define CSR_USB_EP_2_IN_RESPOND_SIZE 1
static inline unsigned char usb_ep_2_in_respond_read(void)
{
unsigned char r = csr_readl(0xe0004894);
return r;
}
static inline void usb_ep_2_in_respond_write(unsigned char value)
{
csr_writel(value, 0xe0004894);
}
#define CSR_USB_EP_2_IN_DTB_ADDR 0xe0004898
#define CSR_USB_EP_2_IN_DTB_SIZE 1
static inline unsigned char usb_ep_2_in_dtb_read(void)
{
unsigned char r = csr_readl(0xe0004898);
return r;
}
static inline void usb_ep_2_in_dtb_write(unsigned char value)
{
csr_writel(value, 0xe0004898);
}
#define CSR_USB_EP_2_IN_IBUF_HEAD_ADDR 0xe000489c
#define CSR_USB_EP_2_IN_IBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_2_in_ibuf_head_read(void)
{
unsigned char r = csr_readl(0xe000489c);
return r;
}
static inline void usb_ep_2_in_ibuf_head_write(unsigned char value)
{
csr_writel(value, 0xe000489c);
}
#define CSR_USB_EP_2_IN_IBUF_EMPTY_ADDR 0xe00048a0
#define CSR_USB_EP_2_IN_IBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_2_in_ibuf_empty_read(void)
{
unsigned char r = csr_readl(0xe00048a0);
return r;
}
/* version */
#define CSR_VERSION_BASE 0xe0007000
#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MAJOR_SIZE 1
static inline unsigned char version_major_read(void)
{
unsigned char r = csr_readl(0xe0007000);
return r;
}
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_MINOR_SIZE 1
static inline unsigned char version_minor_read(void)
{
unsigned char r = csr_readl(0xe0007004);
return r;
}
#define CSR_VERSION_REVISION_ADDR 0xe0007008
#define CSR_VERSION_REVISION_SIZE 1
static inline unsigned char version_revision_read(void)
{
unsigned char r = csr_readl(0xe0007008);
return r;
}
#define CSR_VERSION_GITREV_ADDR 0xe000700c
#define CSR_VERSION_GITREV_SIZE 4
static inline unsigned int version_gitrev_read(void)
{
unsigned int r = csr_readl(0xe000700c);
r <<= 8;
r |= csr_readl(0xe0007010);
r <<= 8;
r |= csr_readl(0xe0007014);
r <<= 8;
r |= csr_readl(0xe0007018);
return r;
}
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
#define CSR_VERSION_GITEXTRA_SIZE 2
static inline unsigned short int version_gitextra_read(void)
{
unsigned short int r = csr_readl(0xe000701c);
r <<= 8;
r |= csr_readl(0xe0007020);
return r;
}
#define CSR_VERSION_DIRTY_ADDR 0xe0007024
#define CSR_VERSION_DIRTY_SIZE 1
static inline unsigned char version_dirty_read(void)
{
unsigned char r = csr_readl(0xe0007024);
return r;
}
/* constants */
#define NMI_INTERRUPT 0
static inline int nmi_interrupt_read(void)
{
return 0;
}
#define TIMER0_INTERRUPT 1
static inline int timer0_interrupt_read(void)
{
return 1;
}
#define UART_INTERRUPT 2
static inline int uart_interrupt_read(void)
{
return 2;
}
#define USB_INTERRUPT 3
static inline int usb_interrupt_read(void)
{
return 3;
}
#define CSR_DATA_WIDTH 8
static inline int csr_data_width_read(void)
{
return 8;
}
#define SYSTEM_CLOCK_FREQUENCY 12000000
static inline int system_clock_frequency_read(void)
{
return 12000000;
}
#define CONFIG_CLOCK_FREQUENCY 12000000
static inline int config_clock_frequency_read(void)
{
return 12000000;
}
#define CONFIG_CPU_RESET_ADDR 0
static inline int config_cpu_reset_addr_read(void)
{
return 0;
}
#define CONFIG_CPU_TYPE "VEXRISCV"
static inline const char *config_cpu_type_read(void)
{
return "VEXRISCV";
}
#define CONFIG_CPU_VARIANT "VEXRISCV"
static inline const char *config_cpu_variant_read(void)
{
return "VEXRISCV";
}
#define CONFIG_CSR_DATA_WIDTH 8
static inline int config_csr_data_width_read(void)
{
return 8;
}
#endif

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#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H
#define VEXRISCV_DEBUG_BASE 0xf00f0000
#define VEXRISCV_DEBUG_SIZE 0x00000010
#define SRAM_BASE 0x10000000
#define SRAM_SIZE 0x00020000
#define ROM_BASE 0x00000000
#define ROM_SIZE 0x00002000
#define SPIFLASH_BASE 0x20000000
#define SPIFLASH_SIZE 0x00200000
#endif

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#ifndef __IRQ_H
#define __IRQ_H
#include <riscv.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __picorv32__
// PicoRV32 has a very limited interrupt support, implemented via custom
// instructions. It also doesn't have a global interrupt enable/disable, so
// we have to emulate it via saving and restoring a mask and using 0/~1 as a
// hardware mask.
// Due to all this somewhat low-level mess, all of the glue is implemented in
// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
// managed by this layer, do not call interrupt instructions directly, as the
// state will go out of sync with the hardware.
// Read only.
extern unsigned int _irq_pending;
// Read only.
extern unsigned int _irq_mask;
// Read only.
extern unsigned int _irq_enabled;
extern void _irq_enable(void);
extern void _irq_disable(void);
extern void _irq_setmask(unsigned int);
#endif
static inline unsigned int irq_getie(void)
{
#if defined (__lm32__)
unsigned int ie;
__asm__ __volatile__("rcsr %0, IE" : "=r" (ie));
return ie;
#elif defined (__or1k__)
return !!(mfspr(SPR_SR) & SPR_SR_IEE);
#elif defined (__picorv32__)
return _irq_enabled != 0;
#elif defined (__vexriscv__)
return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
#elif defined (__minerva__)
return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
#else
#error Unsupported architecture
#endif
}
static inline void irq_setie(unsigned int ie)
{
#if defined (__lm32__)
__asm__ __volatile__("wcsr IE, %0" : : "r" (ie));
#elif defined (__or1k__)
if (ie & 0x1)
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
else
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
#elif defined (__picorv32__)
if (ie & 0x1)
_irq_enable();
else
_irq_disable();
#elif defined (__vexriscv__)
if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
#elif defined (__minerva__)
if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
#else
#error Unsupported architecture
#endif
}
static inline unsigned int irq_getmask(void)
{
#if defined (__lm32__)
unsigned int mask;
__asm__ __volatile__("rcsr %0, IM" : "=r" (mask));
return mask;
#elif defined (__or1k__)
return mfspr(SPR_PICMR);
#elif defined (__picorv32__)
// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
// LiteX sees things.
return ~_irq_mask;
#elif defined (__vexriscv__)
unsigned int mask;
asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
return mask;
#elif defined (__minerva__)
unsigned int mask;
asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
return mask;
#else
#error Unsupported architecture
#endif
}
static inline void irq_setmask(unsigned int mask)
{
#if defined (__lm32__)
__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
#elif defined (__or1k__)
mtspr(SPR_PICMR, mask);
#elif defined (__picorv32__)
// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
// LiteX sees things.
_irq_setmask(~mask);
#elif defined (__vexriscv__)
asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
#elif defined (__minerva__)
asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
#else
#error Unsupported architecture
#endif
}
static inline unsigned int irq_pending(void)
{
#if defined (__lm32__)
unsigned int pending;
__asm__ __volatile__("rcsr %0, IP" : "=r" (pending));
return pending;
#elif defined (__or1k__)
return mfspr(SPR_PICSR);
#elif defined (__picorv32__)
return _irq_pending;
#elif defined (__vexriscv__)
unsigned int pending;
asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
return pending;
#elif defined (__minerva__)
unsigned int pending;
asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
return pending;
#else
#error Unsupported architecture
#endif
}
#ifdef __cplusplus
}
#endif
#endif /* __IRQ_H */

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#ifndef _RGB_H_
#define _RGB_H_
void rgb_init(void);
void rgb_mode_idle(void);
void rgb_mode_done(void);
void rgb_mode_writing(void);
void rgb_mode_error(void);
#endif /* _RGB_H_ */

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#ifndef RISCV_DEFS_H__
#define RISCV_DEFS_H__
#include <fomu/csr.h>
#define CSR_MSTATUS_MIE 0x8
#define CSR_IRQ_MASK 0xBC0
#define CSR_IRQ_PENDING 0xFC0
#define CSR_DCACHE_INFO 0xCC0
#ifdef __cplusplus
extern "C" {
#endif
void flush_cpu_icache(void);
void flush_cpu_dcache(void);
void flush_l2_cache(void);
#define csrr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define csrw(reg, val) ({ \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
else \
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
#define csrs(reg, bit) ({ \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
else \
asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
#define csrc(reg, bit) ({ \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
else \
asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
#ifdef __cplusplus
}
#endif
__attribute__((noreturn)) void reboot(void);
__attribute__((noreturn)) static inline void warmboot_to_image(uint8_t image_index) {
reboot_ctrl_write(0xac | (image_index & 3) << 0);
while (1);
}
#endif /* RISCV_DEFS_H__ */

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#ifndef BB_SPI_H_
#define BB_SPI_H_
#include <stdint.h>
enum spi_state {
SS_UNCONFIGURED = 0,
SS_SINGLE,
SS_DUAL_RX,
SS_DUAL_TX,
SS_QUAD_RX,
SS_QUAD_TX,
SS_HARDWARE,
};
enum spi_type {
ST_UNCONFIGURED,
ST_SINGLE,
ST_DUAL,
ST_QUAD,
ST_QPI,
};
enum spi_pin {
SP_MOSI,
SP_MISO,
SP_HOLD,
SP_WP,
SP_CS,
SP_CLK,
SP_D0,
SP_D1,
SP_D2,
SP_D3,
};
struct spi_id {
uint8_t manufacturer_id; // Result from 0x90
uint8_t device_id; // Result from 0x90
uint8_t _manufacturer_id; // Result from 0x9f
uint8_t memory_type; // Result from 0x9f
uint8_t memory_size; // Result from 0x9f
uint8_t signature; // Result from 0xab
uint8_t serial[4]; // Result from 0x4b
int bytes; // -1 if unknown
const char *manufacturer;
const char *model;
const char *capacity;
};
struct ff_spi;
void spiPause(struct ff_spi *spi);
void spiBegin(struct ff_spi *spi);
void spiEnd(struct ff_spi *spi);
//void spiSingleTx(struct ff_spi *spi, uint8_t out);
//uint8_t spiSingleRx(struct ff_spi *spi);
//void spiDualTx(struct ff_spi *spi, uint8_t out);
//void spiQuadTx(struct ff_spi *spi, uint8_t out);
void spiCommand(struct ff_spi *spi, uint8_t cmd);
//uint8_t spiDualRx(struct ff_spi *spi);
//uint8_t spiQuadRx(struct ff_spi *spi);
int spiTx(struct ff_spi *spi, uint8_t word);
uint8_t spiRx(struct ff_spi *spi);
uint8_t spiReadStatus(struct ff_spi *spi, uint8_t sr);
void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val);
void spiReadSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]);
void spiWriteSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]);
int spiSetType(struct ff_spi *spi, enum spi_type type);
int spiRead(struct ff_spi *spi, uint32_t addr, uint8_t *data, unsigned int count);
int spiIsBusy(struct ff_spi *spi);
int spiBeginErase32(struct ff_spi *spi, uint32_t erase_addr);
int spiBeginErase64(struct ff_spi *spi, uint32_t erase_addr);
int spiBeginWrite(struct ff_spi *spi, uint32_t addr, const void *data, unsigned int count);
void spiEnableQuad(void);
struct spi_id spiId(struct ff_spi *spi);
void spiOverrideSize(struct ff_spi *spi, uint32_t new_size);
//int spi_wait_for_not_busy(struct ff_spi *spi);
int spiWrite(struct ff_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count);
uint8_t spiReset(struct ff_spi *spi);
int spiInit(struct ff_spi *spi);
void spiHold(struct ff_spi *spi);
void spiUnhold(struct ff_spi *spi);
void spiSwapTxRx(struct ff_spi *spi);
struct ff_spi *spiAlloc(void);
void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val);
void spiFree(void);
#endif /* BB_SPI_H_ */

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#ifndef __TIME_H
#define __TIME_H
#ifdef __cplusplus
extern "C" {
#endif
void time_init(void);
int elapsed(int *last_event, int period);
void msleep(int ms);
#ifdef __cplusplus
}
#endif
#endif /* __TIME_H */

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/** @defgroup usb_cdc_defines USB CDC Type Definitions
@brief <b>Defined Constants and Types for the USB CDC Type Definitions</b>
@ingroup USB_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef __CDC_H
#define __CDC_H
/* Definitions of Communications Device Class from
* "Universal Serial Bus Class Definitions for Communications Devices
* Revision 1.2"
*/
/* Table 2: Communications Device Class Code */
#define USB_CLASS_CDC 0x02
/* Table 4: Class Subclass Code */
#define USB_CDC_SUBCLASS_DLCM 0x01
#define USB_CDC_SUBCLASS_ACM 0x02
/* ... */
/* Table 5 Communications Interface Class Control Protocol Codes */
#define USB_CDC_PROTOCOL_NONE 0x00
#define USB_CDC_PROTOCOL_AT 0x01
/* ... */
/* Table 6: Data Interface Class Code */
#define USB_CLASS_DATA 0x0A
/* Table 12: Type Values for the bDescriptorType Field */
#define CS_INTERFACE 0x24
#define CS_ENDPOINT 0x25
/* Table 13: bDescriptor SubType in Communications Class Functional
* Descriptors */
#define USB_CDC_TYPE_HEADER 0x00
#define USB_CDC_TYPE_CALL_MANAGEMENT 0x01
#define USB_CDC_TYPE_ACM 0x02
/* ... */
#define USB_CDC_TYPE_UNION 0x06
/* ... */
/* Table 15: Class-Specific Descriptor Header Format */
struct usb_cdc_header_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint16_t bcdCDC;
} __attribute__((packed));
/* Table 16: Union Interface Functional Descriptor */
struct usb_cdc_union_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bControlInterface;
uint8_t bSubordinateInterface0;
/* ... */
} __attribute__((packed));
/* Definitions for Abstract Control Model devices from:
* "Universal Serial Bus Communications Class Subclass Specification for
* PSTN Devices"
*/
/* Table 3: Call Management Functional Descriptor */
struct usb_cdc_call_management_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
uint8_t bDataInterface;
} __attribute__((packed));
/* Table 4: Abstract Control Management Functional Descriptor */
struct usb_cdc_acm_descriptor {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
} __attribute__((packed));
/* Table 13: Class-Specific Request Codes for PSTN subclasses */
/* ... */
#define USB_CDC_REQ_SET_LINE_CODING 0x20
/* ... */
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
/* ... */
/* Table 17: Line Coding Structure */
struct usb_cdc_line_coding {
uint32_t dwDTERate;
uint8_t bCharFormat;
uint8_t bParityType;
uint8_t bDataBits;
} __attribute__((packed));
enum usb_cdc_line_coding_bCharFormat {
USB_CDC_1_STOP_BITS = 0,
USB_CDC_1_5_STOP_BITS = 1,
USB_CDC_2_STOP_BITS = 2,
};
enum usb_cdc_line_coding_bParityType {
USB_CDC_NO_PARITY = 0,
USB_CDC_ODD_PARITY = 1,
USB_CDC_EVEN_PARITY = 2,
USB_CDC_MARK_PARITY = 3,
USB_CDC_SPACE_PARITY = 4,
};
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
/* ... */
#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
/* ... */
/* Notification Structure */
struct usb_cdc_notification {
uint8_t bmRequestType;
uint8_t bNotification;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} __attribute__((packed));
#endif
/**@}*/

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/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2013 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _usb_desc_h_
#define _usb_desc_h_
#include <stdint.h>
#include <stddef.h>
struct usb_setup_request {
union {
struct {
uint8_t bmRequestType;
uint8_t bRequest;
};
uint16_t wRequestAndType;
};
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
};
struct usb_string_descriptor_struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wString[];
};
#define NUM_USB_BUFFERS 8
#define VENDOR_ID 0x1209 // pid.codes
#define PRODUCT_ID 0x5bf0 // Assigned to Fomu project
#define DEVICE_VER 0x0101 // Bootloader version
#define MANUFACTURER_NAME u"Foosn"
#define MANUFACTURER_NAME_LEN sizeof(MANUFACTURER_NAME)
#define PRODUCT_NAME u"Fomu Factory Test " GIT_VERSION
#define PRODUCT_NAME_LEN sizeof(PRODUCT_NAME)
#define EP0_SIZE 64
#define NUM_INTERFACE 1
#define CONFIG_DESC_SIZE 67
#define USB_DT_INTERFACE_SIZE 9
/* USB Descriptor Types - Table 9-5 */
#define USB_DT_DEVICE 1
#define USB_DT_CONFIGURATION 2
#define USB_DT_STRING 3
#define USB_DT_INTERFACE 4
#define USB_DT_ENDPOINT 5
#define USB_DT_DEVICE_QUALIFIER 6
#define USB_DT_OTHER_SPEED_CONFIGURATION 7
#define USB_DT_INTERFACE_POWER 8
/* From ECNs */
#define USB_DT_OTG 9
#define USB_DT_DEBUG 10
#define USB_DT_INTERFACE_ASSOCIATION 11
#define USB_DT_ENDPOINT_SIZE 7
/* USB Endpoint Descriptor bmAttributes bit definitions - Table 9-13 */
/* bits 1..0 : transfer type */
#define USB_ENDPOINT_ATTR_CONTROL 0x00
#define USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01
#define USB_ENDPOINT_ATTR_BULK 0x02
#define USB_ENDPOINT_ATTR_INTERRUPT 0x03
#define USB_ENDPOINT_ATTR_TYPE 0x03
typedef struct {
uint16_t wValue;
uint16_t length;
const uint8_t *addr;
} usb_descriptor_list_t;
extern const usb_descriptor_list_t usb_descriptor_list[];
#endif

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sw/include/usb.h Normal file
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#ifndef __USB_H
#define __USB_H
#ifdef __cplusplus
extern "C" {
#endif
struct usb_setup_request;
void usb_isr(void);
void usb_init(void);
void usb_connect(void);
void usb_idle(void);
void usb_disconnect(void);
int usb_irq_happened(void);
void usb_setup(const struct usb_setup_request *setup);
void usb_send(const void *data, int total_count);
void usb_ack_in(void);
void usb_ack_out(void);
void usb_err(void);
int usb_recv(void *buffer, unsigned int buffer_len);
void usb_poll(void);
void usb_wait_for_send_done(void);
#ifdef __cplusplus
}
#endif
#endif