146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
#ifndef __IRQ_H
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#define __IRQ_H
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#include <riscv.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __picorv32__
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// PicoRV32 has a very limited interrupt support, implemented via custom
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// instructions. It also doesn't have a global interrupt enable/disable, so
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// we have to emulate it via saving and restoring a mask and using 0/~1 as a
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// hardware mask.
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// Due to all this somewhat low-level mess, all of the glue is implemented in
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// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
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// managed by this layer, do not call interrupt instructions directly, as the
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// state will go out of sync with the hardware.
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// Read only.
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extern unsigned int _irq_pending;
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// Read only.
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extern unsigned int _irq_mask;
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// Read only.
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extern unsigned int _irq_enabled;
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extern void _irq_enable(void);
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extern void _irq_disable(void);
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extern void _irq_setmask(unsigned int);
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#endif
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static inline unsigned int irq_getie(void)
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{
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#if defined (__lm32__)
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unsigned int ie;
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__asm__ __volatile__("rcsr %0, IE" : "=r" (ie));
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return ie;
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#elif defined (__or1k__)
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return !!(mfspr(SPR_SR) & SPR_SR_IEE);
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#elif defined (__picorv32__)
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return _irq_enabled != 0;
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#elif defined (__vexriscv__)
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return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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#elif defined (__minerva__)
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return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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#else
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#error Unsupported architecture
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#endif
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}
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static inline void irq_setie(unsigned int ie)
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{
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#if defined (__lm32__)
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__asm__ __volatile__("wcsr IE, %0" : : "r" (ie));
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#elif defined (__or1k__)
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if (ie & 0x1)
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
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else
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
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#elif defined (__picorv32__)
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if (ie & 0x1)
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_irq_enable();
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else
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_irq_disable();
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#elif defined (__vexriscv__)
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if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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#elif defined (__minerva__)
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if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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#else
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#error Unsupported architecture
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#endif
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}
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static inline unsigned int irq_getmask(void)
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{
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#if defined (__lm32__)
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unsigned int mask;
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__asm__ __volatile__("rcsr %0, IM" : "=r" (mask));
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return mask;
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#elif defined (__or1k__)
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return mfspr(SPR_PICMR);
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#elif defined (__picorv32__)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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return ~_irq_mask;
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#elif defined (__vexriscv__)
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unsigned int mask;
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asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
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return mask;
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#elif defined (__minerva__)
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unsigned int mask;
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asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
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return mask;
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#else
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#error Unsupported architecture
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#endif
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}
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static inline void irq_setmask(unsigned int mask)
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{
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#if defined (__lm32__)
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__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
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#elif defined (__or1k__)
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mtspr(SPR_PICMR, mask);
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#elif defined (__picorv32__)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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_irq_setmask(~mask);
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#elif defined (__vexriscv__)
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asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
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#elif defined (__minerva__)
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asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
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#else
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#error Unsupported architecture
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#endif
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}
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static inline unsigned int irq_pending(void)
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{
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#if defined (__lm32__)
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unsigned int pending;
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__asm__ __volatile__("rcsr %0, IP" : "=r" (pending));
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return pending;
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#elif defined (__or1k__)
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return mfspr(SPR_PICSR);
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#elif defined (__picorv32__)
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return _irq_pending;
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#elif defined (__vexriscv__)
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unsigned int pending;
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asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
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return pending;
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#elif defined (__minerva__)
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unsigned int pending;
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asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
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return pending;
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#else
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#error Unsupported architecture
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IRQ_H */
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