From 8aed600cd63dfca30e32c19b159b5319f5272e93 Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Sun, 10 Mar 2019 21:05:12 +0800
Subject: [PATCH] hw: foboot-bitstream: specify additional clock domain
 constraints

Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>
---
 hw/foboot-bitstream.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py
index cd965f1..7fae8a0 100755
--- a/hw/foboot-bitstream.py
+++ b/hw/foboot-bitstream.py
@@ -132,6 +132,7 @@ class _CRG(Module):
             i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
             o_GLOBAL_BUFFER_OUTPUT=clk12,
         )
+        platform.add_period_constraint(clk12_raw, 1e9/12e6)
 
         self.specials += Instance(
             "SB_PLL40_CORE",