232 lines
5.1 KiB
Markdown
232 lines
5.1 KiB
Markdown
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- [The State of Open Silicon](#the-state-of-open-silicon)
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- [Talk Outline](#talk-outline)
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- [About Me](#about-me)
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- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
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- [Levels of "open"](#levels-of-open)
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- [Parts of chip design](#parts-of-chip-design)
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- [Process Design Kit](#process-design-kit)
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- [Intellectual Property / Libraries](#intellectual-property--libraries)
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- [Digital design (In The Beginning)](#digital-design-in-the-beginning)
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- [Digital logic overview (Today)](#digital-logic-overview-today)
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- [How can we use standard cells?](#how-can-we-use-standard-cells)
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- [Tooling](#tooling)
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- [End-to-end runs take weeks or months](#end-to-end-runs-take-weeks-or-months)
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- [Method to tape out](#method-to-tape-out)
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- [Where are we now (in open source)?](#where-are-we-now-in-open-source)
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- [Things are looking pretty good](#things-are-looking-pretty-good)
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- [End-to-end tool flow possible](#end-to-end-tool-flow-possible)
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- [Open PDKs](#open-pdks)
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- [Available IP](#available-ip)
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- [Standard cells](#standard-cells)
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- [What about tooling?](#what-about-tooling)
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- [Hardware synthesis](#hardware-synthesis)
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- [High level languages](#high-level-languages)
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- [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
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- [Power and Clock generation](#power-and-clock-generation)
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- [Verification](#verification)
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- [What about taping out chips?](#what-about-taping-out-chips)
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- [What can't we do today?](#what-cant-we-do-today)
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- [Memories are still hard](#memories-are-still-hard)
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- [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard)
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- [Analogue IP is still difficult](#analogue-ip-is-still-difficult)
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- [Where are we going from here?](#where-are-we-going-from-here)
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- [Improved languages](#improved-languages)
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- [Improved memories](#improved-memories)
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- [Better inference](#better-inference)
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- [More analogue IP](#more-analogue-ip)
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- [Getting involved!](#getting-involved)
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# The State of Open Silicon
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# Talk Outline
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- What does it mean to be "open"?
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- What can we do today?
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- What can't we do today?
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- Where can we go from here?
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# About Me
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# What does it mean for silicon to be "Open"?
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## Levels of "open"
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1. Manuals available
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2. Source available
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3. GDSII available
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## Parts of chip design
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1. PDKs
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2. IP
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3. Tooling
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4. Method to tape out
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## Process Design Kit
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- <https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg>
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- Process design kits (PDKs) are closed and under NDA
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- Mostly just a blank canvas
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## Intellectual Property / Libraries
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- Memories
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- IO blocks
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- Standard cells
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## Digital design (In The Beginning)
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- [Picture of Z80 or 6502]
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- Magic
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- [Picture of Siliwiz]
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## Digital logic overview (Today)
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- Standard cells
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- Basic boolean logic
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## How can we use standard cells?
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- Manual synthesis
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- Automated synthesis
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Almost all code is automatically synthesized from source code!
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[Example of live generation of cells]
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## Tooling
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- Synthesis
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- Power generation
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- Clock tree
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- Place and route
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- Verification
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- **Industry tools cost $1mm plus per seat**
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## End-to-end runs take weeks or months
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- Specialized tooling requires specialized engineers
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- Large separation between digital designers and tapeout
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## Method to tape out
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- Shuttle runs
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- Full wafer
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- Turnaround time is in months
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# Where are we now (in open source)?
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## Things are looking pretty good
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## End-to-end tool flow possible
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- Open tooling, open PDK
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- Chips have been produced using this flow
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- Digital logic is very doable
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## Open PDKs
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- Real PDKs
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- SKY130
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- SKY90FD
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- GF180MCU
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- "Fake" PDKs
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- FreePDK45
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- ASAP5
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## Available IP
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- OpenMPW projects
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- ADC, LDO, Bandgap, DAC, and more
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## Standard cells
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- SKY130
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- GF180MCU
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- OSU
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- LibreSilicon
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## What about tooling?
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## Hardware synthesis
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- Yosys (Verilog)
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- VHDL
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- SystemVerilog
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## High level languages
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- LiteX [Python]
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- SpinalHDL [Scala]
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- Clash
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These all generate Verilog, and are fully open!
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## Floorplanning, Placement, Routing
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- OpenROAD is the current gold-standard
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- Competitive with closed tools
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## Power and Clock generation
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- Setup and hold timing validation
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- Basic power nets supported
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- Straps are generated as expected
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## Verification
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- Parasitic extraction works
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- Layout-versus-Schematics
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- Simulation of extracted netlist
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- Design Rule Checking
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## What about taping out chips?
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- Google OpenMPW shuttles
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- MPW shuttle runs
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# What can't we do today?
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## Memories are still hard
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- Density is constantly improving
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- Expect kilobytes of RAM on a chip
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- Compare to megabytes of cache
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- A ~4x increase is possible
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## Nonvolatile storage is still hard
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- No EEPROM or flash
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- ReRAM is experimental on SKY130
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## Analogue IP is still difficult
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- Some tapeouts exist, but documentation is scarce
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- Need more integration examples
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# Where are we going from here?
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## Improved languages
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- Type-checking for timing?
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- Bus integration
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- Documentation generation
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## Improved memories
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- OpenRAM coming to more processes
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## Better inference
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## More analogue IP
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# Getting involved!
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- Siliwiz for raw tapeout
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- TinyTapeout
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- Write more blogposts
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- Give it a try
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Thank you!
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