fa23-si/talk.md

• The State of Open Silicon
• Talk Outline
• About Me
• What does it mean for silicon to be "Open"?
  • Levels of "open"
  • Parts of chip design
  • Process Design Kit
  • Intellectual Property / Libraries
  • Digital design (In The Beginning)
  • Digital logic overview (Today)
  • How can we use standard cells?
  • Tooling
  • End-to-end runs take weeks or months
  • Method to tape out
• Where are we now (in open source)?
  • Things are looking pretty good
  • End-to-end tool flow possible
  • Open PDKs
  • Available IP
  • Standard cells
  • What about tooling?
  • Hardware synthesis
  • High level languages
  • Floorplanning, Placement, Routing
  • Power and Clock generation
  • Verification
  • What about taping out chips?
• What can't we do today?
  • Memories are still hard
  • Nonvolatile storage is still hard
  • Analogue IP is still difficult
• Where are we going from here?
  • Improved languages
  • Improved memories
  • Better inference
  • More analogue IP
• Getting involved!

The State of Open Silicon

Talk Outline

• What does it mean to be "open"?
• What can we do today?
• What can't we do today?
• Where can we go from here?

About Me

What does it mean for silicon to be "Open"?

Levels of "open"

1. Manuals available
2. Source available
3. GDSII available

Parts of chip design

1. PDKs
2. IP
3. Tooling
4. Method to tape out

Process Design Kit

• https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg
• Process design kits (PDKs) are closed and under NDA
• Mostly just a blank canvas

Intellectual Property / Libraries

• Memories
• IO blocks
• Standard cells

Digital design (In The Beginning)

• [Picture of Z80 or 6502]
• Magic
• [Picture of Siliwiz]

Digital logic overview (Today)

• Standard cells
• Basic boolean logic

How can we use standard cells?

• Manual synthesis
• Automated synthesis

Almost all code is automatically synthesized from source code!

[Example of live generation of cells]

Tooling

• Synthesis
• Power generation
• Clock tree
• Place and route
• Verification
• Industry tools cost $1mm plus per seat

End-to-end runs take weeks or months

• Specialized tooling requires specialized engineers
• Large separation between digital designers and tapeout

Method to tape out

• Shuttle runs
• Full wafer
• Turnaround time is in months

Where are we now (in open source)?

Things are looking pretty good

End-to-end tool flow possible

• Open tooling, open PDK
• Chips have been produced using this flow
• Digital logic is very doable

Open PDKs

• Real PDKs
  • SKY130
  • SKY90FD
  • GF180MCU
• "Fake" PDKs
  • FreePDK45
  • ASAP5

Available IP

• OpenMPW projects
• ADC, LDO, Bandgap, DAC, and more

Standard cells

• SKY130
• GF180MCU
• OSU
• LibreSilicon

What about tooling?

Hardware synthesis

• Yosys (Verilog)
  • VHDL
  • SystemVerilog

High level languages

• LiteX [Python]
• SpinalHDL [Scala]
• Clash

These all generate Verilog, and are fully open!

Floorplanning, Placement, Routing

• OpenROAD is the current gold-standard
• Competitive with closed tools

Power and Clock generation

• Setup and hold timing validation
• Basic power nets supported
• Straps are generated as expected

Verification

• Parasitic extraction works
• Layout-versus-Schematics
• Simulation of extracted netlist
• Design Rule Checking

What about taping out chips?

• Google OpenMPW shuttles
• MPW shuttle runs

What can't we do today?

Memories are still hard

• Density is constantly improving
• Expect kilobytes of RAM on a chip
  • Compare to megabytes of cache
• A ~4x increase is possible

Nonvolatile storage is still hard

• No EEPROM or flash
• ReRAM is experimental on SKY130

Analogue IP is still difficult

• Some tapeouts exist, but documentation is scarce
• Need more integration examples

Where are we going from here?

Improved languages

• Type-checking for timing?
• Bus integration
• Documentation generation

Improved memories

• OpenRAM coming to more processes

Better inference

More analogue IP

Getting involved!

• Siliwiz for raw tapeout
• TinyTapeout
• Write more blogposts
• Give it a try

Thank you!