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slight reworking 

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2023-04-08 14:44:52 +08:00
parent bce2cbf9b5
commit 86a661f686
2 changed files with 118 additions and 22 deletions
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135
index.html
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@ -19,6 +19,9 @@
<div class="reveal">
<div class="slides">
<section>The State of Open Silicon</section>
<section>
<h2>About Me</h2>
</section>
<section>
<h2>Outline</h2>
<ol>
@ -28,9 +31,6 @@
<li>Where can we go from here?</li>
</ol>
</section>
<section>
<h2>About Me</h2>
</section>
<section>
<section>
<h2>What does it mean to be "open"?</h2>
@ -44,12 +44,17 @@
<section>
<h2>Parts of chip design</h2>
<ul>
<li>Nondisclosure Agreements</li>
<li>Process Design Kit (PDK)</li>
<li>IP (libraries)</li>
<li>Tooling</li>
<li>Fabrication method</li>
</ul>
</section>
<section>
<h2>Nondisclosure Agreements</h2>
NDAs are required for using many packages
</section>
<section>
<h2>Process Design Kit</h2>
<ul>
@ -120,6 +125,10 @@
<section>
<h2>Things are looking pretty good!</h2>
</section>
<section>
<h2>Nondisclosure Agreements</h2>
NDAs are required for using many packages
</section>
<section>
<h2>Open PDKs</h2>
<ul>
@ -138,7 +147,7 @@
</section>
<section>
<h2>Available IP</h2>
Projects that have been taped out
<p>Projects that have been taped out</p>
<ul>
<li>ADC</li>
<li>LDO</li>
@ -149,7 +158,6 @@
</section>
<section>
<h2>Standard cells</h2>
<ul>
<li>SKY130</li>
<li>GF180MCU</li>
@ -157,6 +165,36 @@
<li>LibreSilicon</li>
</ul>
</section>
<section>
<h2>What about tooling?</h2>
</section>
<section>
<h2>Hardware Synthesis</h2>
<ul>
<li>Yosys (Verilog)</li>
<li>Plugins:</li>
<ul>
<li>GHDL (VHDL)</li>
<li>SystemVerilog</li>
</ul>
</ul>
</section>
<section>
<h2>High level languages</h2>
<ul>
<li>LiteX <i>Python</i></li>
<li>SpinalHDL <i>Scala</i></li>
<li>Clash</li>
</ul>
</section>
<section>
<h2>Floorplanning, Placement, Routing, PDN, etc...</h2>
<ul>
<li>OpenROAD</li>
<li>Integrates other tools natively</li>
<li>Competitive with closed tools</li>
</ul>
</section>
<section>
<h2>Simulation</h2>
<ul>
@ -167,28 +205,29 @@
</ul>
</section>
<section>
<h2>Design Synthesis</h2>
<ul>
<li>Verilog / VHDL -> Verilog</li>
</ul>
</section>
<section>
<h2>Place and Route</h2>
</section>
<section>
<h2>Direct Cell Design</h2>
<h2>Direct Cell Design and Inspection</h2>
<ul>
<li>Magic</li>
<li>KLayout</li>
</ul>
</section>
<section>
<h2>What about taping out chips?</h2>
<ul>
<li>Google OpenMPW shuttles</li>
<li>MPW shuttle runs</li>
</ul>
</section>
</section>
<section>
<section>
<h1>What can we do now?</h1>
<h1># What can't we do today?</h1>
</section>
<section>
<h2>Examples of 130 nm</h2>
<h2>PDKs are large nodes</h2>
<ul>
<li>Gamecube CPU "Gekko": 43 mm<sup>2</sup> (2001)</li>
</ul>
@ -197,6 +236,68 @@
<li>Playstation 2 "Emotion Engine"</li>
</ul>
</section>
<section>
<h2>Memories are still hard</h2>
<ul>
<li>Density is constantly improving</li>
<li>Expect kilobytes of RAM on a chip</li>
<ul>
<li>Compare to megabytes of cache</li>
</ul>
<li>A ~4x increase is possible</li>
<li>Experimental ROM support</li>
</ul>
</section>
<section>
<h2>Nonvolatile storage is still hard</h2>
<ul>
<li>No EEPROM or flash</li>
<li>ReRAM is experimental on SKY130</li>
</ul>
</section>
<section>
<h2>Analogue IP is still difficult</h2>
<ul>
<li>Some tapeouts exist, but documentation is scarce</li>
<li>Need more integration examples</li>
</ul>
</section>
</section>
<section>
<section>
<h2>Where are we going from here?</h2>
<h3>And how you help</h3>
</section>
<section>
<h2>Boon for education</h2>
<ul>
<li>NDA-free design</li>
<li>Many more hobbyists</li>
<li>Zero-to-ASIC course</li>
</ul>
</section>
<section>
<h2>Smaller process nodes</h2>
<ul>
<li>OpenROAD has been tested on smaller nodes</li>
<li>No NDA-free PDKs yet</li>
</ul>
</section>
<section>
<h2>More analogue design</h2>
<ul>
<li>Siliwiz</li>
</ul>
</section>
<section>
<h2>More involvement</h2>
<ul>
<li>Tiny Tapeout</li>
<li>Siliwiz</li>
<li>OpenMPW</li>
</ul>
<h2>Thank you</h2>
</section>
</section>
</div>
</div>

5
talk.md
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@ -29,7 +29,6 @@
- [What can't we do today?](#what-cant-we-do-today)
- [Memories are still hard](#memories-are-still-hard)
- [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard)
- [Current PDKs are large nodes](#current-pdks-are-large-nodes)
- [Analogue IP is still difficult](#analogue-ip-is-still-difficult)
- [Where are we going from here?](#where-are-we-going-from-here)
- [Improved languages](#improved-languages)
@ -201,10 +200,6 @@ These all generate Verilog, and are fully open!
- No EEPROM or flash
- ReRAM is experimental on SKY130
## Current PDKs are large nodes
- 180nm was cutting edge in 1999
## Analogue IP is still difficult
- Some tapeouts exist, but documentation is scarce