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<section>
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<h2>Outline</h2>
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<ol>
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<li>What is Open Silicon?</li>
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<li>What can we do now?</li>
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<li>What's to come?</li>
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<li>What does it mean to be "open"?</li>
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<li>What can we do today?</li>
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<li>What can't we do today?</li>
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<li>Where can we go from here?</li>
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</ol>
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</section>
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<section>
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<h2>About Me</h2>
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</section>
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<section>
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<section>
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<h2>What is Open Silicon?</h2>
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<h2>What does it mean to be "open"?</h2>
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<ol>
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<li>A process design kit that can be manufactured</li>
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<li>An open set of tools to go from design to production</li>
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<li>Easy access to a silicon foundary for small-volume production</li>
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<li>Manuals available</li>
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<li>Source available</li>
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<li>Tooling available</li>
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<li>GDSII available</li>
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</ol>
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</section>
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<section>
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<h2>Parts of chip design</h2>
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<ul>
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<li>Process Design Kit (PDK)</li>
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<li>IP (libraries)</li>
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<li>Tooling</li>
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<li>Fabrication method</li>
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</ul>
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</section>
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<section>
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<h2>Process Design Kit</h2>
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<ul>
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<li>https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg</li>
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<li>Process design kits (PDKs) are closed and under NDA</li>
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<li>Mostly just a blank canvas</li>
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</ul>
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</section>
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<section>
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<h2>IP / Libraries</h2>
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<ul>
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<li>Memories</li>
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<li>IO blocks</li>
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<li>Standard cells</li>
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</ul>
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</section>
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<section>
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<h2>Digital design (In The Beginning)</h2>
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<ul>
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<li>[Picture of Z80 or 6502]</li>
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<li>Magic</li>
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<li>[Picture of Siliwiz]</li>
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</ul>
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</section>
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<section>
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<h2>Digital logic overview (Today)</h2>
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<ul>
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<li>Standard cells</li>
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<li>Basic boolean logic</li>
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</ul>
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</section>
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<section>
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<h2>How can we use standard cells?</h2>
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<ul>
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<li>Manual synthesis</li>
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<li>Automated synthesis</li>
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</ul>
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Almost all code is automatically synthesized from source code!
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[Example of live generation of cells]
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</section>
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<section>
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<h2>Tooling</h2>
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<ul>
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<li>Synthesis</li>
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<li>Power generation</li>
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<li>Clock tree</li>
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<li>Place and route</li>
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<li>Verification</li>
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<li><strong>Industry tools cost $1mm plus per seat</strong></li>
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</ul>
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</section>
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<section>
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<h2>Method to tape out</h2>
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<ul>
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<li>Shuttle runs</li>
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<li>Full wafer</li>
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<li>Turnaround time is in months</li>
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</ul>
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</section>
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</section>
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<section>
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<section>
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<h2>The State of the Toolchin</h2>
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<h2>Where are we now (in open source)?</h2>
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</section>
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<section>
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<h2>Process Design Kits (PDKs)</h2>
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<h2>Things are looking pretty good!</h2>
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</section>
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<section>
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<h2>Open PDKs</h2>
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<ul>
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<li>Real PDKs</li>
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<ul>
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<li>SKY130</li>
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<li>SKY90FD</li>
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<li>GF180MCU </li>
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</ul>
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<li>"Fake" PDKs</li>
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<ul>
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<li>FreePDK45</li>
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<li>ASAP5 </li>
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</ul>
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</ul>
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</section>
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<section>
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<h2>Available IP</h2>
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Projects that have been taped out
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<ul>
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<li>ADC</li>
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<li>LDO</li>
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<li>Bandgap</li>
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<li>DAC</li>
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<li>...more...</li>
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</ul>
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</section>
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<section>
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<h2>Standard cells</h2>
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<ul>
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<li>SKY130</li>
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<li>GF180MCU</li>
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<li><small>FreePDK</small></li>
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<li>OSU</li>
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<li>LibreSilicon</li>
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</ul>
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</section>
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<section>
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<h2>Simulation</h2>
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<ul>
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<li>GHDL</li>
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<li>Icarus Verilog</li>
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<li>Verilator</li>
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<li>GTKWave</li>
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</ul>
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</section>
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<section>
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<h2>Design Synthesis</h2>
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<ul>
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<li>Verilog / VHDL -> Verilog</li>
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</ul>
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</section>
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<section>
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<h2>Place and Route</h2>
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</section>
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<section>
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<h2>Direct Cell Design</h2>
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<ul>
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<li>Magic</li>
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<li>KLayout</li>
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</ul>
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</section>
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</section>
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<section>
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<section>
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<h1>What can we do now?</h1>
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</section>
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<section>
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<h2>Examples of 130 nm</h2>
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<ul>
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<li>Gamecube CPU "Gekko": 43 mm<sup>2</sup> (2001)</li>
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</ul>
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<h2>Examples of 180 nm</h2>
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<ul>
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<li>Playstation 2 "Emotion Engine"</li>
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</ul>
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</section>
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</section>
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talk.md
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@ -1,206 +1,236 @@
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- [The State of Open Silicon](#the-state-of-open-silicon)
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- [Talk Outline](#talk-outline)
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- [About Me](#about-me)
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- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
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- [Levels of "open"](#levels-of-open)
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- [Parts of chip design](#parts-of-chip-design)
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- [Open tooling](#open-tooling)
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- [Manual design (In The Beginning)](#manual-design-in-the-beginning)
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- [Digital logic overview](#digital-logic-overview)
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- [Process Design Kit](#process-design-kit)
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- [Intellectual Property / Libraries](#intellectual-property--libraries)
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- [Digital design (In The Beginning)](#digital-design-in-the-beginning)
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- [Digital logic overview (Today)](#digital-logic-overview-today)
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- [How can we use standard cells?](#how-can-we-use-standard-cells)
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- [Digital design](#digital-design)
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- [Process Design Kits](#process-design-kits)
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- [What about blackboxes?](#what-about-blackboxes)
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- [Place and route](#place-and-route)
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- [Other tools](#other-tools)
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- [What is the current state of the art?](#what-is-the-current-state-of-the-art)
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- [Things are looking pretty good!](#things-are-looking-pretty-good)
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- [End-to-end tool flow possible!](#end-to-end-tool-flow-possible)
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- [Current open PDKs are "ginormous"](#current-open-pdks-are-ginormous)
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- [Tooling](#tooling)
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- [End-to-end runs take weeks or months](#end-to-end-runs-take-weeks-or-months)
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- [Method to tape out](#method-to-tape-out)
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- [Where are we now (in open source)?](#where-are-we-now-in-open-source)
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- [Things are looking pretty good](#things-are-looking-pretty-good)
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- [End-to-end tool flow possible](#end-to-end-tool-flow-possible)
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- [Open PDKs](#open-pdks)
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- [Available IP](#available-ip)
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- [Standard cells](#standard-cells)
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- [What about tooling?](#what-about-tooling)
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- [Hardware synthesis](#hardware-synthesis)
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- [High level languages](#high-level-languages)
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- [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
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- [Power and Clock generation](#power-and-clock-generation)
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- [Verification](#verification)
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- [Wide selection of existing chips](#wide-selection-of-existing-chips)
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- [Large selection of existing IP](#large-selection-of-existing-ip)
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- [Where are we going from here?](#where-are-we-going-from-here)
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- [More open PDKs](#more-open-pdks)
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- [Improved analogue IP](#improved-analogue-ip)
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- [Better IP discoverability](#better-ip-discoverability)
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- [Better integration](#better-integration)
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- [What about taping out chips?](#what-about-taping-out-chips)
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- [What can't we do today?](#what-cant-we-do-today)
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- [Memories are still hard](#memories-are-still-hard)
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- [Flash is still hard](#flash-is-still-hard)
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- [EEPROM is still hard](#eeprom-is-still-hard)
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- [Exotic, non-digital IP is hard!](#exotic-non-digital-ip-is-hard)
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- [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard)
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- [Current PDKs are large nodes](#current-pdks-are-large-nodes)
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- [Analogue IP is still difficult](#analogue-ip-is-still-difficult)
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- [Where are we going from here?](#where-are-we-going-from-here)
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- [Improved languages](#improved-languages)
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- [Improved memories](#improved-memories)
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- [Better inference](#better-inference)
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- [More analogue IP](#more-analogue-ip)
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- [Getting involved!](#getting-involved)
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- [Siliwiz for raw tapeout](#siliwiz-for-raw-tapeout)
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- [TinyTapeout](#tinytapeout)
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- [](#)
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# The State of Open Silicon
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# Talk Outline
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- What does it mean to be "open"?
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- What can we do today?
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- What can't we do today?
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- Where can we go from here?
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# About Me
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# What does it mean for silicon to be "Open"?
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## Levels of "open"
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1. Manuals available
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2. Source available
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3. GDSII available
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## Parts of chip design
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* Tooling
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* PDKs
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* IP
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1. PDKs
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2. IP
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3. Tooling
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4. Method to tape out
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## Open tooling
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## Process Design Kit
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* Industry tools cost $1mm plus per seat
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* Process design kits (PDKs) are closed and under NDA
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* Tooling includes synthesis, placement, and routing
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* Tooling also includes verification, clock generation, and power generation
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- <https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg>
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- Process design kits (PDKs) are closed and under NDA
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- Mostly just a blank canvas
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## Manual design (In The Beginning)
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## Intellectual Property / Libraries
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* Rubylith
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* Magic
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* [Picture of Siliwiz]
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- Memories
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- IO blocks
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- Standard cells
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## Digital logic overview
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## Digital design (In The Beginning)
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* Boolean values
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- [Picture of Z80 or 6502]
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- Magic
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- [Picture of Siliwiz]
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## Digital logic overview (Today)
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- Standard cells
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- Basic boolean logic
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## How can we use standard cells?
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* Manual synthesis
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* Automated synthesis
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- Manual synthesis
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- Automated synthesis
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Almost all code is automatically synthesized from source code!
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## Digital design
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Source code can be in a Hardware Description Language. For example:
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* Verilog
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* SystemVerilog
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* VHDL
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[Example of live generation of cells]
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## Process Design Kits
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## Tooling
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* Very low-level logic
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* AND
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* NOR
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* NOT
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* Diode
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* Tie
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- Synthesis
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- Power generation
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- Clock tree
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- Place and route
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- Verification
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- **Industry tools cost $1mm plus per seat**
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Digital logic is, for the most part, a collection of these standard cells!
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## End-to-end runs take weeks or months
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[Image of standard cells]
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- Specialized tooling requires specialized engineers
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- Large separation between digital designers and tapeout
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## What about blackboxes?
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## Method to tape out
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* Frequently called "IP"
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* Blackboxes allow for more functionality, or higher performance
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* Memories, RF, ADC, etc.
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* Usually have Verilog models that are non-synthesizable.
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* Place-and-route tool wires up the ports
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* Blackboxes are how we get analogue!
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- Shuttle runs
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- Full wafer
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- Turnaround time is in months
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## Place and route
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# Where are we now (in open source)?
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The tool will automatically place cells, and will add wires between them!
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## Things are looking pretty good
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## Other tools
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## End-to-end tool flow possible
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* Clock generation
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* Power generation
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* Reset inserters
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* Parasitic extraction
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* Layout-vs-Schematic
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- Open tooling, open PDK
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- Chips have been produced using this flow
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- Digital logic is very doable
|
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|
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# What is the current state of the art?
|
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## Open PDKs
|
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|
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## Things are looking pretty good!
|
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- Real PDKs
|
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- SKY130
|
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- SKY90FD
|
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- GF180MCU
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- "Fake" PDKs
|
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- FreePDK45
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- ASAP5
|
||||
|
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## End-to-end tool flow possible!
|
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## Available IP
|
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|
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* Open tooling, open PDK
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* Chips have been produced using this flow
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* Production is still an issue
|
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- OpenMPW projects
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- ADC, LDO, Bandgap, DAC, and more
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|
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## Current open PDKs are "ginormous"
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## Standard cells
|
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|
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* 180nm and 130nm are peak-1999 technology
|
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* Still can do interesting things at 180/130nm!
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* "Fake" PDKs exist
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- SKY130
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- GF180MCU
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- OSU
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- LibreSilicon
|
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|
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## What about tooling?
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|
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## Hardware synthesis
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||||
|
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* Yosys
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* GHDL
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|
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Ingests Verilog or VHDL and generates basic netlists
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- Yosys (Verilog)
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- VHDL
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- SystemVerilog
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## High level languages
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* LiteX [Python]
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* SpinalHDL [Scala]
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* [Rust]
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- LiteX [Python]
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- SpinalHDL [Scala]
|
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- Clash
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|
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These all geneate Verilog, and are fully open!
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These all generate Verilog, and are fully open!
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## Floorplanning, Placement, Routing
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* OpenROAD is the current gold-standard
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* Compatitive with closed tools
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- OpenROAD is the current gold-standard
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- Competitive with closed tools
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## Power and Clock generation
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* Setup and hold timing validation
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* Basic power nets supported
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* Straps are generated as expected
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- Setup and hold timing validation
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- Basic power nets supported
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- Straps are generated as expected
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## Verification
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* Parasitic extraction works
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* Layout-versus-Schematics
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* Simulation of extracted netlist
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* Design Rule Checking
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- Parasitic extraction works
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- Layout-versus-Schematics
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- Simulation of extracted netlist
|
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- Design Rule Checking
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|
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## Wide selection of existing chips
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## What about taping out chips?
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|
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* Taped out
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* Still being characterized
|
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- Google OpenMPW shuttles
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- MPW shuttle runs
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||||
|
||||
## Large selection of existing IP
|
||||
|
||||
* [Picture of MPW list]
|
||||
|
||||
# Where are we going from here?
|
||||
|
||||
## More open PDKs
|
||||
|
||||
* GF180MCU is relatively new
|
||||
* ??? PDKs
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||||
|
||||
## Improved analogue IP
|
||||
|
||||
* Each run adds even more designs
|
||||
|
||||
## Better IP discoverability
|
||||
|
||||
* Indexes of IP cores
|
||||
|
||||
## Better integration
|
||||
|
||||
* Wishbone is standard in open source
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* AXI4 is common in industry
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# What can't we do today?
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|
||||
## Memories are still hard
|
||||
|
||||
## Flash is still hard
|
||||
- Density is constantly improving
|
||||
- Expect kilobytes of RAM on a chip
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||||
- Compare to megabytes of cache
|
||||
- A ~4x increase is possible
|
||||
|
||||
## EEPROM is still hard
|
||||
## Nonvolatile storage is still hard
|
||||
|
||||
## Exotic, non-digital IP is hard!
|
||||
- No EEPROM or flash
|
||||
- ReRAM is experimental on SKY130
|
||||
|
||||
## Current PDKs are large nodes
|
||||
|
||||
- 180nm was cutting edge in 1999
|
||||
|
||||
## Analogue IP is still difficult
|
||||
|
||||
- Some tapeouts exist, but documentation is scarce
|
||||
- Need more integration examples
|
||||
|
||||
# Where are we going from here?
|
||||
|
||||
## Improved languages
|
||||
|
||||
- Type-checking for timing?
|
||||
- Bus integration
|
||||
- Documentation generation
|
||||
|
||||
## Improved memories
|
||||
|
||||
- OpenRAM coming to more processes
|
||||
|
||||
## Better inference
|
||||
|
||||
## More analogue IP
|
||||
|
||||
# Getting involved!
|
||||
|
||||
## Siliwiz for raw tapeout
|
||||
- Siliwiz for raw tapeout
|
||||
- TinyTapeout
|
||||
- Write more blogposts
|
||||
- Give it a try
|
||||
|
||||
## TinyTapeout
|
||||
|
||||
##
|
||||
Thank you!
|
||||
|
|
|
|||
Loading…
Reference in New Issue