parent
1ad0961c87
commit
b48271308c
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#if __riscv_xlen == 64
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# define STORE sd
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# define LOAD ld
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# define LOG_REGBYTES 3
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#else
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# define STORE sw
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# define LOAD lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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.global start_kmain
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.text
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start_kmain:
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li t0, (1 << 11) | (1 << 5)
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csrw mstatus, t0
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csrw mepc, a0
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add a0, a1, zero
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add a1, a2, zero
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add a2, a3, zero
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add a3, a4, zero
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add a4, a5, zero
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add a5, a6, zero
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add a6, a7, zero
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add a7, zero, zero
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mret // Return to kmain
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# remove existing blobs because otherwise this will append object files to the old blobs
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Remove-Item -Force bin/*.a
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$crate = "xous-kernel"
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
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riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -DSKIP_MULTICORE -o bin/$crate.o
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riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
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riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
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Remove-Item bin/$crate.o
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#!/bin/bash
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set -euxo pipefail
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crate=xous-kernel
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# remove existing blobs because otherwise this will append object files to the old blobs
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mkdir -p bin
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rm -f bin/*.a
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
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ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
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ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -DSKIP_MULTICORE -o bin/$crate.o
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ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
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riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
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ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
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ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
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rm bin/$crate.o
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static mut TIME_MS: u32 = 0;
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pub fn irq(_irq_number: usize) {
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let timer_base = 0xE0002800 as *mut u8;
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unsafe {
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TIME_MS = TIME_MS + 1;
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timer_base.add(0x3c).write_volatile(1);
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};
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}
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pub fn get_time() -> u32 {
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unsafe { TIME_MS }
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}
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pub fn time_init() {
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let timer_base = 0xE0002800 as *mut u8;
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let period = 12_000_000 / 1000; // 12 MHz, 1 ms timer
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unsafe {
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// Disable, so we can update it
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timer_base.add(0x20).write_volatile(0);
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// Update "reload" register
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timer_base.add(0x10).write_volatile((period >> 24) as u8);
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timer_base.add(0x14).write_volatile((period >> 16) as u8);
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timer_base.add(0x18).write_volatile((period >> 8) as u8);
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timer_base.add(0x1c).write_volatile((period >> 0) as u8);
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// Update "load" register
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timer_base.add(0x00).write_volatile((period >> 24) as u8);
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timer_base.add(0x04).write_volatile((period >> 16) as u8);
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timer_base.add(0x08).write_volatile((period >> 8) as u8);
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timer_base.add(0x0c).write_volatile((period >> 0) as u8);
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// Enable ISR
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timer_base.add(0x40).write_volatile(1);
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// Set "pending" as well to clear it
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timer_base.add(0x38).write_volatile(1);
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// Finally, enable it
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timer_base.add(0x20).write_volatile(1);
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}
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}
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Reference in New Issue