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@ -0,0 +1,218 @@
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use core::fmt;
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#[derive(PartialEq)]
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pub enum RiscvException {
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/// When things are all 0
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NoException,
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/// 1 0
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UserSoftwareInterrupt(usize /* mepc */),
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/// 1 1
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SupervisorSoftwareInterrupt(usize /* mepc */),
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// [reserved]
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/// 1 3
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MachineSoftwareInterrupt(usize /* mepc */),
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/// 1 4
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UserTimerInterrupt(usize /* mepc */),
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/// 1 5
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SupervisorTimerInterrupt(usize /* mepc */),
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// [reserved]
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/// 1 7
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MachineTimerInterrupt(usize /* mepc */),
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/// 1 8
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UserExternalInterrupt(usize /* mepc */),
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/// 1 9
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SupervisorExternalInterrupt(usize /* mepc */),
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// [reserved]
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/// 1 11
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MachineExternalInterrupt(usize /* mepc */),
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ReservedInterrupt(usize /* unknown cause number */, usize /* mepc */),
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/// 0 0
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InstructionAddressMisaligned(usize /* mepc */, usize /* target address */),
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/// 0 1
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InstructionAccessFault(usize /* mepc */, usize /* target address */),
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/// 0 2
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IllegalInstruction(usize /* mepc */, usize /* instruction value */),
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/// 0 3
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Breakpoint(usize /* mepc */),
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/// 0 4
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LoadAddressMisaligned(usize /* mepc */, usize /* target address */),
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/// 0 5
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LoadAccessFault(usize /* mepc */, usize /* target address */),
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/// 0 6
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StoreAddressMisaligned(usize /* mepc */, usize /* target address */),
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/// 0 7
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StoreAccessFault(usize /* mepc */, usize /* target address */),
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/// 0 8
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CallFromUMode(usize /* mepc */),
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/// 0 9
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CallFromSMode(usize /* mepc */),
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// [reserved]
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/// 0 11
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CallFromMMode(usize /* mepc */),
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/// 0 12
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InstructionPageFault(usize /* mepc */, usize /* target address */),
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/// 0 13
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LoadPageFault(usize /* mepc */, usize /* target address */),
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// [reserved]
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/// 0 15
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StorePageFault(usize /* mepc */, usize /* target address */),
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ReservedFault(
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usize, /* unknown cause number */
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usize, /* mepc */
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usize, /* mtval */
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),
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}
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impl fmt::Display for RiscvException {
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fn fmt(&self, f: &mut fmt::Formatter) -> Result<(), fmt::Error> {
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use RiscvException::*;
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match *self {
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NoException => write!(f, "No trap"),
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UserSoftwareInterrupt(epc) => write!(f, "User swi from 0x{:08x}", epc),
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SupervisorSoftwareInterrupt(epc) => write!(f, "Supervisor swi from 0x{:08x}", epc),
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// --reserved--
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MachineSoftwareInterrupt(epc) => write!(f, "Machine swi at 0x{:08x}", epc),
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UserTimerInterrupt(epc) => write!(f, "User timer interrupt at 0x{:08x}", epc),
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SupervisorTimerInterrupt(epc) => {
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write!(f, "Supervisor timer interrupt at 0x{:08x}", epc)
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}
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// --reserved--
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MachineTimerInterrupt(epc) => write!(f, "Machine timer interrupt at 0x{:08x}", epc),
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UserExternalInterrupt(epc) => write!(f, "User external interrupt at 0x{:08x}", epc),
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SupervisorExternalInterrupt(epc) => {
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write!(f, "Machine external interrupt at 0x{:08x}", epc)
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}
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// --reserved--
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MachineExternalInterrupt(epc) => {
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write!(f, "Supervisor external interrupt at 0x{:08x}", epc)
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}
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ReservedInterrupt(code, epc) => {
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write!(f, "Reserved interrupt 0x{:08x} at 0x{:08x}", code, epc)
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}
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InstructionAddressMisaligned(epc, mtval) => write!(
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f,
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"Misaligned address instruction 0x{:08x} at 0x{:08x}",
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mtval, epc
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),
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InstructionAccessFault(epc, mtval) => write!(
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f,
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"Instruction access fault to 0x{:08x} at 0x{:08x}",
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mtval, epc
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),
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IllegalInstruction(epc, mtval) => {
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write!(f, "Illegal instruction 0x{:08x} at 0x{:08x}", mtval, epc)
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}
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Breakpoint(epc) => write!(f, "Breakpoint at 0x{:08x}", epc),
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LoadAddressMisaligned(epc, mtval) => write!(
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f,
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"Misaligned load address of 0x{:08x} at 0x{:08x}",
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mtval, epc
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),
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LoadAccessFault(epc, mtval) => {
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write!(f, "Load access fault from 0x{:08x} at 0x{:08x}", mtval, epc)
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}
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StoreAddressMisaligned(epc, mtval) => write!(
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f,
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"Misaligned store address of 0x{:08x} at 0x{:08x}",
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mtval, epc
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),
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StoreAccessFault(epc, mtval) => {
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write!(f, "Store access fault to 0x{:08x} at 0x{:08x}", mtval, epc)
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}
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CallFromUMode(epc) => write!(f, "Call from User mode at 0x{:08x}", epc),
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CallFromSMode(epc) => write!(f, "Call from Supervisor mode at 0x{:08x}", epc),
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// --reserved--
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CallFromMMode(epc) => write!(f, "Call from Machine mode at 0x{:08x}", epc),
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InstructionPageFault(epc, mtval) => write!(
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f,
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"Instruction page fault of 0x{:08x} at 0x{:08x}",
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mtval, epc
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),
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LoadPageFault(epc, mtval) => {
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write!(f, "Load page fault of 0x{:08x} at 0x{:08x}", mtval, epc)
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}
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// --reserved--
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StorePageFault(epc, mtval) => {
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write!(f, "Load page fault of 0x{:08x} at 0x{:08x}", mtval, epc)
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}
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ReservedFault(code, epc, mtval) => write!(
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f,
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"Reserved interrupt 0x{:08x} with cause 0x{:08x} at 0x{:08x}",
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code, mtval, epc
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),
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}
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}
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}
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impl RiscvException {
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pub fn from_regs(mcause: usize, mepc: usize, mtval: usize) -> RiscvException {
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use RiscvException::*;
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if mepc == 0 && mtval == 0 {
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return NoException;
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}
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match mcause {
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0x80000000 => UserSoftwareInterrupt(mepc),
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0x80000001 => SupervisorSoftwareInterrupt(mepc),
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// --reserved--
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0x80000003 => MachineSoftwareInterrupt(mepc),
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0x80000004 => UserTimerInterrupt(mepc),
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0x80000005 => SupervisorTimerInterrupt(mepc),
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// --reserved--
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0x80000007 => MachineTimerInterrupt(mepc),
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0x80000008 => UserExternalInterrupt(mepc),
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0x80000009 => SupervisorExternalInterrupt(mepc),
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// --reserved--
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0x8000000b => MachineExternalInterrupt(mepc),
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0 => InstructionAddressMisaligned(mepc, mtval),
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1 => InstructionAccessFault(mepc, mtval),
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2 => IllegalInstruction(mepc, mtval),
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3 => Breakpoint(mepc),
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4 => LoadAddressMisaligned(mepc, mtval),
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5 => LoadAccessFault(mepc, mtval),
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6 => StoreAddressMisaligned(mepc, mtval),
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7 => StoreAccessFault(mepc, mtval),
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8 => CallFromUMode(mepc),
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9 => CallFromSMode(mepc),
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// --reserved--
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11 => CallFromMMode(mepc),
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12 => InstructionPageFault(mepc, mtval),
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13 => LoadPageFault(mepc, mtval),
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// --reserved--
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15 => StorePageFault(mepc, mtval),
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x @ 10 | x @ 14 | x @ 16..=0x7fffffff => ReservedFault(x, mepc, mtval),
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x => {
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ReservedInterrupt(x & 0x7fffffff, mepc)
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}
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}
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}
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}
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@ -1,43 +1,70 @@
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static mut TIME_MS: u32 = 0;
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pub fn irq(_irq_number: usize) {
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let timer_base = 0xE0002800 as *mut u8;
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unsafe {
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TIME_MS = TIME_MS + 1;
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timer_base.add(0x3c).write_volatile(1);
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};
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}
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pub struct Timer {
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/// Address of the timer
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base: *mut u8,
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pub fn get_time() -> u32 {
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unsafe { TIME_MS }
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/// Number of clock cycles before the timer fires
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period: u32,
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/// Current count of the timer, in milliseconds
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time_ms: u32,
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}
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pub fn time_init() {
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let timer_base = 0xE0002800 as *mut u8;
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let period = 12_000_000 / 1000; // 12 MHz, 1 ms timer
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unsafe {
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// Disable, so we can update it
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timer_base.add(0x20).write_volatile(0);
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// Update "reload" register
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timer_base.add(0x10).write_volatile((period >> 24) as u8);
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timer_base.add(0x14).write_volatile((period >> 16) as u8);
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timer_base.add(0x18).write_volatile((period >> 8) as u8);
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timer_base.add(0x1c).write_volatile((period >> 0) as u8);
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// Update "load" register
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timer_base.add(0x00).write_volatile((period >> 24) as u8);
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timer_base.add(0x04).write_volatile((period >> 16) as u8);
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timer_base.add(0x08).write_volatile((period >> 8) as u8);
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timer_base.add(0x0c).write_volatile((period >> 0) as u8);
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// Enable ISR
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timer_base.add(0x40).write_volatile(1);
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// Set "pending" as well to clear it
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timer_base.add(0x38).write_volatile(1);
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// Finally, enable it
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timer_base.add(0x20).write_volatile(1);
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impl Timer {
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pub fn new() -> Timer {
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Timer {
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base: 0xE0002800 as *mut u8,
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period: 12_000_000 / 1000, // 12 MHz, 1 ms timer
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time_ms: 0,
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}
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}
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pub fn enable(&self) {
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unsafe {
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// Disable, so we can update it
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self.base.add(0x20).write_volatile(0);
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// Update "reload" register
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self.base.add(0x10).write_volatile((self.period >> 24) as u8);
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self.base.add(0x14).write_volatile((self.period >> 16) as u8);
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self.base.add(0x18).write_volatile((self.period >> 8) as u8);
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self.base.add(0x1c).write_volatile((self.period >> 0) as u8);
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// Update "load" register
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self.base.add(0x00).write_volatile((self.period >> 24) as u8);
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self.base.add(0x04).write_volatile((self.period >> 16) as u8);
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self.base.add(0x08).write_volatile((self.period >> 8) as u8);
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self.base.add(0x0c).write_volatile((self.period >> 0) as u8);
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// Enable ISR
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self.base.add(0x40).write_volatile(1);
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// Set "pending" as well to clear it
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self.base.add(0x38).write_volatile(1);
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// Finally, enable it
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self.base.add(0x20).write_volatile(1);
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}
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}
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pub fn elapsed_ms(&self) -> u32 {
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return self.time_ms;
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}
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}
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// pub fn irq(_irq_number: usize) {
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// let timer_base = 0xE0002800 as *mut u8;
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// unsafe {
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// TIME_MS = TIME_MS + 1;
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// timer_base.add(0x3c).write_volatile(1);
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// };
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// }
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// pub fn get_time() -> u32 {
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// unsafe { TIME_MS }
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// }
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// pub fn time_init() {
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// let timer_base = 0xE0002800 as *mut u8;
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// let period = 12_000_000 / 1000; // 12 MHz, 1 ms timer
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// }
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