Commit Graph

141 Commits

Author SHA1 Message Date
36339e63fc hardware: releases: add dvt1c
This fixes up the fab layer, and adds an assembly document.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-12-11 15:41:53 +08:00
5f4fa8891a hardware: pcb: fix drill origin, Fab layer
Fix up the Fab layer so that it is actually useful now.

Additionally, move the drill origin so that it is in a sane place.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-12-11 15:41:12 +08:00
ae5151f750 hardware: footprints: fix up Fab layer for all modules
Modify the `fab` layer so that it defaults to having footprint
identifiers, and places the designators in an area that makes sense.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-12-11 15:39:31 +08:00
c543591bae releases: tag dvt1b
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-30 11:05:42 -05:00
ef4835fc41 hardware: pcb: minor modifications, update footprints
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-30 11:04:23 -05:00
97ccf7a350 hardware: footprint: make "nothing" through-hole
By making it through-hole, it won't show up in the pick-and-place file,
but it will show up in the BOM list.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-30 10:49:00 -05:00
5e1c24ac93 hardware: footprints: fix smd/virtual designation
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-30 10:27:13 -05:00
0a7b84d1c3 hardware: replace VCCPLL regulator with RC network
Having a full regulator on VCCPLL causes the ESD network in the ICE40 to
freak out, dumping VCCPLL into GND and trying very hard to burn out the
regulator.

Replace it with a simple RC filter network, which is less clean but
results in a happier ESD network.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-25 04:08:23 +08:00
f3543e6e03 reference: add 12V ESD reference
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-21 13:48:20 +08:00
a4f319a951 hardware: pcb: change gerber attributes flag
This should be disabled, for maximum compatibility.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-21 00:01:33 +08:00
83ec9a94ea hardware: releases: re-release dvt1a
Some duplicate files made it in, which were not very useful.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:50:53 +08:00
a4cd7e7083 hardware: cache: commit new cache of symbols
Kicad regenerates this file based on what library symbols it uses.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:42:31 +08:00
e2a39f508d hardware: pcb: redo xtal footprint, 12V diode
Redo the xtal footprint, which was just flat out wrong.

Also, replace the +5V TVS diode with one that can handle more than 5V,
so it's not always shorting out.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:41:47 +08:00
66d1048242 hardware: schematic: modify USB 5V TVS
Previously, we would end up shorting power to ground all the time
because the diodes were right on the marginal edge.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:41:13 +08:00
00a305110f hardware: releases: re-release dvt1a
The previous version was very broken.  This also redoes some Gerber
files so that maybe they can be opened by the factory?

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:40:17 +08:00
e535c2fa15 hardware: footprint: add footprint for 11V TVS diode
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 23:39:48 +08:00
6ccdc4e386 hardware: footprints: fix XTAL footprint
The previous footprint was super super broken.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 22:56:38 +08:00
57c0ad62b1 reference: add pdf, jpg for dvt1a
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 16:03:41 +08:00
1468255a55 reference: add extra spi flash documents
Add reference manual for the alternate spi flash chip.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:57:55 +08:00
6959515e79 hardware: release: re-release dvt1a
This tunes the differential pair.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:57:25 +08:00
fcbb4420d3 hardware: pcb: re-tune differential pair
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:56:29 +08:00
d5b7701bc7 hardware: releases: re-release dvt1a
This adds a keepout area around the ground plane underneath the IC, to
try and prevent it from migrating during reflow.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:52:35 +08:00
1af0d1c06e hardware: pcb: increase under-fpga keepout area size
Increase the size of the keepout area in order to remove some extra
copper that was appearing around one of the ground pads.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 15:51:40 +08:00
4da7854799 dvt1a: tag release
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:48:26 +08:00
a3621766c5 hardware: cache: commit kicad's line-ending changes
I really don't know why it keeps doing this...

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:47:27 +08:00
5d90502947 pcb: fix up assembly notes layers
Resize the assembly note layers so that it's usable (in theory).

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-18 14:46:44 +08:00
7a4497b0c9 hardware: pcb: connect usb esd diodes inline first
Move the USB ESD diodes so they connect first.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 17:58:54 +08:00
3e72bd1086 hardware: sch: add column for "DNP"
After discussing with one factory, this is their preferred method of
indicating a part is "Do-Not-Populate".

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 15:19:17 +08:00
28aae5e4a8 hardware: footprints: 8-uson: redo footprint from pdf
Redo the footprint for the SPI flash chip from a recommended footprint
provided by one of the vendors.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-17 15:18:25 +08:00
64020199e8 hardware: cache: commit kicad's line-ending change
Why does it do this?  No one can say.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:45:25 +08:00
5a074ea4e1 hardware: pcb: finish routing with esd diodes
Finish routing the PCB with the esd diodes in place.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:44:49 +08:00
6344d45c1b hardware: sch: define spi part numbers for dvt board
This part is smaller.  Define both the part number and an alternative
part number.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 21:44:12 +08:00
8b7adafd9d hardware: pcb: finish first draft of esd routing
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:52 +08:00
42b7a235c6 reference: add esd, and security pdf
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:43 +08:00
f7cd16496c hardware: footprint: add footprint for esd diode
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 16:44:17 +08:00
dcc33ac81b hardware: pcb: partial routing of new esd diodes
There's still a bit more to go...

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:49:25 +08:00
9ec87cb483 hardware: sch: add esd diodes
These will be placed on the USB lines as well as the captouch lines.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:49:05 +08:00
d0bd902112 hardware: lib: update cache file
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 12:48:37 +08:00
9abd177b38 hardware: sch: remove "-rescue" and "-tomu-fpga"
Somehow, KiCad added these strings to the parts libraries, which
resulted in referencing a file that didn't exist.

Remove them.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-16 10:25:05 +08:00
cc19668309 hardware: pcb: reduce the number of capacitors
This is an initial commit removing the excess capacitors.

We will eventually add ESD protection ICs in the space that has been
freed up.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:24:55 +08:00
a98cd5727e hardware: sch: remove excess decoupling caps
We probably don't need 10nF, because this won't do any very-high-speed
(>100 MHz) operations.  We can think about putting them back in later,
space permitting.

Additionally, remove an extra bank of caps for one of the IO pads.
We'll double-up on capacitors there, which should be alright given the
close proximity and the fact that the only thing on that IO bank is
captouch.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:23:05 +08:00
23106ab57d hardware: pcb: reduce ground fill, loosen up routing
Reduce the ground fill under the IC, to prevent it from sliding around.
This gives less copper, but it should be fine for the currents we're
drawing.

Loosen up the routing of the 5V plane, which involves moving some
components around.  This increases the amount of copper that goes to the
various regulators.

Finally, reorder the caps so that the larger ones are further from the
IC.  This is done because they have a slower response time, and so can
be further away.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 19:14:24 +08:00
22aa8c8aca hardware: pcb: hide usb footprint silk
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:49:14 +08:00
b151d005f2 hardware: pcb: update PCB to use local copies of 3D files
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:46:54 +08:00
06be1fdb35 hardware: footprint: add models for regulator, BGA
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-15 14:46:23 +08:00
ccb5f49d19 reference: dvt1: re-render images
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 18:23:35 +08:00
571646f5c1 hardware: pcb: more tuning of traces and pours
Open up some more pours, and move some vias to make pours larger.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 18:21:39 +08:00
bdf8b8558d hardware: pcb: remove text leftover from EFM32
This was used to select which ARM MCU to use.  It is no longer relevant.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-09 16:45:06 +08:00
77d47db980 hardware: sch: add some spice models to passives
Identify passives and implement the various spice models.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-08 21:43:32 +08:00
294ecfe782 hardware: pcb: add more copper to 1.2V line
Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-08 19:11:24 +08:00