Enlarge some pads, to allow the PCB house to stay within tolerances.
They say that pads must be 0.23mm to ensure the laser doesn't escape the
pad.
Signed-off-by: Sean Cross <sean@xobs.io>
Fix up the Fab layer so that it is actually useful now.
Additionally, move the drill origin so that it is in a sane place.
Signed-off-by: Sean Cross <sean@xobs.io>
Modify the `fab` layer so that it defaults to having footprint
identifiers, and places the designators in an area that makes sense.
Signed-off-by: Sean Cross <sean@xobs.io>
Having a full regulator on VCCPLL causes the ESD network in the ICE40 to
freak out, dumping VCCPLL into GND and trying very hard to burn out the
regulator.
Replace it with a simple RC filter network, which is less clean but
results in a happier ESD network.
Signed-off-by: Sean Cross <sean@xobs.io>
Redo the xtal footprint, which was just flat out wrong.
Also, replace the +5V TVS diode with one that can handle more than 5V,
so it's not always shorting out.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously, we would end up shorting power to ground all the time
because the diodes were right on the marginal edge.
Signed-off-by: Sean Cross <sean@xobs.io>
Increase the size of the keepout area in order to remove some extra
copper that was appearing around one of the ground pads.
Signed-off-by: Sean Cross <sean@xobs.io>
Somehow, KiCad added these strings to the parts libraries, which
resulted in referencing a file that didn't exist.
Remove them.
Signed-off-by: Sean Cross <sean@xobs.io>
This is an initial commit removing the excess capacitors.
We will eventually add ESD protection ICs in the space that has been
freed up.
Signed-off-by: Sean Cross <sean@xobs.io>
We probably don't need 10nF, because this won't do any very-high-speed
(>100 MHz) operations. We can think about putting them back in later,
space permitting.
Additionally, remove an extra bank of caps for one of the IO pads.
We'll double-up on capacitors there, which should be alright given the
close proximity and the fact that the only thing on that IO bank is
captouch.
Signed-off-by: Sean Cross <sean@xobs.io>
Reduce the ground fill under the IC, to prevent it from sliding around.
This gives less copper, but it should be fine for the currents we're
drawing.
Loosen up the routing of the 5V plane, which involves moving some
components around. This increases the amount of copper that goes to the
various regulators.
Finally, reorder the caps so that the larger ones are further from the
IC. This is done because they have a slower response time, and so can
be further away.
Signed-off-by: Sean Cross <sean@xobs.io>
This has more copper, which might make hand-soldering easier. Though
this PCB isn't going to be hand-soldered.
Signed-off-by: Sean Cross <sean@xobs.io>
FPGAs are great, because if there's an alternate method that's easier to
route -- go for it! This modifies some of the connections to ease
routing constraints.
Signed-off-by: Sean Cross <sean@xobs.io>
This is the first cut of a schematic layout of DVT1.
It includes all the decoupling caps still. We'll need to see if they're
kept around.
Signed-off-by: Sean Cross <sean@xobs.io>
