Sean Cross a9e9643143 add opening graphic ...

Signed-off-by: Sean Cross <sean@xobs.io>

2019-06-21 09:53:37 -07:00

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fomu-block-diagram.png

index: finish up to the end of risc-v

2019-06-18 20:04:33 -07:00

fomu-hacker-top-1.jpg

add opening graphic

2019-06-21 09:53:37 -07:00

fomu-memory-layout.png

index: finish up to the end of risc-v

2019-06-18 20:04:33 -07:00

ice40-ledd.png

add initial python section

2019-06-18 15:56:54 -07:00

ice40-lut.png

add initial python section

2019-06-18 15:56:54 -07:00

ice40-rgb.jpg

nearly feature-complete

2019-06-20 11:24:00 -07:00

litex-design.png

index: finish up to the end of risc-v

2019-06-18 20:04:33 -07:00

tomu-fpga-evt-1-small.jpg

add initial python section

2019-06-18 15:56:54 -07:00

under-construction.gif

feature-complete-ish

2019-06-19 19:36:17 -07:00

verilog-synthesis.png

verilog: use a wider example and include an img

2019-06-18 16:06:09 -07:00

wishbone-usb-debug-bridge.png

index: finish up to the end of risc-v

2019-06-18 20:04:33 -07:00

xtal-datasheet-icon.jpg

nearly feature-complete

2019-06-20 11:24:00 -07:00