Regenerate crate with svd2rust v0.14.0

2019-01-16 15:39:25 +01:00
parent e96ee18df6
commit e0ddb38a51
2821 changed files with 598414 additions and 601164 deletions
--- a/src/sim/clkdiv4.rs
+++ b/src/sim/clkdiv4.rs
@ -0,0 +1,281 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLKDIV4 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRACEFRACR {
+    bits: bool,
+}
+impl TRACEFRACR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRACEDIVR {
+    bits: u8,
+}
+impl TRACEDIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `TRACEDIVEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRACEDIVENR {
+    #[doc = "Debug trace divider disabled"]
+    _0,
+    #[doc = "Debug trace divider enabled"]
+    _1,
+}
+impl TRACEDIVENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRACEDIVENR::_0 => false,
+            TRACEDIVENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRACEDIVENR {
+        match value {
+            false => TRACEDIVENR::_0,
+            true => TRACEDIVENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRACEDIVENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRACEDIVENR::_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEFRACW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEFRACW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEDIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEDIVW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRACEDIVEN`"]
+pub enum TRACEDIVENW {
+    #[doc = "Debug trace divider disabled"]
+    _0,
+    #[doc = "Debug trace divider enabled"]
+    _1,
+}
+impl TRACEDIVENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRACEDIVENW::_0 => false,
+            TRACEDIVENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEDIVENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEDIVENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRACEDIVENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Debug trace divider disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRACEDIVENW::_0)
+    }
+    #[doc = "Debug trace divider enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRACEDIVENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
+    #[inline]
+    pub fn tracefrac(&self) -> TRACEFRACR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        TRACEFRACR { bits }
+    }
+    #[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
+    #[inline]
+    pub fn tracediv(&self) -> TRACEDIVR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRACEDIVR { bits }
+    }
+    #[doc = "Bit 28 - Debug Trace Divider control"]
+    #[inline]
+    pub fn tracediven(&self) -> TRACEDIVENR {
+        TRACEDIVENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 268435456 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
+    #[inline]
+    pub fn tracefrac(&mut self) -> _TRACEFRACW {
+        _TRACEFRACW { w: self }
+    }
+    #[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
+    #[inline]
+    pub fn tracediv(&mut self) -> _TRACEDIVW {
+        _TRACEDIVW { w: self }
+    }
+    #[doc = "Bit 28 - Debug Trace Divider control"]
+    #[inline]
+    pub fn tracediven(&mut self) -> _TRACEDIVENW {
+        _TRACEDIVENW { w: self }
+    }
+}