Merge pull request #2 from Tmplt/master

Regenerate crate with svd2rust v0.14.0, release as version 0.10

CHANGELOG.md

@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Added
 ### Changed
 ### Removed
+## [0.10.0] - 2019-01-17
+### Changed
+ - Regenerated crate with svd2rust v0.14.0.
+ - Bumped dependencies.
 ## [0.9.0] - 2018-02-14
 ### Removed
  - Debug assertion in Peripherals::steal() is removed so peripherals can be stolen in panic_fmt.

Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"]
 name = "s32k144"
-version = "0.9.0"
+version = "0.10.0"
 
 description = "Peripheral access API for NXP S32K144 microcontrollers (generated using svd2rust)"
 repository = "https://github.com/kjetilkjeka/s32k144.rs"
@@ -12,13 +12,13 @@ categories = ["embedded", "hardware-support", "no-std"]
 license = "Apache-2.0/MIT"
 
 [dependencies]
-cortex-m = "0.4.3"
+cortex-m = "0.5.8"
-bare-metal = "0.1.1"
+bare-metal = "0.2.0"
 vcell = "0.1.0"
 
 [dependencies.cortex-m-rt]
 optional = true
-version = "0.3.6"
+version = "0.6.5"
 
 [features]
-rt = ["cortex-m-rt"]
+rt = ["cortex-m-rt/device"]

build.rs

@@ -0,0 +1,13 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x")).unwrap().write_all(include_bytes!("device.x")).unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

device.x

@@ -0,0 +1,89 @@
+PROVIDE(DMA0 = DefaultHandler);
+PROVIDE(DMA1 = DefaultHandler);
+PROVIDE(DMA2 = DefaultHandler);
+PROVIDE(DMA3 = DefaultHandler);
+PROVIDE(DMA4 = DefaultHandler);
+PROVIDE(DMA5 = DefaultHandler);
+PROVIDE(DMA6 = DefaultHandler);
+PROVIDE(DMA7 = DefaultHandler);
+PROVIDE(DMA8 = DefaultHandler);
+PROVIDE(DMA9 = DefaultHandler);
+PROVIDE(DMA10 = DefaultHandler);
+PROVIDE(DMA11 = DefaultHandler);
+PROVIDE(DMA12 = DefaultHandler);
+PROVIDE(DMA13 = DefaultHandler);
+PROVIDE(DMA14 = DefaultHandler);
+PROVIDE(DMA15 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(MCM = DefaultHandler);
+PROVIDE(FTFC = DefaultHandler);
+PROVIDE(READ_COLLISION = DefaultHandler);
+PROVIDE(LVD_LVW = DefaultHandler);
+PROVIDE(FTFC_FAULT = DefaultHandler);
+PROVIDE(WDOG_EWM = DefaultHandler);
+PROVIDE(RCM = DefaultHandler);
+PROVIDE(LPI2C0_MASTER = DefaultHandler);
+PROVIDE(LPI2C0_SLAVE = DefaultHandler);
+PROVIDE(LPSPI0 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPUART0_RXTX = DefaultHandler);
+PROVIDE(LPUART1_RXTX = DefaultHandler);
+PROVIDE(LPUART2_RXTX = DefaultHandler);
+PROVIDE(ADC0 = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(CMP0 = DefaultHandler);
+PROVIDE(ERM_SINGLE_FAULT = DefaultHandler);
+PROVIDE(ERM_DOUBLE_FAULT = DefaultHandler);
+PROVIDE(RTC = DefaultHandler);
+PROVIDE(RTC_SECONDS = DefaultHandler);
+PROVIDE(LPIT0_CH0 = DefaultHandler);
+PROVIDE(LPIT0_CH1 = DefaultHandler);
+PROVIDE(LPIT0_CH2 = DefaultHandler);
+PROVIDE(LPIT0_CH3 = DefaultHandler);
+PROVIDE(PDB0 = DefaultHandler);
+PROVIDE(SCG = DefaultHandler);
+PROVIDE(LPTMR0 = DefaultHandler);
+PROVIDE(PORTA = DefaultHandler);
+PROVIDE(PORTB = DefaultHandler);
+PROVIDE(PORTC = DefaultHandler);
+PROVIDE(PORTD = DefaultHandler);
+PROVIDE(PORTE = DefaultHandler);
+PROVIDE(PDB1 = DefaultHandler);
+PROVIDE(FLEXIO = DefaultHandler);
+PROVIDE(CAN0_ORED = DefaultHandler);
+PROVIDE(CAN0_ERROR = DefaultHandler);
+PROVIDE(CAN0_WAKE_UP = DefaultHandler);
+PROVIDE(CAN0_ORED_0_15_MB = DefaultHandler);
+PROVIDE(CAN0_ORED_16_31_MB = DefaultHandler);
+PROVIDE(CAN1_ORED = DefaultHandler);
+PROVIDE(CAN1_ERROR = DefaultHandler);
+PROVIDE(CAN1_ORED_0_15_MB = DefaultHandler);
+PROVIDE(CAN2_ORED = DefaultHandler);
+PROVIDE(CAN2_ERROR = DefaultHandler);
+PROVIDE(CAN2_ORED_0_15_MB = DefaultHandler);
+PROVIDE(FTM0_CH0_CH1 = DefaultHandler);
+PROVIDE(FTM0_CH2_CH3 = DefaultHandler);
+PROVIDE(FTM0_CH4_CH5 = DefaultHandler);
+PROVIDE(FTM0_CH6_CH7 = DefaultHandler);
+PROVIDE(FTM0_FAULT = DefaultHandler);
+PROVIDE(FTM0_OVF_RELOAD = DefaultHandler);
+PROVIDE(FTM1_CH0_CH1 = DefaultHandler);
+PROVIDE(FTM1_CH2_CH3 = DefaultHandler);
+PROVIDE(FTM1_CH4_CH5 = DefaultHandler);
+PROVIDE(FTM1_CH6_CH7 = DefaultHandler);
+PROVIDE(FTM1_FAULT = DefaultHandler);
+PROVIDE(FTM1_OVF_RELOAD = DefaultHandler);
+PROVIDE(FTM2_CH0_CH1 = DefaultHandler);
+PROVIDE(FTM2_CH2_CH3 = DefaultHandler);
+PROVIDE(FTM2_CH4_CH5 = DefaultHandler);
+PROVIDE(FTM2_CH6_CH7 = DefaultHandler);
+PROVIDE(FTM2_FAULT = DefaultHandler);
+PROVIDE(FTM2_OVF_RELOAD = DefaultHandler);
+PROVIDE(FTM3_CH0_CH1 = DefaultHandler);
+PROVIDE(FTM3_CH2_CH3 = DefaultHandler);
+PROVIDE(FTM3_CH4_CH5 = DefaultHandler);
+PROVIDE(FTM3_CH6_CH7 = DefaultHandler);
+PROVIDE(FTM3_FAULT = DefaultHandler);
+PROVIDE(FTM3_OVF_RELOAD = DefaultHandler);
+

src/adc0.rs

@@ -0,0 +1,290 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - ADC Status and Control Register 1"]
+    pub sc1a: SC1,
+    #[doc = "0x04 - ADC Status and Control Register 1"]
+    pub sc1b: SC1,
+    #[doc = "0x08 - ADC Status and Control Register 1"]
+    pub sc1c: SC1,
+    #[doc = "0x0c - ADC Status and Control Register 1"]
+    pub sc1d: SC1,
+    #[doc = "0x10 - ADC Status and Control Register 1"]
+    pub sc1e: SC1,
+    #[doc = "0x14 - ADC Status and Control Register 1"]
+    pub sc1f: SC1,
+    #[doc = "0x18 - ADC Status and Control Register 1"]
+    pub sc1g: SC1,
+    #[doc = "0x1c - ADC Status and Control Register 1"]
+    pub sc1h: SC1,
+    #[doc = "0x20 - ADC Status and Control Register 1"]
+    pub sc1i: SC1,
+    #[doc = "0x24 - ADC Status and Control Register 1"]
+    pub sc1j: SC1,
+    #[doc = "0x28 - ADC Status and Control Register 1"]
+    pub sc1k: SC1,
+    #[doc = "0x2c - ADC Status and Control Register 1"]
+    pub sc1l: SC1,
+    #[doc = "0x30 - ADC Status and Control Register 1"]
+    pub sc1m: SC1,
+    #[doc = "0x34 - ADC Status and Control Register 1"]
+    pub sc1n: SC1,
+    #[doc = "0x38 - ADC Status and Control Register 1"]
+    pub sc1o: SC1,
+    #[doc = "0x3c - ADC Status and Control Register 1"]
+    pub sc1p: SC1,
+    #[doc = "0x40 - ADC Configuration Register 1"]
+    pub cfg1: CFG1,
+    #[doc = "0x44 - ADC Configuration Register 2"]
+    pub cfg2: CFG2,
+    #[doc = "0x48 - ADC Data Result Registers"]
+    pub ra: R,
+    #[doc = "0x4c - ADC Data Result Registers"]
+    pub rb: R,
+    #[doc = "0x50 - ADC Data Result Registers"]
+    pub rc: R,
+    #[doc = "0x54 - ADC Data Result Registers"]
+    pub rd: R,
+    #[doc = "0x58 - ADC Data Result Registers"]
+    pub re: R,
+    #[doc = "0x5c - ADC Data Result Registers"]
+    pub rf: R,
+    #[doc = "0x60 - ADC Data Result Registers"]
+    pub rg: R,
+    #[doc = "0x64 - ADC Data Result Registers"]
+    pub rh: R,
+    #[doc = "0x68 - ADC Data Result Registers"]
+    pub ri: R,
+    #[doc = "0x6c - ADC Data Result Registers"]
+    pub rj: R,
+    #[doc = "0x70 - ADC Data Result Registers"]
+    pub rk: R,
+    #[doc = "0x74 - ADC Data Result Registers"]
+    pub rl: R,
+    #[doc = "0x78 - ADC Data Result Registers"]
+    pub rm: R,
+    #[doc = "0x7c - ADC Data Result Registers"]
+    pub rn: R,
+    #[doc = "0x80 - ADC Data Result Registers"]
+    pub ro: R,
+    #[doc = "0x84 - ADC Data Result Registers"]
+    pub rp: R,
+    #[doc = "0x88 - Compare Value Registers"]
+    pub cv1: CV,
+    #[doc = "0x8c - Compare Value Registers"]
+    pub cv2: CV,
+    #[doc = "0x90 - Status and Control Register 2"]
+    pub sc2: SC2,
+    #[doc = "0x94 - Status and Control Register 3"]
+    pub sc3: SC3,
+    #[doc = "0x98 - BASE Offset Register"]
+    pub base_ofs: BASE_OFS,
+    #[doc = "0x9c - ADC Offset Correction Register"]
+    pub ofs: OFS,
+    #[doc = "0xa0 - USER Offset Correction Register"]
+    pub usr_ofs: USR_OFS,
+    #[doc = "0xa4 - ADC X Offset Correction Register"]
+    pub xofs: XOFS,
+    #[doc = "0xa8 - ADC Y Offset Correction Register"]
+    pub yofs: YOFS,
+    #[doc = "0xac - ADC Gain Register"]
+    pub g: G,
+    #[doc = "0xb0 - ADC User Gain Register"]
+    pub ug: UG,
+    #[doc = "0xb4 - ADC General Calibration Value Register S"]
+    pub clps: CLPS,
+    #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
+    pub clp3: CLP3,
+    #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
+    pub clp2: CLP2,
+    #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
+    pub clp1: CLP1,
+    #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
+    pub clp0: CLP0,
+    #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
+    pub clpx: CLPX,
+    #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
+    pub clp9: CLP9,
+    #[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
+    pub clps_ofs: CLPS_OFS,
+    #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
+    pub clp3_ofs: CLP3_OFS,
+    #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
+    pub clp2_ofs: CLP2_OFS,
+    #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
+    pub clp1_ofs: CLP1_OFS,
+    #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
+    pub clp0_ofs: CLP0_OFS,
+    #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
+    pub clpx_ofs: CLPX_OFS,
+    #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
+    pub clp9_ofs: CLP9_OFS,
+}
+#[doc = "ADC Status and Control Register 1"]
+pub struct SC1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Status and Control Register 1"]
+pub mod sc1;
+#[doc = "ADC Configuration Register 1"]
+pub struct CFG1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Configuration Register 1"]
+pub mod cfg1;
+#[doc = "ADC Configuration Register 2"]
+pub struct CFG2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Configuration Register 2"]
+pub mod cfg2;
+#[doc = "ADC Data Result Registers"]
+pub struct R {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Data Result Registers"]
+pub mod r;
+#[doc = "Compare Value Registers"]
+pub struct CV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Compare Value Registers"]
+pub mod cv;
+#[doc = "Status and Control Register 2"]
+pub struct SC2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status and Control Register 2"]
+pub mod sc2;
+#[doc = "Status and Control Register 3"]
+pub struct SC3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status and Control Register 3"]
+pub mod sc3;
+#[doc = "BASE Offset Register"]
+pub struct BASE_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BASE Offset Register"]
+pub mod base_ofs;
+#[doc = "ADC Offset Correction Register"]
+pub struct OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Offset Correction Register"]
+pub mod ofs;
+#[doc = "USER Offset Correction Register"]
+pub struct USR_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "USER Offset Correction Register"]
+pub mod usr_ofs;
+#[doc = "ADC X Offset Correction Register"]
+pub struct XOFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC X Offset Correction Register"]
+pub mod xofs;
+#[doc = "ADC Y Offset Correction Register"]
+pub struct YOFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Y Offset Correction Register"]
+pub mod yofs;
+#[doc = "ADC Gain Register"]
+pub struct G {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Gain Register"]
+pub mod g;
+#[doc = "ADC User Gain Register"]
+pub struct UG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC User Gain Register"]
+pub mod ug;
+#[doc = "ADC General Calibration Value Register S"]
+pub struct CLPS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC General Calibration Value Register S"]
+pub mod clps;
+#[doc = "ADC Plus-Side General Calibration Value Register 3"]
+pub struct CLP3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 3"]
+pub mod clp3;
+#[doc = "ADC Plus-Side General Calibration Value Register 2"]
+pub struct CLP2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 2"]
+pub mod clp2;
+#[doc = "ADC Plus-Side General Calibration Value Register 1"]
+pub struct CLP1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 1"]
+pub mod clp1;
+#[doc = "ADC Plus-Side General Calibration Value Register 0"]
+pub struct CLP0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 0"]
+pub mod clp0;
+#[doc = "ADC Plus-Side General Calibration Value Register X"]
+pub struct CLPX {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register X"]
+pub mod clpx;
+#[doc = "ADC Plus-Side General Calibration Value Register 9"]
+pub struct CLP9 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 9"]
+pub mod clp9;
+#[doc = "ADC General Calibration Offset Value Register S"]
+pub struct CLPS_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC General Calibration Offset Value Register S"]
+pub mod clps_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
+pub struct CLP3_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
+pub mod clp3_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
+pub struct CLP2_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
+pub mod clp2_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
+pub struct CLP1_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
+pub mod clp1_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
+pub struct CLP0_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
+pub mod clp0_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
+pub struct CLPX_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
+pub mod clpx_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
+pub struct CLP9_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
+pub mod clp9_ofs;

src/adc0/base_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::BASE_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BA_OFSR {
+    bits: u8,
+}
+impl BA_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BA_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BA_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
+    #[inline]
+    pub fn ba_ofs(&self) -> BA_OFSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        BA_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 64 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
+    #[inline]
+    pub fn ba_ofs(&mut self) -> _BA_OFSW {
+        _BA_OFSW { w: self }
+    }
+}

src/adc0/base_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::BASE_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct BA_OFSR {
-    bits: u8,
-}
-impl BA_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _BA_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _BA_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
-    #[inline]
-    pub fn ba_ofs(&self) -> BA_OFSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        BA_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 64 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
-    #[inline]
-    pub fn ba_ofs(&mut self) -> _BA_OFSW {
-        _BA_OFSW { w: self }
-    }
-}

src/adc0/cfg1.rs

@@ -0,0 +1,482 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CFG1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADICLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADICLKR {
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    _00,
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    _01,
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    _10,
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    _11,
+}
+impl ADICLKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADICLKR::_00 => 0,
+            ADICLKR::_01 => 1,
+            ADICLKR::_10 => 2,
+            ADICLKR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADICLKR {
+        match value {
+            0 => ADICLKR::_00,
+            1 => ADICLKR::_01,
+            2 => ADICLKR::_10,
+            3 => ADICLKR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADICLKR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADICLKR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADICLKR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == ADICLKR::_11
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "8-bit conversion."]
+    _00,
+    #[doc = "12-bit conversion."]
+    _01,
+    #[doc = "10-bit conversion."]
+    _10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl MODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MODER::_00 => 0,
+            MODER::_01 => 1,
+            MODER::_10 => 2,
+            MODER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MODER {
+        match value {
+            0 => MODER::_00,
+            1 => MODER::_01,
+            2 => MODER::_10,
+            i => MODER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == MODER::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == MODER::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == MODER::_10
+    }
+}
+#[doc = "Possible values of the field `ADIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADIVR {
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    _00,
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    _01,
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    _10,
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    _11,
+}
+impl ADIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADIVR::_00 => 0,
+            ADIVR::_01 => 1,
+            ADIVR::_10 => 2,
+            ADIVR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADIVR {
+        match value {
+            0 => ADIVR::_00,
+            1 => ADIVR::_01,
+            2 => ADIVR::_10,
+            3 => ADIVR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADIVR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADIVR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADIVR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == ADIVR::_11
+    }
+}
+#[doc = "Values that can be written to the field `ADICLK`"]
+pub enum ADICLKW {
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    _00,
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    _01,
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    _10,
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    _11,
+}
+impl ADICLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADICLKW::_00 => 0,
+            ADICLKW::_01 => 1,
+            ADICLKW::_10 => 2,
+            ADICLKW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADICLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADICLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADICLKW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADICLKW::_00)
+    }
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADICLKW::_01)
+    }
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADICLKW::_10)
+    }
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(ADICLKW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "8-bit conversion."]
+    _00,
+    #[doc = "12-bit conversion."]
+    _01,
+    #[doc = "10-bit conversion."]
+    _10,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MODEW::_00 => 0,
+            MODEW::_01 => 1,
+            MODEW::_10 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "8-bit conversion."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(MODEW::_00)
+    }
+    #[doc = "12-bit conversion."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(MODEW::_01)
+    }
+    #[doc = "10-bit conversion."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(MODEW::_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADIV`"]
+pub enum ADIVW {
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    _00,
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    _01,
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    _10,
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    _11,
+}
+impl ADIVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADIVW::_00 => 0,
+            ADIVW::_01 => 1,
+            ADIVW::_10 => 2,
+            ADIVW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADIVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADIVW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADIVW::_00)
+    }
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADIVW::_01)
+    }
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADIVW::_10)
+    }
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(ADIVW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRLTRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRLTRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Input Clock Select"]
+    #[inline]
+    pub fn adiclk(&self) -> ADICLKR {
+        ADICLKR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Conversion mode selection"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 5:6 - Clock Divide Select"]
+    #[inline]
+    pub fn adiv(&self) -> ADIVR {
+        ADIVR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Input Clock Select"]
+    #[inline]
+    pub fn adiclk(&mut self) -> _ADICLKW {
+        _ADICLKW { w: self }
+    }
+    #[doc = "Bits 2:3 - Conversion mode selection"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bits 5:6 - Clock Divide Select"]
+    #[inline]
+    pub fn adiv(&mut self) -> _ADIVW {
+        _ADIVW { w: self }
+    }
+    #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
+    #[inline]
+    pub fn clrltrg(&mut self) -> _CLRLTRGW {
+        _CLRLTRGW { w: self }
+    }
+}

src/adc0/cfg1/mod.rs

@@ -1,484 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CFG1 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = "Possible values of the field `ADICLK`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADICLKR {
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    _00,
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    _01,
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    _10,
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    _11,
-}
-impl ADICLKR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            ADICLKR::_00 => 0,
-            ADICLKR::_01 => 1,
-            ADICLKR::_10 => 2,
-            ADICLKR::_11 => 3,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> ADICLKR {
-        match value {
-            0 => ADICLKR::_00,
-            1 => ADICLKR::_01,
-            2 => ADICLKR::_10,
-            3 => ADICLKR::_11,
-            _ => unreachable!(),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == ADICLKR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == ADICLKR::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == ADICLKR::_10
-    }
-    #[doc = "Checks if the value of the field is `_11`"]
-    #[inline]
-    pub fn is_11(&self) -> bool {
-        *self == ADICLKR::_11
-    }
-}
-#[doc = "Possible values of the field `MODE`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum MODER {
-    #[doc = "8-bit conversion."]
-    _00,
-    #[doc = "12-bit conversion."]
-    _01,
-    #[doc = "10-bit conversion."]
-    _10,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl MODER {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            MODER::_00 => 0,
-            MODER::_01 => 1,
-            MODER::_10 => 2,
-            MODER::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> MODER {
-        match value {
-            0 => MODER::_00,
-            1 => MODER::_01,
-            2 => MODER::_10,
-            i => MODER::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == MODER::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == MODER::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == MODER::_10
-    }
-}
-#[doc = "Possible values of the field `ADIV`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADIVR {
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    _00,
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    _01,
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    _10,
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    _11,
-}
-impl ADIVR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            ADIVR::_00 => 0,
-            ADIVR::_01 => 1,
-            ADIVR::_10 => 2,
-            ADIVR::_11 => 3,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> ADIVR {
-        match value {
-            0 => ADIVR::_00,
-            1 => ADIVR::_01,
-            2 => ADIVR::_10,
-            3 => ADIVR::_11,
-            _ => unreachable!(),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == ADIVR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == ADIVR::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == ADIVR::_10
-    }
-    #[doc = "Checks if the value of the field is `_11`"]
-    #[inline]
-    pub fn is_11(&self) -> bool {
-        *self == ADIVR::_11
-    }
-}
-#[doc = "Values that can be written to the field `ADICLK`"]
-pub enum ADICLKW {
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    _00,
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    _01,
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    _10,
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    _11,
-}
-impl ADICLKW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            ADICLKW::_00 => 0,
-            ADICLKW::_01 => 1,
-            ADICLKW::_10 => 2,
-            ADICLKW::_11 => 3,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADICLKW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADICLKW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADICLKW) -> &'a mut W {
-        {
-            self.bits(variant._bits())
-        }
-    }
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(ADICLKW::_00)
-    }
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(ADICLKW::_01)
-    }
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(ADICLKW::_10)
-    }
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    #[inline]
-    pub fn _11(self) -> &'a mut W {
-        self.variant(ADICLKW::_11)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `MODE`"]
-pub enum MODEW {
-    #[doc = "8-bit conversion."]
-    _00,
-    #[doc = "12-bit conversion."]
-    _01,
-    #[doc = "10-bit conversion."]
-    _10,
-}
-impl MODEW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            MODEW::_00 => 0,
-            MODEW::_01 => 1,
-            MODEW::_10 => 2,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _MODEW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _MODEW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: MODEW) -> &'a mut W {
-        unsafe { self.bits(variant._bits()) }
-    }
-    #[doc = "8-bit conversion."]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(MODEW::_00)
-    }
-    #[doc = "12-bit conversion."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(MODEW::_01)
-    }
-    #[doc = "10-bit conversion."]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(MODEW::_10)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 2;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `ADIV`"]
-pub enum ADIVW {
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    _00,
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    _01,
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    _10,
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    _11,
-}
-impl ADIVW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            ADIVW::_00 => 0,
-            ADIVW::_01 => 1,
-            ADIVW::_10 => 2,
-            ADIVW::_11 => 3,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADIVW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADIVW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADIVW) -> &'a mut W {
-        {
-            self.bits(variant._bits())
-        }
-    }
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(ADIVW::_00)
-    }
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(ADIVW::_01)
-    }
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(ADIVW::_10)
-    }
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    #[inline]
-    pub fn _11(self) -> &'a mut W {
-        self.variant(ADIVW::_11)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 5;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLRLTRGW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLRLTRGW<'a> {
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 8;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:1 - Input Clock Select"]
-    #[inline]
-    pub fn adiclk(&self) -> ADICLKR {
-        ADICLKR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bits 2:3 - Conversion mode selection"]
-    #[inline]
-    pub fn mode(&self) -> MODER {
-        MODER::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 2;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bits 5:6 - Clock Divide Select"]
-    #[inline]
-    pub fn adiv(&self) -> ADIVR {
-        ADIVR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 5;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:1 - Input Clock Select"]
-    #[inline]
-    pub fn adiclk(&mut self) -> _ADICLKW {
-        _ADICLKW { w: self }
-    }
-    #[doc = "Bits 2:3 - Conversion mode selection"]
-    #[inline]
-    pub fn mode(&mut self) -> _MODEW {
-        _MODEW { w: self }
-    }
-    #[doc = "Bits 5:6 - Clock Divide Select"]
-    #[inline]
-    pub fn adiv(&mut self) -> _ADIVW {
-        _ADIVW { w: self }
-    }
-    #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
-    #[inline]
-    pub fn clrltrg(&mut self) -> _CLRLTRGW {
-        _CLRLTRGW { w: self }
-    }
-}

src/adc0/cfg2.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CFG2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SMPLTSR {
+    bits: u8,
+}
+impl SMPLTSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMPLTSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMPLTSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Sample Time Select"]
+    #[inline]
+    pub fn smplts(&self) -> SMPLTSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SMPLTSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 12 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Sample Time Select"]
+    #[inline]
+    pub fn smplts(&mut self) -> _SMPLTSW {
+        _SMPLTSW { w: self }
+    }
+}

src/adc0/cfg2/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CFG2 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct SMPLTSR {
-    bits: u8,
-}
-impl SMPLTSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _SMPLTSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _SMPLTSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Sample Time Select"]
-    #[inline]
-    pub fn smplts(&self) -> SMPLTSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        SMPLTSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 12 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Sample Time Select"]
-    #[inline]
-    pub fn smplts(&mut self) -> _SMPLTSW {
-        _SMPLTSW { w: self }
-    }
-}

src/adc0/clp0.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP0R {
+    bits: u8,
+}
+impl CLP0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Calibration Value"]
+    #[inline]
+    pub fn clp0(&self) -> CLP0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 46 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Calibration Value"]
+    #[inline]
+    pub fn clp0(&mut self) -> _CLP0W {
+        _CLP0W { w: self }
+    }
+}

src/adc0/clp0/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP0 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP0R {
-    bits: u8,
-}
-impl CLP0R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP0W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP0W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Calibration Value"]
-    #[inline]
-    pub fn clp0(&self) -> CLP0R {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP0R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 46 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Calibration Value"]
-    #[inline]
-    pub fn clp0(&mut self) -> _CLP0W {
-        _CLP0W { w: self }
-    }
-}

src/adc0/clp0_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP0_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP0_OFSR {
+    bits: u8,
+}
+impl CLP0_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP0_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP0_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP0 Offset"]
+    #[inline]
+    pub fn clp0_ofs(&self) -> CLP0_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP0_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP0 Offset"]
+    #[inline]
+    pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
+        _CLP0_OFSW { w: self }
+    }
+}

src/adc0/clp0_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP0_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP0_OFSR {
-    bits: u8,
-}
-impl CLP0_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP0_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP0_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP0 Offset"]
-    #[inline]
-    pub fn clp0_ofs(&self) -> CLP0_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP0_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP0 Offset"]
-    #[inline]
-    pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
-        _CLP0_OFSW { w: self }
-    }
-}

src/adc0/clp1.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP1R {
+    bits: u16,
+}
+impl CLP1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 511;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:8 - Calibration Value"]
+    #[inline]
+    pub fn clp1(&self) -> CLP1R {
+        let bits = {
+            const MASK: u16 = 511;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 92 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:8 - Calibration Value"]
+    #[inline]
+    pub fn clp1(&mut self) -> _CLP1W {
+        _CLP1W { w: self }
+    }
+}

src/adc0/clp1/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP1 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP1R {
-    bits: u16,
-}
-impl CLP1R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP1W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP1W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 511;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:8 - Calibration Value"]
-    #[inline]
-    pub fn clp1(&self) -> CLP1R {
-        let bits = {
-            const MASK: u16 = 511;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP1R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 92 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:8 - Calibration Value"]
-    #[inline]
-    pub fn clp1(&mut self) -> _CLP1W {
-        _CLP1W { w: self }
-    }
-}

src/adc0/clp1_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP1_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP1_OFSR {
+    bits: u8,
+}
+impl CLP1_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP1_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP1_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP1 Offset"]
+    #[inline]
+    pub fn clp1_ofs(&self) -> CLP1_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP1_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP1 Offset"]
+    #[inline]
+    pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
+        _CLP1_OFSW { w: self }
+    }
+}

src/adc0/clp1_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP1_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP1_OFSR {
-    bits: u8,
-}
-impl CLP1_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP1_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP1_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP1 Offset"]
-    #[inline]
-    pub fn clp1_ofs(&self) -> CLP1_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP1_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP1 Offset"]
-    #[inline]
-    pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
-        _CLP1_OFSW { w: self }
-    }
-}

src/adc0/clp2.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP2R {
+    bits: u16,
+}
+impl CLP2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp2(&self) -> CLP2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP2R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 184 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp2(&mut self) -> _CLP2W {
+        _CLP2W { w: self }
+    }
+}

src/adc0/clp2/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP2 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP2R {
-    bits: u16,
-}
-impl CLP2R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP2W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP2W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 1023;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp2(&self) -> CLP2R {
-        let bits = {
-            const MASK: u16 = 1023;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP2R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 184 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp2(&mut self) -> _CLP2W {
-        _CLP2W { w: self }
-    }
-}

src/adc0/clp2_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP2_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP2_OFSR {
+    bits: u8,
+}
+impl CLP2_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP2_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP2_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP2 Offset"]
+    #[inline]
+    pub fn clp2_ofs(&self) -> CLP2_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP2_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP2 Offset"]
+    #[inline]
+    pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
+        _CLP2_OFSW { w: self }
+    }
+}

src/adc0/clp2_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP2_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP2_OFSR {
-    bits: u8,
-}
-impl CLP2_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP2_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP2_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP2 Offset"]
-    #[inline]
-    pub fn clp2_ofs(&self) -> CLP2_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP2_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP2 Offset"]
-    #[inline]
-    pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
-        _CLP2_OFSW { w: self }
-    }
-}

src/adc0/clp3.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP3R {
+    bits: u16,
+}
+impl CLP3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp3(&self) -> CLP3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP3R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 384 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp3(&mut self) -> _CLP3W {
+        _CLP3W { w: self }
+    }
+}

src/adc0/clp3/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP3 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP3R {
-    bits: u16,
-}
-impl CLP3R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP3W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP3W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 1023;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp3(&self) -> CLP3R {
-        let bits = {
-            const MASK: u16 = 1023;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP3R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 384 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp3(&mut self) -> _CLP3W {
-        _CLP3W { w: self }
-    }
-}

src/adc0/clp3_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP3_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP3_OFSR {
+    bits: u8,
+}
+impl CLP3_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP3_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP3_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP3 Offset"]
+    #[inline]
+    pub fn clp3_ofs(&self) -> CLP3_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP3_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP3 Offset"]
+    #[inline]
+    pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
+        _CLP3_OFSW { w: self }
+    }
+}

src/adc0/clp3_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP3_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP3_OFSR {
-    bits: u8,
-}
-impl CLP3_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP3_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP3_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP3 Offset"]
-    #[inline]
-    pub fn clp3_ofs(&self) -> CLP3_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP3_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP3 Offset"]
-    #[inline]
-    pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
-        _CLP3_OFSW { w: self }
-    }
-}

src/adc0/clp9.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP9 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP9R {
+    bits: u8,
+}
+impl CLP9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP9W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clp9(&self) -> CLP9R {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP9R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clp9(&mut self) -> _CLP9W {
+        _CLP9W { w: self }
+    }
+}

src/adc0/clp9/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP9 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP9R {
-    bits: u8,
-}
-impl CLP9R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP9W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP9W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clp9(&self) -> CLP9R {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP9R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clp9(&mut self) -> _CLP9W {
-        _CLP9W { w: self }
-    }
-}

src/adc0/clp9_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP9_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP9_OFSR {
+    bits: u16,
+}
+impl CLP9_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP9_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP9_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 4095;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:11 - CLP9 Offset"]
+    #[inline]
+    pub fn clp9_ofs(&self) -> CLP9_OFSR {
+        let bits = {
+            const MASK: u16 = 4095;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP9_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 576 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:11 - CLP9 Offset"]
+    #[inline]
+    pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
+        _CLP9_OFSW { w: self }
+    }
+}

src/adc0/clp9_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP9_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP9_OFSR {
-    bits: u16,
-}
-impl CLP9_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP9_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP9_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 4095;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:11 - CLP9 Offset"]
-    #[inline]
-    pub fn clp9_ofs(&self) -> CLP9_OFSR {
-        let bits = {
-            const MASK: u16 = 4095;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP9_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 576 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:11 - CLP9 Offset"]
-    #[inline]
-    pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
-        _CLP9_OFSW { w: self }
-    }
-}

src/adc0/clps.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPSR {
+    bits: u8,
+}
+impl CLPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clps(&self) -> CLPSR {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 46 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clps(&mut self) -> _CLPSW {
+        _CLPSW { w: self }
+    }
+}

src/adc0/clps/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPSR {
-    bits: u8,
-}
-impl CLPSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clps(&self) -> CLPSR {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 46 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clps(&mut self) -> _CLPSW {
-        _CLPSW { w: self }
-    }
-}

src/adc0/clps_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPS_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPS_OFSR {
+    bits: u8,
+}
+impl CLPS_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPS_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPS_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLPS Offset"]
+    #[inline]
+    pub fn clps_ofs(&self) -> CLPS_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPS_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLPS Offset"]
+    #[inline]
+    pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
+        _CLPS_OFSW { w: self }
+    }
+}

src/adc0/clps_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPS_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPS_OFSR {
-    bits: u8,
-}
-impl CLPS_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPS_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPS_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLPS Offset"]
-    #[inline]
-    pub fn clps_ofs(&self) -> CLPS_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPS_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLPS Offset"]
-    #[inline]
-    pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
-        _CLPS_OFSW { w: self }
-    }
-}

src/adc0/clpx.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPX {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPXR {
+    bits: u8,
+}
+impl CLPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clpx(&self) -> CLPXR {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clpx(&mut self) -> _CLPXW {
+        _CLPXW { w: self }
+    }
+}

src/adc0/clpx/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPX {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPXR {
-    bits: u8,
-}
-impl CLPXR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPXW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPXW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clpx(&self) -> CLPXR {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPXR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clpx(&mut self) -> _CLPXW {
-        _CLPXW { w: self }
-    }
-}

src/adc0/clpx_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPX_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPX_OFSR {
+    bits: u16,
+}
+impl CLPX_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPX_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPX_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 4095;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:11 - CLPX Offset"]
+    #[inline]
+    pub fn clpx_ofs(&self) -> CLPX_OFSR {
+        let bits = {
+            const MASK: u16 = 4095;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLPX_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1088 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:11 - CLPX Offset"]
+    #[inline]
+    pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
+        _CLPX_OFSW { w: self }
+    }
+}

src/adc0/clpx_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPX_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPX_OFSR {
-    bits: u16,
-}
-impl CLPX_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPX_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPX_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 4095;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:11 - CLPX Offset"]
-    #[inline]
-    pub fn clpx_ofs(&self) -> CLPX_OFSR {
-        let bits = {
-            const MASK: u16 = 4095;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLPX_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 1088 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:11 - CLPX Offset"]
-    #[inline]
-    pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
-        _CLPX_OFSW { w: self }
-    }
-}

src/adc0/cv.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CV {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CVR {
+    bits: u16,
+}
+impl CVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CVW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Compare Value."]
+    #[inline]
+    pub fn cv(&self) -> CVR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CVR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Compare Value."]
+    #[inline]
+    pub fn cv(&mut self) -> _CVW {
+        _CVW { w: self }
+    }
+}

src/adc0/cv/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CV {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CVR {
-    bits: u16,
-}
-impl CVR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CVW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CVW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 65535;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:15 - Compare Value."]
-    #[inline]
-    pub fn cv(&self) -> CVR {
-        let bits = {
-            const MASK: u16 = 65535;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CVR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:15 - Compare Value."]
-    #[inline]
-    pub fn cv(&mut self) -> _CVW {
-        _CVW { w: self }
-    }
-}

src/adc0/g.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::G {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct GR {
+    bits: u16,
+}
+impl GR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _GW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _GW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 2047;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
+    #[inline]
+    pub fn g(&self) -> GR {
+        let bits = {
+            const MASK: u16 = 2047;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        GR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 752 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
+    #[inline]
+    pub fn g(&mut self) -> _GW {
+        _GW { w: self }
+    }
+}

src/adc0/g/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::G {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct GR {
-    bits: u16,
-}
-impl GR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _GW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _GW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 2047;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
-    #[inline]
-    pub fn g(&self) -> GR {
-        let bits = {
-            const MASK: u16 = 2047;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        GR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 752 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
-    #[inline]
-    pub fn g(&mut self) -> _GW {
-        _GW { w: self }
-    }
-}

src/adc0/mod.rs

@@ -1,291 +0,0 @@
-use vcell::VolatileCell;
-#[doc = r" Register block"]
-#[repr(C)]
-pub struct RegisterBlock {
-    #[doc = "0x00 - ADC Status and Control Register 1"]
-    pub sc1a: SC1,
-    #[doc = "0x04 - ADC Status and Control Register 1"]
-    pub sc1b: SC1,
-    #[doc = "0x08 - ADC Status and Control Register 1"]
-    pub sc1c: SC1,
-    #[doc = "0x0c - ADC Status and Control Register 1"]
-    pub sc1d: SC1,
-    #[doc = "0x10 - ADC Status and Control Register 1"]
-    pub sc1e: SC1,
-    #[doc = "0x14 - ADC Status and Control Register 1"]
-    pub sc1f: SC1,
-    #[doc = "0x18 - ADC Status and Control Register 1"]
-    pub sc1g: SC1,
-    #[doc = "0x1c - ADC Status and Control Register 1"]
-    pub sc1h: SC1,
-    #[doc = "0x20 - ADC Status and Control Register 1"]
-    pub sc1i: SC1,
-    #[doc = "0x24 - ADC Status and Control Register 1"]
-    pub sc1j: SC1,
-    #[doc = "0x28 - ADC Status and Control Register 1"]
-    pub sc1k: SC1,
-    #[doc = "0x2c - ADC Status and Control Register 1"]
-    pub sc1l: SC1,
-    #[doc = "0x30 - ADC Status and Control Register 1"]
-    pub sc1m: SC1,
-    #[doc = "0x34 - ADC Status and Control Register 1"]
-    pub sc1n: SC1,
-    #[doc = "0x38 - ADC Status and Control Register 1"]
-    pub sc1o: SC1,
-    #[doc = "0x3c - ADC Status and Control Register 1"]
-    pub sc1p: SC1,
-    #[doc = "0x40 - ADC Configuration Register 1"]
-    pub cfg1: CFG1,
-    #[doc = "0x44 - ADC Configuration Register 2"]
-    pub cfg2: CFG2,
-    #[doc = "0x48 - ADC Data Result Registers"]
-    pub ra: R,
-    #[doc = "0x4c - ADC Data Result Registers"]
-    pub rb: R,
-    #[doc = "0x50 - ADC Data Result Registers"]
-    pub rc: R,
-    #[doc = "0x54 - ADC Data Result Registers"]
-    pub rd: R,
-    #[doc = "0x58 - ADC Data Result Registers"]
-    pub re: R,
-    #[doc = "0x5c - ADC Data Result Registers"]
-    pub rf: R,
-    #[doc = "0x60 - ADC Data Result Registers"]
-    pub rg: R,
-    #[doc = "0x64 - ADC Data Result Registers"]
-    pub rh: R,
-    #[doc = "0x68 - ADC Data Result Registers"]
-    pub ri: R,
-    #[doc = "0x6c - ADC Data Result Registers"]
-    pub rj: R,
-    #[doc = "0x70 - ADC Data Result Registers"]
-    pub rk: R,
-    #[doc = "0x74 - ADC Data Result Registers"]
-    pub rl: R,
-    #[doc = "0x78 - ADC Data Result Registers"]
-    pub rm: R,
-    #[doc = "0x7c - ADC Data Result Registers"]
-    pub rn: R,
-    #[doc = "0x80 - ADC Data Result Registers"]
-    pub ro: R,
-    #[doc = "0x84 - ADC Data Result Registers"]
-    pub rp: R,
-    #[doc = "0x88 - Compare Value Registers"]
-    pub cv1: CV,
-    #[doc = "0x8c - Compare Value Registers"]
-    pub cv2: CV,
-    #[doc = "0x90 - Status and Control Register 2"]
-    pub sc2: SC2,
-    #[doc = "0x94 - Status and Control Register 3"]
-    pub sc3: SC3,
-    #[doc = "0x98 - BASE Offset Register"]
-    pub base_ofs: BASE_OFS,
-    #[doc = "0x9c - ADC Offset Correction Register"]
-    pub ofs: OFS,
-    #[doc = "0xa0 - USER Offset Correction Register"]
-    pub usr_ofs: USR_OFS,
-    #[doc = "0xa4 - ADC X Offset Correction Register"]
-    pub xofs: XOFS,
-    #[doc = "0xa8 - ADC Y Offset Correction Register"]
-    pub yofs: YOFS,
-    #[doc = "0xac - ADC Gain Register"]
-    pub g: G,
-    #[doc = "0xb0 - ADC User Gain Register"]
-    pub ug: UG,
-    #[doc = "0xb4 - ADC General Calibration Value Register S"]
-    pub clps: CLPS,
-    #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
-    pub clp3: CLP3,
-    #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
-    pub clp2: CLP2,
-    #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
-    pub clp1: CLP1,
-    #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
-    pub clp0: CLP0,
-    #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
-    pub clpx: CLPX,
-    #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
-    pub clp9: CLP9,
-    #[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
-    pub clps_ofs: CLPS_OFS,
-    #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
-    pub clp3_ofs: CLP3_OFS,
-    #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
-    pub clp2_ofs: CLP2_OFS,
-    #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
-    pub clp1_ofs: CLP1_OFS,
-    #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
-    pub clp0_ofs: CLP0_OFS,
-    #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
-    pub clpx_ofs: CLPX_OFS,
-    #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
-    pub clp9_ofs: CLP9_OFS,
-}
-#[doc = "ADC Status and Control Register 1"]
-pub struct SC1 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Status and Control Register 1"]
-pub mod sc1;
-#[doc = "ADC Configuration Register 1"]
-pub struct CFG1 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Configuration Register 1"]
-pub mod cfg1;
-#[doc = "ADC Configuration Register 2"]
-pub struct CFG2 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Configuration Register 2"]
-pub mod cfg2;
-#[doc = "ADC Data Result Registers"]
-pub struct R {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Data Result Registers"]
-pub mod r;
-#[doc = "Compare Value Registers"]
-pub struct CV {
-    register: VolatileCell<u32>,
-}
-#[doc = "Compare Value Registers"]
-pub mod cv;
-#[doc = "Status and Control Register 2"]
-pub struct SC2 {
-    register: VolatileCell<u32>,
-}
-#[doc = "Status and Control Register 2"]
-pub mod sc2;
-#[doc = "Status and Control Register 3"]
-pub struct SC3 {
-    register: VolatileCell<u32>,
-}
-#[doc = "Status and Control Register 3"]
-pub mod sc3;
-#[doc = "BASE Offset Register"]
-pub struct BASE_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "BASE Offset Register"]
-pub mod base_ofs;
-#[doc = "ADC Offset Correction Register"]
-pub struct OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Offset Correction Register"]
-pub mod ofs;
-#[doc = "USER Offset Correction Register"]
-pub struct USR_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "USER Offset Correction Register"]
-pub mod usr_ofs;
-#[doc = "ADC X Offset Correction Register"]
-pub struct XOFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC X Offset Correction Register"]
-pub mod xofs;
-#[doc = "ADC Y Offset Correction Register"]
-pub struct YOFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Y Offset Correction Register"]
-pub mod yofs;
-#[doc = "ADC Gain Register"]
-pub struct G {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Gain Register"]
-pub mod g;
-#[doc = "ADC User Gain Register"]
-pub struct UG {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC User Gain Register"]
-pub mod ug;
-#[doc = "ADC General Calibration Value Register S"]
-pub struct CLPS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC General Calibration Value Register S"]
-pub mod clps;
-#[doc = "ADC Plus-Side General Calibration Value Register 3"]
-pub struct CLP3 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register 3"]
-pub mod clp3;
-#[doc = "ADC Plus-Side General Calibration Value Register 2"]
-pub struct CLP2 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register 2"]
-pub mod clp2;
-#[doc = "ADC Plus-Side General Calibration Value Register 1"]
-pub struct CLP1 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register 1"]
-pub mod clp1;
-#[doc = "ADC Plus-Side General Calibration Value Register 0"]
-pub struct CLP0 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register 0"]
-pub mod clp0;
-#[doc = "ADC Plus-Side General Calibration Value Register X"]
-pub struct CLPX {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register X"]
-pub mod clpx;
-#[doc = "ADC Plus-Side General Calibration Value Register 9"]
-pub struct CLP9 {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Value Register 9"]
-pub mod clp9;
-#[doc = "ADC General Calibration Offset Value Register S"]
-pub struct CLPS_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC General Calibration Offset Value Register S"]
-pub mod clps_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
-pub struct CLP3_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
-pub mod clp3_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
-pub struct CLP2_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
-pub mod clp2_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
-pub struct CLP1_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
-pub mod clp1_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
-pub struct CLP0_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
-pub mod clp0_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
-pub struct CLPX_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
-pub mod clpx_ofs;
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
-pub struct CLP9_OFS {
-    register: VolatileCell<u32>,
-}
-#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
-pub mod clp9_ofs;

src/adc0/ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct OFSR {
+    bits: u16,
+}
+impl OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Offset Error Correction Value"]
+    #[inline]
+    pub fn ofs(&self) -> OFSR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Offset Error Correction Value"]
+    #[inline]
+    pub fn ofs(&mut self) -> _OFSW {
+        _OFSW { w: self }
+    }
+}

src/adc0/ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct OFSR {
-    bits: u16,
-}
-impl OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 65535;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:15 - Offset Error Correction Value"]
-    #[inline]
-    pub fn ofs(&self) -> OFSR {
-        let bits = {
-            const MASK: u16 = 65535;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:15 - Offset Error Correction Value"]
-    #[inline]
-    pub fn ofs(&mut self) -> _OFSW {
-        _OFSW { w: self }
-    }
-}

src/adc0/r.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::R {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DR {
+    bits: u16,
+}
+impl DR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:11 - Data result"]
+    #[inline]
+    pub fn d(&self) -> DR {
+        let bits = {
+            const MASK: u16 = 4095;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        DR { bits }
+    }
+}

src/adc0/r/mod.rs

@@ -1,41 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-impl super::R {
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-}
-#[doc = r" Value of the field"]
-pub struct DR {
-    bits: u16,
-}
-impl DR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:11 - Data result"]
-    #[inline]
-    pub fn d(&self) -> DR {
-        let bits = {
-            const MASK: u16 = 4095;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        DR { bits }
-    }
-}

src/adc0/sc1.rs

@@ -0,0 +1,765 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SC1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADCH`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADCHR {
+    #[doc = "Exernal channel 0 is selected as input."]
+    _00000,
+    #[doc = "Exernal channel 1 is selected as input."]
+    _00001,
+    #[doc = "Exernal channel 2 is selected as input."]
+    _00010,
+    #[doc = "Exernal channel 3 is selected as input."]
+    _00011,
+    #[doc = "Exernal channel 4 is selected as input."]
+    _00100,
+    #[doc = "Exernal channel 5 is selected as input."]
+    _00101,
+    #[doc = "Exernal channel 6 is selected as input."]
+    _00110,
+    #[doc = "Exernal channel 7 is selected as input."]
+    _00111,
+    #[doc = "Exernal channel 8 is selected as input."]
+    _01000,
+    #[doc = "Exernal channel 9 is selected as input."]
+    _01001,
+    #[doc = "Exernal channel 10 is selected as input."]
+    _01010,
+    #[doc = "Exernal channel 11 is selected as input."]
+    _01011,
+    #[doc = "Exernal channel 12 is selected as input."]
+    _01100,
+    #[doc = "Exernal channel 13 is selected as input."]
+    _01101,
+    #[doc = "Exernal channel 14 is selected as input."]
+    _01110,
+    #[doc = "Exernal channel 15 is selected as input."]
+    _01111,
+    #[doc = "Exernal channel 18 is selected as input."]
+    _10010,
+    #[doc = "Exernal channel 19 is selected as input."]
+    _10011,
+    #[doc = "Internal channel 0 is selected as input."]
+    _10101,
+    #[doc = "Internal channel 1 is selected as input."]
+    _10110,
+    #[doc = "Internal channel 2 is selected as input."]
+    _10111,
+    #[doc = "Temp Sensor"]
+    _11010,
+    #[doc = "Band Gap"]
+    _11011,
+    #[doc = "Internal channel 3 is selected as input."]
+    _11100,
+    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    _11101,
+    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    _11110,
+    #[doc = "Module is disabled"]
+    _11111,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADCHR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADCHR::_00000 => 0,
+            ADCHR::_00001 => 1,
+            ADCHR::_00010 => 2,
+            ADCHR::_00011 => 3,
+            ADCHR::_00100 => 4,
+            ADCHR::_00101 => 5,
+            ADCHR::_00110 => 6,
+            ADCHR::_00111 => 7,
+            ADCHR::_01000 => 8,
+            ADCHR::_01001 => 9,
+            ADCHR::_01010 => 10,
+            ADCHR::_01011 => 11,
+            ADCHR::_01100 => 12,
+            ADCHR::_01101 => 13,
+            ADCHR::_01110 => 14,
+            ADCHR::_01111 => 15,
+            ADCHR::_10010 => 18,
+            ADCHR::_10011 => 19,
+            ADCHR::_10101 => 21,
+            ADCHR::_10110 => 22,
+            ADCHR::_10111 => 23,
+            ADCHR::_11010 => 26,
+            ADCHR::_11011 => 27,
+            ADCHR::_11100 => 28,
+            ADCHR::_11101 => 29,
+            ADCHR::_11110 => 30,
+            ADCHR::_11111 => 31,
+            ADCHR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADCHR {
+        match value {
+            0 => ADCHR::_00000,
+            1 => ADCHR::_00001,
+            2 => ADCHR::_00010,
+            3 => ADCHR::_00011,
+            4 => ADCHR::_00100,
+            5 => ADCHR::_00101,
+            6 => ADCHR::_00110,
+            7 => ADCHR::_00111,
+            8 => ADCHR::_01000,
+            9 => ADCHR::_01001,
+            10 => ADCHR::_01010,
+            11 => ADCHR::_01011,
+            12 => ADCHR::_01100,
+            13 => ADCHR::_01101,
+            14 => ADCHR::_01110,
+            15 => ADCHR::_01111,
+            18 => ADCHR::_10010,
+            19 => ADCHR::_10011,
+            21 => ADCHR::_10101,
+            22 => ADCHR::_10110,
+            23 => ADCHR::_10111,
+            26 => ADCHR::_11010,
+            27 => ADCHR::_11011,
+            28 => ADCHR::_11100,
+            29 => ADCHR::_11101,
+            30 => ADCHR::_11110,
+            31 => ADCHR::_11111,
+            i => ADCHR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00000`"]
+    #[inline]
+    pub fn is_00000(&self) -> bool {
+        *self == ADCHR::_00000
+    }
+    #[doc = "Checks if the value of the field is `_00001`"]
+    #[inline]
+    pub fn is_00001(&self) -> bool {
+        *self == ADCHR::_00001
+    }
+    #[doc = "Checks if the value of the field is `_00010`"]
+    #[inline]
+    pub fn is_00010(&self) -> bool {
+        *self == ADCHR::_00010
+    }
+    #[doc = "Checks if the value of the field is `_00011`"]
+    #[inline]
+    pub fn is_00011(&self) -> bool {
+        *self == ADCHR::_00011
+    }
+    #[doc = "Checks if the value of the field is `_00100`"]
+    #[inline]
+    pub fn is_00100(&self) -> bool {
+        *self == ADCHR::_00100
+    }
+    #[doc = "Checks if the value of the field is `_00101`"]
+    #[inline]
+    pub fn is_00101(&self) -> bool {
+        *self == ADCHR::_00101
+    }
+    #[doc = "Checks if the value of the field is `_00110`"]
+    #[inline]
+    pub fn is_00110(&self) -> bool {
+        *self == ADCHR::_00110
+    }
+    #[doc = "Checks if the value of the field is `_00111`"]
+    #[inline]
+    pub fn is_00111(&self) -> bool {
+        *self == ADCHR::_00111
+    }
+    #[doc = "Checks if the value of the field is `_01000`"]
+    #[inline]
+    pub fn is_01000(&self) -> bool {
+        *self == ADCHR::_01000
+    }
+    #[doc = "Checks if the value of the field is `_01001`"]
+    #[inline]
+    pub fn is_01001(&self) -> bool {
+        *self == ADCHR::_01001
+    }
+    #[doc = "Checks if the value of the field is `_01010`"]
+    #[inline]
+    pub fn is_01010(&self) -> bool {
+        *self == ADCHR::_01010
+    }
+    #[doc = "Checks if the value of the field is `_01011`"]
+    #[inline]
+    pub fn is_01011(&self) -> bool {
+        *self == ADCHR::_01011
+    }
+    #[doc = "Checks if the value of the field is `_01100`"]
+    #[inline]
+    pub fn is_01100(&self) -> bool {
+        *self == ADCHR::_01100
+    }
+    #[doc = "Checks if the value of the field is `_01101`"]
+    #[inline]
+    pub fn is_01101(&self) -> bool {
+        *self == ADCHR::_01101
+    }
+    #[doc = "Checks if the value of the field is `_01110`"]
+    #[inline]
+    pub fn is_01110(&self) -> bool {
+        *self == ADCHR::_01110
+    }
+    #[doc = "Checks if the value of the field is `_01111`"]
+    #[inline]
+    pub fn is_01111(&self) -> bool {
+        *self == ADCHR::_01111
+    }
+    #[doc = "Checks if the value of the field is `_10010`"]
+    #[inline]
+    pub fn is_10010(&self) -> bool {
+        *self == ADCHR::_10010
+    }
+    #[doc = "Checks if the value of the field is `_10011`"]
+    #[inline]
+    pub fn is_10011(&self) -> bool {
+        *self == ADCHR::_10011
+    }
+    #[doc = "Checks if the value of the field is `_10101`"]
+    #[inline]
+    pub fn is_10101(&self) -> bool {
+        *self == ADCHR::_10101
+    }
+    #[doc = "Checks if the value of the field is `_10110`"]
+    #[inline]
+    pub fn is_10110(&self) -> bool {
+        *self == ADCHR::_10110
+    }
+    #[doc = "Checks if the value of the field is `_10111`"]
+    #[inline]
+    pub fn is_10111(&self) -> bool {
+        *self == ADCHR::_10111
+    }
+    #[doc = "Checks if the value of the field is `_11010`"]
+    #[inline]
+    pub fn is_11010(&self) -> bool {
+        *self == ADCHR::_11010
+    }
+    #[doc = "Checks if the value of the field is `_11011`"]
+    #[inline]
+    pub fn is_11011(&self) -> bool {
+        *self == ADCHR::_11011
+    }
+    #[doc = "Checks if the value of the field is `_11100`"]
+    #[inline]
+    pub fn is_11100(&self) -> bool {
+        *self == ADCHR::_11100
+    }
+    #[doc = "Checks if the value of the field is `_11101`"]
+    #[inline]
+    pub fn is_11101(&self) -> bool {
+        *self == ADCHR::_11101
+    }
+    #[doc = "Checks if the value of the field is `_11110`"]
+    #[inline]
+    pub fn is_11110(&self) -> bool {
+        *self == ADCHR::_11110
+    }
+    #[doc = "Checks if the value of the field is `_11111`"]
+    #[inline]
+    pub fn is_11111(&self) -> bool {
+        *self == ADCHR::_11111
+    }
+}
+#[doc = "Possible values of the field `AIEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AIENR {
+    #[doc = "Conversion complete interrupt is disabled."]
+    _0,
+    #[doc = "Conversion complete interrupt is enabled."]
+    _1,
+}
+impl AIENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AIENR::_0 => false,
+            AIENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AIENR {
+        match value {
+            false => AIENR::_0,
+            true => AIENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == AIENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == AIENR::_1
+    }
+}
+#[doc = "Possible values of the field `COCO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum COCOR {
+    #[doc = "Conversion is not completed."]
+    _0,
+    #[doc = "Conversion is completed."]
+    _1,
+}
+impl COCOR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            COCOR::_0 => false,
+            COCOR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> COCOR {
+        match value {
+            false => COCOR::_0,
+            true => COCOR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == COCOR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == COCOR::_1
+    }
+}
+#[doc = "Values that can be written to the field `ADCH`"]
+pub enum ADCHW {
+    #[doc = "Exernal channel 0 is selected as input."]
+    _00000,
+    #[doc = "Exernal channel 1 is selected as input."]
+    _00001,
+    #[doc = "Exernal channel 2 is selected as input."]
+    _00010,
+    #[doc = "Exernal channel 3 is selected as input."]
+    _00011,
+    #[doc = "Exernal channel 4 is selected as input."]
+    _00100,
+    #[doc = "Exernal channel 5 is selected as input."]
+    _00101,
+    #[doc = "Exernal channel 6 is selected as input."]
+    _00110,
+    #[doc = "Exernal channel 7 is selected as input."]
+    _00111,
+    #[doc = "Exernal channel 8 is selected as input."]
+    _01000,
+    #[doc = "Exernal channel 9 is selected as input."]
+    _01001,
+    #[doc = "Exernal channel 10 is selected as input."]
+    _01010,
+    #[doc = "Exernal channel 11 is selected as input."]
+    _01011,
+    #[doc = "Exernal channel 12 is selected as input."]
+    _01100,
+    #[doc = "Exernal channel 13 is selected as input."]
+    _01101,
+    #[doc = "Exernal channel 14 is selected as input."]
+    _01110,
+    #[doc = "Exernal channel 15 is selected as input."]
+    _01111,
+    #[doc = "Exernal channel 18 is selected as input."]
+    _10010,
+    #[doc = "Exernal channel 19 is selected as input."]
+    _10011,
+    #[doc = "Internal channel 0 is selected as input."]
+    _10101,
+    #[doc = "Internal channel 1 is selected as input."]
+    _10110,
+    #[doc = "Internal channel 2 is selected as input."]
+    _10111,
+    #[doc = "Temp Sensor"]
+    _11010,
+    #[doc = "Band Gap"]
+    _11011,
+    #[doc = "Internal channel 3 is selected as input."]
+    _11100,
+    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    _11101,
+    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    _11110,
+    #[doc = "Module is disabled"]
+    _11111,
+}
+impl ADCHW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADCHW::_00000 => 0,
+            ADCHW::_00001 => 1,
+            ADCHW::_00010 => 2,
+            ADCHW::_00011 => 3,
+            ADCHW::_00100 => 4,
+            ADCHW::_00101 => 5,
+            ADCHW::_00110 => 6,
+            ADCHW::_00111 => 7,
+            ADCHW::_01000 => 8,
+            ADCHW::_01001 => 9,
+            ADCHW::_01010 => 10,
+            ADCHW::_01011 => 11,
+            ADCHW::_01100 => 12,
+            ADCHW::_01101 => 13,
+            ADCHW::_01110 => 14,
+            ADCHW::_01111 => 15,
+            ADCHW::_10010 => 18,
+            ADCHW::_10011 => 19,
+            ADCHW::_10101 => 21,
+            ADCHW::_10110 => 22,
+            ADCHW::_10111 => 23,
+            ADCHW::_11010 => 26,
+            ADCHW::_11011 => 27,
+            ADCHW::_11100 => 28,
+            ADCHW::_11101 => 29,
+            ADCHW::_11110 => 30,
+            ADCHW::_11111 => 31,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADCHW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADCHW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADCHW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Exernal channel 0 is selected as input."]
+    #[inline]
+    pub fn _00000(self) -> &'a mut W {
+        self.variant(ADCHW::_00000)
+    }
+    #[doc = "Exernal channel 1 is selected as input."]
+    #[inline]
+    pub fn _00001(self) -> &'a mut W {
+        self.variant(ADCHW::_00001)
+    }
+    #[doc = "Exernal channel 2 is selected as input."]
+    #[inline]
+    pub fn _00010(self) -> &'a mut W {
+        self.variant(ADCHW::_00010)
+    }
+    #[doc = "Exernal channel 3 is selected as input."]
+    #[inline]
+    pub fn _00011(self) -> &'a mut W {
+        self.variant(ADCHW::_00011)
+    }
+    #[doc = "Exernal channel 4 is selected as input."]
+    #[inline]
+    pub fn _00100(self) -> &'a mut W {
+        self.variant(ADCHW::_00100)
+    }
+    #[doc = "Exernal channel 5 is selected as input."]
+    #[inline]
+    pub fn _00101(self) -> &'a mut W {
+        self.variant(ADCHW::_00101)
+    }
+    #[doc = "Exernal channel 6 is selected as input."]
+    #[inline]
+    pub fn _00110(self) -> &'a mut W {
+        self.variant(ADCHW::_00110)
+    }
+    #[doc = "Exernal channel 7 is selected as input."]
+    #[inline]
+    pub fn _00111(self) -> &'a mut W {
+        self.variant(ADCHW::_00111)
+    }
+    #[doc = "Exernal channel 8 is selected as input."]
+    #[inline]
+    pub fn _01000(self) -> &'a mut W {
+        self.variant(ADCHW::_01000)
+    }
+    #[doc = "Exernal channel 9 is selected as input."]
+    #[inline]
+    pub fn _01001(self) -> &'a mut W {
+        self.variant(ADCHW::_01001)
+    }
+    #[doc = "Exernal channel 10 is selected as input."]
+    #[inline]
+    pub fn _01010(self) -> &'a mut W {
+        self.variant(ADCHW::_01010)
+    }
+    #[doc = "Exernal channel 11 is selected as input."]
+    #[inline]
+    pub fn _01011(self) -> &'a mut W {
+        self.variant(ADCHW::_01011)
+    }
+    #[doc = "Exernal channel 12 is selected as input."]
+    #[inline]
+    pub fn _01100(self) -> &'a mut W {
+        self.variant(ADCHW::_01100)
+    }
+    #[doc = "Exernal channel 13 is selected as input."]
+    #[inline]
+    pub fn _01101(self) -> &'a mut W {
+        self.variant(ADCHW::_01101)
+    }
+    #[doc = "Exernal channel 14 is selected as input."]
+    #[inline]
+    pub fn _01110(self) -> &'a mut W {
+        self.variant(ADCHW::_01110)
+    }
+    #[doc = "Exernal channel 15 is selected as input."]
+    #[inline]
+    pub fn _01111(self) -> &'a mut W {
+        self.variant(ADCHW::_01111)
+    }
+    #[doc = "Exernal channel 18 is selected as input."]
+    #[inline]
+    pub fn _10010(self) -> &'a mut W {
+        self.variant(ADCHW::_10010)
+    }
+    #[doc = "Exernal channel 19 is selected as input."]
+    #[inline]
+    pub fn _10011(self) -> &'a mut W {
+        self.variant(ADCHW::_10011)
+    }
+    #[doc = "Internal channel 0 is selected as input."]
+    #[inline]
+    pub fn _10101(self) -> &'a mut W {
+        self.variant(ADCHW::_10101)
+    }
+    #[doc = "Internal channel 1 is selected as input."]
+    #[inline]
+    pub fn _10110(self) -> &'a mut W {
+        self.variant(ADCHW::_10110)
+    }
+    #[doc = "Internal channel 2 is selected as input."]
+    #[inline]
+    pub fn _10111(self) -> &'a mut W {
+        self.variant(ADCHW::_10111)
+    }
+    #[doc = "Temp Sensor"]
+    #[inline]
+    pub fn _11010(self) -> &'a mut W {
+        self.variant(ADCHW::_11010)
+    }
+    #[doc = "Band Gap"]
+    #[inline]
+    pub fn _11011(self) -> &'a mut W {
+        self.variant(ADCHW::_11011)
+    }
+    #[doc = "Internal channel 3 is selected as input."]
+    #[inline]
+    pub fn _11100(self) -> &'a mut W {
+        self.variant(ADCHW::_11100)
+    }
+    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    #[inline]
+    pub fn _11101(self) -> &'a mut W {
+        self.variant(ADCHW::_11101)
+    }
+    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
+    #[inline]
+    pub fn _11110(self) -> &'a mut W {
+        self.variant(ADCHW::_11110)
+    }
+    #[doc = "Module is disabled"]
+    #[inline]
+    pub fn _11111(self) -> &'a mut W {
+        self.variant(ADCHW::_11111)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AIEN`"]
+pub enum AIENW {
+    #[doc = "Conversion complete interrupt is disabled."]
+    _0,
+    #[doc = "Conversion complete interrupt is enabled."]
+    _1,
+}
+impl AIENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AIENW::_0 => false,
+            AIENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AIENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AIENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AIENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Conversion complete interrupt is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(AIENW::_0)
+    }
+    #[doc = "Conversion complete interrupt is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(AIENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Input channel select"]
+    #[inline]
+    pub fn adch(&self) -> ADCHR {
+        ADCHR::_from({
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 6 - Interrupt Enable"]
+    #[inline]
+    pub fn aien(&self) -> AIENR {
+        AIENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Conversion Complete Flag"]
+    #[inline]
+    pub fn coco(&self) -> COCOR {
+        COCOR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 31 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Input channel select"]
+    #[inline]
+    pub fn adch(&mut self) -> _ADCHW {
+        _ADCHW { w: self }
+    }
+    #[doc = "Bit 6 - Interrupt Enable"]
+    #[inline]
+    pub fn aien(&mut self) -> _AIENW {
+        _AIENW { w: self }
+    }
+}

src/adc0/sc1/mod.rs

@@ -1,767 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::SC1 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = "Possible values of the field `ADCH`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADCHR {
-    #[doc = "Exernal channel 0 is selected as input."]
-    _00000,
-    #[doc = "Exernal channel 1 is selected as input."]
-    _00001,
-    #[doc = "Exernal channel 2 is selected as input."]
-    _00010,
-    #[doc = "Exernal channel 3 is selected as input."]
-    _00011,
-    #[doc = "Exernal channel 4 is selected as input."]
-    _00100,
-    #[doc = "Exernal channel 5 is selected as input."]
-    _00101,
-    #[doc = "Exernal channel 6 is selected as input."]
-    _00110,
-    #[doc = "Exernal channel 7 is selected as input."]
-    _00111,
-    #[doc = "Exernal channel 8 is selected as input."]
-    _01000,
-    #[doc = "Exernal channel 9 is selected as input."]
-    _01001,
-    #[doc = "Exernal channel 10 is selected as input."]
-    _01010,
-    #[doc = "Exernal channel 11 is selected as input."]
-    _01011,
-    #[doc = "Exernal channel 12 is selected as input."]
-    _01100,
-    #[doc = "Exernal channel 13 is selected as input."]
-    _01101,
-    #[doc = "Exernal channel 14 is selected as input."]
-    _01110,
-    #[doc = "Exernal channel 15 is selected as input."]
-    _01111,
-    #[doc = "Exernal channel 18 is selected as input."]
-    _10010,
-    #[doc = "Exernal channel 19 is selected as input."]
-    _10011,
-    #[doc = "Internal channel 0 is selected as input."]
-    _10101,
-    #[doc = "Internal channel 1 is selected as input."]
-    _10110,
-    #[doc = "Internal channel 2 is selected as input."]
-    _10111,
-    #[doc = "Temp Sensor"]
-    _11010,
-    #[doc = "Band Gap"]
-    _11011,
-    #[doc = "Internal channel 3 is selected as input."]
-    _11100,
-    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    _11101,
-    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    _11110,
-    #[doc = "Module is disabled"]
-    _11111,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl ADCHR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            ADCHR::_00000 => 0,
-            ADCHR::_00001 => 1,
-            ADCHR::_00010 => 2,
-            ADCHR::_00011 => 3,
-            ADCHR::_00100 => 4,
-            ADCHR::_00101 => 5,
-            ADCHR::_00110 => 6,
-            ADCHR::_00111 => 7,
-            ADCHR::_01000 => 8,
-            ADCHR::_01001 => 9,
-            ADCHR::_01010 => 10,
-            ADCHR::_01011 => 11,
-            ADCHR::_01100 => 12,
-            ADCHR::_01101 => 13,
-            ADCHR::_01110 => 14,
-            ADCHR::_01111 => 15,
-            ADCHR::_10010 => 18,
-            ADCHR::_10011 => 19,
-            ADCHR::_10101 => 21,
-            ADCHR::_10110 => 22,
-            ADCHR::_10111 => 23,
-            ADCHR::_11010 => 26,
-            ADCHR::_11011 => 27,
-            ADCHR::_11100 => 28,
-            ADCHR::_11101 => 29,
-            ADCHR::_11110 => 30,
-            ADCHR::_11111 => 31,
-            ADCHR::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> ADCHR {
-        match value {
-            0 => ADCHR::_00000,
-            1 => ADCHR::_00001,
-            2 => ADCHR::_00010,
-            3 => ADCHR::_00011,
-            4 => ADCHR::_00100,
-            5 => ADCHR::_00101,
-            6 => ADCHR::_00110,
-            7 => ADCHR::_00111,
-            8 => ADCHR::_01000,
-            9 => ADCHR::_01001,
-            10 => ADCHR::_01010,
-            11 => ADCHR::_01011,
-            12 => ADCHR::_01100,
-            13 => ADCHR::_01101,
-            14 => ADCHR::_01110,
-            15 => ADCHR::_01111,
-            18 => ADCHR::_10010,
-            19 => ADCHR::_10011,
-            21 => ADCHR::_10101,
-            22 => ADCHR::_10110,
-            23 => ADCHR::_10111,
-            26 => ADCHR::_11010,
-            27 => ADCHR::_11011,
-            28 => ADCHR::_11100,
-            29 => ADCHR::_11101,
-            30 => ADCHR::_11110,
-            31 => ADCHR::_11111,
-            i => ADCHR::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00000`"]
-    #[inline]
-    pub fn is_00000(&self) -> bool {
-        *self == ADCHR::_00000
-    }
-    #[doc = "Checks if the value of the field is `_00001`"]
-    #[inline]
-    pub fn is_00001(&self) -> bool {
-        *self == ADCHR::_00001
-    }
-    #[doc = "Checks if the value of the field is `_00010`"]
-    #[inline]
-    pub fn is_00010(&self) -> bool {
-        *self == ADCHR::_00010
-    }
-    #[doc = "Checks if the value of the field is `_00011`"]
-    #[inline]
-    pub fn is_00011(&self) -> bool {
-        *self == ADCHR::_00011
-    }
-    #[doc = "Checks if the value of the field is `_00100`"]
-    #[inline]
-    pub fn is_00100(&self) -> bool {
-        *self == ADCHR::_00100
-    }
-    #[doc = "Checks if the value of the field is `_00101`"]
-    #[inline]
-    pub fn is_00101(&self) -> bool {
-        *self == ADCHR::_00101
-    }
-    #[doc = "Checks if the value of the field is `_00110`"]
-    #[inline]
-    pub fn is_00110(&self) -> bool {
-        *self == ADCHR::_00110
-    }
-    #[doc = "Checks if the value of the field is `_00111`"]
-    #[inline]
-    pub fn is_00111(&self) -> bool {
-        *self == ADCHR::_00111
-    }
-    #[doc = "Checks if the value of the field is `_01000`"]
-    #[inline]
-    pub fn is_01000(&self) -> bool {
-        *self == ADCHR::_01000
-    }
-    #[doc = "Checks if the value of the field is `_01001`"]
-    #[inline]
-    pub fn is_01001(&self) -> bool {
-        *self == ADCHR::_01001
-    }
-    #[doc = "Checks if the value of the field is `_01010`"]
-    #[inline]
-    pub fn is_01010(&self) -> bool {
-        *self == ADCHR::_01010
-    }
-    #[doc = "Checks if the value of the field is `_01011`"]
-    #[inline]
-    pub fn is_01011(&self) -> bool {
-        *self == ADCHR::_01011
-    }
-    #[doc = "Checks if the value of the field is `_01100`"]
-    #[inline]
-    pub fn is_01100(&self) -> bool {
-        *self == ADCHR::_01100
-    }
-    #[doc = "Checks if the value of the field is `_01101`"]
-    #[inline]
-    pub fn is_01101(&self) -> bool {
-        *self == ADCHR::_01101
-    }
-    #[doc = "Checks if the value of the field is `_01110`"]
-    #[inline]
-    pub fn is_01110(&self) -> bool {
-        *self == ADCHR::_01110
-    }
-    #[doc = "Checks if the value of the field is `_01111`"]
-    #[inline]
-    pub fn is_01111(&self) -> bool {
-        *self == ADCHR::_01111
-    }
-    #[doc = "Checks if the value of the field is `_10010`"]
-    #[inline]
-    pub fn is_10010(&self) -> bool {
-        *self == ADCHR::_10010
-    }
-    #[doc = "Checks if the value of the field is `_10011`"]
-    #[inline]
-    pub fn is_10011(&self) -> bool {
-        *self == ADCHR::_10011
-    }
-    #[doc = "Checks if the value of the field is `_10101`"]
-    #[inline]
-    pub fn is_10101(&self) -> bool {
-        *self == ADCHR::_10101
-    }
-    #[doc = "Checks if the value of the field is `_10110`"]
-    #[inline]
-    pub fn is_10110(&self) -> bool {
-        *self == ADCHR::_10110
-    }
-    #[doc = "Checks if the value of the field is `_10111`"]
-    #[inline]
-    pub fn is_10111(&self) -> bool {
-        *self == ADCHR::_10111
-    }
-    #[doc = "Checks if the value of the field is `_11010`"]
-    #[inline]
-    pub fn is_11010(&self) -> bool {
-        *self == ADCHR::_11010
-    }
-    #[doc = "Checks if the value of the field is `_11011`"]
-    #[inline]
-    pub fn is_11011(&self) -> bool {
-        *self == ADCHR::_11011
-    }
-    #[doc = "Checks if the value of the field is `_11100`"]
-    #[inline]
-    pub fn is_11100(&self) -> bool {
-        *self == ADCHR::_11100
-    }
-    #[doc = "Checks if the value of the field is `_11101`"]
-    #[inline]
-    pub fn is_11101(&self) -> bool {
-        *self == ADCHR::_11101
-    }
-    #[doc = "Checks if the value of the field is `_11110`"]
-    #[inline]
-    pub fn is_11110(&self) -> bool {
-        *self == ADCHR::_11110
-    }
-    #[doc = "Checks if the value of the field is `_11111`"]
-    #[inline]
-    pub fn is_11111(&self) -> bool {
-        *self == ADCHR::_11111
-    }
-}
-#[doc = "Possible values of the field `AIEN`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum AIENR {
-    #[doc = "Conversion complete interrupt is disabled."]
-    _0,
-    #[doc = "Conversion complete interrupt is enabled."]
-    _1,
-}
-impl AIENR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            AIENR::_0 => false,
-            AIENR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> AIENR {
-        match value {
-            false => AIENR::_0,
-            true => AIENR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == AIENR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == AIENR::_1
-    }
-}
-#[doc = "Possible values of the field `COCO`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum COCOR {
-    #[doc = "Conversion is not completed."]
-    _0,
-    #[doc = "Conversion is completed."]
-    _1,
-}
-impl COCOR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            COCOR::_0 => false,
-            COCOR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> COCOR {
-        match value {
-            false => COCOR::_0,
-            true => COCOR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == COCOR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == COCOR::_1
-    }
-}
-#[doc = "Values that can be written to the field `ADCH`"]
-pub enum ADCHW {
-    #[doc = "Exernal channel 0 is selected as input."]
-    _00000,
-    #[doc = "Exernal channel 1 is selected as input."]
-    _00001,
-    #[doc = "Exernal channel 2 is selected as input."]
-    _00010,
-    #[doc = "Exernal channel 3 is selected as input."]
-    _00011,
-    #[doc = "Exernal channel 4 is selected as input."]
-    _00100,
-    #[doc = "Exernal channel 5 is selected as input."]
-    _00101,
-    #[doc = "Exernal channel 6 is selected as input."]
-    _00110,
-    #[doc = "Exernal channel 7 is selected as input."]
-    _00111,
-    #[doc = "Exernal channel 8 is selected as input."]
-    _01000,
-    #[doc = "Exernal channel 9 is selected as input."]
-    _01001,
-    #[doc = "Exernal channel 10 is selected as input."]
-    _01010,
-    #[doc = "Exernal channel 11 is selected as input."]
-    _01011,
-    #[doc = "Exernal channel 12 is selected as input."]
-    _01100,
-    #[doc = "Exernal channel 13 is selected as input."]
-    _01101,
-    #[doc = "Exernal channel 14 is selected as input."]
-    _01110,
-    #[doc = "Exernal channel 15 is selected as input."]
-    _01111,
-    #[doc = "Exernal channel 18 is selected as input."]
-    _10010,
-    #[doc = "Exernal channel 19 is selected as input."]
-    _10011,
-    #[doc = "Internal channel 0 is selected as input."]
-    _10101,
-    #[doc = "Internal channel 1 is selected as input."]
-    _10110,
-    #[doc = "Internal channel 2 is selected as input."]
-    _10111,
-    #[doc = "Temp Sensor"]
-    _11010,
-    #[doc = "Band Gap"]
-    _11011,
-    #[doc = "Internal channel 3 is selected as input."]
-    _11100,
-    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    _11101,
-    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    _11110,
-    #[doc = "Module is disabled"]
-    _11111,
-}
-impl ADCHW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            ADCHW::_00000 => 0,
-            ADCHW::_00001 => 1,
-            ADCHW::_00010 => 2,
-            ADCHW::_00011 => 3,
-            ADCHW::_00100 => 4,
-            ADCHW::_00101 => 5,
-            ADCHW::_00110 => 6,
-            ADCHW::_00111 => 7,
-            ADCHW::_01000 => 8,
-            ADCHW::_01001 => 9,
-            ADCHW::_01010 => 10,
-            ADCHW::_01011 => 11,
-            ADCHW::_01100 => 12,
-            ADCHW::_01101 => 13,
-            ADCHW::_01110 => 14,
-            ADCHW::_01111 => 15,
-            ADCHW::_10010 => 18,
-            ADCHW::_10011 => 19,
-            ADCHW::_10101 => 21,
-            ADCHW::_10110 => 22,
-            ADCHW::_10111 => 23,
-            ADCHW::_11010 => 26,
-            ADCHW::_11011 => 27,
-            ADCHW::_11100 => 28,
-            ADCHW::_11101 => 29,
-            ADCHW::_11110 => 30,
-            ADCHW::_11111 => 31,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADCHW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADCHW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADCHW) -> &'a mut W {
-        unsafe { self.bits(variant._bits()) }
-    }
-    #[doc = "Exernal channel 0 is selected as input."]
-    #[inline]
-    pub fn _00000(self) -> &'a mut W {
-        self.variant(ADCHW::_00000)
-    }
-    #[doc = "Exernal channel 1 is selected as input."]
-    #[inline]
-    pub fn _00001(self) -> &'a mut W {
-        self.variant(ADCHW::_00001)
-    }
-    #[doc = "Exernal channel 2 is selected as input."]
-    #[inline]
-    pub fn _00010(self) -> &'a mut W {
-        self.variant(ADCHW::_00010)
-    }
-    #[doc = "Exernal channel 3 is selected as input."]
-    #[inline]
-    pub fn _00011(self) -> &'a mut W {
-        self.variant(ADCHW::_00011)
-    }
-    #[doc = "Exernal channel 4 is selected as input."]
-    #[inline]
-    pub fn _00100(self) -> &'a mut W {
-        self.variant(ADCHW::_00100)
-    }
-    #[doc = "Exernal channel 5 is selected as input."]
-    #[inline]
-    pub fn _00101(self) -> &'a mut W {
-        self.variant(ADCHW::_00101)
-    }
-    #[doc = "Exernal channel 6 is selected as input."]
-    #[inline]
-    pub fn _00110(self) -> &'a mut W {
-        self.variant(ADCHW::_00110)
-    }
-    #[doc = "Exernal channel 7 is selected as input."]
-    #[inline]
-    pub fn _00111(self) -> &'a mut W {
-        self.variant(ADCHW::_00111)
-    }
-    #[doc = "Exernal channel 8 is selected as input."]
-    #[inline]
-    pub fn _01000(self) -> &'a mut W {
-        self.variant(ADCHW::_01000)
-    }
-    #[doc = "Exernal channel 9 is selected as input."]
-    #[inline]
-    pub fn _01001(self) -> &'a mut W {
-        self.variant(ADCHW::_01001)
-    }
-    #[doc = "Exernal channel 10 is selected as input."]
-    #[inline]
-    pub fn _01010(self) -> &'a mut W {
-        self.variant(ADCHW::_01010)
-    }
-    #[doc = "Exernal channel 11 is selected as input."]
-    #[inline]
-    pub fn _01011(self) -> &'a mut W {
-        self.variant(ADCHW::_01011)
-    }
-    #[doc = "Exernal channel 12 is selected as input."]
-    #[inline]
-    pub fn _01100(self) -> &'a mut W {
-        self.variant(ADCHW::_01100)
-    }
-    #[doc = "Exernal channel 13 is selected as input."]
-    #[inline]
-    pub fn _01101(self) -> &'a mut W {
-        self.variant(ADCHW::_01101)
-    }
-    #[doc = "Exernal channel 14 is selected as input."]
-    #[inline]
-    pub fn _01110(self) -> &'a mut W {
-        self.variant(ADCHW::_01110)
-    }
-    #[doc = "Exernal channel 15 is selected as input."]
-    #[inline]
-    pub fn _01111(self) -> &'a mut W {
-        self.variant(ADCHW::_01111)
-    }
-    #[doc = "Exernal channel 18 is selected as input."]
-    #[inline]
-    pub fn _10010(self) -> &'a mut W {
-        self.variant(ADCHW::_10010)
-    }
-    #[doc = "Exernal channel 19 is selected as input."]
-    #[inline]
-    pub fn _10011(self) -> &'a mut W {
-        self.variant(ADCHW::_10011)
-    }
-    #[doc = "Internal channel 0 is selected as input."]
-    #[inline]
-    pub fn _10101(self) -> &'a mut W {
-        self.variant(ADCHW::_10101)
-    }
-    #[doc = "Internal channel 1 is selected as input."]
-    #[inline]
-    pub fn _10110(self) -> &'a mut W {
-        self.variant(ADCHW::_10110)
-    }
-    #[doc = "Internal channel 2 is selected as input."]
-    #[inline]
-    pub fn _10111(self) -> &'a mut W {
-        self.variant(ADCHW::_10111)
-    }
-    #[doc = "Temp Sensor"]
-    #[inline]
-    pub fn _11010(self) -> &'a mut W {
-        self.variant(ADCHW::_11010)
-    }
-    #[doc = "Band Gap"]
-    #[inline]
-    pub fn _11011(self) -> &'a mut W {
-        self.variant(ADCHW::_11011)
-    }
-    #[doc = "Internal channel 3 is selected as input."]
-    #[inline]
-    pub fn _11100(self) -> &'a mut W {
-        self.variant(ADCHW::_11100)
-    }
-    #[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    #[inline]
-    pub fn _11101(self) -> &'a mut W {
-        self.variant(ADCHW::_11101)
-    }
-    #[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
-    #[inline]
-    pub fn _11110(self) -> &'a mut W {
-        self.variant(ADCHW::_11110)
-    }
-    #[doc = "Module is disabled"]
-    #[inline]
-    pub fn _11111(self) -> &'a mut W {
-        self.variant(ADCHW::_11111)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 31;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `AIEN`"]
-pub enum AIENW {
-    #[doc = "Conversion complete interrupt is disabled."]
-    _0,
-    #[doc = "Conversion complete interrupt is enabled."]
-    _1,
-}
-impl AIENW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            AIENW::_0 => false,
-            AIENW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _AIENW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _AIENW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: AIENW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "Conversion complete interrupt is disabled."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(AIENW::_0)
-    }
-    #[doc = "Conversion complete interrupt is enabled."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(AIENW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 6;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:4 - Input channel select"]
-    #[inline]
-    pub fn adch(&self) -> ADCHR {
-        ADCHR::_from({
-            const MASK: u8 = 31;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bit 6 - Interrupt Enable"]
-    #[inline]
-    pub fn aien(&self) -> AIENR {
-        AIENR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 6;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 7 - Conversion Complete Flag"]
-    #[inline]
-    pub fn coco(&self) -> COCOR {
-        COCOR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 7;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 31 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:4 - Input channel select"]
-    #[inline]
-    pub fn adch(&mut self) -> _ADCHW {
-        _ADCHW { w: self }
-    }
-    #[doc = "Bit 6 - Interrupt Enable"]
-    #[inline]
-    pub fn aien(&mut self) -> _AIENW {
-        _AIENW { w: self }
-    }
-}

src/adc0/sc2.rs

@@ -0,0 +1,817 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SC2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `REFSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum REFSELR {
+    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
+    _00,
+    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
+    _01,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl REFSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            REFSELR::_00 => 0,
+            REFSELR::_01 => 1,
+            REFSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> REFSELR {
+        match value {
+            0 => REFSELR::_00,
+            1 => REFSELR::_01,
+            i => REFSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == REFSELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == REFSELR::_01
+    }
+}
+#[doc = "Possible values of the field `DMAEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAENR {
+    #[doc = "DMA is disabled."]
+    _0,
+    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
+    _1,
+}
+impl DMAENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAENR::_0 => false,
+            DMAENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAENR {
+        match value {
+            false => DMAENR::_0,
+            true => DMAENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAENR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACRENR {
+    bits: bool,
+}
+impl ACRENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ACFGTR {
+    bits: bool,
+}
+impl ACFGTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `ACFE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ACFER {
+    #[doc = "Compare function disabled."]
+    _0,
+    #[doc = "Compare function enabled."]
+    _1,
+}
+impl ACFER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ACFER::_0 => false,
+            ACFER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ACFER {
+        match value {
+            false => ACFER::_0,
+            true => ACFER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ACFER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ACFER::_1
+    }
+}
+#[doc = "Possible values of the field `ADTRG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADTRGR {
+    #[doc = "Software trigger selected."]
+    _0,
+    #[doc = "Hardware trigger selected."]
+    _1,
+}
+impl ADTRGR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADTRGR::_0 => false,
+            ADTRGR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADTRGR {
+        match value {
+            false => ADTRGR::_0,
+            true => ADTRGR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ADTRGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ADTRGR::_1
+    }
+}
+#[doc = "Possible values of the field `ADACT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADACTR {
+    #[doc = "Conversion not in progress."]
+    _0,
+    #[doc = "Conversion in progress."]
+    _1,
+}
+impl ADACTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADACTR::_0 => false,
+            ADACTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADACTR {
+        match value {
+            false => ADACTR::_0,
+            true => ADACTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ADACTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ADACTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRGPRNUMR {
+    bits: u8,
+}
+impl TRGPRNUMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `TRGSTLAT`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSTLATR {
+    #[doc = "No trigger request has been latched"]
+    _0,
+    #[doc = "A trigger request has been latched"]
+    _1,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TRGSTLATR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TRGSTLATR::_0 => 0,
+            TRGSTLATR::_1 => 1,
+            TRGSTLATR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TRGSTLATR {
+        match value {
+            0 => TRGSTLATR::_0,
+            1 => TRGSTLATR::_1,
+            i => TRGSTLATR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSTLATR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSTLATR::_1
+    }
+}
+#[doc = "Possible values of the field `TRGSTERR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSTERRR {
+    #[doc = "No error has occurred"]
+    _0,
+    #[doc = "An error has occurred"]
+    _1,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TRGSTERRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TRGSTERRR::_0 => 0,
+            TRGSTERRR::_1 => 1,
+            TRGSTERRR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TRGSTERRR {
+        match value {
+            0 => TRGSTERRR::_0,
+            1 => TRGSTERRR::_1,
+            i => TRGSTERRR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSTERRR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSTERRR::_1
+    }
+}
+#[doc = "Values that can be written to the field `REFSEL`"]
+pub enum REFSELW {
+    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
+    _00,
+    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
+    _01,
+}
+impl REFSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            REFSELW::_00 => 0,
+            REFSELW::_01 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _REFSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _REFSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: REFSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(REFSELW::_00)
+    }
+    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(REFSELW::_01)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DMAEN`"]
+pub enum DMAENW {
+    #[doc = "DMA is disabled."]
+    _0,
+    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
+    _1,
+}
+impl DMAENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAENW::_0 => false,
+            DMAENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "DMA is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAENW::_0)
+    }
+    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ACRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ACRENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ACFGTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ACFGTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ACFE`"]
+pub enum ACFEW {
+    #[doc = "Compare function disabled."]
+    _0,
+    #[doc = "Compare function enabled."]
+    _1,
+}
+impl ACFEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ACFEW::_0 => false,
+            ACFEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ACFEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ACFEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ACFEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Compare function disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ACFEW::_0)
+    }
+    #[doc = "Compare function enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ACFEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADTRG`"]
+pub enum ADTRGW {
+    #[doc = "Software trigger selected."]
+    _0,
+    #[doc = "Hardware trigger selected."]
+    _1,
+}
+impl ADTRGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADTRGW::_0 => false,
+            ADTRGW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADTRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADTRGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADTRGW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Software trigger selected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ADTRGW::_0)
+    }
+    #[doc = "Hardware trigger selected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ADTRGW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Voltage Reference Selection"]
+    #[inline]
+    pub fn refsel(&self) -> REFSELR {
+        REFSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 2 - DMA Enable"]
+    #[inline]
+    pub fn dmaen(&self) -> DMAENR {
+        DMAENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Compare Function Range Enable"]
+    #[inline]
+    pub fn acren(&self) -> ACRENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ACRENR { bits }
+    }
+    #[doc = "Bit 4 - Compare Function Greater Than Enable"]
+    #[inline]
+    pub fn acfgt(&self) -> ACFGTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ACFGTR { bits }
+    }
+    #[doc = "Bit 5 - Compare Function Enable"]
+    #[inline]
+    pub fn acfe(&self) -> ACFER {
+        ACFER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Conversion Trigger Select"]
+    #[inline]
+    pub fn adtrg(&self) -> ADTRGR {
+        ADTRGR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Conversion Active"]
+    #[inline]
+    pub fn adact(&self) -> ADACTR {
+        ADACTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 13:14 - Trigger Process Number"]
+    #[inline]
+    pub fn trgprnum(&self) -> TRGPRNUMR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 13;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRGPRNUMR { bits }
+    }
+    #[doc = "Bits 16:19 - Trigger Status"]
+    #[inline]
+    pub fn trgstlat(&self) -> TRGSTLATR {
+        TRGSTLATR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
+    #[inline]
+    pub fn trgsterr(&self) -> TRGSTERRR {
+        TRGSTERRR::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Voltage Reference Selection"]
+    #[inline]
+    pub fn refsel(&mut self) -> _REFSELW {
+        _REFSELW { w: self }
+    }
+    #[doc = "Bit 2 - DMA Enable"]
+    #[inline]
+    pub fn dmaen(&mut self) -> _DMAENW {
+        _DMAENW { w: self }
+    }
+    #[doc = "Bit 3 - Compare Function Range Enable"]
+    #[inline]
+    pub fn acren(&mut self) -> _ACRENW {
+        _ACRENW { w: self }
+    }
+    #[doc = "Bit 4 - Compare Function Greater Than Enable"]
+    #[inline]
+    pub fn acfgt(&mut self) -> _ACFGTW {
+        _ACFGTW { w: self }
+    }
+    #[doc = "Bit 5 - Compare Function Enable"]
+    #[inline]
+    pub fn acfe(&mut self) -> _ACFEW {
+        _ACFEW { w: self }
+    }
+    #[doc = "Bit 6 - Conversion Trigger Select"]
+    #[inline]
+    pub fn adtrg(&mut self) -> _ADTRGW {
+        _ADTRGW { w: self }
+    }
+}

src/adc0/sc2/mod.rs

@@ -1,819 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::SC2 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = "Possible values of the field `REFSEL`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum REFSELR {
-    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
-    _00,
-    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
-    _01,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl REFSELR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            REFSELR::_00 => 0,
-            REFSELR::_01 => 1,
-            REFSELR::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> REFSELR {
-        match value {
-            0 => REFSELR::_00,
-            1 => REFSELR::_01,
-            i => REFSELR::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == REFSELR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == REFSELR::_01
-    }
-}
-#[doc = "Possible values of the field `DMAEN`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum DMAENR {
-    #[doc = "DMA is disabled."]
-    _0,
-    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
-    _1,
-}
-impl DMAENR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            DMAENR::_0 => false,
-            DMAENR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> DMAENR {
-        match value {
-            false => DMAENR::_0,
-            true => DMAENR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == DMAENR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == DMAENR::_1
-    }
-}
-#[doc = r" Value of the field"]
-pub struct ACRENR {
-    bits: bool,
-}
-impl ACRENR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        self.bits
-    }
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-}
-#[doc = r" Value of the field"]
-pub struct ACFGTR {
-    bits: bool,
-}
-impl ACFGTR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        self.bits
-    }
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-}
-#[doc = "Possible values of the field `ACFE`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ACFER {
-    #[doc = "Compare function disabled."]
-    _0,
-    #[doc = "Compare function enabled."]
-    _1,
-}
-impl ACFER {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            ACFER::_0 => false,
-            ACFER::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> ACFER {
-        match value {
-            false => ACFER::_0,
-            true => ACFER::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == ACFER::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == ACFER::_1
-    }
-}
-#[doc = "Possible values of the field `ADTRG`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADTRGR {
-    #[doc = "Software trigger selected."]
-    _0,
-    #[doc = "Hardware trigger selected."]
-    _1,
-}
-impl ADTRGR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            ADTRGR::_0 => false,
-            ADTRGR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> ADTRGR {
-        match value {
-            false => ADTRGR::_0,
-            true => ADTRGR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == ADTRGR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == ADTRGR::_1
-    }
-}
-#[doc = "Possible values of the field `ADACT`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADACTR {
-    #[doc = "Conversion not in progress."]
-    _0,
-    #[doc = "Conversion in progress."]
-    _1,
-}
-impl ADACTR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            ADACTR::_0 => false,
-            ADACTR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> ADACTR {
-        match value {
-            false => ADACTR::_0,
-            true => ADACTR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == ADACTR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == ADACTR::_1
-    }
-}
-#[doc = r" Value of the field"]
-pub struct TRGPRNUMR {
-    bits: u8,
-}
-impl TRGPRNUMR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = "Possible values of the field `TRGSTLAT`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum TRGSTLATR {
-    #[doc = "No trigger request has been latched"]
-    _0,
-    #[doc = "A trigger request has been latched"]
-    _1,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl TRGSTLATR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            TRGSTLATR::_0 => 0,
-            TRGSTLATR::_1 => 1,
-            TRGSTLATR::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> TRGSTLATR {
-        match value {
-            0 => TRGSTLATR::_0,
-            1 => TRGSTLATR::_1,
-            i => TRGSTLATR::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == TRGSTLATR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == TRGSTLATR::_1
-    }
-}
-#[doc = "Possible values of the field `TRGSTERR`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum TRGSTERRR {
-    #[doc = "No error has occurred"]
-    _0,
-    #[doc = "An error has occurred"]
-    _1,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl TRGSTERRR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            TRGSTERRR::_0 => 0,
-            TRGSTERRR::_1 => 1,
-            TRGSTERRR::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> TRGSTERRR {
-        match value {
-            0 => TRGSTERRR::_0,
-            1 => TRGSTERRR::_1,
-            i => TRGSTERRR::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == TRGSTERRR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == TRGSTERRR::_1
-    }
-}
-#[doc = "Values that can be written to the field `REFSEL`"]
-pub enum REFSELW {
-    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
-    _00,
-    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
-    _01,
-}
-impl REFSELW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            REFSELW::_00 => 0,
-            REFSELW::_01 => 1,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _REFSELW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _REFSELW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: REFSELW) -> &'a mut W {
-        unsafe { self.bits(variant._bits()) }
-    }
-    #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(REFSELW::_00)
-    }
-    #[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(REFSELW::_01)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `DMAEN`"]
-pub enum DMAENW {
-    #[doc = "DMA is disabled."]
-    _0,
-    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
-    _1,
-}
-impl DMAENW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            DMAENW::_0 => false,
-            DMAENW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _DMAENW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _DMAENW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: DMAENW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "DMA is disabled."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(DMAENW::_0)
-    }
-    #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(DMAENW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 2;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ACRENW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ACRENW<'a> {
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 3;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ACFGTW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ACFGTW<'a> {
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 4;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `ACFE`"]
-pub enum ACFEW {
-    #[doc = "Compare function disabled."]
-    _0,
-    #[doc = "Compare function enabled."]
-    _1,
-}
-impl ACFEW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            ACFEW::_0 => false,
-            ACFEW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ACFEW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ACFEW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ACFEW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "Compare function disabled."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(ACFEW::_0)
-    }
-    #[doc = "Compare function enabled."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(ACFEW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 5;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `ADTRG`"]
-pub enum ADTRGW {
-    #[doc = "Software trigger selected."]
-    _0,
-    #[doc = "Hardware trigger selected."]
-    _1,
-}
-impl ADTRGW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            ADTRGW::_0 => false,
-            ADTRGW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADTRGW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADTRGW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADTRGW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "Software trigger selected."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(ADTRGW::_0)
-    }
-    #[doc = "Hardware trigger selected."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(ADTRGW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 6;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:1 - Voltage Reference Selection"]
-    #[inline]
-    pub fn refsel(&self) -> REFSELR {
-        REFSELR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bit 2 - DMA Enable"]
-    #[inline]
-    pub fn dmaen(&self) -> DMAENR {
-        DMAENR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 2;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 3 - Compare Function Range Enable"]
-    #[inline]
-    pub fn acren(&self) -> ACRENR {
-        let bits = {
-            const MASK: bool = true;
-            const OFFSET: u8 = 3;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        };
-        ACRENR { bits }
-    }
-    #[doc = "Bit 4 - Compare Function Greater Than Enable"]
-    #[inline]
-    pub fn acfgt(&self) -> ACFGTR {
-        let bits = {
-            const MASK: bool = true;
-            const OFFSET: u8 = 4;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        };
-        ACFGTR { bits }
-    }
-    #[doc = "Bit 5 - Compare Function Enable"]
-    #[inline]
-    pub fn acfe(&self) -> ACFER {
-        ACFER::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 5;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 6 - Conversion Trigger Select"]
-    #[inline]
-    pub fn adtrg(&self) -> ADTRGR {
-        ADTRGR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 6;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 7 - Conversion Active"]
-    #[inline]
-    pub fn adact(&self) -> ADACTR {
-        ADACTR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 7;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bits 13:14 - Trigger Process Number"]
-    #[inline]
-    pub fn trgprnum(&self) -> TRGPRNUMR {
-        let bits = {
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 13;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        TRGPRNUMR { bits }
-    }
-    #[doc = "Bits 16:19 - Trigger Status"]
-    #[inline]
-    pub fn trgstlat(&self) -> TRGSTLATR {
-        TRGSTLATR::_from({
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 16;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
-    #[inline]
-    pub fn trgsterr(&self) -> TRGSTERRR {
-        TRGSTERRR::_from({
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 24;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:1 - Voltage Reference Selection"]
-    #[inline]
-    pub fn refsel(&mut self) -> _REFSELW {
-        _REFSELW { w: self }
-    }
-    #[doc = "Bit 2 - DMA Enable"]
-    #[inline]
-    pub fn dmaen(&mut self) -> _DMAENW {
-        _DMAENW { w: self }
-    }
-    #[doc = "Bit 3 - Compare Function Range Enable"]
-    #[inline]
-    pub fn acren(&mut self) -> _ACRENW {
-        _ACRENW { w: self }
-    }
-    #[doc = "Bit 4 - Compare Function Greater Than Enable"]
-    #[inline]
-    pub fn acfgt(&mut self) -> _ACFGTW {
-        _ACFGTW { w: self }
-    }
-    #[doc = "Bit 5 - Compare Function Enable"]
-    #[inline]
-    pub fn acfe(&mut self) -> _ACFEW {
-        _ACFEW { w: self }
-    }
-    #[doc = "Bit 6 - Conversion Trigger Select"]
-    #[inline]
-    pub fn adtrg(&mut self) -> _ADTRGW {
-        _ADTRGW { w: self }
-    }
-}

src/adc0/sc3.rs

@@ -0,0 +1,495 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SC3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `AVGS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AVGSR {
+    #[doc = "4 samples averaged."]
+    _00,
+    #[doc = "8 samples averaged."]
+    _01,
+    #[doc = "16 samples averaged."]
+    _10,
+    #[doc = "32 samples averaged."]
+    _11,
+}
+impl AVGSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            AVGSR::_00 => 0,
+            AVGSR::_01 => 1,
+            AVGSR::_10 => 2,
+            AVGSR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> AVGSR {
+        match value {
+            0 => AVGSR::_00,
+            1 => AVGSR::_01,
+            2 => AVGSR::_10,
+            3 => AVGSR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == AVGSR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == AVGSR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == AVGSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == AVGSR::_11
+    }
+}
+#[doc = "Possible values of the field `AVGE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum AVGER {
+    #[doc = "Hardware average function disabled."]
+    _0,
+    #[doc = "Hardware average function enabled."]
+    _1,
+}
+impl AVGER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            AVGER::_0 => false,
+            AVGER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> AVGER {
+        match value {
+            false => AVGER::_0,
+            true => AVGER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == AVGER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == AVGER::_1
+    }
+}
+#[doc = "Possible values of the field `ADCO`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADCOR {
+    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
+    _0,
+    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
+    _1,
+}
+impl ADCOR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADCOR::_0 => false,
+            ADCOR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADCOR {
+        match value {
+            false => ADCOR::_0,
+            true => ADCOR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ADCOR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ADCOR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CALR {
+    bits: bool,
+}
+impl CALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Values that can be written to the field `AVGS`"]
+pub enum AVGSW {
+    #[doc = "4 samples averaged."]
+    _00,
+    #[doc = "8 samples averaged."]
+    _01,
+    #[doc = "16 samples averaged."]
+    _10,
+    #[doc = "32 samples averaged."]
+    _11,
+}
+impl AVGSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            AVGSW::_00 => 0,
+            AVGSW::_01 => 1,
+            AVGSW::_10 => 2,
+            AVGSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVGSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVGSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AVGSW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "4 samples averaged."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(AVGSW::_00)
+    }
+    #[doc = "8 samples averaged."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(AVGSW::_01)
+    }
+    #[doc = "16 samples averaged."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(AVGSW::_10)
+    }
+    #[doc = "32 samples averaged."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(AVGSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `AVGE`"]
+pub enum AVGEW {
+    #[doc = "Hardware average function disabled."]
+    _0,
+    #[doc = "Hardware average function enabled."]
+    _1,
+}
+impl AVGEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            AVGEW::_0 => false,
+            AVGEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _AVGEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _AVGEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: AVGEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Hardware average function disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(AVGEW::_0)
+    }
+    #[doc = "Hardware average function enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(AVGEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADCO`"]
+pub enum ADCOW {
+    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
+    _0,
+    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
+    _1,
+}
+impl ADCOW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADCOW::_0 => false,
+            ADCOW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADCOW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADCOW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADCOW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ADCOW::_0)
+    }
+    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ADCOW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CALW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Hardware Average Select"]
+    #[inline]
+    pub fn avgs(&self) -> AVGSR {
+        AVGSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 2 - Hardware Average Enable"]
+    #[inline]
+    pub fn avge(&self) -> AVGER {
+        AVGER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Continuous Conversion Enable"]
+    #[inline]
+    pub fn adco(&self) -> ADCOR {
+        ADCOR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Calibration"]
+    #[inline]
+    pub fn cal(&self) -> CALR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        CALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Hardware Average Select"]
+    #[inline]
+    pub fn avgs(&mut self) -> _AVGSW {
+        _AVGSW { w: self }
+    }
+    #[doc = "Bit 2 - Hardware Average Enable"]
+    #[inline]
+    pub fn avge(&mut self) -> _AVGEW {
+        _AVGEW { w: self }
+    }
+    #[doc = "Bit 3 - Continuous Conversion Enable"]
+    #[inline]
+    pub fn adco(&mut self) -> _ADCOW {
+        _ADCOW { w: self }
+    }
+    #[doc = "Bit 7 - Calibration"]
+    #[inline]
+    pub fn cal(&mut self) -> _CALW {
+        _CALW { w: self }
+    }
+}

src/adc0/sc3/mod.rs

@@ -1,497 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::SC3 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = "Possible values of the field `AVGS`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum AVGSR {
-    #[doc = "4 samples averaged."]
-    _00,
-    #[doc = "8 samples averaged."]
-    _01,
-    #[doc = "16 samples averaged."]
-    _10,
-    #[doc = "32 samples averaged."]
-    _11,
-}
-impl AVGSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            AVGSR::_00 => 0,
-            AVGSR::_01 => 1,
-            AVGSR::_10 => 2,
-            AVGSR::_11 => 3,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> AVGSR {
-        match value {
-            0 => AVGSR::_00,
-            1 => AVGSR::_01,
-            2 => AVGSR::_10,
-            3 => AVGSR::_11,
-            _ => unreachable!(),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == AVGSR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == AVGSR::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == AVGSR::_10
-    }
-    #[doc = "Checks if the value of the field is `_11`"]
-    #[inline]
-    pub fn is_11(&self) -> bool {
-        *self == AVGSR::_11
-    }
-}
-#[doc = "Possible values of the field `AVGE`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum AVGER {
-    #[doc = "Hardware average function disabled."]
-    _0,
-    #[doc = "Hardware average function enabled."]
-    _1,
-}
-impl AVGER {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            AVGER::_0 => false,
-            AVGER::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> AVGER {
-        match value {
-            false => AVGER::_0,
-            true => AVGER::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == AVGER::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == AVGER::_1
-    }
-}
-#[doc = "Possible values of the field `ADCO`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADCOR {
-    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
-    _0,
-    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
-    _1,
-}
-impl ADCOR {
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        match *self {
-            ADCOR::_0 => false,
-            ADCOR::_1 => true,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: bool) -> ADCOR {
-        match value {
-            false => ADCOR::_0,
-            true => ADCOR::_1,
-        }
-    }
-    #[doc = "Checks if the value of the field is `_0`"]
-    #[inline]
-    pub fn is_0(&self) -> bool {
-        *self == ADCOR::_0
-    }
-    #[doc = "Checks if the value of the field is `_1`"]
-    #[inline]
-    pub fn is_1(&self) -> bool {
-        *self == ADCOR::_1
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CALR {
-    bits: bool,
-}
-impl CALR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bit(&self) -> bool {
-        self.bits
-    }
-    #[doc = r" Returns `true` if the bit is clear (0)"]
-    #[inline]
-    pub fn bit_is_clear(&self) -> bool {
-        !self.bit()
-    }
-    #[doc = r" Returns `true` if the bit is set (1)"]
-    #[inline]
-    pub fn bit_is_set(&self) -> bool {
-        self.bit()
-    }
-}
-#[doc = "Values that can be written to the field `AVGS`"]
-pub enum AVGSW {
-    #[doc = "4 samples averaged."]
-    _00,
-    #[doc = "8 samples averaged."]
-    _01,
-    #[doc = "16 samples averaged."]
-    _10,
-    #[doc = "32 samples averaged."]
-    _11,
-}
-impl AVGSW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            AVGSW::_00 => 0,
-            AVGSW::_01 => 1,
-            AVGSW::_10 => 2,
-            AVGSW::_11 => 3,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _AVGSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _AVGSW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: AVGSW) -> &'a mut W {
-        {
-            self.bits(variant._bits())
-        }
-    }
-    #[doc = "4 samples averaged."]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(AVGSW::_00)
-    }
-    #[doc = "8 samples averaged."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(AVGSW::_01)
-    }
-    #[doc = "16 samples averaged."]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(AVGSW::_10)
-    }
-    #[doc = "32 samples averaged."]
-    #[inline]
-    pub fn _11(self) -> &'a mut W {
-        self.variant(AVGSW::_11)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `AVGE`"]
-pub enum AVGEW {
-    #[doc = "Hardware average function disabled."]
-    _0,
-    #[doc = "Hardware average function enabled."]
-    _1,
-}
-impl AVGEW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            AVGEW::_0 => false,
-            AVGEW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _AVGEW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _AVGEW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: AVGEW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "Hardware average function disabled."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(AVGEW::_0)
-    }
-    #[doc = "Hardware average function enabled."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(AVGEW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 2;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `ADCO`"]
-pub enum ADCOW {
-    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
-    _0,
-    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
-    _1,
-}
-impl ADCOW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> bool {
-        match *self {
-            ADCOW::_0 => false,
-            ADCOW::_1 => true,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADCOW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADCOW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADCOW) -> &'a mut W {
-        {
-            self.bit(variant._bits())
-        }
-    }
-    #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
-    #[inline]
-    pub fn _0(self) -> &'a mut W {
-        self.variant(ADCOW::_0)
-    }
-    #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
-    #[inline]
-    pub fn _1(self) -> &'a mut W {
-        self.variant(ADCOW::_1)
-    }
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 3;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CALW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CALW<'a> {
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 7;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:1 - Hardware Average Select"]
-    #[inline]
-    pub fn avgs(&self) -> AVGSR {
-        AVGSR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bit 2 - Hardware Average Enable"]
-    #[inline]
-    pub fn avge(&self) -> AVGER {
-        AVGER::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 2;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 3 - Continuous Conversion Enable"]
-    #[inline]
-    pub fn adco(&self) -> ADCOR {
-        ADCOR::_from({
-            const MASK: bool = true;
-            const OFFSET: u8 = 3;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        })
-    }
-    #[doc = "Bit 7 - Calibration"]
-    #[inline]
-    pub fn cal(&self) -> CALR {
-        let bits = {
-            const MASK: bool = true;
-            const OFFSET: u8 = 7;
-            ((self.bits >> OFFSET) & MASK as u32) != 0
-        };
-        CALR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:1 - Hardware Average Select"]
-    #[inline]
-    pub fn avgs(&mut self) -> _AVGSW {
-        _AVGSW { w: self }
-    }
-    #[doc = "Bit 2 - Hardware Average Enable"]
-    #[inline]
-    pub fn avge(&mut self) -> _AVGEW {
-        _AVGEW { w: self }
-    }
-    #[doc = "Bit 3 - Continuous Conversion Enable"]
-    #[inline]
-    pub fn adco(&mut self) -> _ADCOW {
-        _ADCOW { w: self }
-    }
-    #[doc = "Bit 7 - Calibration"]
-    #[inline]
-    pub fn cal(&mut self) -> _CALW {
-        _CALW { w: self }
-    }
-}

src/adc0/ug.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::UG {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UGR {
+    bits: u16,
+}
+impl UGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UGW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - User gain error correction value"]
+    #[inline]
+    pub fn ug(&self) -> UGR {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        UGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - User gain error correction value"]
+    #[inline]
+    pub fn ug(&mut self) -> _UGW {
+        _UGW { w: self }
+    }
+}

src/adc0/ug/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::UG {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct UGR {
-    bits: u16,
-}
-impl UGR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _UGW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _UGW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 1023;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:9 - User gain error correction value"]
-    #[inline]
-    pub fn ug(&self) -> UGR {
-        let bits = {
-            const MASK: u16 = 1023;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        UGR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 4 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:9 - User gain error correction value"]
-    #[inline]
-    pub fn ug(&mut self) -> _UGW {
-        _UGW { w: self }
-    }
-}

src/adc0/usr_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::USR_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct USR_OFSR {
+    bits: u8,
+}
+impl USR_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _USR_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _USR_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
+    #[inline]
+    pub fn usr_ofs(&self) -> USR_OFSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        USR_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
+    #[inline]
+    pub fn usr_ofs(&mut self) -> _USR_OFSW {
+        _USR_OFSW { w: self }
+    }
+}

src/adc0/usr_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::USR_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct USR_OFSR {
-    bits: u8,
-}
-impl USR_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _USR_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _USR_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
-    #[inline]
-    pub fn usr_ofs(&self) -> USR_OFSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        USR_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
-    #[inline]
-    pub fn usr_ofs(&mut self) -> _USR_OFSW {
-        _USR_OFSW { w: self }
-    }
-}

src/adc0/xofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::XOFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct XOFSR {
+    bits: u8,
+}
+impl XOFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _XOFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _XOFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - X offset error correction value"]
+    #[inline]
+    pub fn xofs(&self) -> XOFSR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        XOFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 48 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - X offset error correction value"]
+    #[inline]
+    pub fn xofs(&mut self) -> _XOFSW {
+        _XOFSW { w: self }
+    }
+}

src/adc0/xofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::XOFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct XOFSR {
-    bits: u8,
-}
-impl XOFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _XOFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _XOFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 63;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:5 - X offset error correction value"]
-    #[inline]
-    pub fn xofs(&self) -> XOFSR {
-        let bits = {
-            const MASK: u8 = 63;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        XOFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 48 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:5 - X offset error correction value"]
-    #[inline]
-    pub fn xofs(&mut self) -> _XOFSW {
-        _XOFSW { w: self }
-    }
-}

src/adc0/yofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::YOFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct YOFSR {
+    bits: u8,
+}
+impl YOFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _YOFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _YOFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Y offset error correction value"]
+    #[inline]
+    pub fn yofs(&self) -> YOFSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        YOFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 55 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Y offset error correction value"]
+    #[inline]
+    pub fn yofs(&mut self) -> _YOFSW {
+        _YOFSW { w: self }
+    }
+}

src/adc0/yofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::YOFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct YOFSR {
-    bits: u8,
-}
-impl YOFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _YOFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _YOFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Y offset error correction value"]
-    #[inline]
-    pub fn yofs(&self) -> YOFSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        YOFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 55 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Y offset error correction value"]
-    #[inline]
-    pub fn yofs(&mut self) -> _YOFSW {
-        _YOFSW { w: self }
-    }
-}

src/adc1.rs

@@ -0,0 +1,290 @@
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - ADC Status and Control Register 1"]
+    pub sc1a: SC1,
+    #[doc = "0x04 - ADC Status and Control Register 1"]
+    pub sc1b: SC1,
+    #[doc = "0x08 - ADC Status and Control Register 1"]
+    pub sc1c: SC1,
+    #[doc = "0x0c - ADC Status and Control Register 1"]
+    pub sc1d: SC1,
+    #[doc = "0x10 - ADC Status and Control Register 1"]
+    pub sc1e: SC1,
+    #[doc = "0x14 - ADC Status and Control Register 1"]
+    pub sc1f: SC1,
+    #[doc = "0x18 - ADC Status and Control Register 1"]
+    pub sc1g: SC1,
+    #[doc = "0x1c - ADC Status and Control Register 1"]
+    pub sc1h: SC1,
+    #[doc = "0x20 - ADC Status and Control Register 1"]
+    pub sc1i: SC1,
+    #[doc = "0x24 - ADC Status and Control Register 1"]
+    pub sc1j: SC1,
+    #[doc = "0x28 - ADC Status and Control Register 1"]
+    pub sc1k: SC1,
+    #[doc = "0x2c - ADC Status and Control Register 1"]
+    pub sc1l: SC1,
+    #[doc = "0x30 - ADC Status and Control Register 1"]
+    pub sc1m: SC1,
+    #[doc = "0x34 - ADC Status and Control Register 1"]
+    pub sc1n: SC1,
+    #[doc = "0x38 - ADC Status and Control Register 1"]
+    pub sc1o: SC1,
+    #[doc = "0x3c - ADC Status and Control Register 1"]
+    pub sc1p: SC1,
+    #[doc = "0x40 - ADC Configuration Register 1"]
+    pub cfg1: CFG1,
+    #[doc = "0x44 - ADC Configuration Register 2"]
+    pub cfg2: CFG2,
+    #[doc = "0x48 - ADC Data Result Registers"]
+    pub ra: R,
+    #[doc = "0x4c - ADC Data Result Registers"]
+    pub rb: R,
+    #[doc = "0x50 - ADC Data Result Registers"]
+    pub rc: R,
+    #[doc = "0x54 - ADC Data Result Registers"]
+    pub rd: R,
+    #[doc = "0x58 - ADC Data Result Registers"]
+    pub re: R,
+    #[doc = "0x5c - ADC Data Result Registers"]
+    pub rf: R,
+    #[doc = "0x60 - ADC Data Result Registers"]
+    pub rg: R,
+    #[doc = "0x64 - ADC Data Result Registers"]
+    pub rh: R,
+    #[doc = "0x68 - ADC Data Result Registers"]
+    pub ri: R,
+    #[doc = "0x6c - ADC Data Result Registers"]
+    pub rj: R,
+    #[doc = "0x70 - ADC Data Result Registers"]
+    pub rk: R,
+    #[doc = "0x74 - ADC Data Result Registers"]
+    pub rl: R,
+    #[doc = "0x78 - ADC Data Result Registers"]
+    pub rm: R,
+    #[doc = "0x7c - ADC Data Result Registers"]
+    pub rn: R,
+    #[doc = "0x80 - ADC Data Result Registers"]
+    pub ro: R,
+    #[doc = "0x84 - ADC Data Result Registers"]
+    pub rp: R,
+    #[doc = "0x88 - Compare Value Registers"]
+    pub cv1: CV,
+    #[doc = "0x8c - Compare Value Registers"]
+    pub cv2: CV,
+    #[doc = "0x90 - Status and Control Register 2"]
+    pub sc2: SC2,
+    #[doc = "0x94 - Status and Control Register 3"]
+    pub sc3: SC3,
+    #[doc = "0x98 - BASE Offset Register"]
+    pub base_ofs: BASE_OFS,
+    #[doc = "0x9c - ADC Offset Correction Register"]
+    pub ofs: OFS,
+    #[doc = "0xa0 - USER Offset Correction Register"]
+    pub usr_ofs: USR_OFS,
+    #[doc = "0xa4 - ADC X Offset Correction Register"]
+    pub xofs: XOFS,
+    #[doc = "0xa8 - ADC Y Offset Correction Register"]
+    pub yofs: YOFS,
+    #[doc = "0xac - ADC Gain Register"]
+    pub g: G,
+    #[doc = "0xb0 - ADC User Gain Register"]
+    pub ug: UG,
+    #[doc = "0xb4 - ADC General Calibration Value Register S"]
+    pub clps: CLPS,
+    #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
+    pub clp3: CLP3,
+    #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
+    pub clp2: CLP2,
+    #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
+    pub clp1: CLP1,
+    #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
+    pub clp0: CLP0,
+    #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
+    pub clpx: CLPX,
+    #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
+    pub clp9: CLP9,
+    #[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
+    pub clps_ofs: CLPS_OFS,
+    #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
+    pub clp3_ofs: CLP3_OFS,
+    #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
+    pub clp2_ofs: CLP2_OFS,
+    #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
+    pub clp1_ofs: CLP1_OFS,
+    #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
+    pub clp0_ofs: CLP0_OFS,
+    #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
+    pub clpx_ofs: CLPX_OFS,
+    #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
+    pub clp9_ofs: CLP9_OFS,
+}
+#[doc = "ADC Status and Control Register 1"]
+pub struct SC1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Status and Control Register 1"]
+pub mod sc1;
+#[doc = "ADC Configuration Register 1"]
+pub struct CFG1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Configuration Register 1"]
+pub mod cfg1;
+#[doc = "ADC Configuration Register 2"]
+pub struct CFG2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Configuration Register 2"]
+pub mod cfg2;
+#[doc = "ADC Data Result Registers"]
+pub struct R {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Data Result Registers"]
+pub mod r;
+#[doc = "Compare Value Registers"]
+pub struct CV {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Compare Value Registers"]
+pub mod cv;
+#[doc = "Status and Control Register 2"]
+pub struct SC2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status and Control Register 2"]
+pub mod sc2;
+#[doc = "Status and Control Register 3"]
+pub struct SC3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "Status and Control Register 3"]
+pub mod sc3;
+#[doc = "BASE Offset Register"]
+pub struct BASE_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "BASE Offset Register"]
+pub mod base_ofs;
+#[doc = "ADC Offset Correction Register"]
+pub struct OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Offset Correction Register"]
+pub mod ofs;
+#[doc = "USER Offset Correction Register"]
+pub struct USR_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "USER Offset Correction Register"]
+pub mod usr_ofs;
+#[doc = "ADC X Offset Correction Register"]
+pub struct XOFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC X Offset Correction Register"]
+pub mod xofs;
+#[doc = "ADC Y Offset Correction Register"]
+pub struct YOFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Y Offset Correction Register"]
+pub mod yofs;
+#[doc = "ADC Gain Register"]
+pub struct G {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Gain Register"]
+pub mod g;
+#[doc = "ADC User Gain Register"]
+pub struct UG {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC User Gain Register"]
+pub mod ug;
+#[doc = "ADC General Calibration Value Register S"]
+pub struct CLPS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC General Calibration Value Register S"]
+pub mod clps;
+#[doc = "ADC Plus-Side General Calibration Value Register 3"]
+pub struct CLP3 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 3"]
+pub mod clp3;
+#[doc = "ADC Plus-Side General Calibration Value Register 2"]
+pub struct CLP2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 2"]
+pub mod clp2;
+#[doc = "ADC Plus-Side General Calibration Value Register 1"]
+pub struct CLP1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 1"]
+pub mod clp1;
+#[doc = "ADC Plus-Side General Calibration Value Register 0"]
+pub struct CLP0 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 0"]
+pub mod clp0;
+#[doc = "ADC Plus-Side General Calibration Value Register X"]
+pub struct CLPX {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register X"]
+pub mod clpx;
+#[doc = "ADC Plus-Side General Calibration Value Register 9"]
+pub struct CLP9 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Value Register 9"]
+pub mod clp9;
+#[doc = "ADC General Calibration Offset Value Register S"]
+pub struct CLPS_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC General Calibration Offset Value Register S"]
+pub mod clps_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
+pub struct CLP3_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
+pub mod clp3_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
+pub struct CLP2_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
+pub mod clp2_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
+pub struct CLP1_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
+pub mod clp1_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
+pub struct CLP0_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
+pub mod clp0_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
+pub struct CLPX_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
+pub mod clpx_ofs;
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
+pub struct CLP9_OFS {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
+pub mod clp9_ofs;

src/adc1/base_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::BASE_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BA_OFSR {
+    bits: u8,
+}
+impl BA_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BA_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BA_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
+    #[inline]
+    pub fn ba_ofs(&self) -> BA_OFSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        BA_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 64 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
+    #[inline]
+    pub fn ba_ofs(&mut self) -> _BA_OFSW {
+        _BA_OFSW { w: self }
+    }
+}

src/adc1/base_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::BASE_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct BA_OFSR {
-    bits: u8,
-}
-impl BA_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _BA_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _BA_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
-    #[inline]
-    pub fn ba_ofs(&self) -> BA_OFSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        BA_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 64 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
-    #[inline]
-    pub fn ba_ofs(&mut self) -> _BA_OFSW {
-        _BA_OFSW { w: self }
-    }
-}

src/adc1/cfg1.rs

@@ -0,0 +1,482 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CFG1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADICLK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADICLKR {
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    _00,
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    _01,
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    _10,
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    _11,
+}
+impl ADICLKR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADICLKR::_00 => 0,
+            ADICLKR::_01 => 1,
+            ADICLKR::_10 => 2,
+            ADICLKR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADICLKR {
+        match value {
+            0 => ADICLKR::_00,
+            1 => ADICLKR::_01,
+            2 => ADICLKR::_10,
+            3 => ADICLKR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADICLKR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADICLKR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADICLKR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == ADICLKR::_11
+    }
+}
+#[doc = "Possible values of the field `MODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODER {
+    #[doc = "8-bit conversion."]
+    _00,
+    #[doc = "12-bit conversion."]
+    _01,
+    #[doc = "10-bit conversion."]
+    _10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl MODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            MODER::_00 => 0,
+            MODER::_01 => 1,
+            MODER::_10 => 2,
+            MODER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> MODER {
+        match value {
+            0 => MODER::_00,
+            1 => MODER::_01,
+            2 => MODER::_10,
+            i => MODER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == MODER::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == MODER::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == MODER::_10
+    }
+}
+#[doc = "Possible values of the field `ADIV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADIVR {
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    _00,
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    _01,
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    _10,
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    _11,
+}
+impl ADIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADIVR::_00 => 0,
+            ADIVR::_01 => 1,
+            ADIVR::_10 => 2,
+            ADIVR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADIVR {
+        match value {
+            0 => ADIVR::_00,
+            1 => ADIVR::_01,
+            2 => ADIVR::_10,
+            3 => ADIVR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADIVR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADIVR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADIVR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == ADIVR::_11
+    }
+}
+#[doc = "Values that can be written to the field `ADICLK`"]
+pub enum ADICLKW {
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    _00,
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    _01,
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    _10,
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    _11,
+}
+impl ADICLKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADICLKW::_00 => 0,
+            ADICLKW::_01 => 1,
+            ADICLKW::_10 => 2,
+            ADICLKW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADICLKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADICLKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADICLKW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADICLKW::_00)
+    }
+    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADICLKW::_01)
+    }
+    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADICLKW::_10)
+    }
+    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(ADICLKW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `MODE`"]
+pub enum MODEW {
+    #[doc = "8-bit conversion."]
+    _00,
+    #[doc = "12-bit conversion."]
+    _01,
+    #[doc = "10-bit conversion."]
+    _10,
+}
+impl MODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            MODEW::_00 => 0,
+            MODEW::_01 => 1,
+            MODEW::_10 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: MODEW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "8-bit conversion."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(MODEW::_00)
+    }
+    #[doc = "12-bit conversion."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(MODEW::_01)
+    }
+    #[doc = "10-bit conversion."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(MODEW::_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADIV`"]
+pub enum ADIVW {
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    _00,
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    _01,
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    _10,
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    _11,
+}
+impl ADIVW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADIVW::_00 => 0,
+            ADIVW::_01 => 1,
+            ADIVW::_10 => 2,
+            ADIVW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADIVW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADIVW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADIVW::_00)
+    }
+    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADIVW::_01)
+    }
+    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADIVW::_10)
+    }
+    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(ADIVW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLRLTRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLRLTRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Input Clock Select"]
+    #[inline]
+    pub fn adiclk(&self) -> ADICLKR {
+        ADICLKR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 2:3 - Conversion mode selection"]
+    #[inline]
+    pub fn mode(&self) -> MODER {
+        MODER::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 5:6 - Clock Divide Select"]
+    #[inline]
+    pub fn adiv(&self) -> ADIVR {
+        ADIVR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Input Clock Select"]
+    #[inline]
+    pub fn adiclk(&mut self) -> _ADICLKW {
+        _ADICLKW { w: self }
+    }
+    #[doc = "Bits 2:3 - Conversion mode selection"]
+    #[inline]
+    pub fn mode(&mut self) -> _MODEW {
+        _MODEW { w: self }
+    }
+    #[doc = "Bits 5:6 - Clock Divide Select"]
+    #[inline]
+    pub fn adiv(&mut self) -> _ADIVW {
+        _ADIVW { w: self }
+    }
+    #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
+    #[inline]
+    pub fn clrltrg(&mut self) -> _CLRLTRGW {
+        _CLRLTRGW { w: self }
+    }
+}

src/adc1/cfg1/mod.rs

@@ -1,484 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CFG1 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = "Possible values of the field `ADICLK`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADICLKR {
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    _00,
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    _01,
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    _10,
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    _11,
-}
-impl ADICLKR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            ADICLKR::_00 => 0,
-            ADICLKR::_01 => 1,
-            ADICLKR::_10 => 2,
-            ADICLKR::_11 => 3,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> ADICLKR {
-        match value {
-            0 => ADICLKR::_00,
-            1 => ADICLKR::_01,
-            2 => ADICLKR::_10,
-            3 => ADICLKR::_11,
-            _ => unreachable!(),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == ADICLKR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == ADICLKR::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == ADICLKR::_10
-    }
-    #[doc = "Checks if the value of the field is `_11`"]
-    #[inline]
-    pub fn is_11(&self) -> bool {
-        *self == ADICLKR::_11
-    }
-}
-#[doc = "Possible values of the field `MODE`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum MODER {
-    #[doc = "8-bit conversion."]
-    _00,
-    #[doc = "12-bit conversion."]
-    _01,
-    #[doc = "10-bit conversion."]
-    _10,
-    #[doc = r" Reserved"]
-    _Reserved(u8),
-}
-impl MODER {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            MODER::_00 => 0,
-            MODER::_01 => 1,
-            MODER::_10 => 2,
-            MODER::_Reserved(bits) => bits,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> MODER {
-        match value {
-            0 => MODER::_00,
-            1 => MODER::_01,
-            2 => MODER::_10,
-            i => MODER::_Reserved(i),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == MODER::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == MODER::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == MODER::_10
-    }
-}
-#[doc = "Possible values of the field `ADIV`"]
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub enum ADIVR {
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    _00,
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    _01,
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    _10,
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    _11,
-}
-impl ADIVR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        match *self {
-            ADIVR::_00 => 0,
-            ADIVR::_01 => 1,
-            ADIVR::_10 => 2,
-            ADIVR::_11 => 3,
-        }
-    }
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _from(value: u8) -> ADIVR {
-        match value {
-            0 => ADIVR::_00,
-            1 => ADIVR::_01,
-            2 => ADIVR::_10,
-            3 => ADIVR::_11,
-            _ => unreachable!(),
-        }
-    }
-    #[doc = "Checks if the value of the field is `_00`"]
-    #[inline]
-    pub fn is_00(&self) -> bool {
-        *self == ADIVR::_00
-    }
-    #[doc = "Checks if the value of the field is `_01`"]
-    #[inline]
-    pub fn is_01(&self) -> bool {
-        *self == ADIVR::_01
-    }
-    #[doc = "Checks if the value of the field is `_10`"]
-    #[inline]
-    pub fn is_10(&self) -> bool {
-        *self == ADIVR::_10
-    }
-    #[doc = "Checks if the value of the field is `_11`"]
-    #[inline]
-    pub fn is_11(&self) -> bool {
-        *self == ADIVR::_11
-    }
-}
-#[doc = "Values that can be written to the field `ADICLK`"]
-pub enum ADICLKW {
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    _00,
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    _01,
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    _10,
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    _11,
-}
-impl ADICLKW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            ADICLKW::_00 => 0,
-            ADICLKW::_01 => 1,
-            ADICLKW::_10 => 2,
-            ADICLKW::_11 => 3,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADICLKW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADICLKW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADICLKW) -> &'a mut W {
-        {
-            self.bits(variant._bits())
-        }
-    }
-    #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(ADICLKW::_00)
-    }
-    #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(ADICLKW::_01)
-    }
-    #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(ADICLKW::_10)
-    }
-    #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
-    #[inline]
-    pub fn _11(self) -> &'a mut W {
-        self.variant(ADICLKW::_11)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `MODE`"]
-pub enum MODEW {
-    #[doc = "8-bit conversion."]
-    _00,
-    #[doc = "12-bit conversion."]
-    _01,
-    #[doc = "10-bit conversion."]
-    _10,
-}
-impl MODEW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            MODEW::_00 => 0,
-            MODEW::_01 => 1,
-            MODEW::_10 => 2,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _MODEW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _MODEW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: MODEW) -> &'a mut W {
-        unsafe { self.bits(variant._bits()) }
-    }
-    #[doc = "8-bit conversion."]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(MODEW::_00)
-    }
-    #[doc = "12-bit conversion."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(MODEW::_01)
-    }
-    #[doc = "10-bit conversion."]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(MODEW::_10)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 2;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = "Values that can be written to the field `ADIV`"]
-pub enum ADIVW {
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    _00,
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    _01,
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    _10,
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    _11,
-}
-impl ADIVW {
-    #[allow(missing_docs)]
-    #[doc(hidden)]
-    #[inline]
-    pub fn _bits(&self) -> u8 {
-        match *self {
-            ADIVW::_00 => 0,
-            ADIVW::_01 => 1,
-            ADIVW::_10 => 2,
-            ADIVW::_11 => 3,
-        }
-    }
-}
-#[doc = r" Proxy"]
-pub struct _ADIVW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _ADIVW<'a> {
-    #[doc = r" Writes `variant` to the field"]
-    #[inline]
-    pub fn variant(self, variant: ADIVW) -> &'a mut W {
-        {
-            self.bits(variant._bits())
-        }
-    }
-    #[doc = "The divide ratio is 1 and the clock rate is input clock."]
-    #[inline]
-    pub fn _00(self) -> &'a mut W {
-        self.variant(ADIVW::_00)
-    }
-    #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
-    #[inline]
-    pub fn _01(self) -> &'a mut W {
-        self.variant(ADIVW::_01)
-    }
-    #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
-    #[inline]
-    pub fn _10(self) -> &'a mut W {
-        self.variant(ADIVW::_10)
-    }
-    #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
-    #[inline]
-    pub fn _11(self) -> &'a mut W {
-        self.variant(ADIVW::_11)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 3;
-        const OFFSET: u8 = 5;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLRLTRGW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLRLTRGW<'a> {
-    #[doc = r" Sets the field bit"]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r" Clears the field bit"]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        const MASK: bool = true;
-        const OFFSET: u8 = 8;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:1 - Input Clock Select"]
-    #[inline]
-    pub fn adiclk(&self) -> ADICLKR {
-        ADICLKR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bits 2:3 - Conversion mode selection"]
-    #[inline]
-    pub fn mode(&self) -> MODER {
-        MODER::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 2;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-    #[doc = "Bits 5:6 - Clock Divide Select"]
-    #[inline]
-    pub fn adiv(&self) -> ADIVR {
-        ADIVR::_from({
-            const MASK: u8 = 3;
-            const OFFSET: u8 = 5;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        })
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:1 - Input Clock Select"]
-    #[inline]
-    pub fn adiclk(&mut self) -> _ADICLKW {
-        _ADICLKW { w: self }
-    }
-    #[doc = "Bits 2:3 - Conversion mode selection"]
-    #[inline]
-    pub fn mode(&mut self) -> _MODEW {
-        _MODEW { w: self }
-    }
-    #[doc = "Bits 5:6 - Clock Divide Select"]
-    #[inline]
-    pub fn adiv(&mut self) -> _ADIVW {
-        _ADIVW { w: self }
-    }
-    #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
-    #[inline]
-    pub fn clrltrg(&mut self) -> _CLRLTRGW {
-        _CLRLTRGW { w: self }
-    }
-}

src/adc1/cfg2.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CFG2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SMPLTSR {
+    bits: u8,
+}
+impl SMPLTSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMPLTSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMPLTSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Sample Time Select"]
+    #[inline]
+    pub fn smplts(&self) -> SMPLTSR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SMPLTSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 12 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Sample Time Select"]
+    #[inline]
+    pub fn smplts(&mut self) -> _SMPLTSW {
+        _SMPLTSW { w: self }
+    }
+}

src/adc1/cfg2/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CFG2 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct SMPLTSR {
-    bits: u8,
-}
-impl SMPLTSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _SMPLTSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _SMPLTSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Sample Time Select"]
-    #[inline]
-    pub fn smplts(&self) -> SMPLTSR {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        SMPLTSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 12 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Sample Time Select"]
-    #[inline]
-    pub fn smplts(&mut self) -> _SMPLTSW {
-        _SMPLTSW { w: self }
-    }
-}

src/adc1/clp0.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP0R {
+    bits: u8,
+}
+impl CLP0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP0W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP0W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Calibration Value"]
+    #[inline]
+    pub fn clp0(&self) -> CLP0R {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP0R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 46 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Calibration Value"]
+    #[inline]
+    pub fn clp0(&mut self) -> _CLP0W {
+        _CLP0W { w: self }
+    }
+}

src/adc1/clp0/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP0 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP0R {
-    bits: u8,
-}
-impl CLP0R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP0W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP0W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 255;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:7 - Calibration Value"]
-    #[inline]
-    pub fn clp0(&self) -> CLP0R {
-        let bits = {
-            const MASK: u8 = 255;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP0R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 46 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:7 - Calibration Value"]
-    #[inline]
-    pub fn clp0(&mut self) -> _CLP0W {
-        _CLP0W { w: self }
-    }
-}

src/adc1/clp0_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP0_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP0_OFSR {
+    bits: u8,
+}
+impl CLP0_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP0_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP0_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP0 Offset"]
+    #[inline]
+    pub fn clp0_ofs(&self) -> CLP0_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP0_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP0 Offset"]
+    #[inline]
+    pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
+        _CLP0_OFSW { w: self }
+    }
+}

src/adc1/clp0_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP0_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP0_OFSR {
-    bits: u8,
-}
-impl CLP0_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP0_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP0_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP0 Offset"]
-    #[inline]
-    pub fn clp0_ofs(&self) -> CLP0_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP0_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP0 Offset"]
-    #[inline]
-    pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
-        _CLP0_OFSW { w: self }
-    }
-}

src/adc1/clp1.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP1R {
+    bits: u16,
+}
+impl CLP1R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP1W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP1W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 511;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:8 - Calibration Value"]
+    #[inline]
+    pub fn clp1(&self) -> CLP1R {
+        let bits = {
+            const MASK: u16 = 511;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP1R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 92 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:8 - Calibration Value"]
+    #[inline]
+    pub fn clp1(&mut self) -> _CLP1W {
+        _CLP1W { w: self }
+    }
+}

src/adc1/clp1/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP1 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP1R {
-    bits: u16,
-}
-impl CLP1R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP1W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP1W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 511;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:8 - Calibration Value"]
-    #[inline]
-    pub fn clp1(&self) -> CLP1R {
-        let bits = {
-            const MASK: u16 = 511;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP1R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 92 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:8 - Calibration Value"]
-    #[inline]
-    pub fn clp1(&mut self) -> _CLP1W {
-        _CLP1W { w: self }
-    }
-}

src/adc1/clp1_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP1_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP1_OFSR {
+    bits: u8,
+}
+impl CLP1_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP1_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP1_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP1 Offset"]
+    #[inline]
+    pub fn clp1_ofs(&self) -> CLP1_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP1_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP1 Offset"]
+    #[inline]
+    pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
+        _CLP1_OFSW { w: self }
+    }
+}

src/adc1/clp1_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP1_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP1_OFSR {
-    bits: u8,
-}
-impl CLP1_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP1_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP1_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP1 Offset"]
-    #[inline]
-    pub fn clp1_ofs(&self) -> CLP1_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP1_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP1 Offset"]
-    #[inline]
-    pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
-        _CLP1_OFSW { w: self }
-    }
-}

src/adc1/clp2.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP2R {
+    bits: u16,
+}
+impl CLP2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP2W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp2(&self) -> CLP2R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP2R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 184 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp2(&mut self) -> _CLP2W {
+        _CLP2W { w: self }
+    }
+}

src/adc1/clp2/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP2 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP2R {
-    bits: u16,
-}
-impl CLP2R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP2W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP2W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 1023;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp2(&self) -> CLP2R {
-        let bits = {
-            const MASK: u16 = 1023;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP2R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 184 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp2(&mut self) -> _CLP2W {
-        _CLP2W { w: self }
-    }
-}

src/adc1/clp2_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP2_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP2_OFSR {
+    bits: u8,
+}
+impl CLP2_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP2_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP2_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP2 Offset"]
+    #[inline]
+    pub fn clp2_ofs(&self) -> CLP2_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP2_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP2 Offset"]
+    #[inline]
+    pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
+        _CLP2_OFSW { w: self }
+    }
+}

src/adc1/clp2_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP2_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP2_OFSR {
-    bits: u8,
-}
-impl CLP2_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP2_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP2_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP2 Offset"]
-    #[inline]
-    pub fn clp2_ofs(&self) -> CLP2_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP2_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP2 Offset"]
-    #[inline]
-    pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
-        _CLP2_OFSW { w: self }
-    }
-}

src/adc1/clp3.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP3R {
+    bits: u16,
+}
+impl CLP3R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP3W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP3W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 1023;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp3(&self) -> CLP3R {
+        let bits = {
+            const MASK: u16 = 1023;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP3R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 384 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:9 - Calibration Value"]
+    #[inline]
+    pub fn clp3(&mut self) -> _CLP3W {
+        _CLP3W { w: self }
+    }
+}

src/adc1/clp3/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP3 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP3R {
-    bits: u16,
-}
-impl CLP3R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP3W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP3W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 1023;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp3(&self) -> CLP3R {
-        let bits = {
-            const MASK: u16 = 1023;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP3R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 384 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:9 - Calibration Value"]
-    #[inline]
-    pub fn clp3(&mut self) -> _CLP3W {
-        _CLP3W { w: self }
-    }
-}

src/adc1/clp3_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP3_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP3_OFSR {
+    bits: u8,
+}
+impl CLP3_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP3_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP3_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLP3 Offset"]
+    #[inline]
+    pub fn clp3_ofs(&self) -> CLP3_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP3_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLP3 Offset"]
+    #[inline]
+    pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
+        _CLP3_OFSW { w: self }
+    }
+}

src/adc1/clp3_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP3_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP3_OFSR {
-    bits: u8,
-}
-impl CLP3_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP3_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP3_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLP3 Offset"]
-    #[inline]
-    pub fn clp3_ofs(&self) -> CLP3_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP3_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLP3 Offset"]
-    #[inline]
-    pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
-        _CLP3_OFSW { w: self }
-    }
-}

src/adc1/clp9.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP9 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP9R {
+    bits: u8,
+}
+impl CLP9R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP9W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP9W<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clp9(&self) -> CLP9R {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLP9R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clp9(&mut self) -> _CLP9W {
+        _CLP9W { w: self }
+    }
+}

src/adc1/clp9/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP9 {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP9R {
-    bits: u8,
-}
-impl CLP9R {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP9W<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP9W<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clp9(&self) -> CLP9R {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLP9R { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clp9(&mut self) -> _CLP9W {
-        _CLP9W { w: self }
-    }
-}

src/adc1/clp9_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLP9_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLP9_OFSR {
+    bits: u16,
+}
+impl CLP9_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLP9_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLP9_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 4095;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:11 - CLP9 Offset"]
+    #[inline]
+    pub fn clp9_ofs(&self) -> CLP9_OFSR {
+        let bits = {
+            const MASK: u16 = 4095;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLP9_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 576 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:11 - CLP9 Offset"]
+    #[inline]
+    pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
+        _CLP9_OFSW { w: self }
+    }
+}

src/adc1/clp9_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLP9_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLP9_OFSR {
-    bits: u16,
-}
-impl CLP9_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLP9_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLP9_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 4095;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:11 - CLP9 Offset"]
-    #[inline]
-    pub fn clp9_ofs(&self) -> CLP9_OFSR {
-        let bits = {
-            const MASK: u16 = 4095;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLP9_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 576 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:11 - CLP9 Offset"]
-    #[inline]
-    pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
-        _CLP9_OFSW { w: self }
-    }
-}

src/adc1/clps.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPSR {
+    bits: u8,
+}
+impl CLPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clps(&self) -> CLPSR {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 46 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clps(&mut self) -> _CLPSW {
+        _CLPSW { w: self }
+    }
+}

src/adc1/clps/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPSR {
-    bits: u8,
-}
-impl CLPSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clps(&self) -> CLPSR {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 46 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clps(&mut self) -> _CLPSW {
-        _CLPSW { w: self }
-    }
-}

src/adc1/clps_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPS_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPS_OFSR {
+    bits: u8,
+}
+impl CLPS_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPS_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPS_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - CLPS Offset"]
+    #[inline]
+    pub fn clps_ofs(&self) -> CLPS_OFSR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPS_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - CLPS Offset"]
+    #[inline]
+    pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
+        _CLPS_OFSW { w: self }
+    }
+}

src/adc1/clps_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPS_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPS_OFSR {
-    bits: u8,
-}
-impl CLPS_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPS_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPS_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 15;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:3 - CLPS Offset"]
-    #[inline]
-    pub fn clps_ofs(&self) -> CLPS_OFSR {
-        let bits = {
-            const MASK: u8 = 15;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPS_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:3 - CLPS Offset"]
-    #[inline]
-    pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
-        _CLPS_OFSW { w: self }
-    }
-}

src/adc1/clpx.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPX {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPXR {
+    bits: u8,
+}
+impl CLPXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 127;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clpx(&self) -> CLPXR {
+        let bits = {
+            const MASK: u8 = 127;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CLPXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:6 - Calibration Value"]
+    #[inline]
+    pub fn clpx(&mut self) -> _CLPXW {
+        _CLPXW { w: self }
+    }
+}

src/adc1/clpx/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPX {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPXR {
-    bits: u8,
-}
-impl CLPXR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u8 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPXW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPXW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        const MASK: u8 = 127;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clpx(&self) -> CLPXR {
-        let bits = {
-            const MASK: u8 = 127;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u8
-        };
-        CLPXR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:6 - Calibration Value"]
-    #[inline]
-    pub fn clpx(&mut self) -> _CLPXW {
-        _CLPXW { w: self }
-    }
-}

src/adc1/clpx_ofs.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLPX_OFS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CLPX_OFSR {
+    bits: u16,
+}
+impl CLPX_OFSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CLPX_OFSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CLPX_OFSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 4095;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:11 - CLPX Offset"]
+    #[inline]
+    pub fn clpx_ofs(&self) -> CLPX_OFSR {
+        let bits = {
+            const MASK: u16 = 4095;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CLPX_OFSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1088 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:11 - CLPX Offset"]
+    #[inline]
+    pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
+        _CLPX_OFSW { w: self }
+    }
+}

src/adc1/clpx_ofs/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CLPX_OFS {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CLPX_OFSR {
-    bits: u16,
-}
-impl CLPX_OFSR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CLPX_OFSW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CLPX_OFSW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 4095;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:11 - CLPX Offset"]
-    #[inline]
-    pub fn clpx_ofs(&self) -> CLPX_OFSR {
-        let bits = {
-            const MASK: u16 = 4095;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CLPX_OFSR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 1088 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:11 - CLPX Offset"]
-    #[inline]
-    pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
-        _CLPX_OFSW { w: self }
-    }
-}

src/adc1/cv.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CV {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CVR {
+    bits: u16,
+}
+impl CVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CVW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Compare Value."]
+    #[inline]
+    pub fn cv(&self) -> CVR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CVR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Compare Value."]
+    #[inline]
+    pub fn cv(&mut self) -> _CVW {
+        _CVW { w: self }
+    }
+}

src/adc1/cv/mod.rs

@@ -1,105 +0,0 @@
-#[doc = r" Value read from the register"]
-pub struct R {
-    bits: u32,
-}
-#[doc = r" Value to write to the register"]
-pub struct W {
-    bits: u32,
-}
-impl super::CV {
-    #[doc = r" Modifies the contents of the register"]
-    #[inline]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
-    {
-        let bits = self.register.get();
-        let r = R { bits: bits };
-        let mut w = W { bits: bits };
-        f(&r, &mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Reads the contents of the register"]
-    #[inline]
-    pub fn read(&self) -> R {
-        R {
-            bits: self.register.get(),
-        }
-    }
-    #[doc = r" Writes to the register"]
-    #[inline]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W) -> &mut W,
-    {
-        let mut w = W::reset_value();
-        f(&mut w);
-        self.register.set(w.bits);
-    }
-    #[doc = r" Writes the reset value to the register"]
-    #[inline]
-    pub fn reset(&self) {
-        self.write(|w| w)
-    }
-}
-#[doc = r" Value of the field"]
-pub struct CVR {
-    bits: u16,
-}
-impl CVR {
-    #[doc = r" Value of the field as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u16 {
-        self.bits
-    }
-}
-#[doc = r" Proxy"]
-pub struct _CVW<'a> {
-    w: &'a mut W,
-}
-impl<'a> _CVW<'a> {
-    #[doc = r" Writes raw bits to the field"]
-    #[inline]
-    pub unsafe fn bits(self, value: u16) -> &'a mut W {
-        const MASK: u16 = 65535;
-        const OFFSET: u8 = 0;
-        self.w.bits &= !((MASK as u32) << OFFSET);
-        self.w.bits |= ((value & MASK) as u32) << OFFSET;
-        self.w
-    }
-}
-impl R {
-    #[doc = r" Value of the register as raw bits"]
-    #[inline]
-    pub fn bits(&self) -> u32 {
-        self.bits
-    }
-    #[doc = "Bits 0:15 - Compare Value."]
-    #[inline]
-    pub fn cv(&self) -> CVR {
-        let bits = {
-            const MASK: u16 = 65535;
-            const OFFSET: u8 = 0;
-            ((self.bits >> OFFSET) & MASK as u32) as u16
-        };
-        CVR { bits }
-    }
-}
-impl W {
-    #[doc = r" Reset value of the register"]
-    #[inline]
-    pub fn reset_value() -> W {
-        W { bits: 0 }
-    }
-    #[doc = r" Writes raw bits to the register"]
-    #[inline]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.bits = bits;
-        self
-    }
-    #[doc = "Bits 0:15 - Compare Value."]
-    #[inline]
-    pub fn cv(&mut self) -> _CVW {
-        _CVW { w: self }
-    }
-}

src/adc1/g.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::G {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct GR {
+    bits: u16,
+}
+impl GR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _GW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _GW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 2047;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
+    #[inline]
+    pub fn g(&self) -> GR {
+        let bits = {
+            const MASK: u16 = 2047;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        GR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 752 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
+    #[inline]
+    pub fn g(&mut self) -> _GW {
+        _GW { w: self }
+    }
+}